Digital clock jitter measuring circuit and measuring method

Abstract

The invention provides a digital clock jitter measuring circuit and a digital clock jitter measuring method. The measuring circuit comprises a time delay module, the time delay module receives a clock signal to be measured and generates a first clock signal and a second clock signal, and the phase difference between the first clock signal and the second clock signal is a clock period; and the measuring module comprises a sampling unit, an oscillator control unit, a measuring unit and a counter unit. The measuring unit comprises a slow frequency oscillator, an intermediate frequency oscillator, a fast frequency oscillator, a first edge detector and a second edge detector, the first edge detector is connected with the slow frequency oscillator and the intermediate frequency oscillator, and the second edge detector is connected with the intermediate frequency oscillator and the fast frequency oscillator. According to the clock jitter measurement circuit and measurement method provided by the invention, the matched oscillator can be automatically selected according to the phase relationship between the first clock signal and the second clock signal, so that automatic measurement of clock jitter is realized.

Description

Technical Field

[0001] The present application relates to the field of digital circuit design, and in particular to a digital clock jitter measurement circuit and measurement method. Background Art

[0002] With the explosive growth in data throughput demand from artificial intelligence and big data centers, system-on-chip (SoC) designs are evolving toward high-frequency, highly integrated, and multi-heterogeneous modules. Clock signal jitter, a crucial component of these systems, can directly lead to sampling inaccuracies and protocol interaction failures. Therefore, clock jitter measurement has become a critical component in ensuring system performance.

[0003] Off-chip measurements require expensive specialized equipment such as high-speed input / output (I / O) circuits, high-frequency probes, and probe stations, and are complex and costly. System-on-chip (SoC) jitter measurement functionality is integrated within the chip, eliminating the need for additional, expensive external equipment and reducing measurement costs. At the same time, off-chip systems struggle to comprehensively and accurately measure and control jitter in complex on-chip environments. SoCs, on the other hand, are better suited to their complex internal structures, enabling comprehensive monitoring of jitter across individual modules and the entire system, meeting the stringent jitter measurement requirements of complex systems.

[0004] In on-chip testing, methods based on adjustable delay line structures, which exploit the delay differences between delay cells to digitize the jitter of the measured signal, are widely used. However, while this type of technology improves measurement resolution, it also increases chip area.

[0005] Therefore, it is necessary to provide a circuit and method that can implement digital clock jitter measurement with lower area cost. Summary of the Invention

[0006] In view of this, the present application provides a digital clock jitter measurement circuit and measurement method to solve the above technical problems in the prior art.

[0007] According to one aspect of the present application, a digital clock jitter measurement circuit is provided, the measurement circuit comprising: A delay module, wherein the delay module receives a clock signal to be measured and generates a first clock signal and a second clock signal, wherein a phase difference between the first clock signal and the second clock signal is one clock cycle; A measurement module, comprising a sampling unit, an oscillator control unit, a measurement unit and a counter unit, The measuring unit includes a slow frequency oscillator, an intermediate frequency oscillator, and a fast frequency oscillator, as well as a first edge detector and a second edge detector. The first edge detector is connected to the slow frequency oscillator and the intermediate frequency oscillator, and the second edge detector is connected to the intermediate frequency oscillator and the fast frequency oscillator. The counter unit includes a first counter and a second counter, the first counter is used to count the number of oscillations of the slow frequency oscillator or the intermediate frequency oscillator, and the second counter is used to count the number of oscillations of the intermediate frequency oscillator or the fast frequency oscillator; The sampling unit samples the first clock signal and the second clock signal respectively and outputs the sampled signals to the oscillator control unit. When the second clock signal lags behind the first clock signal, the oscillator control unit controls the slow frequency oscillator and the intermediate frequency oscillator to start, and the counter unit outputs the value of the first counter; When the second clock signal is ahead of the first clock signal, the oscillator control unit controls the fast frequency oscillator and the intermediate frequency oscillator to start, and the counter unit outputs the value of the second counter.

[0008] According to a preferred embodiment of the present application, the sampling unit includes a first D flip-flop and a second D flip-flop, the first D flip-flop is used to adopt the rising edge of the first clock signal, and the second D flip-flop is used to sample the rising edge of the second clock signal.

[0009] According to a preferred embodiment of the present application, the first edge detector is configured to detect the phase of the oscillation clock signal in the slow frequency oscillator and the intermediate frequency oscillator. When the oscillation clock signal of the slow frequency oscillator lags behind the oscillation clock signal of the intermediate frequency oscillator, the first edge detector outputs a feedback signal PD1 to enable the oscillator control unit to turn off the slow frequency oscillator and the intermediate frequency oscillator; When the oscillation clock signal of the intermediate frequency oscillator lags behind the oscillation clock signal of the fast frequency oscillator, the second edge detector outputs a feedback signal PD2 to enable the oscillator control unit to turn off the intermediate frequency oscillator and the fast frequency oscillator.

[0010] According to a preferred embodiment of the present application, the oscillator control unit includes an OR gate, a third D flip-flop, a first AND gate, and a second AND gate. The input of the OR gate is the feedback signal PD1 output by the first phase detector and the feedback signal PD2 output by the second phase detector. The input of the first AND gate is the Q end of the first D flip-flop and the non-Q end of the third flip-flop. The input of the second AND gate is the Q end of the second D flip-flop and the non-Q end of the third flip-flop. The output end of the OR gate is connected to the input end of the third D flip-flop. The output end of the first AND gate is connected to the slow frequency oscillator and the fast frequency oscillator. The output end of the second AND gate is connected to the intermediate frequency oscillator.

[0011] According to a preferred embodiment of the present application, the counter unit further includes a phase detector and a selector, the input end of the phase detector is connected to the output end of the first D flip-flop and the second D flip-flop, the output end of the phase detector is connected to the control end of the selector, and when the phase detector detects that the phase of the first clock signal is ahead of the second clock, the selector selects the output of the first counter under the control of the phase detector; when the phase detector detects that the phase of the first clock signal lags behind the second clock, the selector selects the output of the second counter under the control of the phase detector.

[0012] According to a preferred embodiment of the present application, the measurement unit includes a slow intermediate frequency measurement unit and a medium-fast frequency measurement unit. The slow intermediate frequency measurement unit includes a slow frequency oscillator, an intermediate frequency oscillator and a first edge detector. The medium-fast frequency measurement unit includes an intermediate frequency oscillator, a fast frequency oscillator and a second edge detector.

[0013] According to a preferred embodiment of the present application, the slow frequency oscillator, the intermediate frequency oscillator and the fast frequency oscillator include an adjustable load for adjusting the resolution of the measurement unit.

[0014] According to a preferred embodiment of the present application, the first edge detector and the second edge detector are used to detect a rising edge or a falling edge of the clock signal.

[0015] According to a preferred embodiment of the present application, the measurement circuit further includes a synchronous reset unit for synchronously resetting the first D flip-flop, the second D flip-flop and the third D flip-flop DFF3 and clearing the data of the first counter and the second counter.

[0016] According to another aspect of the present application, a clock jitter measurement method is provided. The method is executed by the measurement circuit described above under the control of an automatic control module. The method includes the following steps: Step S1, adjusting the delay module to generate a first clock signal and a second clock signal; Step S2, resetting the measurement module; Step S3, measuring the jitter of the clock signal to be measured within a given time; Step S4, record the measurement results and update the measurement times; Step S5: If the number of measurements reaches the preset value, the measurement is ended; if the number of measurements does not reach the preset value, the process returns to step S2.

[0017] As can be seen from the above technical solutions, the measurement circuit provided by this application can automatically select a matching oscillator, achieving fast and accurate measurement of digital clock jitter with a low area cost. Furthermore, in the measurement circuit provided by this application, the oscillator can have an adjustable load. By digitally controlling the load capacitance, measurement accuracy can be adjusted, improving measurement resolution. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings are used to provide a further understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application, but do not constitute a limitation on the technical solution of the present application.

[0019] Figure 1 A schematic structural diagram of a clock jitter measurement circuit according to an exemplary embodiment of the present application is shown; Figure 2 A schematic structural diagram of a measurement module according to an exemplary embodiment of the present application is shown; Figure 3 shows a signal waveform diagram in a measuring unit of an exemplary embodiment of the present application; Figure 4 A schematic structural diagram of an oscillator according to an exemplary embodiment of the present application is shown; Figure 5 A schematic structural diagram of an edge detector according to an exemplary embodiment of the present application is shown; Figure 6 A schematic structural diagram of a synchronous reset unit according to an exemplary embodiment of the present application is shown; Figure 7 The flowchart of the clock jitter measurement method according to the exemplary embodiment of the present application is shown. DETAILED DESCRIPTION

[0020] Various exemplary embodiments of the present application will be described in detail below with reference to the accompanying drawings. The description of the exemplary embodiments is merely illustrative and is not intended to limit the present application, its application, or use. The present application can be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided to make the present application thorough and complete and to fully convey the scope of the present application to those skilled in the art.

[0021] Unless explicitly stated, if the number of an element is not specifically limited, the element may be one or more. The term "plurality" means two or more, the term "based on" should be interpreted as "based at least in part on," and the terms "and / or" and "at least one of..." encompass any and all possible combinations of the listed items. Furthermore, terms such as "first," "second," and the like are for descriptive purposes only and do not indicate or imply relative importance or implicitly specify the number of the technical features being referred to.

[0022] refer to Figure 1 , which shows a schematic structural diagram of a clock jitter measurement circuit according to an exemplary embodiment of the present application. Figure 1As shown, the clock jitter measurement circuit includes a delay module and a measurement module. The clock signal to be measured, CK_IN, passes through the delay module to generate two clock signals: a first clock signal, CK1, and a second clock signal, CK2. The phase difference between the two clock signals, CK1 and CK2, is one clock cycle. The measurement module processes the clock signals CK1 and CK2 output by the delay module, quantizes the phase difference between the clock signals CK1 and CK2, and outputs a jitter signal, J_OUT. The clock jitter measurement circuit also includes an automatic control module for controlling the measurement module to achieve automated measurement.

[0023] refer to Figure 2 , which shows a schematic structural diagram of a measurement module of an exemplary embodiment of the present application. Figure 2 As shown, the measurement module includes: a sampling unit, an oscillator control unit, a measurement unit and a counter unit.

[0024] The sampling unit includes a first D flip-flop DFF1 and a second D flip-flop DFF2. The first D flip-flop DFF1 is used to sample the rising edge of the input first clock signal CK1, and the second D flip-flop DFF2 is used to sample the rising edge of the input second clock signal CK2.

[0025] The measurement unit includes a slow intermediate frequency measurement unit and a medium-fast frequency measurement unit. The slow intermediate frequency measurement unit includes a slow frequency oscillator, an intermediate frequency oscillator, and a first edge detector. The medium-fast frequency measurement unit includes an intermediate frequency oscillator, a fast frequency oscillator, and a second edge detector. The oscillation frequencies F1 of the slow frequency oscillator, F2 of the intermediate frequency oscillator, and F3 of the fast frequency oscillator increase in sequence. The oscillators preferably have adjustable loads.

[0026] When the input first clock signal CK1 leads the input second clock signal CK2, the slow intermediate frequency measurement unit operates, and the slow frequency oscillator and intermediate frequency oscillator therein begin to oscillate. Initially, the phase of the slow frequency oscillator's oscillation clock signal RO_S leads the phase of the intermediate frequency oscillator's oscillation clock signal RO_M. When the edge detector detects that the phase of the slow frequency oscillator's oscillation clock signal RO_S lags the phase of the intermediate frequency oscillator's oscillation clock signal RO_M, the first edge detector of the slow intermediate frequency measurement unit outputs a phase detection feedback signal PD1, which controls the slow frequency oscillator and intermediate frequency oscillator to shut down the oscillation state. When the input second clock signal CK2 leads the input first clock signal CK1, the intermediate and fast frequency measurement unit operates. The intermediate frequency oscillator and the fast frequency oscillator begin to oscillate. Initially, the phase of the intermediate frequency oscillator's oscillation clock signal RO_M leads the phase of the fast frequency oscillator's oscillation clock signal RO_F. When the edge detector detects that the phase of the intermediate frequency oscillator's oscillation clock signal RO_M lags the phase of the fast frequency oscillator's oscillation clock signal RO_F, the edge detector of the intermediate and fast frequency measurement unit outputs a phase detection feedback signal PD2, which controls the intermediate frequency oscillator and the fast frequency oscillator to shut down. By controlling the adjustable load of the oscillator, the resolution of the measurement unit can be adjusted.

[0027] The oscillator control unit includes an OR gate OR with the first phase detection feedback signal PD1 of the slow intermediate frequency measurement unit and the second phase detection feedback signal PD2 of the intermediate-fast frequency measurement unit as inputs; a third D-type flip-flop DFF3; a first AND gate AND1 with the non-Q terminal of the third D-type flip-flop DFF3 and the Q terminal of the first D-type flip-flop DFF1 as input signals; and a second AND gate AND2 with the non-Q terminal of the third D-type flip-flop DFF3 and the Q terminal of the second D-type flip-flop DFF2 as input signals. The oscillator control unit is used to control the activation and deactivation of the slow intermediate frequency measurement unit and the intermediate-fast frequency measurement unit.

[0028] The counter unit includes two counters (a first counter and a second counter), a selector MUX, and a phase detector. The counter unit is used to count the number of oscillations CNT1 of the oscillation clock RO1 generated by the slow intermediate frequency measurement unit and the number of oscillations CNT2 of the oscillation clock RO2 of the medium-fast frequency measurement unit. The selector MUX selects either the number of oscillations CNT1 of the slow intermediate frequency measurement unit or the number of oscillations CNT2 of the medium-fast frequency measurement unit. The output of the phase detector is connected to the select signal SEL of the selector MUX. When the input first clock signal CK1 leads the input second clock signal CK2, the phase detector arbitrates the phase relationship and provides the select signal SEL to the selector MUX to select the number of oscillations CNT1 generated by the slow intermediate frequency measurement unit. When the input first clock signal CK1 lags the input second clock signal CK2, the phase detector arbitrates the phase relationship and provides the select signal SEL to the selector MUX to select the number of oscillations CNT2 generated by the medium-fast frequency measurement unit. The output jitter value J_OUT is:

[0029] Where F1 is the slow frequency oscillator frequency, F2 is the medium frequency oscillator frequency, and F3 is the fast frequency oscillator frequency.

[0030] The measurement circuit according to an embodiment of the present application may further include a synchronous reset unit configured to perform a synchronous reset operation on an input reset signal RST. The synchronous reset operation includes resetting the first D flip-flop DFF1 and the second D flip-flop DFF2 of the sampling module and the third D flip-flop DFF3 of the oscillator control unit, and clearing the counter data of the counter units CNT1 and CNT2.

[0031] refer to Figure 3 , which shows a signal waveform diagram in the measurement unit of an exemplary embodiment of the present application. Figure 3As shown, when the input first clock signal CK1 101 leads the input second clock signal CK2 102, the first D flip-flop samples the rising edge of the input clock signal CK1 to obtain a rising edge pulse 103, and the second D flip-flop samples the rising edge of the input clock signal CK2 to obtain a rising edge pulse 104. The oscillation control unit then activates the slow intermediate frequency measurement unit, and the slow frequency oscillator and the intermediate frequency oscillator begin to oscillate. Initially, the phase 105 of the slow frequency oscillator's oscillation clock signal RO_S leads the phase 106 of the intermediate frequency oscillator's oscillation clock signal RO_M. When the edge detector detects that the phase 107 of the slow frequency oscillator's oscillation clock signal RO_S lags the phase 108 of the intermediate frequency oscillator's oscillation clock signal RO_M, the edge detector of the slow intermediate frequency measurement unit raises the level of the phase detection feedback signal PD1 109, which is then fed back to the slow intermediate frequency measurement unit, controlling the slow frequency oscillator and the intermediate frequency oscillator to shut down their oscillation state. When the input first clock signal CK1 201 lags behind the input second clock signal CK2 202, the first D flip-flop samples the rising edge of the input clock signal CK1 to obtain a rising edge pulse 203, and the second D flip-flop samples the rising edge of the input clock signal CK2 to obtain a rising edge pulse 204. The oscillation control unit then activates the intermediate- and fast-frequency measurement units, and the intermediate- and fast-frequency oscillators begin oscillating. Initially, the phase 205 of the intermediate- and fast-frequency oscillator's oscillation clock signal RO_M leads the phase 206 of the fast-frequency oscillator's oscillation clock signal RO_F. When the edge detector detects that the phase 207 of the intermediate- and fast-frequency oscillator's oscillation clock signal RO_M lags the phase 208 of the fast-frequency oscillator's oscillation clock signal RO_F, the edge detector of the intermediate- and fast-frequency measurement unit raises the level of the phase detection feedback signal PD2 209 and feeds it back to the intermediate- and fast-frequency measurement units, controlling the intermediate- and fast-frequency oscillators to shut down their oscillation states.

[0032] refer to Figure 4 , which shows a schematic structural diagram of an oscillator according to an exemplary embodiment of the present application. Figure 2 The slow frequency oscillator, medium frequency oscillator or fast frequency oscillator shown in FIG can all adopt this oscillator structure. The embodiment of the present application does not limit the oscillator circuit structure. Figure 4 The oscillator receives an output signal 10 of the oscillator control unit and generates an oscillation output signal 11. In the oscillator, the total number of combinational logic elements including the NAND gate is an odd number. Figure 4 The inverter in the circuit can be replaced by other combinational logic elements, such as a NAND gate or an XOR gate. A slow-frequency oscillator, an intermediate-frequency oscillator, or a fast-frequency oscillator can use the same circuit, adjusting the frequency of the circuit by adjusting the adjustable load. Different circuit structures can also be used, but the slow-frequency oscillator frequency must be lower than the intermediate-frequency oscillator frequency, and the intermediate-frequency oscillator frequency must be lower than the high-frequency oscillator frequency.

[0033] refer to Figure 5 , which shows a schematic structural diagram of an edge detector of an exemplary embodiment of the present application. Figure 2 The first edge oscillator and the second edge oscillator shown in FIG can both adopt the edge detector structure. Figure 5 As shown, the edge detector can detect the phase of the edge (rising edge or falling edge) of the two oscillator output clocks 20 and 21 to generate a phase detection feedback signal PD1 or PD2 (number 22 in the figure). The output terminal 23 of the AND gate is connected to Figure 2 The middle counter is connected to output the number of oscillations of the oscillator.

[0034] refer to Figure 6 , which shows a schematic diagram of the structure of a synchronous reset unit of an exemplary embodiment of the present application. The synchronous reset unit performs a reset operation on the falling edge of the input first clock CK1 and the second clock CK2, thereby avoiding the uncertainty of asynchronous reset that may cause abnormal state of the measurement module.

[0035] refer to Figure 7 , which shows a flow chart of a clock jitter measurement method according to an exemplary embodiment of the present application. The measurement method is executed by an automatic control module controlling the measurement circuit described above. The automatic control module can be logically designed using a hardware description language and implemented as a hardware circuit. The measurement method includes the following steps: Step S1, adjusting the delay module to generate a first clock signal and a second clock signal; Step S2, resetting the measurement module; Step S3, measuring the jitter of the clock signal to be measured within a given time; Step S4, record the measurement results and update the measurement times; In step S5, if the number of measurements reaches the preset value, the measurement is ended; if the number of measurements does not reach the preset value, the process returns to step S2 to continue the measurement.

[0036] In step S1, the delay module receives a clock signal to be measured, and delays the clock signal to be measured to generate a first clock signal and a second clock signal, wherein the phase difference between the first clock signal and the second clock signal is one clock cycle; In step S2, the measurement circuit is initialized by resetting the first D flip-flop, the second D flip-flop, and the third D flip-flop DFF3 through a synchronous reset unit, and clearing the data of the first counter and the second counter.

[0037] In step S3, the first clock signal CK1 and the second clock signal CK2 are sampled within a given time, and the jitter signal J_OUT is measured and output. This given time is typically set to a fixed value during the test. Because jitter values ​​generally have an empirical range, the greater the jitter, the longer it takes for PD1 / PD2 to be generated. In practice, the measurement time can be estimated and set based on the maximum jitter.

[0038] In step S4, the measurement results are stored and the number of measurements is recorded by a counter.

[0039] In step S5, it is determined whether the number of measurements reaches a predetermined number of measurements, for example, 1000. If not, the process proceeds to step S2 to reset the measurement module. If it reaches the predetermined number of measurements, the measurement ends.

[0040] After the measurement is completed, jitter parameters can be calculated based on the stored jitter signal data using the following method. The method includes: collecting raw jitter data; constructing a probability density function (PDF) based on the raw jitter data; obtaining the probability distribution corresponding to different jitter values ​​based on the curve of the PDF; and calculating or deriving the peak-to-peak jitter and root mean square (RMS) jitter based on the PDF.

[0041] The description and illustration of the present application in the foregoing text and the accompanying drawings are not restrictive. It is obvious to those skilled in the art that the present application is not limited to the details of the above exemplary embodiments and that the present application can be implemented in other specific forms without departing from the spirit or essential characteristics of the present application. Therefore, the scope of protection claimed by the present application is defined by the claims rather than the above description, and all variations that fall within the meaning and scope of equivalents of the claims are intended to be included within the scope of protection of the present application.

Claims

1. A digital clock jitter measurement circuit, characterized in that: The measuring circuit comprises: A delay module, wherein the delay module receives a clock signal to be measured and generates a first clock signal and a second clock signal, wherein a phase difference between the first clock signal and the second clock signal is one clock cycle; A measurement module, comprising a sampling unit, an oscillator control unit, a measurement unit and a counter unit, The measuring unit includes a slow frequency oscillator, an intermediate frequency oscillator, and a fast frequency oscillator, as well as a first edge detector and a second edge detector. The first edge detector is connected to the slow frequency oscillator and the intermediate frequency oscillator, and the second edge detector is connected to the intermediate frequency oscillator and the fast frequency oscillator. The counter unit includes a first counter and a second counter, the first counter is used to count the number of oscillations of the slow frequency oscillator or the intermediate frequency oscillator, and the second counter is used to count the number of oscillations of the intermediate frequency oscillator or the fast frequency oscillator; The sampling unit samples the first clock signal and the second clock signal respectively and outputs the sampled signals to the oscillator control unit. When the second clock signal lags behind the first clock signal, the oscillator control unit controls the slow frequency oscillator and the intermediate frequency oscillator to start, and the counter unit outputs the value of the first counter; When the second clock signal is ahead of the first clock signal, the oscillator control unit controls the fast frequency oscillator and the intermediate frequency oscillator to start, and the counter unit outputs the value of the second counter.

2. The measuring circuit according to claim 1, characterized in that The sampling unit includes a first D flip-flop and a second D flip-flop, the first D flip-flop is used to sample the rising edge of the first clock signal, and the second D flip-flop is used to sample the rising edge of the second clock signal.

3. The measuring circuit according to claim 2, characterized in that The first edge detector is configured to detect the phase relationship between the oscillating clock signals in the slow frequency oscillator and the intermediate frequency oscillator, When the oscillation clock signal of the slow frequency oscillator lags behind the oscillation clock signal of the intermediate frequency oscillator, the first edge detector outputs a feedback signal PD1 to enable the oscillator control unit to turn off the slow frequency oscillator and the intermediate frequency oscillator; When the oscillation clock signal of the intermediate frequency oscillator lags behind the oscillation clock signal of the fast frequency oscillator, the second edge detector outputs a feedback signal PD2 to enable the oscillator control unit to turn off the intermediate frequency oscillator and the fast frequency oscillator.

4. The measuring circuit according to claim 3, characterized in that The oscillator control unit includes an OR gate, a third D flip-flop, a first AND gate, and a second AND gate. The inputs of the OR gate are the feedback signal PD1 output by the first phase detector and the feedback signal PD2 output by the second phase detector. The inputs of the first AND gate are the Q end of the first D flip-flop and the non-Q end of the third flip-flop. The inputs of the second AND gate are the Q end of the second D flip-flop and the non-Q end of the third flip-flop. The output of the OR gate is connected to the input of the third D flip-flop. The output of the first AND gate is connected to the slow frequency oscillator and the fast frequency oscillator. The output of the second AND gate is connected to the intermediate frequency oscillator.

5. The measurement circuit according to claim 2, characterized in that The counter unit includes a phase detector and a selector, wherein an input end of the phase detector is connected to output ends of the first D flip-flop and the second D flip-flop, and an output end of the phase detector is connected to a control end of the selector. When the phase detector detects that the phase of the first clock signal is ahead of the second clock signal, the selector selects the output of the first counter under the control of the phase detector. When the phase detector detects that the phase of the first clock signal lags behind the second clock, the selector selects the output of the second counter under the control of the phase detector.

6. The measurement circuit according to claim 1, characterized in that The measuring unit includes a slow intermediate frequency measuring unit and an intermediate-fast frequency measuring unit. The slow intermediate frequency measuring unit includes a slow frequency oscillator, an intermediate frequency oscillator and a first edge detector. The intermediate-fast frequency measuring unit includes an intermediate frequency oscillator, a fast frequency oscillator and a second edge detector.

7. The measurement circuit according to claim 1, characterized in that The slow frequency oscillator, the medium frequency oscillator, and the fast frequency oscillator include adjustable loads for adjusting the resolution of the measurement unit.

8. The measurement circuit according to claim 3, characterized in that The first edge detector and the second edge detector are used to detect a rising edge or a falling edge of the clock signal.

9. The measurement circuit according to claim 4, characterized in that The measurement circuit further includes a synchronous reset unit for synchronously resetting the first D flip-flop, the second D flip-flop and the third D flip-flop DFF3 and clearing the data of the first counter and the second counter.

10. A clock jitter measurement method, characterized in that: The method is executed by controlling the measurement circuit according to any one of claims 1 to 9 by an automatic control module, and the method comprises the following steps: Step S1, adjusting the delay module to generate a first clock signal and a second clock signal; Step S2, resetting the measurement module; Step S3, measuring the jitter of the clock signal to be measured within a given time; Step S4, record the measurement results and update the measurement times; Step S5: If the number of measurements reaches the preset value, the measurement is ended; if the number of measurements does not reach the preset value, the process returns to step S2.

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