Processor pipeline system, pipeline fast recovery method and related devices

Abstract

This invention relates to a processor pipeline system, a pipeline fast recovery method, and related equipment. The processor pipeline system includes a branch prediction module, an instruction fetch module, a decoding module, a branch filtering and judgment module, a prefetch module, an L1 instruction cache module, an L0 instruction cache module, and an execution module. The system proposed in this invention fetches instructions from the predicted branch result and multiple alternative results separately, and stores the alternative results in the L0 instruction cache. When a branch prediction fails, the pipeline can quickly fetch instructions from the L0 instruction cache. This design reduces the instruction fetch clock cycle and the processor pipeline's downtime. Simultaneously, the system utilizes branch filtering and prediction to select alternative results with higher accuracy, improving the processor pipeline's execution efficiency with relatively low L0 instruction cache capacity overhead and L1 instruction cache module read / write bandwidth overhead.

Description

Technical Field

[0001] This invention relates to the field of processor pipeline design technology, and in particular to a processor pipeline system, a pipeline fast recovery method, and related equipment. Background Technology

[0002] When a high-performance central processing unit (CPU) front-end fetch pipeline encounters a branch instruction, it will predict the target address or direction of the jump based on the branch history information in order to improve performance, and then execute the branch instruction opportunistically.

[0003] like Figure 1 As shown, in existing processor pipelines, after obtaining the branch jump address, this address is passed to the instruction fetch module. The instruction fetch module reads the instruction from the instruction cache and passes it to the instruction decode module, which then hands it over to the instruction execution module (also known as the execution backend). For branch prediction, if the branch prediction result is correct, the processor performance will be improved; conversely, if the branch prediction is incorrect, the processor pipeline needs to clear the incorrectly executed instruction and roll back to the execution state before the branch. This situation generally causes the pipeline to pause for several clock cycles.

[0004] Therefore, reducing the processor pipeline pause time after a branch prediction failure will help improve processor performance.

[0005] Related technologies offer the following optimization methods for branch prediction failures: First, using a hybrid coupled and decoupled front-end instruction fetch architecture to enable rapid CPU front-end startup; second, using a small-capacity Uops cache (micro-instruction cache) to store decoded instructions, further accelerating CPU front-end startup. However, in the above methods, for the decoupled instruction fetch front-end pipeline design, when branch prediction fails, according to existing schemes, the instruction will still need to undergo instruction fetching and decoding before being transmitted to the back-end, which will still consume several clock cycles. If all instruction streams are pre-decoded and placed in the micro-instruction cache, when the jump distance is short, the instruction will be directly read from the micro-instruction cache without having to read it from the L1 cache. When the jump distance is long, the micro-instruction cache may not contain the required instruction, and the instruction fetch front-end pipeline will still need to read the instruction from the L1 cache, which will still consume multiple clock cycles to complete the instruction fetch operation.

[0006] Therefore, it is necessary to propose a new method to address the problem of long processor pipeline pause times after branch prediction failure. Summary of the Invention

[0007] This invention provides a processor pipeline system, a pipeline fast recovery method, and related equipment, aiming to solve the problem of long pause times after existing processor pipeline branch prediction failures.

[0008] To solve the above-mentioned technical problems, in a first aspect, the present invention provides a processor pipeline system, the processor pipeline system comprising a branch prediction module, an instruction fetch module, a decoding module, a branch filtering and judgment module, a prefetch module, an L1 instruction cache module, an L0 instruction cache module, and an execution module;

[0009] The branch prediction module is used to perform branch prediction on the instructions input to the processor pipeline system to obtain multiple jump addresses, wherein the multiple jump addresses include one predicted jump address and at least one alternative jump address;

[0010] The instruction fetch module is used to send the predicted jump address and the alternative jump address to the L1 instruction cache module for instruction fetching, and send the returned instruction to the decoding module.

[0011] The L1 instruction cache module is used to read instructions from the predicted jump address and the alternative jump address, obtain the corresponding instructions, and return them to the instruction fetch module.

[0012] The decoding module is used to decode the instruction corresponding to the predicted jump address or the alternative jump address to obtain the corresponding decoding result, and according to the preset processing logic, send the decoding result of the instruction corresponding to the predicted jump address to the execution module, or send the decoding result of the instruction corresponding to the alternative jump address to the branch filtering and judgment module or the L0 instruction cache module.

[0013] The branch filtering and judgment module is used to perform branch filtering and judgment on the decoding result of the instruction corresponding to the candidate jump address output by the decoding module according to the preset filtering conditions. If the branch filtering and judgment module determines that the instruction corresponding to the decoding result is a branch instruction and the branch instruction needs to be pre-read, then the candidate jump address corresponding to the decoding result is sent to the pre-reading module.

[0014] The prefetch module is used to determine the branch address that the branch instruction needs to be prefetched based on the alternative jump address, and to pass the alternative jump address and the branch address to the L1 instruction cache module for reading the instruction;

[0015] The L0 instruction cache module is used to store the decoding results of the instructions output by the decoding module that correspond to the alternative jump addresses and the branch addresses;

[0016] The execution module is used to execute instructions based on the decoding result output by the decoding module, or to execute instructions based on the decoding result stored in the L0 instruction cache module.

[0017] Furthermore, the instruction fetching module is also used for:

[0018] The address of the next instruction to be executed is stored using an instruction counter.

[0019] Furthermore, the branch filtering and judgment module is specifically used to perform branch filtering and judgment on the decoding result corresponding to the candidate jump address output by the decoding module, and the preset filtering condition is:

[0020] Whether the decoding result of the candidate jump address involves reading or writing a preset register, wherein: if yes, the instruction corresponding to the decoding result is determined to be a branch instruction that needs to be pre-fetched; if no, the instruction corresponding to the decoding result is determined to be a branch instruction that does not need to be pre-fetched.

[0021] Furthermore, the L1 instruction cache module is also used for:

[0022] The module receives the alternative jump address and the branch address sent by the pre-fetch module, performs a read instruction, and sends the read instruction to the decoding module. When the L1 instruction cache module performs a read instruction on the alternative jump address and the branch address, it adds preset flag information to the read instruction according to the preset register.

[0023] Furthermore, based on the branch filtering judgment result of the branch filtering judgment module, if the instruction corresponding to the decoding result of the candidate jump address is a branch instruction, the decoding module is further configured to:

[0024] The instructions corresponding to the alternative jump addresses and the branch addresses are decoded, and the decoded results are sent to the L0 instruction cache module.

[0025] Furthermore, the L0 instruction cache module is also used for:

[0026] If the execution module discovers a branch prediction failure during instruction execution based on the decoding result corresponding to the predicted jump address, after the instruction counter of the instruction fetch module is redirected, the L0 instruction cache module queries the entries of the decoded results it stores according to the preset flag information. If the query result is not empty, then...

[0027] The decoding result is read out and sent to the execution module to execute the instruction, while the instruction counter of the instruction fetch module jumps to the next line.

[0028] Furthermore, when the L0 instruction cache module writes the decoding results corresponding to the candidate jump address and its branch address, it queries the stored entries. If the address of an existing entry overlaps with the candidate jump address or branch address, the decoding result is overwritten with the existing entry at the overlapping address and then written; otherwise, the writing is performed directly.

[0029] Secondly, the present invention also provides a pipeline fast recovery method, which is implemented based on the processor pipeline system described above, and includes the following steps:

[0030] The branch prediction module performs branch prediction on the instruction and obtains one predicted jump address and at least one alternative jump address.

[0031] The instruction fetching module sends the predicted jump address and the alternative jump address to the L1 instruction cache module for reading instructions, obtains the read instruction content, and then sends the predicted jump address, the alternative jump address and their respective read instruction content to the decoding module.

[0032] The decoding module decodes the read instruction content corresponding to the predicted jump address and sends it to the execution module to execute the instruction. At the same time, the decoding module decodes the read instruction content corresponding to the candidate jump address and sends it to the branch filtering judgment module for branch filtering. The pre-fetching module and the L1 instruction cache module process the read instruction content of the candidate jump address and its branch address that meet the preset filtering conditions and have preset flag information. Then, the decoding result obtained by decoding the read instruction content corresponding to the candidate jump address and its branch address that meet the preset filtering conditions and have preset flag information is written into the L0 instruction cache module.

[0033] If the execution module finds that branch prediction has failed during the execution of instructions based on the decoded content of the predicted jump address, it queries the decoding result with the preset flag information from the L0 instruction cache module and sends the decoding result to the execution module so that it executes instructions according to the decoding result stored in the L0 instruction cache module.

[0034] Thirdly, the present invention also provides a computer device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps in the pipeline fast recovery method as described in the above embodiments.

[0035] Fourthly, the present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the pipeline fast recovery method as described in any of the above embodiments.

[0036] The beneficial effects achieved by this invention lie in proposing a processor pipeline system that combines branch prediction filtering and L0 instruction cache. This system fetches instructions from the prediction result of branch prediction and multiple alternative results separately, and stores the alternative results in the L0 instruction cache. When a branch prediction fails, the pipeline can quickly fetch instructions from the L0 instruction cache. This design reduces the instruction fetch clock cycle and the pause time of the processor pipeline. At the same time, the system uses branch prediction filtering to select alternative results with a higher accuracy rate, improving the execution efficiency of the processor pipeline with a smaller L0 instruction cache capacity overhead and L1 instruction cache module read / write bandwidth overhead. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of the processing logic of a processor pipeline in existing technology;

[0038] Figure 2 This is a schematic diagram of the processor pipeline system provided in an embodiment of the present invention;

[0039] Figure 3 This is a flowchart of the steps of the rapid recovery method for pipelines provided in the embodiments of the present invention;

[0040] Figure 4 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0042] Please refer to Figure 2 , Figure 2 This is a schematic diagram of the structure of a processor pipeline system provided in an embodiment of the present invention. The processor pipeline system 100 includes a branch prediction module 101, an instruction fetch module 102, a decoding module 103, a branch filtering and judgment module 104, a prefetch module 105, an L1 instruction cache module 106, an L0 instruction cache module 107 (L0 cache), and an execution module 108.

[0043] The branch prediction module 101 is used to perform branch prediction on the instructions input to the processor pipeline system 100 to obtain multiple jump addresses, wherein the multiple jump addresses include one predicted jump address and at least one alternative jump address.

[0044] The instruction fetch module 102 is used to send the predicted jump address and the alternative jump address to the L1 instruction cache module 106 for instruction fetching, and send the returned instruction to the decoding module 103;

[0045] The L1 instruction cache module 106 is used to read instructions from the predicted jump address and the alternative jump address, obtain the corresponding instructions, and return them to the instruction fetch module 102;

[0046] The decoding module 103 is used to decode the instruction corresponding to the predicted jump address or the alternative jump address to obtain the decoding result, and according to the preset processing logic, send the decoding result of the instruction corresponding to the predicted jump address to the execution module 108, or send the decoding result of the instruction corresponding to the alternative jump address to the branch filtering and judgment module 107 or the L0 instruction cache module 107.

[0047] The branch filtering and judgment module 104 is used to perform branch filtering and judgment on the decoding result of the instruction corresponding to the candidate jump address output by the decoding module 103 according to the preset filtering conditions. If the branch filtering and judgment module 104 determines that the instruction corresponding to the decoding result is a branch instruction and the branch instruction needs to be pre-read, then the candidate jump address corresponding to the decoding result is sent to the pre-reading module 105.

[0048] The prefetch module 105 is used to determine the branch address that the branch instruction needs to be prefetched based on the alternative jump address, and to transmit the alternative jump address and the branch address to the L1 instruction cache module 106 for reading the instruction;

[0049] The L0 instruction cache module 107 is used to store the decoding results of the instructions output by the decoding module 103 that correspond to the alternative jump addresses and the branch addresses;

[0050] The execution module 108 is used to execute instructions according to the decoding result output by the decoding module 103, or according to the decoding result stored in the L0 instruction cache module 107.

[0051] The branch prediction module 101 (BPU) in this embodiment of the invention functions similarly to the branch predictor in a conventional processor pipeline, used to predict the execution path of a program in order to obtain potentially needed instructions in advance. The branch prediction module 101 determines whether an instruction is a branch instruction by looking up a table based on the instruction address. Simultaneously, it uses certain branch prediction logic to obtain two or more jump addresses for the branch instruction, one of which is the predicted jump address, and the others are candidate jump addresses. During implementation, the branch prediction logic used by the branch prediction module 101 can be selected according to actual needs, such as static branch prediction and dynamic branch prediction.

[0052] In this embodiment of the invention, the instruction fetch module 102 is responsible for retrieving instructions from the instruction cache and sending them to the instruction queue. Specifically, the instruction fetch module 102 is further used for:

[0053] The address of the next instruction to be executed is stored using an instruction counter.

[0054] The decoding module 103 does not directly send the decoding result of the candidate jump address obtained from the instruction fetch module 102 to the execution module 108, but instead uses it for the branch filtering process designed in this embodiment of the invention. The branch filtering judgment module 104 is specifically used to perform branch filtering judgment on the decoding result corresponding to the candidate jump address output by the decoding module 103, whereby the preset filtering condition is:

[0055] Whether the decoding result of the candidate jump address involves reading or writing a preset register, wherein: if yes, the instruction corresponding to the decoding result is determined to be a branch instruction that needs to be pre-fetched; if no, the instruction corresponding to the decoding result is determined to be a branch instruction that does not need to be pre-fetched.

[0056] In a real-world pipelined system, different branch instructions have multiple possible jump directions. For some branches, statistical tools can be used to identify which branches have a low prediction success rate. Therefore, for branches with a high prediction success rate, the pipelined system can predict the correct jump direction and target with a high probability, eliminating the need to prefetch alternative jump addresses and thus reducing resource waste. However, for branches with a low prediction success rate, the probability of prediction failure is high, and there is a certain probability that the instruction will jump to an alternative jump address during execution. In this case, prefetching provides performance benefits.

[0057] In this embodiment of the invention, branches with low branch prediction success rate are selected during the compilation process, and then the registers of these instructions are replaced with specific registers (i.e. preset registers) as prompt information for the processor pipeline system. When a branch is found to use a preset register, it can be determined that the branch contains branch instructions that need to be prefetched.

[0058] When the branch prediction module 101 outputs, it will output multiple candidate jump addresses depending on the branch prediction logic. These candidate jump addresses and the single predicted jump address may all be correct jump addresses. For the instruction fetch module 102 and instruction cache in the processor pipeline, it is very resource-intensive to process too many jump address read instructions and decode instructions at the same time, because among the multiple jump addresses, only one jump address needs to be executed correctly.

[0059] In this embodiment of the invention, the branch filtering and judgment module 104 is used to filter the decoding results of the branches, thereby filtering out the branch instructions with low branch prediction success rate. Furthermore, the pre-reading module 105 determines the address of the next branch of the candidate jump address and pre-reads the target data of the next branch, thereby reducing the number of candidate jump addresses, saving cache resources, and improving cache coverage through pre-reading.

[0060] The L1 instruction cache module 106 is also used for:

[0061] The module receives the alternative jump address and the branch address sent by the pre-read module 105, performs a read instruction, and sends the read instruction to the decoding module 103. When the L1 instruction cache module performs a read instruction on the alternative jump address and the branch address, it adds preset flag information to the read instruction according to the preset register.

[0062] Specifically, based on the output of the branch filtering judgment module 104, the pre-fetch module 105 determines the instruction address of the next branch and forwards it to the L1 instruction cache module 106 for instruction reading. At this stage, the selected candidate jump addresses are obtained. The instruction reading of the L1 instruction cache module 106 at this time is performed on the candidate jump address and the instruction address of its next branch. The difference between this and the initial instruction fetching process of the L1 instruction cache module 106 on the predicted jump address and the candidate jump address is that the instruction fetching at this time also adds preset flag information to the instruction to mark that the instruction read at this time is the result obtained after branch filtering processing.

[0063] Based on the branch filtering judgment result of the branch filtering judgment module 104, if the instruction corresponding to the decoding result of the candidate jump address is a branch instruction, the decoding module 103 is further configured to:

[0064] The instructions corresponding to the alternative jump addresses and the branch addresses are decoded, and the decoded results are sent to the L0 instruction cache module 107.

[0065] In fact, in the processor pipeline, it is normal logic for the decoding module 103 to send the decoding result corresponding to the predicted jump address to the execution module 108. This behavior does not conflict with the behavior of the L0 instruction cache module 107 writing the decoding result corresponding to the alternative jump address.

[0066] When the decoding module 103 sends the decoding results of the candidate jump addresses and the instructions corresponding to the branch addresses to the L0 instruction cache module 107 for storage, the execution module 108 executes the instructions according to the decoding results corresponding to the predicted jump addresses, and determines whether the branch prediction of the instructions is hit during this stage.

[0067] The L0 instruction cache module 107 is also used for:

[0068] If the execution module 108 detects a branch prediction failure during the execution of the instruction based on the decoded result corresponding to the predicted jump address, after the instruction counter of the instruction fetch module 102 is redirected, the L0 instruction cache module 107 queries the entries of the decoded result it stores according to the preset flag information. If the query result is not empty, then...

[0069] The decoding result is read out and sent to the execution module 108 to execute the instruction, while the instruction counter of the instruction fetch module 102 jumps to the next line.

[0070] When the L0 instruction cache module 107 writes the decoding results corresponding to the candidate jump address and its branch address, it queries the stored entries. If the address of an existing entry overlaps with the candidate jump address or branch address, the decoding result is overwritten with the existing entry with the overlapping address and written; otherwise, the writing is performed directly.

[0071] The L0 instruction cache module 107 is logically closer to the processor pipeline than the L1 instruction cache module 106. Compared to the L1 instruction cache module 106, the L0 instruction cache module 107 has faster read and write speeds and lower latency. Correspondingly, in actual processor design, the capacity of the L0 instruction cache module 107 will be much smaller than that of the L1 instruction cache module 106 or instruction cache modules at a later level. Therefore, the capacity overhead of the L0 instruction cache module 107 needs to be as small as possible.

[0072] In this embodiment of the invention, when the execution module 108 encounters a branch prediction failure (a branch prediction error) during the execution of instructions based on the decoding result corresponding to the predicted jump address, the processor pipeline needs to quickly fetch the next instruction. Before the next instruction is fetched, the processor pipeline will pause. However, this embodiment stores multiple alternative instruction decoding results that have been fetched and decoded and do not have duplicate address names (achieved by overwriting cache entries with overlapping addresses) in the L0 instruction cache module 107. By quickly reading the alternative jump addresses and their branch instruction decoding results from the L0 instruction cache module 107, the execution module 108 can quickly obtain the next instruction. Obviously, this design, based on the proximity of the L0 instruction cache module 107 to the execution module 108's jump location and its fast read / write speed, can greatly reduce the pause period of the front-end pipeline when the processor restarts after encountering a branch prediction error.

[0073] The beneficial effects achieved by this invention lie in proposing a processor pipeline system that combines branch prediction filtering and L0 instruction cache. This system fetches instructions from the prediction result of branch prediction and multiple alternative results separately, and stores the alternative results in the L0 instruction cache. When branch prediction fails, the pipeline can quickly fetch instructions from the L0 instruction cache. This design reduces the instruction fetch clock cycle and the pause time of the processor pipeline. At the same time, the system uses branch prediction filtering to select alternative results with higher accuracy, which can also reduce the instruction read frequency of the L1 instruction cache and reduce the capacity overhead of the L0 instruction cache, thereby improving the execution efficiency of the processor pipeline.

[0074] This invention also provides a method for rapid recovery of a production line; please refer to [reference needed]. Figure 3 , Figure 3 This is a flowchart illustrating the steps of a pipeline fast recovery method provided in this embodiment of the invention. The pipeline fast recovery method is implemented based on the processor pipeline system 100 described in the above embodiment, and includes the following steps:

[0075] S201. The branch prediction module 101 performs branch prediction on the instruction and obtains one predicted jump address and at least one alternative jump address.

[0076] S202, The predicted jump address and the alternative jump address are sent to the L1 instruction cache module 106 by the instruction fetch module 102 to read the instruction, obtain the read instruction content, and send the predicted jump address, the alternative jump address and their respective read instruction content to the decoding module 103.

[0077] S203. The decoding module 103 decodes the read instruction content corresponding to the predicted jump address and sends it to the execution module 108 to execute the instruction. At the same time, the decoding module 103 decodes the read instruction content corresponding to the candidate jump address and sends it to the branch filtering judgment module 104 for branch filtering. The pre-reading module 105 and the L1 instruction cache module 106 process the read instruction content of the candidate jump address and its branch address that meet the preset filtering conditions and have preset flag information. Then, the decoding result obtained by decoding the read instruction content corresponding to the candidate jump address and its branch address that meet the preset filtering conditions and have preset flag information is written into the L0 instruction cache module 107.

[0078] S204. If the execution module 108 finds that the branch prediction has failed during the execution of the instruction based on the decoded content of the predicted jump address, it queries the decoding result with the preset flag information from the L0 instruction cache module 107 and sends the decoding result to the execution module 108 so that it executes the instruction according to the decoding result stored in the L0 instruction cache module.

[0079] The pipeline fast recovery method briefly describes the execution flow of the processor pipeline system 100 in the above embodiments when encountering a branch prediction error.

[0080] It is understandable that, for scenarios where branch prediction executes normally, the processor pipeline system 100 proposed in this embodiment of the invention can still perform normal instruction fetching, decoding, and execution according to the logical order of instruction fetch module 102, decoding module 103, and execution module 108. The fetch results of other alternative predicted instructions generated by branch prediction module 101 and the branch instructions filtered by branch filtering module 104, after decoding, are stored in the L0 instruction cache module 107 according to their corresponding execution order. Since the processor system executes instructions in a periodic manner, the decoding results of each address entry stored in the L0 instruction cache module 107 can be adjusted according to the periodic characteristics of the program or instructions that the processor needs to process, depending on the actual requirements, to maximize the performance of the L0 instruction cache module 107 in handling pipeline stalls.

[0081] The steps in the pipeline fast recovery method are implemented based on the processor pipeline system 100 described in the above embodiment, and can achieve the same technical effect. Refer to the description in the above embodiment, and it will not be repeated here.

[0082] This invention also provides a computer device, please refer to... Figure 4 , Figure 4This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. The computer device 300 includes: a memory 302, a processor 301, and a computer program stored in the memory 302 and executable on the processor 301.

[0083] The processor 301 calls the computer program stored in the memory 302 to execute the steps in the pipeline fast recovery method provided in this embodiment of the invention. Please refer to... Figure 3 Specifically, it includes the following steps:

[0084] S201. The branch prediction module 101 performs branch prediction on the instruction and obtains one predicted jump address and at least one alternative jump address.

[0085] S202, The predicted jump address and the alternative jump address are sent to the L1 instruction cache module 106 by the instruction fetch module 102 to read the instruction, obtain the read instruction content, and send the predicted jump address, the alternative jump address and their respective read instruction content to the decoding module 103.

[0086] S203. The decoding module 103 decodes the read instruction content corresponding to the predicted jump address and sends it to the execution module 108 to execute the instruction. At the same time, the decoding module 103 decodes the read instruction content corresponding to the candidate jump address and sends it to the branch filtering judgment module 104 for branch filtering. The pre-reading module 105 and the L1 instruction cache module 106 process the read instruction content of the candidate jump address and its branch address that meet the preset filtering conditions and have preset flag information. Then, the decoding result obtained by decoding the read instruction content corresponding to the candidate jump address and its branch address that meet the preset filtering conditions and have preset flag information is written into the L0 instruction cache module 107.

[0087] S204. If the execution module 108 finds that the branch prediction has failed during the execution of the instruction based on the decoded content of the predicted jump address, it queries the decoding result with the preset flag information from the L0 instruction cache module 107 and sends the decoding result to the execution module 108 so that it executes the instruction according to the decoding result stored in the L0 instruction cache module.

[0088] The computer device 300 provided in this embodiment of the invention can implement the steps in the pipeline rapid recovery method as described in the above embodiments, and can achieve the same technical effect. Refer to the description in the above embodiments, which will not be repeated here.

[0089] This invention also provides a computer-readable storage medium storing a computer program. When executed by a processor, the computer program implements the various processes and steps in the pipeline fast recovery method provided in this invention and achieves the same technical effect. To avoid repetition, it will not be described again here.

[0090] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware (such as a mobile phone, computer, server, air conditioner, or network device, etc.). The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0091] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0092] The embodiments of the present invention have been described above with reference to the accompanying drawings. The disclosed embodiments are merely preferred embodiments of the present invention. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many equivalent changes in form without departing from the spirit and scope of the claims of the present invention, and all such changes are within the protection scope of the present invention.

Claims

1. A processor pipeline system, characterized in that, The processor pipeline system includes a branch prediction module, an instruction fetch module, a decoding module, a branch filtering and judgment module, a prefetch module, an L1 instruction cache module, an L0 instruction cache module, and an execution module; The branch prediction module is used to perform branch prediction on the instructions input to the processor pipeline system to obtain multiple jump addresses, wherein the multiple jump addresses include one predicted jump address and at least one alternative jump address; The instruction fetch module is used to send the predicted jump address and the alternative jump address to the L1 instruction cache module for instruction fetching, and send the returned instruction to the decoding module. The L1 instruction cache module is used to read instructions from the predicted jump address and the alternative jump address, obtain the corresponding instructions, and return them to the instruction fetch module. The decoding module is used to decode the instruction corresponding to the predicted jump address or the alternative jump address to obtain the corresponding decoding result, and according to the preset processing logic, send the decoding result of the instruction corresponding to the predicted jump address to the execution module, or send the decoding result of the instruction corresponding to the alternative jump address to the branch filtering and judgment module or the L0 instruction cache module. The branch filtering and judgment module is used to perform branch filtering and judgment on the decoding result of the instruction corresponding to the candidate jump address output by the decoding module according to the preset filtering conditions. If the branch filtering and judgment module determines that the instruction corresponding to the decoding result is a branch instruction and the branch instruction needs to be pre-read, then the candidate jump address corresponding to the decoding result is sent to the pre-reading module. The prefetch module is used to determine the branch address that the branch instruction needs to be prefetched based on the alternative jump address, and to pass the alternative jump address and the branch address to the L1 instruction cache module for reading the instruction; The L0 instruction cache module is used to store the decoding results of the instructions output by the decoding module that correspond to the alternative jump addresses and the branch addresses; The execution module is used to execute instructions according to the decoding result output by the decoding module, or to execute instructions according to the decoding result stored in the L0 instruction cache module; The L1 instruction cache module is further used for: The module receives the alternative jump address and the branch address sent by the pre-fetch module, performs a read instruction, and sends the read instruction to the decoding module. When the L1 instruction cache module performs a read instruction on the alternative jump address and the branch address, it adds preset flag information to the read instruction according to a preset register. The L0 instruction cache module is also used for: If the execution module discovers a branch prediction failure during instruction execution based on the decoding result corresponding to the predicted jump address, after the instruction counter of the instruction fetch module is redirected, the L0 instruction cache module queries the entries of the decoded results it stores according to the preset flag information. If the query result is not empty, then... The decoding result is read out and sent to the execution module to execute the instruction, while the instruction counter of the instruction fetch module jumps to the next line.

2. The processor pipeline system according to claim 1, characterized in that, The instruction fetching module is also used for: The address of the next instruction to be executed is stored using an instruction counter.

3. The processor pipeline system according to claim 2, characterized in that, The branch filtering and judgment module is specifically used to perform branch filtering and judgment on the decoding result corresponding to the candidate jump address output by the decoding module. The preset filtering condition is: Whether the decoding result of the candidate jump address involves reading or writing a preset register, wherein: if yes, the instruction corresponding to the decoding result is determined to be a branch instruction that needs to be pre-fetched; if no, the instruction corresponding to the decoding result is determined to be a branch instruction that does not need to be pre-fetched.

4. The processor pipeline system according to claim 3, characterized in that, Based on the branch filtering judgment result of the branch filtering judgment module, if the instruction corresponding to the decoding result of the candidate jump address is a branch instruction, the decoding module is further configured to: The instructions corresponding to the alternative jump addresses and the branch addresses are decoded, and the decoded results are sent to the L0 instruction cache module.

5. The processor pipeline system according to claim 4, characterized in that, When the L0 instruction cache module writes the decoding result corresponding to the candidate jump address and the branch address, it queries the stored entries. If the address of an existing entry overlaps with the candidate jump address or the branch address, the decoding result is overwritten with the existing entry at the overlapping address and then written; otherwise, the writing is performed directly.

6. A pipeline fast recovery method, said pipeline fast recovery method being implemented based on the processor pipeline system according to any one of claims 1-5, characterized in that, The rapid recovery method for the production line includes the following steps: The branch prediction module performs branch prediction on the instruction and obtains one predicted jump address and at least one alternative jump address. The instruction fetching module sends the predicted jump address and the alternative jump address to the L1 instruction cache module for reading instructions, obtains the read instruction content, and then sends the predicted jump address, the alternative jump address and their respective read instruction content to the decoding module. The decoding module decodes the read instruction content corresponding to the predicted jump address and sends it to the execution module to execute the instruction. At the same time, the decoding module decodes the read instruction content corresponding to the candidate jump address and sends it to the branch filtering judgment module for branch filtering. The pre-fetching module and the L1 instruction cache module process the read instruction content of the candidate jump address and its branch address that meet the preset filtering conditions and have preset flag information. Then, the decoding result obtained by decoding the read instruction content corresponding to the candidate jump address and its branch address that meet the preset filtering conditions and have preset flag information is written into the L0 instruction cache module. If the execution module finds that branch prediction has failed during the execution of instructions based on the decoded content of the predicted jump address, it queries the decoding result with the preset flag information from the L0 instruction cache module and sends the decoding result to the execution module so that it executes instructions according to the decoding result stored in the L0 instruction cache module.

7. A computer device, characterized in that, include: The memory, the processor, and the computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the steps of the pipeline fast recovery method as described in claim 6.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the pipeline fast recovery method as described in claim 6.

Images