Processor pipeline system, long distance jump processing method and related device

Abstract

This invention relates to a processor pipeline system, a long-distance jump processing method, and related equipment. The system is optimized for long-distance jump scenarios. During the instruction fetch stage, long-distance jump detection is designed for the jump address, and an L0 instruction cache is added to the cache system. When a long-distance jump occurs, the instruction fetch timing is optimized by simultaneously querying multiple levels of cache, thereby saving additional cache read time caused by potential cache misses. Furthermore, based on the fast read / write performance of the L0 instruction cache, this invention designs a pre-fetch instruction method, which can further reduce instruction read latency and optimize processor performance.

Description

Technical Field

[0001] This invention relates to the field of processor technology, and in particular to a processor pipeline system, a long-distance jump processing method, and related equipment. Background Technology

[0002] The program counter (PC) in modern processor systems stores the address of the next instruction to be executed. During program execution, the program counter always points to the address of the currently executing instruction. After each instruction is executed, the program counter is automatically updated to point to the next instruction. When encountering conditional branch or unconditional jump instructions, the value of the program counter is updated according to the instruction's requirements to guide the processor in fetching the new instruction sequence. Therefore, the program counter is a key component for implementing sequential program execution and branch jumps.

[0003] The instruction cache in a processor stores recently accessed or frequently accessed instructions. Since fetching instructions from main memory is much slower than executing them, the instruction cache, as a fast storage mechanism, reduces the number of times the processor accesses main memory, thereby improving overall execution efficiency. Multi-level cache structures (such as L1, L2, and L3 instruction caches) are common designs in modern processors. The L1 instruction cache is typically divided into an instruction cache and a data cache to support simultaneous instruction and data fetching operations.

[0004] However, when the processor jumps based on the program counter and attempts to fetch data from the instruction cache, but the requested data is not in the instruction cache, it must fetch the data from the slower main memory. This situation is called a cache miss. Cache misses generally occur due to capacity misses. When the amount of data accessed by the program exceeds the total capacity of the cache, some data blocks are replaced. If these replaced data blocks are accessed again later, a capacity miss occurs. The impact of cache misses on system performance is mainly reflected in the following two aspects:

[0005] Delay increases, such as Figure 1 As shown, cache misses cause the read instruction stage to sequentially query different levels of cache (including the stage of reading tag data and the stage of selecting hit data). When the required data is not found in the cache, the data still needs to be read from main memory, which is much slower than directly retrieving data from the cache, resulting in additional latency and performance degradation. Furthermore, frequent cache misses can prevent the processor from effectively utilizing the cache, thereby reducing the overall performance of the system.

[0006] When the processor executes a jump instruction, a long-distance program counter jump may occur. In this case, the program counter jumps to the code at the valid location and continues execution, and the change in the program counter value exceeds a threshold. Predictably, long-distance program counter jumps are more likely to trigger cache misses than short-distance jumps. Therefore, it is necessary to optimize for the performance degradation caused by cache misses in long-distance jump scenarios. Summary of the Invention

[0007] This invention provides a processor pipeline system, a long-distance jump processing method, and related equipment, aiming to solve the performance degradation problem of existing processor systems due to cache deficiency.

[0008] To solve the above-mentioned technical problems, in a first aspect, the present invention provides a processor pipeline system, the processor pipeline system comprising a program counter module, a branch prediction module, an instruction cache module, an instruction fetch module, a decoding module, and an execution module;

[0009] The program counter module is used to count the sequential instructions input to the processor pipeline system or the branch prediction instructions output by the branch prediction module, and points to the jump address corresponding to the sequential instruction or the branch prediction instruction.

[0010] The branch prediction module is used to perform branch prediction on the sequential instructions and output the address of the corresponding branch prediction instruction;

[0011] The instruction cache module includes a multi-level cache consisting of an L0 instruction cache, an L1 instruction cache, and an L2 instruction cache. The instruction cache module is used to store instruction data that the processor pipeline system needs to access through the multi-level cache.

[0012] The instruction extraction module is used to send a read instruction request to the instruction cache module according to the jump address, and receive the instruction data corresponding to the jump address returned by the instruction cache module; wherein, the instruction extraction module performs long-distance jump judgment according to the jump address, and sends read instruction requests to the multi-level caches in different instruction cache modules according to the judgment result;

[0013] The decoding module is used to decode the instruction data extracted by the instruction extraction module, obtain the decoding result, and send the decoding result to the execution module;

[0014] The execution module is used to execute instructions based on the decoding result.

[0015] Furthermore, the instruction extraction module includes a long-distance jump judgment unit, and the instruction extraction module is also used for:

[0016] Based on the long-distance jump determination unit, a long-distance jump determination is performed on the jump address, wherein:

[0017] If the jump address is a long-distance jump, the instruction extraction module simultaneously sends read instruction requests corresponding to the jump address to the L0 instruction cache, the L1 instruction cache, and the L2 instruction cache.

[0018] If the jump address is not a long-distance jump, the instruction extraction module simultaneously sends read instruction requests corresponding to the jump address to both the L0 instruction cache and the L1 instruction cache.

[0019] Furthermore, the instruction cache module is also used for:

[0020] After the instruction extraction module sends a read instruction request corresponding to the jump address to the L0 instruction cache, the L1 instruction cache and the L2 instruction cache, and the instruction cache module returns the corresponding instruction data to the instruction extraction module, the pre-read data corresponding to the instruction data is read through the L2 instruction cache, and the pre-read data is sent to the L0 instruction cache and the L1 instruction cache for storage.

[0021] Furthermore, the instruction cache module is also used for:

[0022] After the instruction extraction module sends a read instruction request corresponding to the jump address to the L0 instruction cache and the L1 instruction cache, and the instruction cache module returns the corresponding instruction data to the instruction extraction module, the pre-read data corresponding to the instruction data is read through the L1 instruction cache, and the pre-read data is sent to the L0 instruction cache for storage.

[0023] Furthermore, the instruction extraction module enables bidirectional data transmission with the L0 instruction cache, L1 instruction cache, and L2 instruction cache in the instruction cache module, respectively. The L1 instruction cache and L2 instruction cache enable bidirectional data transmission, while the L0 instruction cache and L1 instruction cache enable unidirectional data transmission from the L1 instruction cache to the L0 instruction cache.

[0024] Furthermore, the pre-read data is the downward multi-line data corresponding to the instruction data.

[0025] Secondly, the present invention also provides a long-distance jump processing method, which is implemented based on the processor pipeline system described above, and includes the following steps:

[0026] The jump address of the next instruction corresponding to the sequential instruction input into the processor pipeline system is obtained based on the program counter module, or the jump address corresponding to the branch prediction instruction output by the branch prediction module.

[0027] The instruction extraction module performs long-distance jump determination on the jump address, and issues read instruction requests to the multi-level caches in different instruction caching modules based on the determination result, wherein:

[0028] If the jump address is a long-distance jump, the instruction extraction module simultaneously sends read instruction requests to the L0 instruction cache, L1 instruction cache and L2 instruction cache;

[0029] If the jump address is not a long-distance jump, the instruction extraction module simultaneously sends a read instruction request to both the L0 instruction cache and the L1 instruction cache.

[0030] The instruction caching module reads the instruction from the multi-level cache according to the read instruction request issued by the instruction extraction module, and returns the corresponding instruction data to the instruction extraction module.

[0031] The decoding module decodes the instruction data obtained by the instruction extraction module to obtain the decoding result, and the execution module executes the instruction according to the decoding result.

[0032] Furthermore, the long-distance jump processing method also includes the following steps:

[0033] After the instruction extraction module sends a read instruction request corresponding to the jump address to the L0 instruction cache, the L1 instruction cache and the L2 instruction cache, and the instruction cache module returns the corresponding instruction data to the instruction extraction module, the pre-read data corresponding to the instruction data is read through the L2 instruction cache, and the pre-read data is sent to the L0 instruction cache and the L1 instruction cache for storage;

[0034] After the instruction extraction module sends a read instruction request corresponding to the jump address to the L0 instruction cache and the L1 instruction cache, and the instruction cache module returns the corresponding instruction data to the instruction extraction module, the pre-read data corresponding to the instruction data is read through the L1 instruction cache, and the pre-read data is sent to the L0 instruction cache for storage.

[0035] Thirdly, the present invention also provides a computer device, comprising: a memory, a processor, and a long-distance jump processing program stored in the memory and executable on the processor, wherein the processor executes the long-distance jump processing program to implement the steps of the long-distance jump processing method as described in the above embodiments.

[0036] Fourthly, the present invention also provides a computer-readable storage medium storing a long-distance jump processing program, wherein when the long-distance jump processing program is executed by a processor, it implements the steps of the long-distance jump processing method as described in the above embodiments.

[0037] The beneficial effects achieved by this invention lie in proposing a processor pipeline system optimized for long-distance jump scenarios. This system designs long-distance jump detection for jump addresses during the instruction fetch stage and adds an L0 instruction cache to the cache system. When a long-distance jump occurs, the instruction fetch timing is optimized by simultaneously querying multiple levels of cache, thereby saving additional cache read time caused by possible cache misses. Furthermore, this invention designs a prefetch instruction method based on the fast read and write performance of the L0 instruction cache, which can further reduce instruction read latency and optimize processor performance. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of the multi-level cache read timing in the processor pipeline of existing technology;

[0039] Figure 2 This is a schematic diagram of the logical structure of the processor pipeline system provided in an embodiment of the present invention;

[0040] Figure 3 This is a schematic diagram of the multi-level cache read timing of the processor pipeline system provided in an embodiment of the present invention;

[0041] Figure 4 This is a flowchart of the steps of the long-distance jump processing method provided in the embodiments of the present invention;

[0042] Figure 5 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0044] Please refer to Figure 2 , Figure 2 This is a schematic diagram of the logical structure of a processor pipeline system provided in an embodiment of the present invention. The processor pipeline system 100 includes a program counter module 101, a branch prediction module 102, an instruction cache module 103, an instruction fetch module 104, a decoding module 105, and an execution module 106.

[0045] The program counter module 101 is used to count the sequential instructions input to the processor pipeline system 100 or the branch prediction instructions output by the branch prediction module 102, and points to the jump address corresponding to the sequential instruction or the branch prediction instruction.

[0046] The branch prediction module 102 (BPU) is used to perform branch prediction on the sequential instructions and output the address of the corresponding branch prediction instruction;

[0047] The instruction cache module 103 includes a multi-level cache consisting of an L0 instruction cache, an L1 instruction cache, and an L2 instruction cache. The instruction cache module 103 is used to store instruction data that the processor pipeline system 100 needs to access through the multi-level cache.

[0048] The instruction extraction module 104 is used to send a read instruction request to the instruction cache module 103 according to the jump address, and receive the instruction data corresponding to the jump address returned by the instruction cache module 103. The instruction extraction module 104 performs long-distance jump judgment according to the jump address, and sends read instruction requests to the multi-level caches in different instruction cache modules 103 according to the judgment result.

[0049] The decoding module 105 is used to decode the instruction data extracted by the instruction extraction module 104 to obtain a decoding result, and send the decoding result to the execution module 106;

[0050] The execution module 106 is used to execute instructions based on the decoding result.

[0051] The branch prediction module 102 in this embodiment of the invention functions similarly to the branch predictor in a conventional processor pipeline, used to predict the execution path of a program in order to obtain potentially needed instructions in advance. The branch prediction module 102 determines whether an instruction is a branch instruction by looking up a table based on the instruction address, and simultaneously obtains the jump address of the branch instruction by looking up the table. During implementation, the branch prediction logic used by the branch prediction module 102 can be selected according to actual needs, such as static branch prediction and dynamic branch prediction.

[0052] Specifically, in this embodiment of the invention, the instruction extraction module 104 includes a long-distance jump judgment unit 1041, and the instruction extraction module 104 is further used for:

[0053] Based on the long-distance jump determination unit 1041, a long-distance jump determination is performed on the jump address, wherein:

[0054] If the jump address is a long-distance jump, the instruction extraction module simultaneously sends read instruction requests corresponding to the jump address to the L0 instruction cache, the L1 instruction cache, and the L2 instruction cache.

[0055] If the jump address is not a long-distance jump, the instruction extraction module simultaneously sends read instruction requests corresponding to the jump address to both the L0 instruction cache and the L1 instruction cache.

[0056] The long-distance jump judgment unit 1041 can be implemented in software. For the judgment of long-distance jump, the value of the program counter module 101 can be compared during the implementation process. Since long-distance jump and short-distance jump are relative concepts, the threshold of short-distance jump can also be set according to the actual size of the instruction cache during the implementation process. The long-distance jump judgment unit 1041 can realize the judgment of long-distance jump by detecting the size of the threshold.

[0057] During long-distance jumps, due to the large jump address span, the probability of data loss is relatively higher according to the principle of locality of reference. In contrast, during short-distance jumps, the required instruction data is more likely to be hit in the earlier instruction cache. Therefore, L2 instruction cache request and lookup processing is not performed during short-distance jumps, thereby optimizing the bandwidth overhead of the lookup cache and achieving the effect of reducing processor power consumption.

[0058] In the above judgment process, the difference in handling long-distance jumps lies in which multi-level caches are simultaneously accessed for read instructions. However, there are differences in read performance between multi-level caches. Therefore, in this embodiment of the invention, based on the above processing logic, the read instruction timing diagram using L1 instruction cache and L2 instruction cache as examples is shown below. Figure 3 As shown, when simultaneously querying both the L1 and L2 instruction caches, the instruction read timing is optimized. Within the same clock cycle, if a cache miss occurs in the L1 instruction cache, the L2 instruction cache can also quickly enter the data selection phase. Compared to existing instruction cache timing (such as...), this is significantly improved. Figure 1 As shown in the figure, the latency caused by cache misses is greatly reduced.

[0059] Unlike existing processor pipelines, this embodiment of the invention incorporates an L0 instruction cache in the instruction cache module 103. This is to enable simultaneous lookups across multiple cache levels, such as... Figure 2As shown, the instruction extraction module implements bidirectional data transmission with the L0 instruction cache, the L1 instruction cache and the L2 instruction cache in the instruction cache module, respectively;

[0060] Due to the significant differences in read performance between different levels of cache, the L0 instruction cache cannot directly transfer data with other slower instruction caches (in this embodiment, only the L2 instruction cache is used, but depending on the processor's design requirements, it may also include L3, L4, etc.). Therefore, in the design of the instruction cache module 103 in this embodiment, bidirectional data transfer is implemented between the L1 instruction cache and the L2 instruction cache, and unidirectional data transfer is implemented between the L0 instruction cache and the L1 instruction cache.

[0061] Furthermore, in order to maximize the performance of the L0 instruction cache in handling cache misses, the instruction cache module 103 is further configured to:

[0062] After the instruction extraction module 104 sends a read instruction request corresponding to the jump address to the L0 instruction cache, the L1 instruction cache and the L2 instruction cache, and the instruction cache module 103 returns the corresponding instruction data to the instruction extraction module 104, the pre-read data corresponding to the instruction data is read through the L2 instruction cache, and the pre-read data is sent to the L0 instruction cache and the L1 instruction cache for storage.

[0063] In the above scenario, the L2 instruction cache reads the pre-read data corresponding to the instruction data, sends the pre-read data to the L1 instruction cache, and then sends it to the L0 instruction cache for storage via a transmission channel connected to the L1 instruction cache. Through this design, the L0 instruction cache can pre-store instruction data that may be used by subsequent instructions, and in the subsequent instruction read stage (compared to the L1 and L2 instruction caches), it prioritizes returning the instruction data to the instruction extraction module 104, thereby optimizing instruction read performance.

[0064] Preferably, the prefetched data is the downward multi-line data corresponding to the instruction data. Due to the spatial locality between instructions, when prefetching instruction data in the instruction cache, an appropriate amount of subsequent data can be prefetched and stored according to the size of the L0 instruction cache, thereby optimizing the performance over multiple clock cycles.

[0065] The instruction cache module is also used for:

[0066] After the instruction extraction module 104 sends a read instruction request corresponding to the jump address to the L0 instruction cache and the L1 instruction cache, and the instruction cache module 103 returns the corresponding instruction data to the instruction extraction module 104, the pre-read data corresponding to the instruction data is read through the L1 instruction cache, and the pre-read data is sent to the L0 instruction cache for storage.

[0067] Correspondingly, even if no long-distance jump occurs during the instruction read phase, this embodiment of the invention also uses the L1 instruction cache to pre-read instruction data when the L0 instruction cache is added, thereby optimizing the performance of the processor pipeline system 100 during the instruction read phase.

[0068] The beneficial effects achieved by this invention lie in proposing a processor pipeline system optimized for long-distance jump scenarios. This system designs long-distance jump detection for jump addresses during the instruction fetch stage and adds an L0 instruction cache to the cache system. When a long-distance jump occurs, the instruction fetch timing is optimized by simultaneously querying multiple levels of cache, thereby saving additional cache read time caused by possible cache misses. Furthermore, this invention designs a prefetch instruction method based on the fast read and write performance of the L0 instruction cache, which can further reduce instruction read latency and optimize processor performance.

[0069] This invention also provides a long-distance jump processing method, which is implemented based on the processor pipeline system described above. Please refer to [link / reference]. Figure 4 , Figure 4 This is a flowchart illustrating the steps of a long-distance jump processing method provided in an embodiment of the present invention. The long-distance jump processing method includes the following steps:

[0070] S201. Obtain the jump address of the next instruction corresponding to the sequential instruction input into the processor pipeline system based on the program counter module, or the jump address corresponding to the branch prediction instruction output by the branch prediction module.

[0071] S202. The instruction extraction module performs long-distance jump judgment on the jump address, and issues read instruction requests to the multi-level caches in different instruction cache modules according to the judgment result, wherein:

[0072] S2021. If the jump address is a long-distance jump, the instruction extraction module simultaneously sends read instruction requests to the L0 instruction cache, L1 instruction cache and L2 instruction cache.

[0073] S2022. If the jump address is not a long-distance jump, the instruction extraction module simultaneously sends a read instruction request to both the L0 instruction cache and the L1 instruction cache.

[0074] S203. The instruction cache module reads the instruction from the multi-level cache according to the read instruction request issued by the instruction extraction module, and returns the corresponding instruction data to the instruction extraction module.

[0075] S204. The instruction data obtained by the instruction extraction module is decoded by the decoding module to obtain the decoding result, and the execution module executes the instruction according to the decoding result.

[0076] Preferably, the long-distance jump processing method further includes the following steps:

[0077] S2051, after the instruction extraction module sends a read instruction request corresponding to the jump address to the L0 instruction cache, the L1 instruction cache and the L2 instruction cache, and the instruction cache module returns the corresponding instruction data to the instruction extraction module, the pre-read data corresponding to the instruction data is read through the L2 instruction cache, and the pre-read data is sent to the L0 instruction cache and the L1 instruction cache for storage;

[0078] S2052, after the instruction extraction module sends a read instruction request corresponding to the jump address to the L0 instruction cache and the L1 instruction cache, and the instruction cache module returns the corresponding instruction data to the instruction extraction module, the pre-read data corresponding to the instruction data is read through the L1 instruction cache, and the pre-read data is sent to the L0 instruction cache for storage.

[0079] The steps in the long-distance jump processing method are implemented based on the processor pipeline system 100 described in the above embodiment, and can achieve the same technical effect. Refer to the description in the above embodiment, and it will not be repeated here.

[0080] This invention also provides a computer device, please refer to... Figure 5 , Figure 5 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. The computer device 300 includes: a memory 302, a processor 301, and a long-distance jump processing program stored in the memory 302 and capable of running on the processor 301.

[0081] The processor 301 calls the long-distance jump processing program stored in the memory 302 and executes the steps in the long-distance jump processing method provided in this embodiment of the invention. Please refer to... Figure 4 Specifically, it includes the following steps:

[0082] S201. Obtain the jump address of the next instruction corresponding to the sequential instruction input into the processor pipeline system based on the program counter module, or the jump address corresponding to the branch prediction instruction output by the branch prediction module.

[0083] S202. The instruction extraction module performs long-distance jump judgment on the jump address, and issues read instruction requests to the multi-level caches in different instruction cache modules according to the judgment result, wherein:

[0084] S2021. If the jump address is a long-distance jump, the instruction extraction module simultaneously sends read instruction requests to the L0 instruction cache, L1 instruction cache and L2 instruction cache.

[0085] S2022. If the jump address is not a long-distance jump, the instruction extraction module simultaneously sends a read instruction request to both the L0 instruction cache and the L1 instruction cache.

[0086] S203. The instruction cache module reads the instruction from the multi-level cache according to the read instruction request issued by the instruction extraction module, and returns the corresponding instruction data to the instruction extraction module.

[0087] S204. The instruction data obtained by the instruction extraction module is decoded by the decoding module to obtain the decoding result, and the execution module executes the instruction according to the decoding result.

[0088] The long-distance jump processing method also includes the following steps:

[0089] S2051, after the instruction extraction module sends a read instruction request corresponding to the jump address to the L0 instruction cache, the L1 instruction cache and the L2 instruction cache, and the instruction cache module returns the corresponding instruction data to the instruction extraction module, the pre-read data corresponding to the instruction data is read through the L2 instruction cache, and the pre-read data is sent to the L0 instruction cache and the L1 instruction cache for storage;

[0090] S2052, after the instruction extraction module sends a read instruction request corresponding to the jump address to the L0 instruction cache and the L1 instruction cache, and the instruction cache module returns the corresponding instruction data to the instruction extraction module, the pre-read data corresponding to the instruction data is read through the L1 instruction cache, and the pre-read data is sent to the L0 instruction cache for storage.

[0091] The computer device 300 provided in this embodiment of the invention can implement the steps in the long-distance jump processing method in the above embodiments and can achieve the same technical effect. Refer to the description in the above embodiments, which will not be repeated here.

[0092] This invention also provides a computer-readable storage medium storing a long-distance jump processing program. When executed by a processor, the long-distance jump processing program implements the various processes and steps in the method provided in this invention and achieves the same technical effect. To avoid repetition, it will not be described again here.

[0093] Those skilled in the art will understand that implementing all or part of the processes in the above embodiments can be accomplished by instructing related hardware (such as mobile phones, computers, servers, air conditioners, or network devices, etc.) through long-distance jump processing programs. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0094] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0095] The embodiments of the present invention have been described above with reference to the accompanying drawings. The disclosed embodiments are merely preferred embodiments of the present invention. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many equivalent changes in form without departing from the spirit and scope of the claims of the present invention, and all such changes are within the protection scope of the present invention.

Claims

1. A processor pipeline system, characterized in that, The processor pipeline system includes a program counter module, a branch prediction module, an instruction cache module, an instruction fetch module, a decoding module, and an execution module; The program counter module is used to count the sequential instructions input to the processor pipeline system, or the branch prediction instructions output by the branch prediction module, and points to the jump address corresponding to the sequential instruction or the branch prediction instruction. The branch prediction module is used to perform branch prediction on the sequential instructions and output the jump address of the corresponding branch prediction instruction; The instruction cache module includes a multi-level cache consisting of an L0 instruction cache, an L1 instruction cache, and an L2 instruction cache. The instruction cache module is used to store instruction data that the processor pipeline system needs to access through the multi-level cache. The instruction extraction module is used to send a read instruction request to the instruction cache module according to the jump address, and receive the instruction data corresponding to the jump address returned by the instruction cache module; wherein, the instruction extraction module performs long-distance jump judgment according to the jump address, and sends read instruction requests to the multi-level caches in different instruction cache modules according to the judgment result; The decoding module is used to decode the instruction data extracted by the instruction extraction module, obtain the decoding result, and send the decoding result to the execution module; The execution module is used to execute instructions based on the decoding result; The instruction extraction module includes a long-distance jump judgment unit, and the instruction extraction module is further used for: Based on the long-distance jump determination unit, a long-distance jump determination is performed on the jump address, wherein issuing read instruction requests to the multi-level caches in different instruction cache modules according to the determination result includes: If the jump address is a long-distance jump, the instruction extraction module simultaneously sends read instruction requests corresponding to the jump address to the L0 instruction cache, the L1 instruction cache, and the L2 instruction cache. If the jump address is not a long-distance jump, the instruction extraction module simultaneously sends a read instruction request corresponding to the jump address to both the L0 instruction cache and the L1 instruction cache. The instruction cache module is also used for: After the instruction extraction module simultaneously sends read instruction requests corresponding to the jump address to the L0 instruction cache, the L1 instruction cache, and the L2 instruction cache, and the instruction cache module returns the corresponding instruction data to the instruction extraction module, the pre-read data corresponding to the instruction data is read through the L2 instruction cache, and the pre-read data is sent to the L0 instruction cache and the L1 instruction cache for storage.

2. The processor pipeline system according to claim 1, characterized in that, The instruction cache module is also used for: After the instruction extraction module simultaneously sends a read instruction request corresponding to the jump address to both the L0 instruction cache and the L1 instruction cache, and the instruction cache module returns the corresponding instruction data to the instruction extraction module, the pre-read data corresponding to the instruction data is read through the L1 instruction cache, and the pre-read data is sent to the L0 instruction cache for storage.

3. The processor pipeline system according to claim 1, characterized in that, The instruction extraction module implements bidirectional data transmission with the L0 instruction cache, L1 instruction cache and L2 instruction cache in the instruction cache module respectively. The L1 instruction cache and L2 instruction cache implement bidirectional data transmission. The L0 instruction cache and L1 instruction cache implement unidirectional data transmission from the L1 instruction cache to the L0 instruction cache.

4. The processor pipeline system according to claim 1 or 2, characterized in that, The pre-read data is the downward multi-line data corresponding to the instruction data.

5. A long-distance jump processing method, wherein the long-distance jump processing method is implemented based on the processor pipeline system according to any one of claims 1-4, characterized in that, The long-distance jump processing method includes the following steps: The jump address of the next instruction corresponding to the sequential instruction input into the processor pipeline system is obtained based on the program counter module, or the jump address corresponding to the branch prediction instruction output by the branch prediction module. The instruction extraction module performs long-distance jump determination on the jump address and issues read instruction requests to the multi-level caches in different instruction caching modules based on the determination result, including: If the jump address is a long-distance jump, the instruction extraction module simultaneously sends read instruction requests to the L0 instruction cache, L1 instruction cache and L2 instruction cache; If the jump address is not a long-distance jump, the instruction extraction module simultaneously sends a read instruction request to both the L0 instruction cache and the L1 instruction cache. The instruction caching module reads the instruction from the multi-level cache according to the read instruction request issued by the instruction extraction module, and returns the corresponding instruction data to the instruction extraction module. The instruction data obtained by the instruction extraction module is decoded by the decoding module to obtain the decoding result, and the execution module executes the instruction according to the decoding result; The long-distance jump processing method also includes the following steps: After the instruction extraction module simultaneously sends read instruction requests corresponding to the jump address to the L0 instruction cache, the L1 instruction cache, and the L2 instruction cache, and the instruction cache module returns the corresponding instruction data to the instruction extraction module, the pre-read data corresponding to the instruction data is read through the L2 instruction cache, and the pre-read data is sent to the L0 instruction cache and the L1 instruction cache for storage.

6. The long-distance jump processing method according to claim 5, characterized in that, The long-distance jump processing method also includes the following steps: After the instruction extraction module simultaneously sends a read instruction request corresponding to the jump address to both the L0 instruction cache and the L1 instruction cache, and the instruction cache module returns the corresponding instruction data to the instruction extraction module, the pre-read data corresponding to the instruction data is read through the L1 instruction cache, and the pre-read data is sent to the L0 instruction cache for storage.

7. A computer device, characterized in that, include: The system includes a memory, a processor, and a long-distance jump processing program stored in the memory and executable on the processor, wherein the processor, when executing the long-distance jump processing program, implements the steps of the long-distance jump processing method as described in any one of claims 5-6.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a long-distance jump processing program, which, when executed by a processor, implements the steps of the long-distance jump processing method as described in any one of claims 5-6.

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