FPGA-based module prototype verification apparatus, method, device and storage medium

Abstract

Embodiments of the present application disclose an FPGA-based module prototype verification device, method, equipment and storage medium. The device comprises an FPGA board, an FMC daughter card and a host computer. The FPGA board comprises a signal generator, a module to be tested, a physical layer module, a second preset interface module, a frame decoding module and a cache module. The module to be tested comprises a digital down converter module and a first preset interface module. The FMC daughter card is connected with the FPGA board, and is used to provide a clock source required by a data channel of the FPGA board. The host computer is connected with the FPGA board, and is used to send a preset instruction to the FPGA board to control the FPGA board to test the module to be tested. Thus, full-process automation from signal generation to acquisition and analysis is achieved, and the accuracy and economy of chip testing are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip testing technical field, in particular to a module prototype verification device, method and equipment based on FPGA and a storage medium. BACKGROUND

[0002] In a high-speed high-precision ADC (Analog to Digital Converter) chip, a DDC (Digital Down-Converter) module and a JESD204B high-speed serial interface module have become common technical modules. At present, in the related art, ADC chip testing can be performed only after the chip manufacturing process is completed, which is slow in feedback to the chip design process, high in technical cost, and needs to rely on manual experience for performance analysis after each test, resulting in poor chip testing accuracy and economy. SUMMARY

[0003] To solve the above technical problems, the embodiments of the present application provide a module prototype verification device, method, equipment and storage medium based on FPGA, so as to improve the accuracy and efficiency of chip testing.

[0004] According to an aspect of an embodiment of the present application, a module prototype verification device based on FPGA is provided, comprising: a to-be-tested module connected with an FPGA board card, the to-be-tested module comprising a digital down-converter module and a first preset interface module;

[0005] an FPGA board card comprising a signal generator, a physical layer module, a second preset interface module, a de-framing module and a cache module; the signal generator is configured to output a preset signal; the physical layer module is configured as a physical layer of the first preset interface module, and is configured to convert a parallel signal output by the to-be-tested module into a serial signal and send the serial signal to the physical layer module; the physical layer module is further configured as a physical layer of the second preset interface module, and is configured to receive the serial signal and convert the serial signal into a parallel signal and send the parallel signal to the second preset interface module; the second preset interface module is configured to process the received parallel signal to obtain a to-be-de-framed signal; the de-framing module is configured to restore the to-be-de-framed signal into an original sampling signal; and the cache module is configured to cache the original sampling signal.

[0006] an FMC sub-card connected with the FPGA board card, the FMC sub-card being configured to provide a clock source required by a data path of the FPGA board card;

[0007] An upper computer is connected with the FPGA board card, and the upper computer is configured to send a preset instruction to the FPGA board card to control the FPGA board card to test the to-be-tested module.

[0008] In some embodiments, the FPGA board card further comprises a clock management module, and the clock management module comprises a first phase-locked loop, a second phase-locked loop, a first clock buffer, a second clock buffer and an integrated circuit bus master module.

[0009] The integrated circuit bus master module is configured to configure a crystal oscillator of the FMC sub-card, so that the FMC sub-card provides a clock source to the FPGA board card.

[0010] One end of the first phase-locked loop is connected with a system clock source, and the other end of the first phase-locked loop is connected with the physical layer module and the microprocessor core; the first phase-locked loop is configured to generate a dynamic reconfiguration clock of the physical layer module and a bus clock of the microprocessor core according to a system clock output by the system clock source.

[0011] One end of the first clock buffer is connected with the FMC sub-card, and the other end of the first clock buffer is connected with the physical layer module; the first clock buffer is configured to buffer an external clock output by the FMC sub-card and output a reference clock to the physical layer module.

[0012] One end of the second clock buffer is connected with the FMC sub-card, and the other end of the second clock buffer is connected with an input end of the second phase-locked loop; an output end of the second phase-locked loop is connected with the digital down converter module and the first preset interface module; the second clock buffer is configured to buffer an external clock output by the FMC sub-card, output a preset clock to the digital down converter module through the output end of the second phase-locked loop, and output a sampling clock and a character clock to the first preset interface module.

[0013] In some embodiments, the signal generator comprises a digital controlled oscillator configured to configure a frequency and a phase through a preset configuration interface to output a single-tone signal with a preset bit number.

[0014] In some embodiments, a system synchronization reference signal generation module is arranged between the first preset interface module and the second preset interface module, and the system synchronization reference signal generation module is configured to generate a system synchronization reference signal and send the system synchronization reference signal to the first preset interface module and the second preset interface module.

[0015] In some embodiments, the de-framing module is configured to restore the to-be-de-framed signal output by the second preset interface module to an original sampling signal according to a first preset configuration parameter.

[0016] The first preset configuration parameter includes a number of effective digital-to-analog conversions in each frame of data, a number of signal samples of each signal converter in each frame of data, a number of bits per sample, a number of transmission links, and a number of transmission bytes.

[0017] In some embodiments, the FPGA board card further includes a block random access memory control module connected to an output end of the de-framing module and connected to an output end of the digital down converter module; the block random access memory control module is configured to perform down-sampling on data written into the cache module according to a second preset configuration parameter; the second preset configuration parameter includes an output down-sampling configuration parameter of the digital down converter module.

[0018] In some embodiments, the host computer is further configured to perform volatile parameter configuration on the FPGA board card and the module to be tested according to volatile configuration parameters, and perform signal reading and analysis in the cache module; and / or,

[0019] performing non-volatile parameter configuration on the FPGA board card and the module to be tested according to non-volatile configuration parameters;

[0020] The volatile configuration parameters include a signal frequency and a phase output by the signal generator module and a corresponding configuration parameter of the digital down converter module; the non-volatile configuration parameters include a framing parameter corresponding to the first preset interface module, a clock configuration parameter corresponding to the FMC sub-card, a clock configuration parameter corresponding to the module to be tested, and an interface configuration parameter corresponding to the physical layer module.

[0021] According to an aspect of an embodiment of the present application, a module prototype verification method of a module prototype verification device based on an FPGA is provided, including: obtaining volatile configuration parameters and non-volatile configuration parameters; the volatile configuration parameters include a signal frequency and a phase output by the signal generator module and a corresponding configuration parameter of the digital down converter module; the non-volatile configuration parameters include a framing parameter and a link establishment configuration parameter corresponding to the first preset interface module, a clock configuration parameter corresponding to the FMC sub-card, a clock configuration parameter corresponding to the module to be tested, and an interface configuration parameter corresponding to the physical layer module;

[0022] write the volatile configuration parameters and the non-volatile configuration parameters into the FPGA board card, and run according to a preset number of times to control the FPGA board card to test the module to be tested.

[0023] According to an aspect of an embodiment of the present application, an electronic device is provided, comprising: one or more processors; and a storage device for storing one or more programs, which, when executed by the one or more processors, cause the electronic device to implement the module prototype verification method of the FPGA-based module prototype verification apparatus as described above.

[0024] According to an aspect of an embodiment of the present application, a computer-readable storage medium is provided, having stored thereon computer-readable instructions, which, when executed by a processor of a computer, cause the computer to perform the module prototype verification method of the FPGA-based module prototype verification apparatus as described above.

[0025] In the technical solutions provided by the embodiments of the present application, on one hand, by integrating each module required for testing the to-be-tested module onto the FPGA board card, a prototype verification platform is built on the FPGA board card, and the to-be-tested module is tested through the FPGA board card, so that design defects and potential problems can be found in advance, and manufacturing risks and costs can be reduced; on the other hand, the input signal and data transmission in the actual working environment are simulated by the signal generator embedded in the FPGA board card, so that the to-be-tested module can be tested in real time and analyzed in performance, thereby realizing full-process automation of signal generation, collection and analysis, without relying on manual experience, and improving the accuracy and economy of chip testing.

[0026] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0027] The drawings incorporated into the specification and forming a part thereof, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the application. It is clear that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those of ordinary skill in the art without creative labor on the basis of these drawings. In the drawings:

[0028] Figure 1 is a result schematic diagram of the FPGA-based module prototype verification apparatus according to an exemplary embodiment of the present application;

[0029] Figure 2 is an architecture schematic diagram of a clock management module according to an exemplary embodiment of the present application;

[0030] Figure 3 is a flow schematic diagram of parameter configuration and data analysis according to an exemplary embodiment of the present application;

[0031] Figure 4is a flow chart of a module prototype verification method of an FPGA-based module prototype verification device shown in an example embodiment of the present application;

[0032] Figure 5 is an application diagram of a method for separately testing a digital down converter module in a module to be tested, shown in an example embodiment of the present application;

[0033] Figure 6 is a flow chart of a method for separately testing a first preset interface module in a module to be tested, shown in an example embodiment of the present application;

[0034] Figure 7 is a structural diagram of a verification device, shown in an example embodiment of the present application;

[0035] Figure 8 shows a structural diagram of a computer system of an electronic device suitable for implementing embodiments of the present application. DETAILED DESCRIPTION

[0036] The example embodiments will be described in detail herein with reference to the accompanying drawings. In the following description, the same numbers refer to the same or similar elements unless otherwise represented. The implementations described in the following example embodiments do not represent all implementations consistent with the present application. Instead, they only represent examples of apparatuses and methods consistent with some aspects of the present application, as detailed in the appended claims.

[0037] The block diagrams shown in the accompanying drawings are merely functional entities, and do not necessarily correspond to physically independent entities. That is, the functional entities can be implemented in the form of application programs, or in one or more hardware modules or integrated circuits, or in different models and / or processor devices and / or microcontroller devices.

[0038] The flow charts shown in the accompanying drawings are merely exemplary illustrations, and do not necessarily include all contents and operations / steps, nor are they necessarily executed in the order described. For example, some operations / steps can be further divided, and some operations / steps can be combined or partially combined, so that the actual execution order can be changed according to actual conditions.

[0039] It should be noted that "multiple" as mentioned in the present application means two or more. The association relationship of "and / or" associated objects indicates that there can be three relationships, for example, A and / or B can represent the three cases of A alone, A and B together, and B alone. The character " / " generally represents an "or" relationship between the associated objects before and after it.

[0040] To facilitate understanding of the FPGA-based module prototype verification device provided in the embodiments of the present application, the module prototype verification scenario is introduced below in conjunction with an implementation environment shown in Figure 1 The implementation environment is specifically a FPGA-based module prototype verification device, as shown in Figure 1 The FPGA-based module prototype verification device includes an FPGA board card 110, an FMC (FPGA Mizzanine Card) daughter card 120, and a host computer 130. The FPGA board card 110 includes a signal generator 111, a module to be tested 112, a physical layer module 113, a second preset interface module 114, a frame demodulation module 115, and a cache module 116. The module to be tested 112 includes a digital down converter module 112a and a first preset interface module 112b. The FMC daughter card 120 is connected to the FPGA board card 110, and is configured to provide a clock source required by a data path of the FPGA board card 110. The host computer 130 is connected to the FPGA board card 110, and is configured to send a preset instruction to the FPGA board card 110 to control the FPGA board card 110 to test the module to be tested 112.

[0041] The FPGA board card 110 includes the signal generator 111, the module to be tested 112, the physical layer module 113, the second preset interface module 114, the frame demodulation module 115, and the cache module 116. In some embodiments, the FPGA board card 110 is obtained by the following method: the signal generator 111, the module to be tested 112, the physical layer module 113, the second preset interface module 114, the frame demodulation module 115, and the cache module 116 are burned into a preset FPGA development board to obtain the FPGA board card 110. The output end of the signal generator 111 is connected to the input end of the module to be tested 112, the output end of the module to be tested 112 is connected to the input end of the physical layer module 113, the output end of the physical layer module 113 is connected to the input end of the second preset interface module 114, the output end of the second preset interface module 114 is connected to the input end of the frame demodulation module 115, and the output end of the frame demodulation module 115 is connected to the input end of the cache module 116.

[0042] The signal generator 111 is configured to output a preset signal. The signal generator 111 is composed of a digital controlled oscillator, which is configured to configure the frequency and phase of the output signal through a preset configuration interface to output a single-tone signal with a preset bit number. A preset algorithm is configured in the signal generator 111 to reduce quantization noise. In some embodiments, the preset configuration interface is an AXI-Lite interface, the preset algorithm includes a Dithering algorithm, and the single-tone signal with the preset bit number is a 16-bit single-tone signal of a sine function wave and a cosine function wave.

[0043] The to-be-tested module 112 includes a digital down-converter module 112a and a first preset interface module 112b. In the embodiment of the application, the digital down-converter module 112a is a DDC (Digital Down-Converter) module, which is a kind of digital signal processing module, used for converting high-frequency digital signals through frequency conversion, low-pass filtering, down-sampling and complex-real conversion. The first preset interface module 112b is a JESD204B module, used for framing, character replacement, scrambling and 8b10b coding of the signals output by the DDC module. In some embodiments, the to-be-tested module can also be other kinds of modules.

[0044] In some embodiments, the register configuration interface of the to-be-tested module can be packaged as an AXI bus slave device with an AXI-Lite interface: the to-be-tested module is configured with a register table of input configuration parameters, which can also be configured with a native interface, an spi interface or an apb interface. The AXI2apb or AXI2spi module can be connected through the AXI-Lite bus at the register offset address. For the JESD204B module in the to-be-tested module, the clock driving the data path includes a sampling clock and a character clock. After the to-be-tested module is connected with the FPGA board, it is determined whether the to-be-tested module connects the sampling clock and the character clock to the module top port; if yes, no intermediate conversion or logic processing is needed, and the bus can be directly connected with the corresponding clock of the FPGA board; if not, the original clock input is switched to the clock provided by the FPGA board at the specific data path register inside the to-be-tested module.

[0045] The physical layer module 113 is a JESD204_phy module. The physical layer module 113 has two functions. The first function is to be configured as the physical layer of the first preset interface module 112b (i.e., the JESD204B module), used for converting the parallel signals output by the to-be-tested module 112 into serial signals and sending the serial signals to the physical layer module 113. The second function is to be configured as the physical layer of the second preset interface module 114 (i.e., the JESD204C module), used for receiving the serial signals from the previous stage and converting the serial signals into parallel signals and sending the parallel signals to the second preset interface module 114.

[0046] The second preset interface module 114 is configured to process the received parallel signal to obtain a to-be-de-framed signal. In some embodiments, the second preset interface module 114 is a JESD204C module, which implements a data link layer specified in a JESD204C protocol, is compatible with a JESD204B protocol, and restores the received parallel signal to the to-be-de-framed signal in a character transmission clock domain. In some embodiments, a system synchronization reference signal generation module is arranged between the first preset interface module 112b and the second preset interface module 114, and is configured to generate a system synchronization reference signal and send the system synchronization reference signal to the first preset interface module 112b and the second preset interface module 114. In the present application, the generated system synchronization reference signal is sent to the first preset interface module and the second preset interface module respectively, so that a sub-class 1 type link building specified in the JESD204B protocol is implemented, and a deterministic delay between modules is provided according to the protocol, so that the timing accuracy of data transmission is ensured, and system jitter and uncertainty are reduced.

[0047] The de-framing module 115 is configured to restore the received to-be-de-framed signal to an original sampling signal. In the present application, the to-be-de-framed signal output by the second preset interface module 114 is input to the de-framing module 115, and the de-framing module 115 restores the data output by the second preset interface module 114 to a state after output by the digital down converter module 112a and before sampling by the first preset interface module 112b based on the first preset configuration parameter. In some embodiments, the first preset configuration parameter includes parameters M, S, Nb, L, and F specified in the JESD204B protocol, where the parameter M is used to represent the number of effective digital-to-analog conversions in each frame of data, the parameter S is used to represent the number of signal samples of each signal converter in each frame of data, the parameter Nb is used to represent the number of bits per sample, the parameter L is used to represent the number of transmission links, and the parameter F is used to represent the number of transmission bytes.

[0048] The cache module 116 is configured to cache the original sampling signal output by the de-framing module 115. In some embodiments, the cache module 116 is a true dual-port BRAM (Block RAM, block random access memory) that can support two ports to read and write independently at the same time, so as to allow two modules to access the same block of storage space in parallel.

[0049] The FMC daughter card 120 is configured to provide a clock source required by a data path of the FPGA board card 110. In some embodiments, the FMC daughter card 120 is connected with the physical layer module 113 in the FPGA board card, and the FMC daughter card is further configured to perform a high-speed serial signal loopback of the physical layer module 113, i.e., directly returning the high-speed serial signal sent by the sending end of the physical layer module 113 to the receiving end. In this way, the physical layer module 113 can be used as a physical layer connected after the first preset interface module 112b and as a physical layer connected before the second preset interface module 114, thereby realizing data conversion between parallel and serial, supporting efficient transmission of high-speed data, providing a reliable data transmission channel for a data link layer of an upper layer, and ensuring accuracy and stability of data transmission.

[0050] In some embodiments, the FPGA board card 110 further includes a clock management module connected with two independent clock sources, i.e., a system clock of the FPGA board card 110 and an external clock of the FMC daughter card 120.

[0051] Please refer to Figure 2 , Figure 2 which is a schematic structural diagram of the clock management module according to an example embodiment of the present application; as shown in Figure 2 , the clock management module includes a first phase-locked loop 210, a second phase-locked loop 220, a first clock buffer 230, a second clock buffer 240, and an integrated circuit bus master module 250.

[0052] One end of the first phase-locked loop 210 is connected with the system clock source, and the other end of the first phase-locked loop 210 is connected with the physical layer module 113 and the microprocessor core; the first phase-locked loop 210 is configured to generate a dynamic reconfiguration clock of the physical layer module 113 and a bus clock of the microprocessor core according to the system clock output by the system clock source.

[0053] In the embodiment of the present application, the system clock of the FPGA board card is output from outside the chip to the first phase-locked loop, and then two stable clocks are generated, one of which is given to the microprocessor core and the AXI bus connected therewith to serve as an AXI bus clock, and the other of which is given to the physical layer module to serve as a DRP (Dynamic Reconfiguration Port) clock of the module.

[0054] One end of the first clock buffer 230 is connected with the FMC daughter card 120, and the other end of the first clock buffer 230 is connected with the physical layer module 113; the first clock buffer 230 is configured to buffer the external clock output by the FMC daughter card 120 and output a reference clock to the physical layer module 113.

[0055] One end of the second clock buffer 240 is connected with the FMC sub-card 120, and the other end of the second clock buffer 240 is connected with the input end of the second phase-locked loop 220; the output end of the second phase-locked loop 220 is connected with the digital down converter module 112a and the first preset interface module 112b; the second clock buffer 240 is used for buffering the external clock output by the FMC sub-card 120, and outputting the preset clock to the digital down converter module 112a through the output end of the second phase-locked loop 220, and outputting the sampling clock and the character clock to the first preset interface module 112b.

[0056] It can be understood that the external clock output by the FMC sub-card is buffered by the two clock buffers after being introduced into the FPGA board card, so that the quality of the clock signal is improved.

[0057] The clock output by the first clock buffer 230 is directly given to the physical layer module 113 as the reference clock of the physical layer module 113. The clock output by the second clock buffer 240 is connected to the second phase-locked loop 220, and three clock signals are output through the second phase-locked loop 220, which are respectively the clock signal (i.e., the preset clock) of the signal generator 111 and the digital down converter module 112a, the clock (i.e., the sampling clock) of the sampling logic of the first preset interface module 112b, and the clock (i.e., the character clock) of the character transmission logic.

[0058] For the digital down converter module 112a, by outputting the preset clock to the digital down converter module 112a, it can be ensured that the sampling, data processing and transmission of the digital down converter module 112a are performed in the same clock domain, thereby ensuring the timing consistency and system stability.

[0059] For the first preset interface module 112b, the first preset interface module 112b is a JESD204B module, and in the framing operation of the protocol layer, there will be a sampling clock before framing and a character clock after framing, and the two clocks are homologous clocks and have a frequency and a phase relationship determined by the protocol and parameters. Moreover, the digital down converter module is usually configured with filtering and downsampling functions, which require that the sampling clock of the JESD204B module in the subsequent stage matched with the clock of the DDC has a certain frequency and phase relationship, and at the same time, the character transmission clock of the JESD204B module also needs to change accordingly, so as to ensure that the data processed by the DDC module can be completely sampled, and the transmission rate is not wasted. In the present application, by setting the second phase-locked loop to be capable of dynamically reconfiguring the frequency and phase through the AXI-Lite bus, the frequency and phase relationship between the clock of the DDC module and the sampling clock and the character clock of the JESD204B module can be accurately controlled while ensuring that the two clocks are homologous.

[0060] The integrated circuit bus master module 250 is configured to configure the crystal oscillator of the FMC daughter card 120, so that the FMC daughter card 120 provides a clock source for the FPGA board card 110.

[0061] In the embodiment, all devices hanging on the AXI bus in the AXI bus clock driving system of the FPGA board card include the IIC Master module. The IIC Master module is configured to configure the crystal oscillator of the FMC daughter card, and the clock provided by the FMC daughter card is the clock source of the entire data path.

[0062] The host computer 130 is connected with the FPGA board card 110. The host computer 130 is configured to send a preset instruction to the FPGA board card 110, so as to control the FPGA board card 110 to test the to-be-tested module 112. In the embodiment, the host computer 130 is further configured to perform variable parameter configuration on the FPGA board card and the to-be-tested module according to variable configuration parameters, and perform signal reading and analysis in the cache module; and / or perform non-variable parameter configuration on the FPGA board card and the to-be-tested module according to non-variable configuration parameters.

[0063] It can be understood that when the digital down converter module and the first preset interface module in the to-be-tested module are simultaneously tested, the variable parameter configuration and the non-variable parameter configuration can be sent to the FPGA board card and the to-be-tested module, so as to realize simultaneous testing. When only the digital down converter module is tested, only the variable configuration parameters can be sent for configuration; and when only the first preset interface module is tested, only the non-variable parameter configuration can be sent. In this way, the compatibility of the prototype verification platform in the embodiment can be improved, so that the prototype verification platform can test different to-be-tested modules. In this way, the two kinds of modules can be jointly tested and each module can be tested individually. The construction of the FPGA-based module prototype verification platform is more convenient, and the portability of different to-be-tested modules is also enhanced. Moreover, the configuration parameters acting on different modules are classified into variable configuration parameters and non-variable configuration parameters according to whether the configuration parameters are related to the clock, so that the levels of the configurability and reconfigurability of the entire system are more clear. Moreover, the test results can be transmitted and processed in real time, the work is stable, and the test efficiency is significantly improved.

[0064] In some embodiments, the variable configuration parameters include a signal frequency and a phase output by the signal generator module, and configuration parameters corresponding to the digital down converter module; and the non-variable configuration parameters include framing parameters corresponding to the first preset interface module, clock configuration parameters corresponding to the FMC daughter card, clock configuration parameters corresponding to the to-be-tested module, and interface configuration parameters corresponding to the physical layer module.

[0065] In some embodiments, the FPGA board card 110 further comprises a microprocessor core, an AXI bus (a high-performance bus based on the ARM AMBA protocol), an AXI Interconnect module and a UART (universal asynchronous receiver-transmitter) transceiver module. The microprocessor core is connected to the host computer 130 through a JTAG interface, and is connected to the AXI Interconnect module to realize the reading and writing of all AXI bus-mounted slave devices, i.e., the configuration of all AXI slave device modules, and two random access memories in the FPGA board card are allocated to buffer data and instructions. The microprocessor core does not run an operating system and does not carry a DDR cache. The microprocessor core is only used for simple operations such as transmitting configuration parameters. The FPGA board card transmits data to the host computer through the UART transceiver module.

[0066] Exemplarily, the host computer 130 sends the variable configuration parameters to the microprocessor core in the FPGA board card through a preset interface. The microprocessor core receives the data signal transmitted by the host computer through the UART transceiver module in ASCII code format, decodes the required configuration target, and calculates the specific configuration parameters to control the microprocessor core to perform parameter configuration according to the variable configuration parameters. In some embodiments, the variable configuration parameters are signal frequency and phase output by the signal generator and corresponding configuration parameters of the digital downconverter module, such as carrier frequency, filtering parameters, output bit width, etc.

[0067] It can be understood that for variable configuration parameters, tens or even hundreds of bits of configuration input are often required to achieve a certain specific configuration after calculation. Therefore, receiving and decoding calculation of data through the UART transceiver module can improve the transmission efficiency of the configuration parameters.

[0068] In combination with Figure 3 as shown, Figure 3 is a flowchart of parameter configuration and data analysis according to an exemplary embodiment of the present application, wherein the transmitted configuration parameters are variable configuration parameters; at least comprising steps S310-S360, which are described in detail as follows:

[0069] Step S310: transmitting variable configuration parameters to the FPGA board card and the module to be tested through a preset interface.

[0070] In the embodiment of the present application, the host computer transmits variable configuration parameters through a serial port, which can transmit the ASCII code format corresponding to the configuration of the signal with a precision of 0.001M.

[0071] Step S320: reading signals in the buffer module and performing signal data type conversion.

[0072] In some embodiments, the signal data type conversion comprises: processing the signal read from the buffer module in signed decimal and storing the signal into a file.

[0073] In step S330, the converted signal is filtered to obtain a filtered signal.

[0074] It can be understood that, since the digital down converter module in the to-be-tested module is configured with a spectrum shift and a low-pass filtering function, it is possible that, under the configuration of some input signals and filtering parameters, the spectrum peak of the effective signal is filtered out, resulting in invalid data under the present configuration. By filtering such signals, the testing accuracy can be improved.

[0075] In step S340, the filtered signal is windowed to obtain a signal sequence, and the signal sequence is subjected to Fourier transform to obtain spectrum information, and the spectrum information is subjected to data visualization processing.

[0076] In step S350, peak detection is performed on the spectrum information to extract an effective signal frequency point, and a signal quality parameter is calculated according to the effective signal frequency point; wherein the preset signal quality parameter comprises a signal-to-noise ratio and a spurious-free dynamic range.

[0077] In step S360, the signal quality parameter and the spectrum information are compared with preset standard data.

[0078] In the embodiments of the present application, the loop calling part is run for a preset number of times, and a random number is generated each time to be input into the FPGA board card as a changeable configuration. In this way, by combining FPGA testing, real-time verification and dynamic performance analysis, the full-process automation from signal generation to data acquisition, spectrum comparison and performance analysis is realized, and the testing accuracy and economy are greatly improved, thereby providing an efficient and flexible comprehensive verification solution for the development and debugging of high-speed digital signal processing systems. Meanwhile, by means of error detection and statistical analysis algorithm, the signal input and the result of digital mixing, low-pass filtering and decimation of the signal input inside the DDC and transmission through the JESD204B module are analyzed online, and the signal processing and data visualization are automatically completed.

[0079] In some embodiments, the FPGA board card 110 further comprises a block random access memory control module (i.e., a first BRAM controller module); the first BRAM controller module is connected with the output end of the de-framing module and the output end of the digital down converter module; the first BRAM controller module is configured to perform down-sampling on the data written into the buffer module according to second preset configuration parameters; wherein the second preset configuration parameters comprise output down-sampling configuration parameters of the digital down converter module.

[0080] It can be understood that, in the embodiment of the application, the output end of the digital down converter module is directly connected with the first BRAM controller module, and the output signal of the digital down converter module does not pass through the link of the first preset interface module, but is directly connected into the first BRAM controller module, so that the separate test of the digital down converter module in the to-be-tested module can be realized. Moreover, by configuring the output downsampling parameters of the digital down converter module into the first BRAM controller module, the output signal of the digital down converter module can be downsampled and then written into the cache module, so that the physical bandwidth limitation of the cache module can be matched, the repeated writing or overflow caused by the unmatched data rate is avoided, and the transmission bandwidth waste caused by the repeated writing or overflow is further avoided.

[0081] In some embodiments, the first BRAM controller module is an AXI-Lite slave device, which can control the reading and writing of the cache module in the FPGA board card by receiving an AXI-Lite signal, and an 8-bit address is used to encode when reading and writing a specific address to adapt to the AXI-Lite bus. The cache module is used to isolate the clock domain, and the data stored in the cache module is derived from the clock domain after the frame is decomposed, which is the same as the sampling clock domain of the first preset interface module, so that multi-frame synchronization and data alignment can be realized, and the test accuracy is improved.

[0082] In some embodiments, the FPGA board card 110 further comprises a second BRAM controller module, and the second BRAM controller module controls and transmits data through an AXI-Lite interface. In the embodiment of the application, the second BRAM controller module and the host computer can be connected through various interfaces such as Ethernet, PCIE, etc., and the UART transceiver module is used for data transmission with the host computer in the embodiment.

[0083] Please refer to Figure 4 , Figure 4 The module prototype verification method of the FPGA-based module prototype verification device shown in the example embodiment of the application can be applied to electronic equipment. The electronic equipment includes but is not limited to a host computer, a tablet computer, etc.

[0084] The verification method proposed in the embodiment of the application will be described in detail below with the host computer as a specific execution subject.

[0085] As shown in Figure 4 , in an example embodiment, the verification method for the to-be-tested module at least includes steps S410 to S420, which are described in detail as follows:

[0086] Step S410: Obtain the volatile configuration parameters and the non-volatile configuration parameters.

[0087] In the embodiments of the present application, the variable configuration parameters include signal frequency and phase output by the signal generator module, and the corresponding configuration parameters of the digital down converter module. The non-variable configuration parameters include the framing parameters and the link establishment configuration parameters corresponding to the first preset interface module, the clock configuration parameters corresponding to the FMC subcard, the clock configuration parameters corresponding to the module to be tested, and the interface configuration parameters corresponding to the physical layer module. In some embodiments, the non-variable configuration parameters further include the data link transmission rate of the first preset interface module.

[0088] For example, the framing parameters corresponding to the first preset interface module include the framing parameters and the link establishment configuration parameters required by the first preset interface module. The framing parameters include the number of effective digital-to-analog conversions in each frame of data, the number of signal samples of each signal converter in each frame of data, the number of bits per sample, the number of transmission links, and the number of transmission bytes. The link establishment configuration parameters include link establishment sub-classes, whether to perform scrambling processing, and other parameters.

[0089] The clock configuration parameters corresponding to the FMC subcard include the crystal frequency configuration parameters of the FMC subcard.

[0090] The clock configuration parameters corresponding to the module to be tested include the configuration parameters of the second phase-locked loop. In the embodiments of the present application, the frequency, duty cycle, and phase of the clock of the signal generator and the digital down converter module, the sampling clock and character clock of the first preset interface module can be configured through the configuration parameters of the second phase-locked loop.

[0091] The interface configuration parameters corresponding to the physical layer module include the transmission rate. In some embodiments, the transmission rate can be adjusted from 1G to 16G.

[0092] In step S420, the variable configuration parameters and the non-variable configuration parameters are written into the FPGA board card, and the FPGA board card is run according to a preset running number to control the FPGA board card to test the module to be tested.

[0093] In the embodiments of the present application, on the one hand, the configuration parameters acting on different modules are classified into two categories of variable parameters and non-variable parameters according to whether they are related to the clock, and the variable parameters and the non-variable parameters in the module to be tested are configured at the same time, and the clock configuration parameters in the non-variable configuration parameters realize accurate clock control and data alignment, ensuring accurate collection of test point data and maximum utilization of transmission bandwidth in the verification process. On the other hand, the joint test of the two modules (the digital down converter module and the first preset interface module) can be realized, and the test automation degree is high, the configurability and reconfigurability are high, and the design of the FPGA program and the host computer program for signal generation, signal input, data acquisition, and data processing is universalized.

[0094] Please refer to Figure 5 , Figure 5is a flow chart of a method for separately testing a digital down converter module in a to-be-tested module according to an example embodiment of the present application; at least comprising steps S510-S520, which are described in detail as follows:

[0095] In step S510, an output down-sampling configuration parameter corresponding to the digital down converter module is acquired, and the output down-sampling configuration parameter is written into the block random access memory control module.

[0096] In step S520, the FPGA board card is controlled to test the digital down converter module according to a preset running number.

[0097] In the example embodiment of the present application, the output end of the digital down converter module is directly connected to the first BRAM controller module, so that the output signal of the digital down converter module is not transmitted through the link of the first preset interface module, but is directly connected to the first BRAM controller module, so that the separate testing of the digital down converter module in the to-be-tested module can be realized. Moreover, by configuring the output down-sampling parameter of the digital down converter module into the first BRAM controller module, the output signal of the digital down converter module can be down-sampled and then written into the cache module, so that the physical bandwidth limitation of the cache module can be matched, and repeated writing or overflow caused by the mismatch of data rates can be avoided, thereby avoiding the waste of transmission bandwidth.

[0098] Please refer to Figure 6 , Figure 6 is a flow chart of a method for separately testing a first preset interface module in a to-be-tested module according to an example embodiment of the present application; at least comprising steps S610-S630, which are described in detail as follows:

[0099] In step S610, a non-volatile configuration parameter is acquired.

[0100] In the example embodiment of the present application, the non-volatile configuration parameter includes a framing parameter and a link establishment configuration parameter corresponding to the first preset interface module, a clock configuration parameter corresponding to the FMC subcard, a clock configuration parameter corresponding to the first preset interface module, and an interface configuration parameter corresponding to the physical layer module. In some embodiments, the non-volatile configuration parameter further includes a data link transmission rate of the first preset interface module.

[0101] In step S620, the non-volatile configuration parameter is written into the FPGA board card and the first preset interface module.

[0102] In step S630, the FPGA board card is controlled to test the first preset interface module according to a preset running number.

[0103] In the embodiment of the present application, the non-volatile configuration parameters are written into the FPGA board and the first preset interface module by the host computer, accurate clock control and data alignment can be realized by the clock configuration parameters in the non-volatile configuration parameters, accurate collection of test point data and maximum utilization of transmission bandwidth in the verification process are ensured, and only the first preset interface module can be tested alone.

[0104] In combination Figure 7 As shown in the figure, Figure 7 is a structural diagram of a verification device corresponding to the verification method shown in an exemplary embodiment of the present application. As shown in the figure, Figure 7 The exemplary verification device includes an acquisition module 710 and a test module 720. The acquisition module 710 is configured to acquire volatile configuration parameters and non-volatile configuration parameters, and the test module 720 is configured to write the volatile configuration parameters and the non-volatile configuration parameters into the FPGA board and run according to a preset running number to control the FPGA board to test the to-be-tested module.

[0105] In the embodiment of the present application, each module can be tested alone or jointly tested. The FPGA-based module prototype verification platform is more convenient to build, and the portability of different to-be-tested modules is enhanced. Moreover, the configuration parameters acting on different modules are classified into volatile configuration parameters and non-volatile configuration parameters according to whether they are related to the clock, so that the levels of the configurability and reconfigurability of the entire system are more clear. Moreover, the test results can be transmitted and processed in real time, the work is stable, and the test efficiency is significantly improved.

[0106] It should be noted that the verification device provided in the above embodiment and the FPGA-based module prototype verification method provided in the above embodiment belong to the same concept, wherein the specific manner in which each module and unit performs operations has been described in detail in the method embodiments, which will not be described here. The verification device provided in the above embodiment can be divided into different functional modules to complete the above-described functions according to the needs in actual application, that is, the internal structure of the device is divided into different functional modules to complete all or part of the above-described functions, which is not limited herein.

[0107] The embodiment of the present application also provides an electronic device, including: one or more processors; a storage device for storing one or more programs, when the one or more programs are executed by the one or more processors, the electronic device implements the FPGA-based module prototype verification method provided in each of the above embodiments.

[0108] Figure 8 The structure of a computer system suitable for implementing the electronic device of the embodiment of the present application is shown. It should be noted that, Figure 8The computer system 800 of the electronic device shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of this application.

[0109] like Figure 8 As shown, the computer system 800 includes a Central Processing Unit (CPU) 801, which can perform various appropriate actions and processes based on programs stored in Read-Only Memory (ROM) 802 or programs loaded from storage portion 808 into Random Access Memory (RAM) 803, such as performing the methods described in the above embodiments. The RAM 803 also stores various programs and data required for system operation. The CPU 801, ROM 802, and RAM 803 are interconnected via a bus 804. An Input / Output (I / O) interface 805 is also connected to the bus 804.

[0110] The following components are connected to I / O interface 805: an input section 806 including a keyboard, mouse, etc.; an output section 807 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and speakers, etc.; a storage section 808 including a hard disk, etc.; and a communication section 809 including a model interface card such as a LAN (Local Area Network) card, modem, etc. The communication section 809 performs communication processing via a model such as the Internet. A drive 810 is also connected to I / O interface 805 as needed. A removable medium 811, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on drive 810 as needed so that computer programs read from it can be installed into storage section 808 as needed.

[0111] Specifically, according to embodiments of this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program including a computer program for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a model via communication section 809, and / or installed from removable medium 811. When the computer program is executed by central processing unit (CPU) 801, it performs various functions defined in the system of this application.

[0112] It should be noted that the computer readable medium shown in the embodiments of the present application can be a computer readable signal medium or a computer readable storage medium or any combination of the two. The computer readable storage medium may, for example, be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or apparatus, or any combination thereof. More specific examples of the computer readable storage medium can include, but are not limited to, an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, an optical fiber, a portable compact disk read-only memory (Compact Disc Read-Only Memory, CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, the computer readable signal medium can include a data signal carried in a baseband or as a carrier wave part of a carrier wave, which carries the computer readable computer program. Such a propagated data signal can take various forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination thereof. The computer readable signal medium can also be any computer readable medium other than the computer readable storage medium, which can send, propagate or transmit the program for use by or in connection with an instruction execution system, apparatus or device. The computer program contained on the computer readable medium can be transmitted by any suitable medium, including but not limited to wireless, wired, etc., or any suitable combination thereof.

[0113] Another aspect of the present application also provides a computer readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the FPGA-based module prototype verification method as described above. The computer readable storage medium can be included in the electronic device described in the above embodiments, or can exist separately and not be assembled into the electronic device.

[0114] Another aspect of the present application also provides a computer program product or computer program, which includes computer instructions stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions to make the computer device execute the FPGA-based module prototype verification method provided in each of the above embodiments.

[0115] The above merely describes preferred exemplary embodiments of the present application, and is not intended to limit the implementation of the present application. Based on the main concept and spirit of the present application, a person of ordinary skill in the art can easily make corresponding modifications or changes, and the protection scope of the present application should be subject to the protection scope required by the claims.

[0116] It should be noted that when the embodiments of the present application are applied to specific products or technologies, such as obtaining configuration parameters, it is inevitable to obtain the configuration parameters of the to-be-tested module and the configuration parameters of the FPGA board card. Therefore, the permission or consent of the relevant object needs to be obtained, and the collection, use and processing of the relevant data need to comply with the relevant laws, regulations and standards of the relevant countries and regions.

Claims

1. A module prototype verification device based on FPGA, characterized in that, include: The FPGA board includes a signal generator, a module under test, a physical layer module, a second preset interface module, a frame decompression module, and a buffer module; the module under test includes a digital downconverter module and a first preset interface module. The signal generator is used to output a preset signal; the physical layer module is configured as the physical layer of the first preset interface module, and is used to convert the parallel signal output by the module under test into a serial signal and send it to the physical layer module. The physical layer module is also configured as the physical layer of the second preset interface module, used to receive the serial signal and convert the serial signal into a parallel signal and send it to the second preset interface module; the second preset interface module is used to process the received parallel signal to obtain the frame signal to be decoded; the frame decoding module is used to restore the frame signal to be decoded to the original sampled signal; the buffer module is used to buffer the original sampled signal. An FMC daughter card is connected to the FPGA board, and the FMC daughter card is used to provide the clock source required for the data path of the FPGA board. A host computer is connected to the FPGA board. The host computer is used to send preset instructions to the FPGA board to control the FPGA board to test the module under test.

2. The apparatus according to claim 1, characterized in that, The FPGA board also includes a clock management module; the clock management module includes a first phase-locked loop, a second phase-locked loop, a first clock buffer, a second clock buffer, and an integrated circuit bus master module; The integrated circuit bus master module is used to configure the crystal oscillator of the FMC daughter card so that the FMC daughter card provides a clock source to the FPGA board; One end of the first phase-locked loop is connected to the system clock source, and the other end of the first phase-locked loop is connected to the physical layer module and the microprocessor core; the first phase-locked loop is used to generate the dynamic reconfiguration clock of the physical layer module and the bus clock of the microprocessor core according to the system clock output by the system clock source; One end of the first clock buffer is connected to the FMC daughter card, and the other end of the first clock buffer is connected to the physical layer module. The first clock buffer is used to buffer the external clock output by the FMC daughter card and output a reference clock to the physical layer module; One end of the second clock buffer is connected to the FMC daughter card, and the other end of the second clock buffer is connected to the input of the second phase-locked loop; the output of the second phase-locked loop is connected to the digital down-converter module and the first preset interface module; the second clock buffer is used to buffer the external clock output by the FMC daughter card, and output a preset clock to the digital down-converter module through the output of the second phase-locked loop, as well as output a sampling clock and a character clock to the first preset interface module.

3. The apparatus according to claim 1, characterized in that, The signal generator includes a numerically controlled oscillator, which is used to configure the frequency and phase through a preset configuration interface to output a single-tone signal with a preset number of bits.

4. The apparatus according to claim 1, characterized in that, A system synchronization reference signal generation module is provided between the first preset interface module and the second preset interface module. The system synchronization reference signal generation module is used to generate a system synchronization reference signal and send it to the first preset interface module and the second preset interface module.

5. The apparatus according to claim 1, characterized in that, The frame decoding module is configured to restore the frame signal to be decoded output by the second preset interface module to the original sampled signal according to the first preset configuration parameters. The first preset configuration parameters include the number of valid digital-to-analog converters in each frame of data, the number of signal samples for each signal converter in each frame of data, the number of bits per sample, the number of transmission links, and the number of transmitted bytes.

6. The apparatus according to claim 1, characterized in that, The FPGA board also includes a block random access memory control module, which is connected to the output of the frame deframe module and the output of the digital downconverter module. The block random access memory control module is used to downsample the data written to the cache module according to a second preset configuration parameter. The second preset configuration parameter includes the output downsampling configuration parameter of the digital downconverter module.

7. The apparatus according to claim 1, characterized in that, The host computer is also configured to configure variable parameters for the FPGA board and the module under test according to variable configuration parameters, and to perform signal reading and parsing in the cache module; and / or, Configure the FPGA board and the module under test with non-volatile parameters according to the non-volatile configuration parameters. The variable configuration parameters include the signal frequency and phase output by the signal generator module, and the configuration parameters corresponding to the digital downconverter module; the non-variable configuration parameters include the framing parameters corresponding to the first preset interface module, the clock configuration parameters corresponding to the FMC daughter card, the clock configuration parameters corresponding to the module under test, and the interface configuration parameters corresponding to the physical layer module.

8. A module prototype verification method based on the FPGA-based module prototype verification device as described in claim 1, characterized in that, include: Obtain volatile and non-volatile configuration parameters; wherein, the volatile configuration parameters include the signal frequency and phase output by the signal generator module, and the configuration parameters corresponding to the digital downconverter module; the non-volatile configuration parameters include the framing parameters and link establishment configuration parameters corresponding to the first preset interface module, the clock configuration parameters corresponding to the FMC daughter card, the clock configuration parameters corresponding to the module under test, and the interface configuration parameters corresponding to the physical layer module; The volatile configuration parameters and the non-volatile configuration parameters are written into the FPGA board and run according to a preset number of times to control the FPGA board to test the module under test.

9. An electronic device, characterized in that, include: One or more processors; A storage device for storing one or more programs, which, when executed by one or more processors, cause the electronic device to implement the module prototype verification method of the FPGA-based module prototype verification device as described in claim 8.

10. A computer-readable storage medium, characterized in that, It stores computer-readable instructions, which, when executed by the computer's processor, cause the computer to perform the module prototype verification method of the FPGA-based module prototype verification device as described in claim 8.

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