Integrated circuit test excitation generation method and related equipment

Abstract

The invention discloses an integrated circuit test excitation generation method and related equipment, and the method comprises the steps: analyzing a coverage point code file and an RTL file, obtaining an input signal combination for triggering each coverage point according to the coverage points in the coverage point code file and a logic relation in the RTL file, and generating test excitation according to the input signals. Manual participation is greatly reduced, and the overall test efficiency is improved. Moreover, according to the method, an input signal combination is accurately deduced according to the logic relationship in the coverage point and the RTL file, the test excitation matched with the input signal combination is generated, and the accuracy and comprehensiveness of test excitation generation are improved, so that the function of the integrated circuit is comprehensively detected, and the test accuracy is improved.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit testing, and in particular to a method for generating integrated circuit test stimuli and related equipment. Background Art

[0002] In integrated circuit (IC) verification, coverpoints are an important metric for measuring the comprehensiveness of IC verification. Coverpoints define the critical signal states and logic conditions that need to be tested in the IC chip design.

[0003] Typically, integrated circuit testing requires verification engineers to manually complete the entire process, such as extracting coverage points and designing test stimuli.

[0004] Verification engineers spend a significant amount of time and effort extracting coverage points and designing test stimuli, resulting in low IC verification efficiency. Furthermore, manual operations can easily lead to errors and omissions in verification plans due to complex logic, failing to meet verification requirements and impacting verification cycles. Summary of the Invention

[0005] Based on the above problems, the present application provides a method for generating integrated circuit test stimuli and related equipment.

[0006] In a first aspect, an embodiment of the present application provides a method for generating an integrated circuit test stimulus, the method comprising:

[0007] Obtaining a coverpoint code file of an integrated circuit and a register transfer level (RTL) file corresponding to the coverpoint code file; the coverpoint code file includes at least one coverpoint; the RTL file is used to record the logical relationship of internal signals of the integrated circuit;

[0008] Obtaining an input signal combination that triggers each of the cover points according to at least one of the cover points and the logical relationship;

[0009] A corresponding test stimulus is generated according to each combination of the input signals; the test stimulus is used to drive the integrated circuit to trigger the cover point.

[0010] In a possible implementation, obtaining, according to at least one of the cover points and the logical relationship, a combination of input signals for triggering each of the cover points includes:

[0011] Parsing the cover point code file to identify target signals corresponding to each cover point and target values ​​of the target signals;

[0012] Determining the type of each target signal based on the RTL file;

[0013] The input signal combination of each of the cover points is determined according to the type of each of the target signals and the logical relationship recorded in the RTL file.

[0014] In a possible implementation, the signal type of the target signal includes an input signal, an intermediate signal, or an output signal;

[0015] Determining an input signal combination of the cover point according to the type of the target signal and the logical relationship recorded in the RTL file includes:

[0016] In a case where the target signal is an input signal, the target signal and a target value corresponding to the target signal are used as an input signal combination;

[0017] In the case where the target signal is an intermediate signal or an output signal, the target signal is reversely deduced according to the logical relationship recorded in the RTL file to obtain an input signal combination that enables the target signal to meet the target value.

[0018] In a possible implementation, reversely deducing the target signal according to the logical relationship recorded in the RTL file includes:

[0019] Locating the assignment logic of the target signal in the RTL file, and extracting the upstream signal combination in the assignment logic;

[0020] Establishing a mapping relationship between a target value of the target signal and a value of the upstream signal combination based on the assignment logic;

[0021] The value of the upstream signal combination that enables the target signal to meet the target value is determined according to the mapping relationship, and the input signal combination is obtained according to the value of the upstream signal combination.

[0022] In a possible implementation, establishing a mapping relationship between a target value of the target signal and a value of the upstream signal combination based on the assignment logic includes:

[0023] When the assignment logic indicates that multiple groups of upstream signal combinations can make the target signal meet the target value, a mapping relationship is established between the target value of the target signal and the values ​​of each group of upstream signal combinations.

[0024] In a possible implementation, the method further includes:

[0025] Converting the test stimulus corresponding input signal combination into a signal driving code that conforms to the syntax specification of the test platform;

[0026] The signal driving code is embedded in the test platform; the signal driving code includes a signal assignment statement and a timing control statement; the signal assignment statement is used to define the specific value of the input signal, and the timing control statement is used to define the time node of signal application.

[0027] In a possible implementation, the method further includes:

[0028] Performing simulation verification on the test stimulus to determine whether the test stimulus triggers a corresponding coverage point;

[0029] In the case that the cover point is not triggered, determining a failure type of the test stimulus that does not trigger the corresponding cover point;

[0030] Adjustments are made according to the failure type, and the test stimulus corresponding to the cover point is regenerated until the cover point is triggered.

[0031] In a second aspect, an embodiment of the present application provides a device for generating an integrated circuit test stimulus, the device comprising:

[0032] an acquisition module, configured to acquire a coverpoint code file of an integrated circuit and a register transfer level (RTL) file corresponding to the coverpoint code file; the coverpoint code file includes at least one coverpoint; and the RTL file is configured to record the logical relationship between internal signals of the integrated circuit;

[0033] a parsing module, configured to obtain, according to at least one of the cover points and the logical relationship, a combination of input signals that trigger each of the cover points;

[0034] A generation module is used to generate corresponding test stimuli according to each combination of the input signals; the test stimuli are used to generate signal driving codes of the test platform, and the signal driving codes are used to drive the integrated circuit to trigger the coverage of the coverage points.

[0035] In one possible implementation, the parsing module is specifically configured to parse the cover point code file, identify the target signal corresponding to each cover point and the target value of the target signal; determine the type of each target signal based on the RTL file; and determine the input signal combination of each cover point according to the type of each target signal and the logical relationship recorded in the RTL file.

[0036] In a possible implementation, the signal type of the target signal includes an input signal, an intermediate signal, or an output signal;

[0037] The parsing module is specifically used to, when the target signal is an input signal, use the target signal and the target value corresponding to the target signal as an input signal combination; when the target signal is an intermediate signal or an output signal, reversely deduce the target signal according to the logical relationship recorded in the RTL file to obtain an input signal combination that makes the target signal meet the target value.

[0038] In one possible implementation, the parsing module is specifically used to locate the assignment logic of the target signal in the RTL file and extract the upstream signal combination involved in the assignment logic; establish a mapping relationship between the target value of the target signal and the value of the upstream signal combination based on the assignment logic; determine the value of the upstream signal combination that makes the target signal meet the target value according to the mapping relationship, and obtain the input signal combination according to the value of the upstream signal combination.

[0039] In one possible implementation, the parsing module is specifically used to establish a mapping relationship between the target value of the target signal and the values ​​of each group of upstream signal combinations when the assignment logic represents that multiple groups of upstream signal combinations can make the target signal meet the target value.

[0040] In one possible implementation, the generation module is also used to convert the input signal combination corresponding to the test stimulus into a signal-driven code that conforms to the syntax specifications of the test platform; embed the signal-driven code into the test platform; the signal-driven code includes a signal assignment statement and a timing control statement; the signal assignment statement is used to define the specific value of the input signal, and the timing control statement is used to define the time node of the signal application.

[0041] In a possible implementation, the device further includes a verification module;

[0042] A verification module is used to simulate and verify the test stimulus to determine whether the test stimulus triggers the corresponding cover point; if the cover point is not triggered, determine the failure type of the test stimulus that does not trigger the corresponding cover point; make adjustments based on the failure type, and regenerate the test stimulus corresponding to the cover point until the cover point is triggered.

[0043] In a third aspect, an embodiment of the present application provides a control device comprising a processor and a memory, wherein the memory is used to store programs, instructions or codes, and the processor is used to execute the programs, instructions or codes in the memory to complete the method for generating integrated circuit test stimuli as described in any one of the first aspects.

[0044] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium storing a computer program, which is loaded by a processor to execute the method for generating integrated circuit test stimuli as described in the first aspect.

[0045] The present application provides a method for generating integrated circuit test stimuli and related equipment. The method parses the coverpoint code file and the RTL file, and obtains the input signal combination that triggers each coverpoint based on the logical relationship between the coverpoints in the coverpoint code file and the RTL file, and then generates test stimuli based on the input signals. This greatly reduces manual participation and improves overall test efficiency. In addition, the method accurately derives the input signal combination based on the logical relationship between the coverpoints and the RTL file, generates a test stimulus that matches it, and improves the accuracy and comprehensiveness of the test stimulus generation, thereby comprehensively detecting the functions of the integrated circuit and improving the accuracy of the test. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0047] Figure 1 A flowchart of a method for generating integrated circuit test stimuli provided in an embodiment of the present application;

[0048] Figure 2 A flowchart of another method for generating integrated circuit test stimuli provided in an embodiment of the present application;

[0049] Figure 3 A flowchart for determining an input signal combination provided in an embodiment of the present application;

[0050] Figure 4 A schematic diagram of a software module of a controller provided in an embodiment of the present application. DETAILED DESCRIPTION

[0051] Typically, integrated circuit verification engineers manually extract coverage points from the design verification plan and then develop test stimuli based on the verification plan. This not only requires verification engineers to spend a significant amount of time and effort developing the test stimuli, but also requires time to debug the test stimuli to compensate for the lack of accuracy associated with manual development.

[0052] To address this technical problem, an embodiment of the present application provides a method for generating integrated circuit test stimuli and related equipment. This method parses the coverpoint code file and the register transfer level (RTL) design file, and obtains the input signal combination that triggers each coverpoint based on the coverpoints in the coverpoint code file and the logical relationship in the RTL file, and then generates test stimuli based on the input signals. This greatly reduces manual participation and improves overall testing efficiency. In addition, the method accurately derives the input signal combination based on the logical relationship between the coverpoints and the RTL file, generates a test stimulus that matches it, and improves the accuracy and comprehensiveness of the test stimulus generation, thereby comprehensively detecting the functions of the integrated circuit and improving the accuracy of the test.

[0053] In order to help those skilled in the art better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0054] See also Figure 1 , which is a flow chart of a method for generating integrated circuit test stimuli provided by an embodiment of the present application. This method can be executed by a controller in an electronic device or by other devices with computing capabilities. The following description uses the controller as the execution subject. The method includes:

[0055] S101: The controller obtains a coverpoint code file of an integrated circuit and an RTL file corresponding to the coverpoint code file.

[0056] Coverage code files are used to define integrated circuit verification targets, typically written in hardware description languages ​​such as SystemVerilog (SV). Coverpoints are key checkpoints used to measure the completeness of an integrated circuit. They can also be understood as describing key test scenarios for the integrated circuit. During IC testing and verification, test stimuli are used to trigger the IC to reach the required test scenarios, thereby triggering the coverpoints.

[0057] In an embodiment of the present application, a coverpoint code file includes at least one coverpoint. A coverpoint is used to define a corresponding target signal and a target value of the target signal. It is understood that the target signal and the target value of the target signal defined by the coverpoint correspond to the scenario to be tested described by the coverpoint. Based on the target signal and the target value of the target signal, a corresponding input signal combination can be derived, and the input signal combination is used to drive the integrated circuit to implement the test scenario described by the coverpoint.

[0058] The target signal defined by a coverage point can be one or more target signals, that is, a group of target signals. Correspondingly, the target value of the target signal defined by the coverage point refers to the target value of each target signal defined by the coverage point.

[0059] RTL files are the core design files of integrated circuits and are usually written in Verilog or VHDL. RTL files are used to record the logical relationships between the internal signals of the integrated circuit.

[0060] The logical relationship between signals within an integrated circuit can also be understood as the operation rules between signals, such as the signal conversion relationship implemented by modules such as logic gates, adders, or state machines.

[0061] Internal signals of an integrated circuit include input signals, intermediate signals, and output signals. Input signals refer to control signals or data signals transmitted from external devices to the integrated circuit, intermediate signals refer to signals output by the internal logic units of the integrated circuit, and output signals refer to signals output by the integrated circuit to the outside.

[0062] It is important to note that the type of the enable signal (en) must be determined based on its definition in integrated circuit design. The enable signal can be an input signal or an intermediate signal.

[0063] If the enable signal is input from outside the integrated circuit, for example, provided by a controller, host computer, or other device external to the integrated circuit to control the startup or shutdown of a module within the integrated circuit, the enable signal is an input signal. If the enable signal is generated by the internal logic of the integrated circuit, for example, generated by the output of an internal state machine, counter, or other module within the integrated circuit to control other modules within the chip, the enable signal is an intermediate signal.

[0064] S102: The controller parses the coverpoint code file and the RTL file, and obtains an input signal combination that triggers each coverpoint according to at least one coverpoint and a logical relationship.

[0065] The controller can perform structural analysis on the coverpoint code file using an automated tool (such as a compiler or a syntax analyzer) to extract each coverpoint from the coverpoint code file. Furthermore, the controller can extract the logical relationship of the internal signals of the integrated circuit from the RTL file.

[0066] For each cover point, the controller determines the corresponding input signal combination based on the logical relationship between the integrated circuit's internal signals. The input signal combination includes at least one input signal and the values ​​of each input signal. Driving the integrated circuit based on the input signal combination triggers the cover point.

[0067] As an example, if the cover point is "data_out=8'hFF", and "data_out=in1+in2" is defined in the RTL file, and when "in1=8'hAA,in2=8'h55", "data_out=8'hFF" can be made, then the input signal combination that triggers the cover point can be "in1=8'hAA,in2=8'h55".

[0068] The controller parses the coverpoint code file and RTL file to infer the input signals required to trigger the coverpoints and determine the corresponding input signal combinations. Step S102 converts the abstract coverpoints into concrete, actionable input signal combinations, providing a direct basis for subsequent test stimulus generation. This replaces the manual derivation of input signals and avoids derivation errors or omissions caused by complex RTL file logic.

[0069] S103: The controller generates corresponding test stimuli according to each input signal combination.

[0070] Test stimulus describes the signal sequence used to drive the operation of an integrated circuit. Essentially, it represents the timing and coding of input signal combinations. For example, a test stimulus might be in1 = 0xAA and in2 = 0x55 at the rising edge of the clock. There is a one-to-one correspondence between input signal combinations and test stimulus.

[0071] The testbench's signal-driven code is the specific implementation of the test stimulus. This code can be directly integrated into the testbench of an integrated circuit. By running this code, the testbench can drive the integrated circuit to trigger coverage points.

[0072] In related technologies, verification engineers must manually derive input signal combinations based on coverpoints, write test stimuli, and repeatedly debug them. However, the present invention provides a method that combines the logical relationships in the RTL file with the coverpoints to reversely derive input signal combinations, thereby obtaining the test stimuli corresponding to each coverpoint. This method eliminates the repetitive work of verification engineers, significantly reduces the time and cost of test stimulus development, and shortens the integrated circuit verification cycle.

[0073] Furthermore, when manually deducing input signal combinations, key signals can be missed due to the complex logic of RTL files and the cumbersome coverpoints, resulting in the test stimulus failing to cover the corresponding coverpoints. This method, through structured analysis of the coverpoint code files and RTL files, reverse-infers the input signal combinations based on logical relationships. This ensures that the generated test stimulus meets the coverage requirements of the coverpoints documented in the coverpoint code files, improving the accuracy and comprehensiveness of IC verification.

[0074] In order to test the integrated circuit using the test stimulus, after generating the test stimulus according to the input signal combination, the controller can generate a signal driving code for the test platform according to the test stimulus.

[0075] In one possible implementation, Figure 2 As shown, after step S103, the method further includes:

[0076] S104: The controller generates corresponding signal driving code according to the test stimulus, and embeds the signal driving code into the test platform.

[0077] The test stimulus is essentially a logical description of the input signal combination and the values ​​of each input signal, while the signal driver code is the specific code implementation of the test stimulus. The controller needs to convert the test stimulus into a code format supported by the test platform, that is, convert the test stimulus into the corresponding signal driver code.

[0078] Signal driver code is used to apply input signals to the input terminals of the integrated circuit in the testbench. This signal driver code must conform to the testbench's syntax specifications. This signal driver code can include signal assignment statements and timing control statements. Signal assignment statements define the specific values ​​of the input signals, while timing control statements define the timing for signal application. By designing timing control statements, signals can be applied at the correct time, meeting the timing requirements of the integrated circuit and avoiding test failures caused by signal timing errors.

[0079] A test platform is a virtual environment used to verify the functionality of integrated circuits (ICs). It is typically written in code. For example, a test platform may include a stimulus generation module, a chip under test (CUT), and a signal monitoring module. The test platform simulates actual integrated circuit operating scenarios, applying input signals and collecting output signals to determine whether the IC meets design requirements.

[0080] After the controller converts the test stimulus into a signal-driven code that conforms to the syntax specification, the controller can embed the signal-driven code into the test platform through a preset interface or template, so that the signal-driven code runs automatically when the test is started.

[0081] The embodiment of the present application converts an abstract test stimulus into an executable signal-driven code, so that the test stimulus can be recognized and run by the test platform, thereby realizing the test verification of the integrated circuit.

[0082] In the method provided in the embodiment of the present application, the input signal combination corresponding to each cover point can be obtained based on the cover point code file and the RTL file, which reduces the dependence on the professional skills of the verification engineer and simplifies the verification process.

[0083] For ease of understanding, the specific implementation of step S102 will be further introduced below.

[0084] In one possible implementation, Figure 3 As shown, step S102 includes:

[0085] S1021: The controller parses the cover point code file to identify the target signal corresponding to each cover point and the target value of the target signal.

[0086] Coverpoints are used to define target signals and target values ​​of target signals. The controller can determine the coverpoints recorded in the coverpoint code file by parsing the coverpoint code file, and then determine the target signal and target value defined by the coverpoint based on the coverpoint.

[0087] A cover point is used to define at least one target signal and at least one target value of the target signal. For ease of understanding, the present embodiment of the application takes an example in which a cover point defines a target signal and a target value of the target signal.

[0088] S1022: The controller determines the type of each target signal based on the RTL file.

[0089] After identifying the target signal and target value corresponding to a coverage point, the controller needs to determine the target signal's type. The target signal's type characterizes its position within the integrated circuit's internal signal logic. The RTL file, which documents the relationships within the integrated circuit's internal signals, can be used to determine the target signal's type.

[0090] The controller determines the type of target signal to provide a basis for the logical deduction of subsequent steps, so as to adopt an adaptive processing method for different types of target signals.

[0091] S1023: The controller determines the input signal combination of each coverage point according to the type of each target signal and the logical relationship recorded in the RTL file.

[0092] The controller combines the target signal type and the logical relationship recorded in the RTL file to convert the target signal and target value defined by the coverpoint into an input signal combination that can be directly applied to the input end of the integrated circuit, and establishes the relationship between the coverpoint and the test stimulus.

[0093] The controller determines the input signal combination in different ways depending on the type of the target signal. In the embodiment of the present application, the types of the target signal include input signal, intermediate signal and output signal.

[0094] Input signals are signals input from outside the integrated circuit and are declared as input in the module port list of the RTL file.

[0095] Intermediate signals are signals generated by the internal logic of the integrated circuit and are only declared inside the RTL file. The value of the intermediate signal is determined by the internal logic of the integrated circuit.

[0096] The output signal is a signal output by the integrated circuit to the outside. It is declared as output in the module port list of the RTL file. The value of the output signal is also determined by the internal logic of the integrated circuit.

[0097] It's easy to see that the input signal is directly input from outside the integrated circuit and does not undergo any internal logic operations. The intermediate signal and output signal are both the result of the input signal undergoing internal logic operations. The intermediate signal is the intermediate result, while the output signal is the final output of the integrated circuit.

[0098] When the target signal is the input signal, there is no need to derive the target signal, and the value of the target signal defined by the coverage point can be directly used as the input signal combination.

[0099] When the target signal is an intermediate signal or output signal, the target signal must be reverse-derived based on the logic relationships within the integrated circuit (IC) as described in the target RTL file to obtain the input signal combination. This input signal combination, after undergoing internal logic operations within the IC, can achieve the target value.

[0100] In one possible implementation, reverse deduction of the target signal is performed based on the logical relationship recorded in the RTL file, including:

[0101] Locate the assignment logic of the target signal in the RTL file and extract the upstream signal combination involved in the assignment logic;

[0102] Establishing a mapping relationship between a target value of a target signal and a value of an upstream signal combination based on an assignment logic;

[0103] The value of the upstream signal combination that makes the target signal meet the target value is derived according to the mapping relationship, and the input signal combination is traced back according to the value of the upstream signal combination.

[0104] Assignment logic is the logic for determining the value of a target signal as described in the RTL file. It also relates the value of the target signal to the values ​​of other signals. In the RTL file, assignment logic can be represented as code statements that determine the value of the target signal. Examples include continuous assignment statements, procedural assignment statements, and conditional assignment statements.

[0105] The upstream signal combination refers to the set of signals that directly participate in the target signal value calculation in the assignment logic. For example, in data_out=in1+in2, the upstream signal combination is {in1, in2}, and the target signal is data_out.

[0106] A mapping relationship is the correspondence between the target value of a target signal and the value of the upstream signal combination. This mapping relationship can also be understood as the inverse of the assignment logic. For example, if the assignment logic is data_out = in1 + in2 and the target value is data_out = 5, then the mapping relationship is in1 + in2 = 5.

[0107] The controller uses the location assignment logic to locate all upstream signals that determine the target signal's value. It then establishes a mapping relationship between the target signal's target value and the values ​​of the upstream signal combination. This translates the forward calculation rules of the assignment logic into reverse query rules, clarifying the upstream signal values ​​that ensure the target signal meets the target value. Finally, based on this mapping relationship, the controller reverse-infers the upstream signal values ​​and ultimately locates the directly controllable input signal, completing the conversion from the target signal's target value to the input signal combination.

[0108] In one possible scenario, the value of an output signal or intermediate signal may be affected by multiple signals, and there may be multiple combinations of input signals that result in the same output signal or intermediate signal. In this case, the assignment logic may indicate that multiple upstream signal combinations can all make the target signal meet the target value.

[0109] In an embodiment of the present application, when the assignment logic represents that multiple groups of upstream signal combinations can make the target signal meet the target value, multiple groups of upstream signal combinations that can make the target signal meet the target value are determined, and a mapping relationship between the target value of the target signal and the value of each group of upstream signal combinations is established.

[0110] When the target signal's assignment logic allows for multiple signal value combinations that can all satisfy the target signal's coverage point's target value, each signal value combination constitutes a set of upstream signal combinations. For example, if the target signal out's assignment logic is out=a|b (an "OR" operation) and the target value is out=1, then the upstream signal combinations {a=1,b=0}, {a=0,b=1}, and {a=1,b=1} can all satisfy the target value. In other words, multiple upstream signal combinations can all satisfy the target signal's target value.

[0111] When there are multiple sets of upstream signal combinations that can make the target signal meet the target value, the mapping relationship is no longer one-to-one, but one-to-many, that is, the target value of the target signal corresponds to the values ​​of multiple sets of upstream signal combinations (for example, out=1 corresponds to [{a=1,b=0},{a=0,b=1},{a=1,b=1}]).

[0112] By identifying all possible upstream signal combinations, we can avoid missing a combination that could lead to incomplete input signal combinations. This provides sufficient evidence for subsequent tracing and improves the comprehensiveness of verification.

[0113] Moreover, in the process of generating input signal combinations based on upstream signal combinations, if there is a situation where the target signal corresponds to multiple groups of upstream signal combinations, it is necessary to reversely deduce the corresponding input signal combination for each group of upstream signal combinations, and then generate corresponding test stimuli based on each group of input signal combinations. Finally, multiple test stimuli corresponding to the same coverage point are obtained.

[0114] When a coverpoint code file records multiple coverpoints, at least one test stimulus is generated for each coverpoint, thereby improving the accuracy and comprehensiveness of integrated circuit testing.

[0115] As an example, if the assignment logic is as follows:

[0116] Input b,d; / / define input

[0117] Output a; / / Define output

[0118] Logic c; / / Intermediate variable

[0119] assign a=b&c:

[0120] always_ff @(posedge clk) begin

[0121] c=!rst_n ? 1'b0 : d;

[0122] …

[0123] end

[0124] …

[0125] As an example, assume that output signal a = 0. When back-deriving and analyzing the statement assign a = b & c, the value of output signal a depends on this statement. This statement indicates that when a = 0, either b = 0 or c = 0 is required.

[0126] b is used as an input signal, and a feasible input signal combination can be directly recorded: %a_0=("b"≥0).

[0127] c is an intermediate signal and requires further reverse deduction. When analyzing the statement c = !rst_n ? 1'b0 : d, the value of intermediate signal c depends on the statement. Specifically, when c = 0, rst_n = 0 is required, or, alternatively, rst_n = 1 and d = 0. In this case, the code statement for a = 0 can be expressed as %a_0 = ("b" ≥ 0, "rst_n" ≥ 0, "comb1" ≥ {"rst_n" ≥ 1, "d" ≥ 0}).

[0128] Since a = 0 only requires either b = 0 or c = 0, the code statement for a = 0 can be expressed as %a_0=("comb1"≥{"b"≥0,"rst_n"≥"?","d"≥"?"},"comb2"≥{"rst_n"≥"0","b"≥"?","d"≥"?"},"comb3"≥{"rst_n"≥"1","b"≥"?","d"≥"1"}). The "?" in the code statement indicates that the signal value can be random. At this point, all input signal combinations corresponding to the output signal a = 0 are obtained.

[0129] As another example, suppose output signal a = 1. When back-deriving and analyzing the statement assign a = b & c, the value of output signal a depends on this statement. This statement states that when a = 0, b = 1 and c = 1 are required.

[0130] b is the input signal, directly recorded as a required signal: %a_1=("comb1"≥{"b"≥1}). It also requires c=1. c is the intermediate signal. Continue the reverse deduction of c to determine its value: c=!rst_n ? 1'b0:d. Furthermore, this statement is contained within the always_ff block. This means that b must remain at 1 for one cycle after d reaches 1. That is, when c=1, rst_n=1 and d=1, and b must also remain at 1 for one cycle.

[0131] Here, a = 1 requires that both b = 1 and c = 1 are 1. The code for a = 0 is represented as %a_1=("comb1"≥{"b"≥1,"rsn_n"≥"1","d"≥"1","cycle1"≥"1"}). This gives us all the input signal combinations that correspond to the output signal a = 1.

[0132] To further improve the accuracy and reliability of the test stimulus, the method further includes:

[0133] Performing simulation verification on the test stimulus to determine whether the test stimulus triggers a corresponding coverage point;

[0134] In the case that the cover point is not triggered, determining a failure type of the test stimulus that does not trigger the corresponding cover point;

[0135] Adjustments are made according to the failure type, and the test stimulus corresponding to the cover point is regenerated until the cover point is triggered.

[0136] The controller can input the signal driving code corresponding to the test stimulus into the Electronic Design Automation (EDA) simulation tool, and virtually run the generated test stimulus through the EDA simulation tool to simulate the working state of the integrated circuit under the test stimulus, and collect and analyze the signal changes of the integrated circuit.

[0137] EDA simulation tools automatically compare the target signal values ​​output by the IC simulation with the target values ​​defined by the coverpoint to determine the coverage status of the coverpoint. If the target signal values ​​output by the simulation match the target values ​​defined by the coverpoint, the coverpoint is triggered. If the target signal values ​​output by the simulation differ from the target values ​​defined by the coverpoint, the coverpoint is not triggered.

[0138] There may be two situations where the cover point is not triggered. First,

[0139] When the coverage point is not covered, step S102 may be re-executed to modify the input signal combination derived in step S102 so that it can trigger the target value of the target signal during re-simulation.

[0140] The method for generating integrated circuit test stimulus provided in the embodiment of the present application can also be executed by a software module in the controller, specifically, Figure 4 As shown, the software modules in the controller for implementing the method may include an analyzer, an inverse inference module, and an excitation generator.

[0141] The parser is responsible for performing structural analysis on the coverpoint code file and the RTL file, extracting the coverpoints in the coverpoint code file and the logical relationship between the internal signals of the integrated circuit recorded in the RTL file.

[0142] The backpropagator is used to convert the target requirements of the coverpoint into a directly controllable input signal combination based on the results obtained by the parser. The backpropagator determines the type of target signal in the coverpoint based on the logical relationships documented in the RTL file. If the target signal is an input signal, its target value is directly used as the input signal combination. If the target signal is an intermediate signal or output signal, the backpropagator traces back from the target value of the target signal based on the logical relationships documented in the RTL file. Starting from the target value of the target signal, the values ​​of the upstream signals are deduced through the assignment logic, and then traced back layer by layer to the input signal, ultimately obtaining the input signal combination that can trigger the target value.

[0143] The stimulus generator is used to convert the input signal combination obtained by the backpropagator into executable test code and complete the integration with the test platform.

[0144] The stimulus generator can convert the input signal combination into signal-driven code that conforms to the testbench syntax specification, and integrate the generated signal-driven code into the testbench so that the signal-driven code can be called during simulation.

[0145] It should be noted that if the test stimulus still fails to trigger the corresponding cover point coverage after repeatedly executing step S102, it is possible to check whether the parser, inverse analyzer and stimulus generator need to be updated or repaired to ensure the accuracy of the test stimulus generation.

[0146] The method provided in the embodiment of the present application is applicable to all types of integrated circuits, and when the integrated circuit design changes, it is only necessary to update the coverpoint code file and the RTL file, and the method can regenerate the corresponding test stimulus without the need for a large amount of manual design and debugging. It responds quickly to design changes and has strong adaptability. Moreover, the method performs unified parsing and test stimulus generation based on the coverpoint code file and the RTL file, providing a standardized process for integrated circuit testing. Different testers and projects can follow the same method to generate test stimuli, reducing test differences caused by human differences, which is conducive to establishing a standardized test system and improving the reliability and repeatability of the test.

[0147] Based on the above method embodiment, the embodiment of the present application further provides a device for generating integrated circuit test stimuli, the device comprising:

[0148] an acquisition module, configured to acquire a coverpoint code file of an integrated circuit and a register transfer level (RTL) file corresponding to the coverpoint code file; the coverpoint code file includes at least one coverpoint; and the RTL file is configured to record the logical relationship between internal signals of the integrated circuit;

[0149] a parsing module, configured to obtain, according to at least one of the cover points and the logical relationship, a combination of input signals that trigger each of the cover points;

[0150] A generation module is used to generate corresponding test stimuli according to each combination of the input signals; the test stimuli are used to generate signal driving codes of the test platform, and the signal driving codes are used to drive the integrated circuit to trigger the coverage of the coverage points.

[0151] In one possible implementation, the parsing module is specifically configured to parse the cover point code file, identify the target signal corresponding to each cover point and the target value of the target signal; determine the type of each target signal based on the RTL file; and determine the input signal combination of each cover point according to the type of each target signal and the logical relationship recorded in the RTL file.

[0152] In a possible implementation, the signal type of the target signal includes an input signal, an intermediate signal, or an output signal;

[0153] The parsing module is specifically used to, when the target signal is an input signal, use the target signal and the target value corresponding to the target signal as an input signal combination; when the target signal is an intermediate signal or an output signal, reversely deduce the target signal according to the logical relationship recorded in the RTL file to obtain an input signal combination that makes the target signal meet the target value.

[0154] In one possible implementation, the parsing module is specifically used to locate the assignment logic of the target signal in the RTL file and extract the upstream signal combination involved in the assignment logic; establish a mapping relationship between the target value of the target signal and the value of the upstream signal combination based on the assignment logic; determine the value of the upstream signal combination that makes the target signal meet the target value according to the mapping relationship, and obtain the input signal combination according to the value of the upstream signal combination.

[0155] In one possible implementation, the parsing module is specifically used to establish a mapping relationship between the target value of the target signal and the values ​​of each group of upstream signal combinations when the assignment logic represents that multiple groups of upstream signal combinations can make the target signal meet the target value.

[0156] In one possible implementation, the generation module is also used to convert the input signal combination corresponding to the test stimulus into a signal-driven code that conforms to the syntax specification of the test platform; embed the signal-driven code into the test platform; the signal-driven code includes a signal assignment statement and a timing control statement; the signal assignment statement is used to define the specific value of the input signal, and the timing control statement is used to define the time node of the signal application.

[0157] In a possible implementation, the device further includes a verification module;

[0158] A verification module is used to simulate and verify the test stimulus to determine whether the test stimulus triggers the corresponding cover point; if the cover point is not triggered, determine the reason why the test stimulus does not trigger the corresponding cover point, and make adjustments based on the reason until the cover point is triggered.

[0159] In a possible implementation manner, an embodiment of the present application further provides a control device.

[0160] The control device may include a memory and a processor. The memory may be a random access memory (RAM), flash memory, read only memory (ROM), EPROM memory, non-volatile read only memory (EPROM), register, hard disk, removable disk, etc.

[0161] The memory can store computer instructions. When the computer instructions stored in the memory are executed by the processor, the processor can be used to execute the method for generating integrated circuit test stimulus. The memory can also store data.

[0162] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When software is used for implementation, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, computer, server or data center to another website, computer, server or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrations. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), or a semiconductor medium (e.g., a solid-state drive (SSD)).

[0163] The present application also provides a readable storage medium for storing the methods provided in the above embodiments, such as a random access memory (RAM), flash memory, read-only memory (ROM), EPROM, electronic programmable ROM (EPROM), register, hard disk, removable disk, or any other form of storage medium known in the art.

[0164] The "first" and "second" (if any) in the names mentioned in the embodiments of this application are only used as name identifiers and do not represent the first or second in order.

[0165] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from the other embodiments. Similar or identical parts between the various embodiments can be referred to in conjunction with each other. The methods disclosed in the embodiments are described briefly because they correspond to the product embodiments disclosed in the embodiments. For relevant details, refer to the description of the product embodiments.

[0166] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for generating an integrated circuit test stimulus, characterized in that: The method comprises: Obtaining a coverpoint code file of an integrated circuit and a register transfer level (RTL) file corresponding to the coverpoint code file; the coverpoint code file includes at least one coverpoint; the RTL file is used to record the logical relationship of internal signals of the integrated circuit; Obtaining an input signal combination that triggers each of the cover points according to at least one of the cover points and the logical relationship; A corresponding test stimulus is generated according to each combination of the input signals; the test stimulus is used to drive the integrated circuit to trigger the cover point.

2. The method according to claim 1, characterized in that The obtaining, according to at least one of the cover points and the logical relationship, a combination of input signals that trigger each of the cover points, comprises: Parsing the cover point code file to identify target signals corresponding to each cover point and target values ​​of the target signals; Determining the type of each target signal based on the RTL file; The input signal combination of each of the cover points is determined according to the type of each of the target signals and the logical relationship recorded in the RTL file.

3. The method according to claim 2, characterized in that The signal type of the target signal includes an input signal, an intermediate signal or an output signal; Determining an input signal combination of the cover point according to the type of the target signal and the logical relationship recorded in the RTL file includes: In a case where the target signal is an input signal, the target signal and a target value corresponding to the target signal are used as an input signal combination; In the case where the target signal is an intermediate signal or an output signal, the target signal is reversely deduced according to the logical relationship recorded in the RTL file to obtain an input signal combination that enables the target signal to meet the target value.

4. The method according to claim 3, characterized in that The reverse deducing of the target signal according to the logical relationship recorded in the RTL file includes: Locating the assignment logic of the target signal in the RTL file, and extracting the upstream signal combination in the assignment logic; Establishing a mapping relationship between a target value of the target signal and a value of the upstream signal combination based on the assignment logic; The value of the upstream signal combination that enables the target signal to meet the target value is determined according to the mapping relationship, and the input signal combination is obtained according to the value of the upstream signal combination.

5. The method according to claim 4, characterized in that The establishing, based on the assignment logic, a mapping relationship between the target value of the target signal and the value of the upstream signal combination includes: When the assignment logic indicates that multiple groups of upstream signal combinations can make the target signal meet the target value, a mapping relationship is established between the target value of the target signal and the values ​​of each group of upstream signal combinations.

6. The method according to claim 1, characterized in that The method further comprises: Converting the test stimulus corresponding input signal combination into a signal driving code that conforms to the syntax specification of the test platform; The signal driving code is embedded in the test platform; the signal driving code includes a signal assignment statement and a timing control statement; the signal assignment statement is used to define the specific value of the input signal, and the timing control statement is used to define the time node of signal application.

7. The method according to claim 1, characterized in that The method further comprises: Performing simulation verification on the test stimulus to determine whether the test stimulus triggers a corresponding coverage point; In the case that the cover point is not triggered, determining a failure type of the test stimulus that does not trigger the corresponding cover point; Adjustments are made according to the failure type, and the test stimulus corresponding to the cover point is regenerated until the cover point is triggered.

8. A device for generating an integrated circuit test stimulus, characterized in that: The device comprises: an acquisition module, configured to acquire a coverpoint code file of an integrated circuit and a register transfer level (RTL) file corresponding to the coverpoint code file; the coverpoint code file includes at least one coverpoint; and the RTL file is configured to record the logical relationship between internal signals of the integrated circuit; a parsing module, configured to parse the coverpoint code file and the RTL file, and obtain an input signal combination that triggers each coverpoint according to at least one coverpoint and the logical relationship; A generation module is used to generate corresponding test stimuli according to each combination of the input signals; the test stimuli are used to generate signal driving codes of the test platform, and the signal driving codes are used to drive the integrated circuit to trigger the coverage of the coverage points.

9. A control device, characterized in that: It includes a processor and a memory, the memory is used to store programs, instructions or codes, and the processor is used to execute the programs, instructions or codes in the memory to complete the method for generating integrated circuit test stimulus as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that A computer program is stored, and the computer program is loaded by a processor to execute the method for generating integrated circuit test stimulus according to any one of claims 1 to 7.

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