Method, product and device for etching simulation of layout patterns

Abstract

The application provides a layout pattern etching simulation method, product and equipment. The method comprises the following steps: obtaining a target process flow and an initial layout pattern operated by the target process flow; determining a plurality of etching operations in the target process flow, and obtaining a corresponding stage etching model for each etching operation; performing simulation processing on the etching operation through the stage etching model; inputting a simulation result of the simulation processing of the stage etching model into a final etching model, and fitting the simulation result by using the final etching model to obtain a final simulation result corresponding to the target process flow. According to the method, a corresponding composite etching model can be established according to the target process flow, and the target process flow is simulated through the composite etching model, so that the influence between each etching operation in the target process flow is comprehensively considered, and finally an accurate simulation result is obtained for subsequent detection.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method, product, and equipment for etching simulation of layout patterns. Background Technology

[0002] In the current semiconductor technology field, the most crucial step in semiconductor chip manufacturing is transferring the chip's design pattern onto a silicon wafer. Among the many process steps in chip manufacturing, photolithography and etching are the most directly related to pattern transfer. Both photolithography and etching processes introduce deviations, resulting in differences between the lithographic and etched patterns and the mask pattern. Therefore, when designing the mask pattern, it is necessary to compensate for photolithographic and etching deviations. Currently, optical proximity correction (OPC) is primarily used to compensate for photolithographic deviations. For etching deviations, the current approach mainly involves establishing an etching deviation table to store the etching deviations corresponding to different patterns. Then, based on the corresponding pattern style, the corresponding etching deviation is matched to the etching deviation table. For example, the corresponding etching deviation can be determined based on the line width and spacing of the current polygon's edges; thus, etching deviation compensation is completed.

[0003] However, etching differs from photolithography in that its physical and chemical processes are far more complex. For patterns with varying linewidths and spacings, etching deviations will differ. For simple patterns, current methods based on etching deviation tables are applicable. However, in actual production, the line density of the pattern also affects etching deviation. For complex patterns, current methods based on etching deviation tables are difficult to use effectively, leading to inaccurate determination of etching deviations and ultimately resulting in mask patterns that fail to meet practical requirements. Summary of the Invention

[0004] In view of the above problems, the present invention proposes an etching simulation method, product and equipment for layout patterns that overcomes or at least partially solves the above problems.

[0005] One objective of this invention is to establish a composite etching model that can comprehensively consider the influence between various etching operations in the target process flow;

[0006] Another further objective of this invention is to improve the accuracy of simulations of complex etching processes.

[0007] Specifically, the present invention provides an etching simulation method for a layout pattern, comprising:

[0008] Obtain the initial layout graphics of the target process flow and the operation of the target process flow;

[0009] Identify multiple etching operations in the target process flow and obtain the stage etching model corresponding to each etching operation;

[0010] The etching operation was simulated using a staged etching model.

[0011] The simulation results of the stage etching model simulation are input into the final etching model, and the simulation results are fitted using the final etching model to obtain the final simulation results corresponding to the target process flow.

[0012] Optionally, the etching operation includes a dependent etching operation, which corresponds to a dependent stage etching model. The dependent stage etching model is used to perform simulation processing based on the simulation results of the preceding operations on which the dependent etching operation depends.

[0013] The steps for simulating etching operations using a staged etching model include:

[0014] When the etching operation is a dependent etching operation, determine the target preceding operation that the dependent etching operation depends on;

[0015] Obtain the etching model of the preceding stage corresponding to the target preceding operation, and perform simulation processing on the target preceding operation through the etching model of the preceding stage to obtain the preceding simulation result.

[0016] Obtain the dependent stage etching model corresponding to the dependent etching operation, and input the previous simulation results into the dependent stage etching model for simulation processing.

[0017] Optionally, the target preceding operation includes the preceding etching operation and the preceding process operation between the preceding etching operation and the dependent etching operation;

[0018] The steps for obtaining the simulation results of the preceding operations by simulating the target preceding operations using the preceding stage etching model include:

[0019] The preceding stage etching model was used to simulate the preceding etching operation and obtain the preceding etching results.

[0020] The preceding logical operation result is obtained by performing process logic operations on the preceding etching result based on the preceding process operation;

[0021] The preceding etching results and the preceding logic operation results are combined to form the preceding simulation results.

[0022] Optionally, the steps of inputting the preceding simulation results into the dependent stage etching model for simulation processing include:

[0023] Obtain the preceding etching profile corresponding to the preceding simulation results;

[0024] The preceding etch contour is transformed using a preset curve mask sampling method to obtain the preceding mask image;

[0025] The preceding mask image is input into the dependent stage etching model for simulation processing.

[0026] Optionally, the etching operation also includes an independent etching operation, which corresponds to an independent stage etching model. The independent stage etching model is used for simulation processing based on the initial layout pattern.

[0027] The steps for simulating etching operations using a staged etching model include:

[0028] When the etching operation is an independent etching operation, obtain the independent stage etching model corresponding to the independent etching operation, and input the initial layout graphic into the independent stage etching model for simulation processing.

[0029] Optionally, the steps of fitting the simulation results to obtain the final simulation results corresponding to the target process flow using the final etching model include:

[0030] Obtain the dependent simulation results corresponding to the dependent stage etching model and the independent simulation results corresponding to the independent stage etching model;

[0031] Based on the target process flow, process logic operations are performed on the dependent simulation results and the independent simulation results to obtain preprocessed results;

[0032] The preprocessing results, dependent simulation results, and independent simulation results are input into the final etching model for simulation processing to obtain the final simulation results.

[0033] Optionally, the steps of inputting preprocessing results, dependent simulation results, and independent simulation results into the final etching model for simulation processing to obtain the final simulation results include:

[0034] Obtain the etching profiles corresponding to the preprocessing results, dependent simulation results, and independent simulation results respectively;

[0035] The etched contour is transformed using a preset curve mask sampling method to obtain a mask image;

[0036] The mask image is input into the final etching model for simulation processing to obtain the final simulation result.

[0037] Optionally, after the step of fitting the simulation results using the final etching model to obtain the final simulation results corresponding to the target process flow, the method further includes:

[0038] The final simulation results are used to detect bad pixels, and the results are used to determine whether the initial layout graphics meet the preset requirements.

[0039] According to another aspect of the present invention, a computer program product is also provided, comprising a computer program that, when executed by a processor, implements the steps of the etching simulation method for any of the above-described layout patterns.

[0040] According to another aspect of the present invention, a computer device is also provided, including a memory, a processor, and a machine-executable program stored in the memory and running on the processor, wherein the processor executes the machine-executable program to implement the steps of the etching simulation method for any of the above-described layout patterns.

[0041] The etching simulation method for the layout pattern of this invention first obtains the target process flow and the initial layout pattern of the target process flow operations; then, it identifies multiple etching operations in the target process flow and obtains a stage etching model corresponding to each etching operation; next, it simulates the etching operations using the stage etching model; finally, it inputs the simulation results of the stage etching model simulation into the final etching model, and uses the final etching model to fit the simulation results to obtain the final simulation result corresponding to the target process flow. This method can establish a corresponding composite etching model based on the target process flow, and simulate the target process flow using the composite etching model, thereby comprehensively considering the influence between various etching operations in the target process flow, and finally obtaining accurate simulation results for subsequent detection.

[0042] The above and other objects, advantages and features of the present invention will become more apparent to those skilled in the art from the following detailed description of specific embodiments of the invention in conjunction with the accompanying drawings. Attached Figure Description

[0043] The following sections will describe some specific embodiments of the invention in detail by way of example and not limitation, with reference to the accompanying drawings. The same reference numerals in the drawings denote the same or similar parts or portions. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings:

[0044] Figure 1 This is a schematic flowchart of an etching simulation method for a layout pattern according to an embodiment of the present invention;

[0045] Figure 2 This is a schematic diagram of a composite etching model architecture established by an etching simulation method for layout patterns according to an embodiment of the present invention.

[0046] Figure 3 This is a schematic diagram of a composite etching model architecture established by an etching simulation method for layout patterns according to another embodiment of the present invention.

[0047] Figure 4This is a schematic diagram of a computer program product according to an embodiment of the present invention;

[0048] Figure 5 This is a schematic diagram of a computer-readable storage medium according to an embodiment of the present invention; and

[0049] Figure 6 This is a schematic diagram of a computer device according to an embodiment of the present invention. Detailed Implementation

[0050] Those skilled in the art should understand that the embodiments described below are merely a part of the embodiments of the present invention, and not all of the embodiments of the present invention. These partial embodiments are intended to explain the technical principles of the present invention and are not intended to limit the scope of protection of the present invention. Based on the embodiments provided by the present invention, all other embodiments obtained by those skilled in the art without creative effort should still fall within the scope of protection of the present invention.

[0051] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus or device (such as a computer-based system, a processor-included system or other system that can fetch and execute instructions from, an instruction execution system, apparatus or device).

[0052] In the current semiconductor technology field, in the mainstream integrated circuit manufacturing process, photolithography involves exposing photoresist to light of a specific wavelength, causing a chemical change, and then transferring the pattern designed on the mask to the photoresist morphology on the silicon wafer through development. Etching, on the other hand, selectively removes unwanted material with the help of the photoresist morphology, ultimately creating the desired micro-patterns on the silicon wafer.

[0053] As chip technology nodes continue to evolve, the size of their design patterns has become much smaller than the wavelength of photolithography (193nm), leading to optical proximity effect and thus photolithography deviation. To compensate for this deviation, optical proximity correction (OPC) is required.

[0054] In the manufacturing process of integrated circuits, after photolithography, an etching process is required. Etching can cause etching deviations, meaning that the linewidth of the photoresist before and after etching is inconsistent. For example, when a wafer contains both sparse and dense patterns to be etched, the etching rate of the dense areas is lower than that of the sparse areas; this is called the micro-loading effect. Another example is in the etching of high aspect ratio structures, such as deep holes or trenches; the etching rate of smaller holes or trenches is lower than that of larger holes or trenches; this is called the aperture effect.

[0055] It is evident that different etching rates correspond to different areas. This not only leads to changes in the overall pattern size after etching, but more importantly, patterns of the same size obtained after photolithography will also have different sizes after etching. When designing mask patterns, etching deviations must be considered; otherwise, even if the size of the photolithographic pattern obtained after exposure meets expectations, it will still deviate from the target size after etching.

[0056] Currently, the main approach to address etching deviations is to create a Bis-Table to store the etching deviations corresponding to different graphics. Then, based on the corresponding graphic style, the appropriate etching deviation is matched against the Bis-Table. The current Bis-Table primarily determines the etching deviation based on the line width and spacing of the top edge of the current polygon. This is barely sufficient for simple graphics, but the accuracy of this traditional method decreases as the graphics become more complex.

[0057] For two edges with identical linewidth and spacing, different pattern densities around them will lead to different final etching deviations. Matching etching deviations using existing bias tables inevitably introduces errors. As semiconductor technology nodes evolve, the precision requirements for pattern transfer (photolithography and etching) become increasingly stringent; traditional methods cannot meet these demands. Furthermore, with the continuous evolution of semiconductor manufacturing technology nodes, when the patterning cycle is shorter, multiple patterning processes are required, meaning the transfer of patterns from the layout to the silicon wafer involves a combination of multiple patterning processes (photolithography + etching). At this point, a single etching model is insufficient for comprehensive defect prediction based on the results of multiple etching processes.

[0058] To address the aforementioned problems, this invention provides an etching simulation method for layout patterns, the specific process of which is as follows: Figure 1 As shown, Figure 1 This is a schematic flowchart of an etching simulation method for a layout pattern according to an embodiment of the present invention. The etching simulation method for the layout pattern includes at least the following steps S101 to S104.

[0059] Step S101: Obtain the target process flow and the initial layout pattern of the target process flow operation. The target process flow generally refers to a multi-patterning process, such as self-aligned double patterning (SADP), self-aligned reversed patterning (SARP), and double lithography (Litho-Etch-Litho–Etch, LELE).

[0060] Furthermore, taking the SARP process as an example, the final pattern is not formed by SARP itself, but rather by an added cutting process. In actual processing, there are multiple cutting layers, resulting in a final patterning outcome formed by multiple cuts on top of the SARP result. Similarly, the results of these multiple cuts influence each other during the etching process to form the final pattern, a factor that a single-step etching model cannot account for. Correspondingly, the LELE process also incorporates cutting processes due to practical needs, resulting in different types of multi-patterning processes such as LELE+CUT and LELELE+CUT.

[0061] Step S102: Determine multiple etching operations in the target process flow and obtain the stage etching model corresponding to each etching operation.

[0062] In some optional embodiments, etching operations generally include dependent etching operations and independent etching operations. Dependent etching operations correspond to a dependent stage etching model, which is generally used for simulation processing based on the simulation results of preceding operations on which the dependent etching operation depends. Independent etching operations correspond to an independent stage etching model, which is generally used for simulation processing based on the initial layout pattern. Dependent stage etching models typically need to consider the influence of preceding operations on the current stage operation, i.e., consider the mutual coupling relationship between the two, and therefore need to obtain the simulation results of the preceding operations. Independent stage etching models, on the other hand, typically do not consider the influence of preceding operations on the current operation and directly obtain the initial target pattern for simulation processing.

[0063] Taking the SARP process as an example, the first etching operation forms a mandrel (MDL) pattern. Spacer layers are then deposited on both sides of the MDL, and the gaps are filled to form a non-mandrel (NMDL) pattern. Finally, both the MDL and NMDL patterns are transferred to a hard mask through a second etching operation. The first and final etching processes differ slightly. The first etching is purely based on the results of the first lithography step, and modeling would be a single-step etching model. However, in the second etching, because the MDL pattern already exists, the final result is related to the previous etching results. Therefore, to model the second etching result for simulation and defect prediction, the modeling results of the first etching must be included, and their coupling relationship must be considered. Thus, the second etching operation is a dependent etching operation, and its corresponding etching model is a dependent stage etching model, while the first etching operation is a pre-process operation of the second etching operation.

[0064] It should be noted that the various stage etching models and the final etching model in this invention can be pre-trained or specifically established according to the specific process. Furthermore, to further improve the accuracy of the etching models, this invention introduces artificial intelligence (AI) into both the stage and final etching models. AI-assisted etching modeling can fit effects that cannot be captured by traditional modeling methods, resulting in higher accuracy and enabling the accurate determination of etching deviations. Those skilled in the art can determine the method of introducing AI according to the actual situation, such as adding neural networks to the etching model so that the corresponding etching model can autonomously simulate the corresponding simulation operation, or simulating each etching model through reinforcement learning, etc.

[0065] Step S103: Simulate the etching operation using a staged etching model.

[0066] Optionally, when the etching operation is a dependent etching operation, the steps of simulating the etching operation using a staged etching model generally include: determining the target preceding operation that the dependent etching operation depends on; obtaining the preceding staged etching model corresponding to the target preceding operation, and simulating the target preceding operation using the preceding staged etching model to obtain the preceding simulation result; obtaining the dependent staged etching model corresponding to the dependent etching operation, and inputting the preceding simulation result into the dependent staged etching model for simulation processing.

[0067] Taking the SARP process as an example, the first and second etching processes differ slightly. The first etching is purely based on the results of the first photolithography step, and any modeling would be a single-step etching model. However, in the second etching, because the MDL pattern already exists, the result of the second etching is related to the previous etching results. Therefore, if we want to model the second etching result for simulation defect prediction, we must incorporate the results of the first etching model and consider their coupling relationship, rather than simply using the photolithography result as input as in ordinary etching modeling.

[0068] Optionally, the target preceding operation includes the preceding etching operation and the preceding process operation between the preceding etching operation and the dependent etching operation; the step of simulating the target preceding operation using the preceding stage etching model to obtain the preceding simulation result generally includes: simulating the preceding etching operation using the preceding stage etching model to obtain the preceding etching result; performing process logic operation on the preceding etching result based on the preceding process operation to obtain the preceding logic operation result; and merging the preceding etching result and the preceding logic operation result as the preceding simulation result.

[0069] For example, the second etching operation in the SARP process is a dependent etching operation, while the first etching operation is a preceding operation to the second etching operation. The process operations between the first and second etching operations are considered preceding process operations, such as spacer layer deposition and gap filling operations after mandrel etching. Therefore, to establish a corresponding composite etching model based on the SARP process, it is necessary to first obtain the preceding stage etching model corresponding to the preceding etching operation, simulate the preceding etching operation to obtain the preceding simulation results, then perform process logic operations on the preceding simulation results based on the preceding process operations such as spacer layer deposition and gap filling to obtain the preceding logic operation results, and finally input the preceding simulation results and the preceding logic operation results into the dependent stage etching model corresponding to the second etching operation for simulation processing.

[0070] However, since models obtained through conventional modeling methods typically require the input of mask images, and the simulation results of each etching model in this invention are generally etching contours, this invention chooses to convert them into mask images. Specifically, the steps of inputting the preceding simulation results into the dependent-stage etching model for simulation processing generally include: obtaining the preceding etching contours corresponding to the preceding simulation results; converting the preceding etching contours into preceding mask images using a preset curve mask sampling method; and inputting the preceding mask images into the dependent-stage etching model for simulation processing. The specific operation of the preset curve mask sampling method can be to treat the etching contours as curve masks, and then convert the curve masks into mask images using the curve mask sampling method. This process of converting etching contours to mask images can be called the CMI process (Contour to Mask Image). Through the CMI process, multiple results from the preceding operations can be converted into mask images and input into the dependent-stage etching model for simulation processing. Those skilled in the art can determine the sampling logic and subsequent specific algorithms in the preset curve mask sampling method according to the actual situation.

[0071] Optionally, when the etching operation is an independent etching operation, the steps for simulating the etching operation using a staged etching model generally include: obtaining the independent staged etching model corresponding to the independent etching operation, and inputting the initial layout pattern into the independent staged etching model for simulation processing. Some possible examples of independent etching operations include: a cutting process (CUT) added after obtaining the SARP result in the SARP process. For such independent etching operations, the initial layout pattern can first be simulated using its corresponding independent staged etching model to obtain the corresponding independent simulation result, which can then be fitted in subsequent processes.

[0072] Step S104: Input the simulation results of the stage etching model simulation processing into the final etching model, and use the final etching model to fit the simulation results to obtain the final simulation results corresponding to the target process flow.

[0073] In some optional embodiments, since the dependent stage etching model and the independent stage etching model process different objects, but each subsequent etching operation in the actual target process is processed based on the result of the previous operation, after each etching model is processed, a final fitting is required to comprehensively consider the coupling effect between the various operations. Therefore, the steps of fitting the simulation results with the final etching model to obtain the final simulation result corresponding to the target process generally include: obtaining the dependent simulation result corresponding to the dependent stage etching model and the independent simulation result corresponding to the independent stage etching model; performing process logic operations on the dependent simulation result and the independent simulation result according to the target process to obtain the preprocessing result; and inputting the preprocessing result, the dependent simulation result, and the independent simulation result into the final etching model for simulation processing to obtain the final simulation result.

[0074] Optionally, since the final etching model generally also requires input mask images for processing, the steps of inputting the preprocessing results, dependent simulation results, and independent simulation results into the final etching model for simulation processing to obtain the final simulation results can generally include: obtaining the etching contours corresponding to the preprocessing results, dependent simulation results, and independent simulation results respectively; converting the etching contours using a preset curve mask sampling method to obtain a mask image; and inputting the mask image into the final etching model for simulation processing to obtain the final simulation results.

[0075] This method enables the establishment of a corresponding composite etching model based on the target process flow, and the simulation of the target process flow is performed using the composite etching model. This allows for a comprehensive consideration of the influence between various etching operations in the target process flow, ultimately yielding accurate simulation results for subsequent testing.

[0076] In some optional embodiments, the cumulative effect of multiple patterning processes (such as SADP and LELE) can easily lead to hidden defects. Traditional methods, relying solely on single etching inspection, cannot identify composite defects caused by multi-step process coupling. Therefore, in the method of this invention, after the step of fitting the simulation results to obtain the final simulation result corresponding to the target process flow using the final etching model, it generally further includes: performing simulation defect detection on the final simulation result and determining whether the initial layout pattern meets preset requirements based on the detection results. If defects are detected, the parameters in the optical proximity effect correction scheme for the initial layout pattern can be adjusted accordingly.

[0077] To clearly illustrate the composite etching model established by the present invention for multi-patterning processes, an optional implementation is provided, for example... Figure 2 As shown, Figure 2This is a schematic diagram of a composite etching model architecture established by an etching simulation method for layout patterns according to an embodiment of the present invention.

[0078] Figure 2 This is a composite etching model established based on a SARP process. The specific process flow of the SARP process generally includes: first, performing a first etching operation on the initial pattern, which forms a mandrel (MDL) pattern; then depositing spacer layers on both sides of the MDL structure, followed by filling the gaps to form a non-mandrel (NMDL) pattern; finally, both the MDL and NMDL patterns are transferred to a hard mask through a second etching operation; after obtaining the pattern formed by SARP, multiple cutting processes are added to it, which are set to two cutting processes in this embodiment (hereinafter referred to as CUT1 and CUT2) to obtain the final pattern.

[0079] Based on this target process flow, it can be determined that the first etching operation only needs to process the initial pattern after photolithography, while the second etching operation depends on the result of the first etching operation for further processing. Therefore, the second etching operation is a dependent etching operation, and the first etching operation is a pre-processing etching operation of a dependent etching operation. Furthermore, the subsequent two dicing processes (CUT1 and CUT2) do not completely depend on the second etching operation. They can first perform corresponding dicing operations on the initial pattern, and then perform unified fitting in subsequent processes; therefore, they are independent etching operations.

[0080] The composite etching model established by this invention based on this target process flow ultimately includes: a mandrel etching model 210 (MDL Etching Model), a self-aligned reverse patterning etching model 220 (SARP Etching Model), a first cutting process etching model 230 (CUT1 Etching Model), a second cutting process etching model 240 (CUT2 Etching Model), and a final etching model 250 (Final Etching Model). Among these, the self-aligned reverse patterning etching model 220 is a dependent stage etching model; the mandrel etching model 210 is a preceding stage etching model of the self-aligned reverse patterning etching model 220; and the first cutting process etching model 230 and the second cutting process etching model 240 are independent stage etching models.

[0081] The processing procedure for the composite etching model is as follows: First, the mandrel etching model 210 simulates the initial pattern to obtain the mandrel etching contour 211 (MDL Etch Contour). Since there are other process operations (deposition of spacer layers and filling of gaps) between the mandrel etching model 210 and the self-aligned reverse patterning etching model 220, process logic operations are performed on the simulation results of the mandrel etching model 210 to obtain the non-mandrel virtual contour 212 (NMDLfake Contour). Considering that the size of the MDL is different from the original MDL due to the subsequent etching process, and the size of the NDML is also affected by the existing MDL during etching, the coupling effect between the MDL and NMDL must be considered. Therefore, process logic operations are performed to obtain the mandrel and non-mandrel merged contour 213 (NDML+MDLcontour). Subsequently, the mandrel etching profile 211, the non-mandrel virtual profile 212, and the mandrel and non-mandrel merged profile 213 are input together into the self-aligned reverse patterned etching model 220 for simulation processing. Since models obtained through conventional modeling methods typically require the input of mask images, and the simulation results of each etching model in this invention are generally etching profiles, this invention chooses to convert them into mask images. Specifically, the input etching profile can be treated as a curve mask, and then the curve mask is converted into a mask image using a curve mask sampling method. This conversion process from etching profile to mask image can be called the CMI process (Contour to Mask Image).

[0082] Finally, the mandrel etching profile 211, the non-mandrel virtual profile 212, and the mandrel and non-mandrel merged profile 213 are converted into mask images and input into the self-aligned reverse patterning etching model 220 for simulation processing to obtain the self-aligned reverse patterning etching profile 221. By inputting all the results of the preceding operations into the self-aligned reverse patterning etching model 220 for simulation processing, the coupling effect between the various results can be more comprehensively fitted, thereby improving the accuracy of the etching model simulation.

[0083] Subsequently, the first dicing process etching model 230 and the second dicing process etching model 240 each acquire the initial layout graphics and perform simulation processing to obtain the first dicing process etching contour 231 (CUT1 Etch Contour) and the second dicing process etching contour 241 (CUT2 Etch Contour).

[0084] To further ensure the accuracy of the final simulation results, this invention, on the one hand, selects to perform process logic operations on the self-aligned reverse patterned etching contour 221, the first dicing process etching contour 231, and the second dicing process etching contour 241 according to specific process conditions, thereby merging them to obtain the pre-processed final contour 251 (pre-processed FinalContour). On the other hand, the simulation results of the patterned etching contour 221, the first dicing process etching contour 231, and the second dicing process etching contour 241, along with the pre-processed final contour 251 obtained from the process logic operations, are input into the final etching model 250. The target of the final etching model 250 is the silicon wafer data after the final etching step is completed. Since its model uses AI-based Flexible Terms, it can utilize inserted artificial intelligence to fit coupling effects that cannot be captured by traditional modeling methods. Furthermore, the input of the final etching model 250 includes not only the pre-processed final contour 251 but also the other three etching contours, enabling the final etching model 250 to fit more accurately based on a large amount of data, thereby further improving the accuracy of the etching model simulation.

[0085] In addition, since the input of the final etching model 250 is generally also a mask pattern, it is also necessary to use the conversion operation of the present invention to treat the etching contour to be input as a curve mask, and then convert the curve mask into a mask image through the curve mask sampling method.

[0086] After the entire modeling and fitting process is completed, a composite etching model consisting of multi-layered etching models can be used to simulate and obtain the final etched contour 252. Then, based on the final contour 252, simulation of bad spot detection can be carried out, making it possible to complete tasks that could not be done with ordinary etching models before.

[0087] Figure 2 The example is based on the specific process flow of the SARP process, but the method of the present invention can also be applied to other multi-patterning processes, such as the LELE process, SADP process, LELE+CUT process, LELELE+CUT process, etc.

[0088] Taking the LELE process as an example, in some alternative embodiments, the composite etching model architecture constructed according to the LELE process is shown in Figure 3. Figure 3 This is a schematic diagram of a composite etching model architecture established by an etching simulation method for layout patterns according to another embodiment of the present invention.

[0089] LELE process, or photolithography-etching-photolithography-etching, is a dual photolithography technique. First, a first photolithography step is performed, resulting in the morphology of the photoresist. Then, a first etching step transfers this morphology onto a hard mask. Next, photoresist is applied again, followed by a second photolithography step and a second etching step. Ultimately, both left and right patterns are transferred to the hard mask. During the first etching step, the hard mask has no existing pattern, so the etching result is purely based on the first photolithography result; modeling would be a single-step etching model. However, during the second etching step, the pattern from the first etching already exists on the hard mask, inevitably affecting the second etching process. The final result depends not only on the second photolithography result but also on the result after the first etching. The final pattern transfer effect is essentially the result of transferring all patterns to the hard mask after the second etching step. Therefore, for simulation defect prediction, a single-step etching model is unusable; a composite etching model using the method of this invention is required.

[0090] First, the types of the two etching operations in the LELE process are determined: since the two etching operations in the LELE process can be performed separately first and then uniformly fitted, the two etching operations are determined to be independent etching operations, divided into LE1 and LE2. Based on this target process flow, the composite etching model established by this invention ultimately includes: a first etching model 310 (LE1 Etching Model), a second etching model 320 (LE2 Etching Model), and a final etching model 330 (Final Etching Model).

[0091] The processing procedure of the composite etching model is as follows: The first etching model 310 and the second etching model 320 each perform simulations based on the initial layout pattern to obtain corresponding simulation results, namely the first etching contour 311 (LE1 Etch Contour) and the second etching contour 321 (LE2 Etch Contour). Then, the two simulation results are processed according to specific process conditions to obtain the preprocessed final contour 331 (preprocessed Final Contour). Subsequently, the preprocessed final contour 331, along with the first etching contour 311 and the second etching contour 321, are converted into a mask image and input into the final etching model 330 for fitting. The target of the final etching model 330 is the silicon wafer data after the final etching step. The coupling effect between LE1 and LE2 is captured by artificial intelligence during the fitting process. Finally, the composite etching model simulates the final etched contour, and then performs simulated defect detection based on this contour.

[0092] In summary, this invention proposes the concept of Combine Etching Modeling and provides a composite etching modeling framework based on a multi-patterning process architecture. This makes it possible to directly simulate the final graphical effect of multi-patterning processes, thereby enabling simulation-based defect detection based on the model results. Furthermore, to better address the problem of stitching together the various etching sub-models into a composite model, this invention also proposes a method using existing curve mask sampling to convert the contour after process logic operations into a "mask image." This allows the contour after process logic operations to be conveniently used as input for the next step of the model, thus organically combining the various layers of models in the multi-patterning process architecture.

[0093] It should be noted that the composite etching model concept and modeling process proposed in this invention are applicable to various multi-patterning processes. In addition to the SARP and LELE processes explicitly mentioned in this invention, they can also be applied to SADP, LELE+CUT, LELELE+CUT and other processes. Those skilled in the art can determine the corresponding composite etching model architecture based on the actual process flow, thereby completing the simulation of the corresponding process.

[0094] The flowchart provided in this embodiment is not intended to indicate that the operations of the method will be performed in any particular order, or that all operations of the method are included in every case. Furthermore, the method may include additional operations. Within the scope of the technical concept provided by the method in this embodiment, additional variations can be made to the above method.

[0095] It should be understood that in some embodiments, the components may be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods may be implemented using software or firmware stored in memory and executed by a suitable instruction execution system.

[0096] This embodiment also provides a computer program product 10, a computer-readable storage medium 20, and a computer device 30. Figure 4 This is a schematic diagram of a computer program product 10 according to an embodiment of the present invention. Figure 5 This is a schematic diagram of a computer-readable storage medium 20 according to an embodiment of the present invention. Figure 6This is a schematic diagram of a computer device 30 according to an embodiment of the present invention. The computer program product 10 includes a computer program 11, which, when executed by the processor 32, implements the steps of the etching simulation method for the layout pattern described above. A computer-readable storage medium 20 stores the computer program 11 thereon, which, when executed by the processor 32, implements the steps of the etching simulation method for the layout pattern described above. The computer device 30 may include a memory 31, a processor 32, and the computer program 11 stored in the memory 31 and running on the processor 32.

[0097] The computer program 11 used to perform the operations of this invention may be assembly instructions, Instruction Set Architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages ​​and procedural programming languages. The computer program 11 may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a Local Area Network (LAN) or Wide Area Network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, to perform aspects of this invention, electronic circuits, including, for example, programmable logic circuits, Field-Programmable Gate Arrays (FPGAs), or Programmable Logic Arrays (PLAs), may execute computer-readable program instructions using status information from computer-readable program instructions to personalize the electronic circuits.

[0098] For the purposes of this embodiment, computer program product 10 is a related product containing computer program 11. For the purposes of this embodiment, computer-readable storage medium 20 is a tangible device capable of holding and storing computer program 11, and can be any device capable of containing, storing, communicating, propagating, or transmitting program 11 for use by or in conjunction with an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable storage medium 20 include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable optical disc read-only memory (CD-ROM), digital versatile disc (DVD), memory stick, floppy disk, mechanical encoding device, and any suitable combination thereof.

[0099] Computer device 30 can be, for example, a server, desktop computer, laptop computer, tablet computer, or smartphone. In some examples, computer device 30 can be a cloud computing node. Computer device 30 can be described in the general context of computer system executable instructions (such as program modules) executed by a computer system. Typically, program modules can include routines, programs, object programs, components, logic, data structures, etc., that perform specific tasks or implement specific abstract data types. Computer device 30 can be implemented in a distributed cloud computing environment where tasks are performed by remote processing devices linked through a communication network. In a distributed cloud computing environment, program modules can reside on local or remote computing system storage media, including storage devices.

[0100] Computer device 30 may include a processor 32 adapted to execute stored instructions and a memory 31 that provides temporary storage space for the operation of said instructions during operation. The processor 32 may be a single-core processor, a multi-core processor, a computing cluster, or any other configuration. The memory 31 may include random access memory (RAM), read-only memory, flash memory, or any other suitable storage system.

[0101] Computer device 30 may also include a network adapter / interface and an input / output (I / O) interface. The I / O interface allows external devices that can be connected to the computer device to input and output data. The network adapter / interface provides communication between the computer device and a network, typically represented as a communication network.

[0102] Therefore, those skilled in the art should recognize that although numerous exemplary embodiments of the present invention have been shown and described in detail herein, many other variations or modifications conforming to the principles of the present invention can be directly determined or derived from the disclosure of the present invention without departing from the spirit and scope of the invention. Thus, the scope of the present invention should be understood and construed as covering all such other variations or modifications.

Claims

1. A method for etching simulation of a layout pattern, comprising: obtaining a target process flow and an initial layout pattern operated by the target process flow; determining a plurality of etching operations in the target process flow, and obtaining a corresponding stage etching model for each of the etching operations; simulating the etching operations by using the stage etching models; inputting a simulation result of the simulation of the stage etching models into a final etching model, and fitting the simulation result by using the final etching model to obtain a final simulation result corresponding to the target process flow. 2.The method of claim 1, wherein: the etching operations comprise a dependent etching operation, the dependent etching operation corresponding to a dependent stage etching model, the dependent stage etching model being used to simulate on a basis of a simulation result of a previous operation on which the dependent etching operation depends; and the step of simulating the etching operations by using the stage etching models comprises: in a case that the etching operation is the dependent etching operation, determining a target previous operation on which the dependent etching operation depends; obtaining a previous stage etching model corresponding to the target previous operation, and simulating the target previous operation by using the previous stage etching model to obtain a previous simulation result; obtaining the dependent stage etching model corresponding to the dependent etching operation, and inputting the previous simulation result into the dependent stage etching model for simulation. 3.The method of claim 2, wherein: the target previous operation comprises a previous etching operation and a previous process operation between the previous etching operation and the dependent etching operation; and the step of simulating the target previous operation by using the previous stage etching model to obtain the previous simulation result comprises: simulating the previous etching operation by using the previous stage etching model to obtain a previous etching result; performing a process logic operation on the previous etching result according to the previous process operation to obtain a previous logic operation result; and combining the previous etching result and the previous logic operation result as the previous simulation result. 4.The method of claim 2, wherein: the step of inputting the previous simulation result into the dependent stage etching model for simulation comprises: obtaining a previous etching profile corresponding to the previous simulation result; converting the previous etching profile by using a preset curve mask sampling method to obtain a previous mask image; and inputting the previous mask image into the dependent stage etching model for simulation. 5.The method of claim 2, wherein: the etching operations further comprise an independent etching operation, the independent etching operation corresponding to an independent stage etching model, the independent stage etching model being used to simulate on a basis of the initial layout pattern; and the step of simulating the etching operations by using the stage etching models comprises: ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ In a case that the etching operation is the independent-type etching operation, an independent-type stage etching model corresponding to the independent-type etching operation is acquired, and the initial layout pattern is input into the independent-type stage etching model for simulation processing.

6. The etching simulation method of layout pattern according to claim 5, wherein, The step of fitting the simulation result by using the final etching model to obtain the final simulation result corresponding to the target process flow comprises: acquiring a dependent-type simulation result corresponding to the dependent-type stage etching model and an independent-type simulation result corresponding to the independent-type stage etching model; performing process logic operation on the dependent-type simulation result and the independent-type simulation result according to the target process flow to obtain a pretreatment result; inputting the pretreatment result, the dependent-type simulation result and the independent-type simulation result into the final etching model for simulation processing to obtain the final simulation result.

7. The etching simulation method of layout pattern according to claim 6, wherein, The step of inputting the pretreatment result, the dependent-type simulation result and the independent-type simulation result into the final etching model for simulation processing to obtain the final simulation result comprises: acquiring an etching contour corresponding to each of the pretreatment result, the dependent-type simulation result and the independent-type simulation result, respectively; converting the etching contour by using a preset curve mask sampling method to obtain a mask image; inputting the mask image into the final etching model for simulation processing to obtain the final simulation result.

8. The etching simulation method of layout pattern according to claim 1, wherein, after the step of fitting the simulation result by using the final etching model to obtain the final simulation result corresponding to the target process flow, the method further comprises: performing simulation bad point detection on the final simulation result and determining whether the initial layout pattern meets preset requirements according to a detection result.

9. A computer program product comprising a computer program which, when executed by a processor, implements the steps of the etching simulation method of layout pattern according to any one of claims 1 to 8.

10. A computer device comprising a memory, a processor and a machine executable program stored on the memory and running on the processor, and the processor implements the steps of the etching simulation method of layout pattern according to any one of claims 1 to 8 when executing the machine executable program.

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