A layout region division method, a clock tree construction method, a computer medium, a device, and a program product

Abstract

The present application relates to the technical field of electronic design automation, in particular to a layout area division method, a clock tree construction method, a computer medium device and a program product, the method comprises the following steps: providing a layout area, dividing the layout area into a plurality of unit length and array distribution squares; obtaining the length information of two adjacent sides of the layout area; based on the length information, the layout area is processed in stages to divide the layout area into four secondary areas with close areas and composed of squares, the obtained secondary areas are iteratively processed in stages until the area of the secondary area is 4*3, 3*3 or 3*4, wherein the unit of area is the product of unit length; the secondary area is divided into corresponding sub-areas, and the sub-areas are divided into unit areas with an area equal to the area of the square to complete the division of the layout area. The method solves the problem that the traditional layout area division method can only divide 4n times of unit areas.

Description

Technical Field

[0001] This invention relates to the field of electronic design automation technology, and in particular to a method for dividing layout areas, a method for constructing clock trees, computer media devices, and program products. Background Technology

[0002] In the field of integrated circuits, clock tree synthesis is a crucial part connecting the placement and routing phases. The quality of the clock tree significantly impacts the timing convergence and power consumption of the entire design. The delay from the clock source to the load is typically called clock delay, and the difference in clock delay between all loads is called clock skew. Clock skew affects the final clock convergence. In a zero-skew clock tree, considering that timing convergence is largely achieved during the placement optimization phase, the clock tree only needs to achieve zero skew. However, real-world designs often cannot achieve zero clock skew, and due to on-chip variations, the pessimism rates applied to the trigger clock path and the capture clock path differ, leading to timing convergence results that do not match expectations.

[0003] To construct a clock tree with near-zero skew, chips typically use an H-tree for clock tree construction. An H-tree is a clock tree construction method that divides the layout area into multiple levels of sub-regions by progressively subdividing the layout region. Finally, caches are placed within each level of the sub-region, usually at the center point of each level, ensuring that the distance from each cache to the next level is equal, thus achieving zero skew. However, traditional H-trees can only divide regions into 4^n units, making it impossible to divide regions of other sizes. Therefore, finding a method to divide the layout region is crucial. Summary of the Invention

[0004] To address the limitation that traditional layout area division methods can only divide 4 to the power of n unit areas, this invention provides a layout area division method, a clock tree construction method, a computer media device, and a program product.

[0005] To solve the above-mentioned technical problems, the present invention provides the following technical solution: a method for dividing a layout region, used to divide the layout region and place a buffer to construct a clock tree. The method for dividing the layout region includes the following steps: providing a rectangular layout region; dividing the layout region into several unit-length and array-distributed squares; obtaining the side length information of two adjacent sides of the layout region; performing multiple hierarchical processing on the layout region based on the side length information to divide the layout region into four secondary regions with similar areas and composed of squares; iterating the hierarchical processing of the obtained secondary regions until the area of ​​the secondary region is 4*3, 3*3, or 3*4, where the unit of area is the product of unit lengths; determining whether the area of ​​the secondary region is... If the area is 3*3, then the secondary area with an area of ​​3*3 is divided into sub-areas with areas equal to the product of the side lengths of 2*2, 2*1, 1*2, and 1*1. The sub-areas with areas of 2*2, 1*2, and 2*1 are then divided into unit areas with areas equal to the area of ​​the cube to complete the layout area division. If not, then the secondary area with an area of ​​4*3 is divided into sub-areas with areas equal to the product of the side lengths of 2*2, 1*2, and 1*1, or the secondary area with an area of ​​3*4 is divided into sub-areas with areas equal to the product of the side lengths of 2*2, 2*1, and 1*1. The sub-areas with areas of 2*2 and 1*2 or with areas of 2*2 and 2*1 are then divided into unit areas with areas equal to the area of ​​the cube to complete the layout area division.

[0006] Preferably, dividing the layout area into four secondary areas composed of squares with similar areas includes: determining whether the side lengths of the layout area are all even; if the side lengths of the layout area are all even, dividing the layout area into four secondary areas with an area of ​​(side length / 2)*(side length*2); if the side lengths of the layout area are odd, obtaining the side lengths with odd lengths, dividing the layout area into two secondary areas with an area of ​​[(odd side length + 1) / 2]*[even side length / 2], and two secondary areas with an area of ​​[(odd side length - 1) / 2]*[even side length / 2]; if the side lengths of the layout area are all odd, obtaining the side lengths with odd lengths, dividing the layout area into two secondary areas with an area of ​​[(odd side length + 1) / 2]*[(odd side length + 1) / 2], and two secondary areas with an area of ​​[(odd side length - 1) / 2]*[(odd side length - 1) / 2].

[0007] Preferably, when performing hierarchical processing in the iteration, the layout area with the largest area is hierarchically divided into smaller areas. Each hierarchical division will result in a smaller secondary area until the area of ​​the secondary area is 4*3, 3*3 or 3*4, where the unit of area is the product of unit lengths.

[0008] Preferably, the block is a block with a unit length of 1. If the four secondary regions are not equal in the last hierarchical processing, the smaller area will be supplemented with a filler block with an area equal to that of the block, so that the area and side length information of the four secondary regions in the last hierarchical processing are equal.

[0009] Preferably, the division of the 3*3 secondary region is as follows: inserting a row and a column of fill blocks in the middle of the 3*3 secondary region to obtain a 4*4 secondary region; dividing the 4*4 secondary region into four 2*2 sub-regions; removing the fill blocks from the 2*2 sub-regions to obtain sub-regions with areas of 2*2, 1*2, and 1*1.

[0010] Preferably, the division of the 4*3 secondary region includes: inserting a row of fill blocks in the middle of the 4*3 region to obtain a 4*4 secondary region; dividing the 4*4 secondary region into four 2*2 sub-regions; removing the fill blocks from the 2*2 sub-regions to obtain sub-regions with areas of 2*2, 2*1, and 1*1; or the division of the 3*4 secondary region includes: inserting a column of fill blocks in the middle of the 3*4 region to obtain a 4*4 secondary region; dividing the 4*4 secondary region into four 2*2 sub-regions; removing the fill blocks from the 2*2 sub-regions to obtain sub-regions with areas of 2*2, 1*2, or 1*1.

[0011] To solve the above-mentioned technical problems, the present invention provides another technical solution as follows: a method for constructing a clock tree, comprising the following steps: dividing the layout area using the above-mentioned layout area division method; placing a buffer for the central area at the center point of the layout area; when performing hierarchical processing on the layout area, the layout area will be hierarchically divided in a way that the area decreases, and after each hierarchical processing, four secondary areas will be obtained, and a secondary area buffer will be placed at the center point of the four secondary areas after each hierarchical processing; when the area of ​​the secondary area is equal to the product of the side lengths of 4*3, 3*3 or 3*4, inserting a filler block in the secondary area to obtain a secondary area with an area of ​​4*4, dividing the secondary area into four sub-areas with an area of ​​2*2, and placing a sub-area buffer at the center point of the sub-area; after completing the division of the layout area, obtaining the position of the unit area, and placing a unit area buffer at the center point of the unit area; connecting the buffer for the central area, the secondary area buffer during the hierarchical processing, the sub-area buffer, and the unit area buffer in descending order of the area where the buffer is located to complete the construction of the clock tree.

[0012] To solve the above-mentioned technical problems, the present invention provides another technical solution as follows: a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, the computer instructions being used to cause the computer to execute the layout area division method described above.

[0013] To solve the above-mentioned technical problems, the present invention provides another technical solution as follows: a computer device applied to the above-mentioned layout area division method, comprising a memory, a processor, and a computer program stored in the memory, wherein the processor executes the above-mentioned computer program to implement the layout area division method.

[0014] To solve the above-mentioned technical problems, the present invention provides another technical solution as follows: a computer program product, including a computer program or instructions, wherein the computer program or instructions, when executed by a processor, implement the above-mentioned layout area division method.

[0015] Compared with the prior art, the layout area division method, clock tree construction method, computer media device, and program product provided by the present invention have the following beneficial effects:

[0016] 1. An embodiment of the present invention provides a method for dividing a layout region, used to divide the layout region and place a buffer to construct a clock tree. The method for dividing the layout region includes the following steps: providing a rectangular layout region; dividing the layout region into several unit-length and array-distributed squares; obtaining the side length information of two adjacent sides of the layout region; performing multiple hierarchical processing on the layout region based on the side length information to divide the layout region into four secondary regions with similar areas and composed of squares; iterating the hierarchical processing of the obtained secondary regions until the area of ​​the secondary region is 4*3, 3*3, or 3*4, where the unit of area is the product of unit lengths; determining whether the area of ​​the secondary region is 3*3; if so, If the first subregion has an area of ​​3*3, then divide it into subregions whose area is equal to the product of their side lengths (2*2, 2*1, 1*2, and 1*1). Then divide the subregions with areas of 2*2, 1*2, and 2*1 into unit regions with areas equal to the area of ​​the cube to complete the layout area division. If not, then divide the second subregion with an area of ​​4*3 into subregions whose area is equal to the product of their side lengths (2*2, 1*2, and 1*1), or divide the second subregion with an area of ​​3*4 into subregions whose area is equal to the product of their side lengths (2*2, 2*1, and 1*1). Then divide the subregions with areas of 2*2 and 1*2 or the subregions with areas of 2*2 and 2*1 into unit regions with areas equal to the area of ​​the cube to complete the layout area division. This invention solves the problem that existing layout area divisions can only accommodate 4 to the power of n unit areas, and cannot divide areas of other sizes. By recursively classifying the layout areas and setting a classification termination condition, it successfully enables the division of layout areas of any rectangle, and classifies the layout areas from top to bottom until the layout area is divided into the smallest unit area.

[0017] 2. A clock tree construction method provided in this embodiment of the invention uses the above-mentioned layout area division method to divide the layout area; a buffer for the central area is placed at the center point of the layout area; when the layout area is hierarchically processed, the layout area will be hierarchically divided in a way that the area decreases, and four secondary areas will be obtained after each hierarchical processing. A secondary area buffer is placed at the center point of the four secondary areas after each hierarchical processing; when the area of ​​the secondary area is equal to the product of the side lengths of 4*3, 3*3 or 3*4, a fill block is inserted in the secondary area to obtain a secondary area with an area of ​​4*4. The secondary area is divided into four sub-areas with an area of ​​2*2, and a sub-area buffer is placed at the center point of the sub-area; after the layout area is divided, the position of the unit area is obtained, and a unit area buffer is placed at the center point of the unit area; the buffer for the central area, the secondary area buffer during the hierarchical processing, the sub-area buffer, and the unit area buffer are connected in descending order of the area of ​​the buffer to complete the construction of the clock tree. After the chip layout area is divided, caches can be set in each divided area, ensuring that the distance from each cache level to the next cache level is equal, thus constructing a zero-skew clock tree. Furthermore, in the first embodiment, the layout area is divided from largest to smallest area. In this embodiment, when constructing the clock tree, the clock tree will form a top-down construction order similar to the hierarchical processing in this embodiment.

[0018] 3. Embodiments of the present invention also provide a computer-readable storage medium, which has the same beneficial effects as the above-described layout area division method, and will not be described in detail here.

[0019] 4. This invention also provides a computer device that has the same beneficial effects as the above-described layout area division method, which will not be described in detail here.

[0020] 5. A computer program product provided in this embodiment of the invention includes a computer program or instructions, which, when executed by a processor, implement the above-mentioned layout area division method. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a flowchart illustrating the layout area division method provided in the first embodiment of the present invention.

[0023] Figure 2a This is a schematic diagram of the layout area provided in the first embodiment of the present invention. Figure 1 .

[0024] Figure 2b This is a second schematic diagram of the layout area provided in the first embodiment of the present invention.

[0025] Figure 3a This is a schematic diagram illustrating the process of dividing a 3*3 secondary region into sub-regions, as provided in the first embodiment of the present invention.

[0026] Figure 3b This is a schematic diagram illustrating the process of dividing a 3*4 secondary region into sub-regions, as provided in the first embodiment of the present invention.

[0027] Figure 4a This is a schematic diagram illustrating the process of dividing a 6*7 layout area into secondary areas, as provided in the first embodiment of the present invention.

[0028] Figure 4b yes Figure 4a The diagram above shows the location where the buffer is placed.

[0029] Figure 5a This is a schematic diagram illustrating the process of dividing a 5*5 layout area into secondary areas according to the first embodiment of the present invention.

[0030] Figure 5b yes Figure 5a The diagram above shows the location where the buffer is placed.

[0031] Figure 5c This is a flowchart illustrating the process of dividing the secondary region 5B1 into sub-regions in the first embodiment of the present invention.

[0032] Figure 5d This is a diagram illustrating the process of dividing the secondary region 5C1 into sub-regions in the first embodiment of the present invention.

[0033] Figure 5e This is a diagram illustrating the process of dividing the secondary region 5D1 into sub-regions in the first embodiment of the present invention.

[0034] Figure 6 This is a schematic diagram of the structure of a computer-readable storage medium provided in the third embodiment of the present invention.

[0035] Figure 7 This is a schematic diagram of the structure of the computer device provided in the fourth embodiment of the present invention.

[0036] Figure 8 This is a schematic diagram of the structure of the computer program product provided in the fifth embodiment of the present invention. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0038] In the embodiments provided by this invention, it should be understood that "B corresponding to A" means that B is associated with A, and B can be determined based on A. However, it should also be understood that determining B based on A does not mean determining B solely based on A; B can also be determined based on A and / or other information.

[0039] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of the invention. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Those skilled in the art should also recognize that the embodiments described in the specification are optional embodiments, and the actions and modules involved are not necessarily essential to the invention.

[0040] In various embodiments of the present invention, it should be understood that the sequence number of each process does not necessarily imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0041] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, or they may sometimes be executed in reverse order, depending on the functions involved. It is particularly important to note that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0042] In the field of integrated circuits, clock tree synthesis is a crucial part connecting the placement and routing phases. The quality of the clock tree significantly impacts the timing convergence and power consumption of the entire design. The delay from the clock source to the load is typically called clock delay, and the difference in clock delay between all loads is called clock skew. Clock skew affects the final clock convergence. In a zero-skew clock tree, considering that timing convergence is largely achieved during the placement optimization phase, the clock tree only needs to achieve zero skew. However, real-world designs often cannot achieve zero clock skew, and due to on-chip variations, the pessimism rates applied to the trigger clock path and the capture clock path differ, leading to timing convergence results that do not match expectations.

[0043] To construct a clock tree with near-zero skew, chips typically employ H-trees. H-trees are a clock tree construction method that divides the layout area into multiple levels of sub-regions, and then places caches within each level, ensuring that the distance from each cache level to the next is equidistant, thus achieving zero skew. H-trees guarantee that the clock latency is essentially consistent across all loads or regions, significantly reducing clock skew. Furthermore, because H-trees often use dedicated, non-default rules for upper-layer network connections and employ larger caches, they reduce backbone latency. Additionally, H-trees handle common clock paths, minimizing the impact of on-chip variations. For these three reasons, H-trees better guarantee timing convergence and are particularly useful in certain design scenarios.

[0044] However, the traditional H-tree can only divide 4 to the power of n unit regions, and cannot divide regions of other sizes. Therefore, it is particularly important to find a way to divide the layout region.

[0045] To address the aforementioned technical problems, the first embodiment of the present invention provides a method for dividing a layout region for constructing a clock tree. The method for dividing the layout region includes the following steps:

[0046] S1 provides a rectangular layout area, which is divided into several unit-length squares in an array.

[0047] S2, obtain the side length information of two adjacent sides of the layout area;

[0048] S3, based on the side length information, performs multiple hierarchical processing on the layout area to divide the layout area into four secondary areas with similar areas and composed of squares. The obtained secondary areas are iteratively hierarchically processed until the area of ​​the secondary area is 4*3, 3*3 or 3*4, where the unit of area is the product of unit lengths.

[0049] S4, determine if the area of ​​the secondary region is 3*3;

[0050] S5, if so, then divide the secondary region with an area of ​​3*3 into sub-regions with an area equal to the product of the side lengths of 2*2, 2*1, 1*2 and 1*1, and divide the sub-regions with an area of ​​2*2, 1*2 and 2*1 into unit regions with an area equal to the area of ​​the square to complete the division of the layout region.

[0051] S6. If not, then divide the secondary region with an area of ​​4*3 into sub-regions with an area equal to the product of the side lengths of 2*2, 1*2, and 1*1, or divide the secondary region with an area of ​​3*4 into sub-regions with an area equal to the product of the side lengths of 2*2, 2*1, and 1*1, and divide the sub-regions with an area of ​​2*2 and 1*2 or the sub-regions with an area of ​​2*2 and 2*1 into unit regions with an area equal to the area of ​​the square to complete the division of the layout area.

[0052] The center point of the layout area, the secondary area of ​​each level, and the unit area is the location where the cache is placed.

[0053] Understandably, traditional HTree construction methods are limited by 4 to the power of n region partitioning rules, such as only being able to partition into 16 or 64 squares. This makes it difficult to flexibly handle asymmetrical layouts, such as partitioning into rectangular regions composed of 5x7 squares. Forced partitioning can lead to imbalanced sub-region areas, making it impossible to achieve zero skew between the previous and next level caches when confirming their positions. This solution uses recursive hierarchical processing to partition the layout region area, enabling the partitioning of rectangular local regions of any shape. It should be understood that the rectangular region is first decomposed into an array of smallest unit squares, and the number of layers in the layout region is obtained through side length information. For example, ... Figure 2a As shown, the layout area is divided into rectangular areas composed of 6x6 squares, and Figure 2bAs shown, the layout area is divided into rectangular regions composed of 8x6 squares. Further, the layout area is processed in multiple hierarchical steps until a termination condition is met: the hierarchical processing stops when the area of ​​a secondary region equals a product of its side lengths of 4x3, 3x3, or 3x4. It should be understood that continuing the hierarchical processing when the area of ​​a secondary region equals a product of its side lengths of 4x3, 3x3, or 3x4 would result in an imbalance in the area of ​​the sub-regions generated during the partitioning process. Therefore, the hierarchical processing stops once the termination condition is met. Before reaching the termination condition, the hierarchical processing aims to create a top-down partition of the layout area. It should be understood that if a bottom-up partitioning method is used, the inverter's situation and the correct handling of design rule violations cannot be adequately considered when constructing the clock tree. This typically requires two additional checks for correction, which increases runtime and power consumption. Therefore, in this embodiment, the layout area is divided from the largest area to the smallest area. When the clock tree is built subsequently, the clock tree will form a top-down construction order similar to the hierarchical processing in this embodiment.

[0054] It's important to understand that this embodiment divides the layout area from top to bottom. "Top to bottom" means dividing the layout area from the largest area of ​​the entire layout area to the smallest unit area. Each division typically represents a different level of area, with the area decreasing and the level decreasing accordingly. The purpose of dividing the area is to ensure that the distance between the buffers placed in the previous division and the buffers placed in the next division is equal. The final result of the layout area division will be several squares; that is, the area of ​​the last-level unit area will be equal to the area of ​​the square, and the center point of the last unit area will be where the last-level buffer is placed.

[0055] It should be noted that the length of the cube in this embodiment is a unit length, and its specific value can be set according to the user's specific needs. The area in this embodiment is the product of unit lengths, that is, n*n times the area of ​​the cube. For example, assume the area of ​​the cube is 1 mm². 2 When the area of ​​the secondary region is equal to the product of its side lengths (4 * 3), it means that the secondary region has a shorter side that is 3 times the unit length and a longer side that is 4 times the unit length, resulting in an area of ​​4 * 3 = 12 mm. 2 When the area of ​​the secondary region is equal to the product of its side lengths (3*3), it means that the secondary region is represented by a shorter side being 3 times the unit length and a longer side being 3 times the unit length, resulting in an area of ​​3*3=9mm². 2 .

[0056] Specifically, once the area of ​​the secondary region reaches the termination condition, first check if the area of ​​the secondary region is 3*3. If the area of ​​the secondary region is 3*3, then... Figure 3a As shown, the 3*3 secondary region will be divided into sub-regions 3A1 (area equal to 2*2), 3B1 (area equal to 1*2), 3C1 (area equal to 1*1), and 3D1 (area equal to 2*1). That is, generally, as long as the area of ​​the secondary region is determined to be 3*3, this embodiment will directly obtain the result based on dividing the secondary region with an area of ​​3*3 when dividing the layout area. Figure 3a The sub-region is defined as follows: If the area of ​​the sub-region is not 3x3, that is, if the area of ​​the sub-region is 4x3 or 3x4, then... Figure 3b The 4*3 secondary region shown will be divided into sub-regions 3A2 (area equal to 2*2), 3B2 (area equal to 1*2), 3C2 (area equal to 1*2), and 3D2 (area equal to 2*2). Typically, it is sufficient to determine if the area of ​​the secondary region is 4*3. In this embodiment, when dividing the layout area, it will directly obtain the result based on dividing the secondary region with an area of ​​3*3. Figure 3a The sub-regions within. It should be understood that the result of dividing a 3*4 secondary region is... Figure 3a The inversion of the characters will not be discussed in detail here.

[0057] It should be understood that this embodiment addresses the problem that existing layout area divisions can only accommodate 4 to the power of n unit areas, and cannot divide areas of other sizes. It achieves this by recursively hierarchizing the layout area and setting a classification termination condition. The type of termination condition is then determined, and different methods are used to divide the secondary area into 3*3, 4*3, or 3*4 areas, until the layout area is progressively divided into unit areas. This successfully enables the division of any rectangular layout area, hierarchically dividing the layout area from top to bottom until the layout area is divided into the smallest unit area. Furthermore, after each division, it facilitates the user's subsequent placement of buffers at the center of the divided area, ensuring that the distance between buffers in adjacent levels is equal, which helps in quickly constructing a zero-skew clock tree.

[0058] Further, in step S2, the layout area is divided into four secondary areas with similar areas and composed of squares, including:

[0059] Determine if all side lengths of the layout region are even numbers;

[0060] If the side lengths of the layout area are all even numbers, the layout area is divided into four secondary areas with an area of ​​(side length / 2)*(side length*2).

[0061] If the side length of the layout area is odd, then obtain the side length with odd length, and divide the layout area into two secondary areas with an area of ​​[(odd side length + 1) / 2] * [even side length / 2], and two secondary areas with an area of ​​[(odd side length - 1) / 2] * [even side length / 2].

[0062] If all sides of the layout area have odd lengths, then obtain the side lengths with odd lengths and divide the layout area into two secondary areas with an area of ​​[(odd side length + 1) / 2] * [(odd side length + 1) / 2] and an area of ​​two secondary areas with an area of ​​[(odd side length - 1) / 2] * [(odd side length - 1) / 2].

[0063] Understandably, the layout area in this embodiment is composed of several unit-length blocks. The length of each block is 1, so the side length of the layout area is a multiple of 1. This method adapts to the segmentation of the layout area by using the parity of the side length of the layout area, so that a large layout area can be quickly segmented into secondary areas with a termination condition of 4*3, 3*3 or 3*4.

[0064] For example, if the number of rows and columns is even, such as a layout area with a side length of 8*6, then during the first hierarchical processing, a direct halving is performed, dividing the 8*6 area into four 4*3 secondary areas. In this scenario, the four sub-areas have strictly equal areas, each containing 24 blocks. When placing caches subsequently, the highest-level cache will be placed at the center of the original 8*6 area, and the four next-level caches will be placed at the center of each of the four 4*3 secondary areas. The distance from the highest-level cache in the layout area to the caches in the next-level secondary areas will be exactly the same.

[0065] For example, when only the side length of the layout area is odd, that is, when the number of rows or columns in the layout area is odd, such as a layout area with a side length of 7*6, this implementation will use the method of expanding virtual rows, expanding to 8*6 by "adding one" in the row direction, and then performing asymmetrical division. It should be noted that during expansion, the expansion should be carried out as close to the center point as possible. This generates two (7+1) / 2*6 / 2=4*3 sub-regions and two (7-1) / 2*6 / 2=3*3 secondary regions. This embodiment provides a mechanism for virtual region supplementation, which generates virtual rows or columns by expanding the odd-numbered side lengths, and after hierarchical division, performs clipping in the corresponding secondary regions. Figure 4a As shown, the dashed area represents the truncated virtual column to ensure that subsequent buffer placements are only placed in the center of physically existing blocks. Traditional methods suffer from area imbalance due to odd-numbered rows. This embodiment uses a combination of virtual compensation and truncated virtual compensation to ensure that the path lengths from the highest-level buffer to the boundaries of the four secondary regions are equal. Figure 4a and Figure 4bAs shown, Figure 4a This is the first hierarchical process for a layout area with a side length of 7*6. Figure 4b This is a cache placement diagram, where 4oA is the center of the layout area and the placement position of the highest-level cache. 4o1, 4o2, 4o3, and 4o4 are the placement positions of caches in the secondary areas of the first level, respectively. Figure 4b As shown, the distances from 4oA to 4o1, 4o2, 4o3, and 4o4 are equal.

[0066] For example, when the side lengths of the layout area are all odd, that is, when the number of rows and columns of the layout area is odd, a layout area with a side length of 5*5 will first be expanded simultaneously in both directions: the row and column directions will both be expanded by "one" to a 6*6 area. It should be noted that during expansion, the expansion should be carried out as close to the center point as possible. Then, the expanded area is symmetrically divided: two (5+1) / 2*(5+1) / 2=3*3 secondary areas and two (5-1) / 2*(5-1) / 2=2*2 secondary areas are generated.

[0067] It should be understood that the hierarchical processing in this embodiment differs from traditional partitioning methods and is not limited to dividing only unit regions of 4 to the power of n. Instead, the partitioning method can be freely chosen based on whether the side length of the layout region is odd or even. That is, this implementation has geometric compatibility for rectangular layout regions. Furthermore, it ultimately ensures that the path length from all secondary regions to the center point of the layout region is equal, facilitating the subsequent placement of buffers to construct the clock tree.

[0068] It should be noted that the area mentioned above is just a simple example. The actual layout area is much larger and requires multiple hierarchical processing to obtain secondary areas of 4*3, 3*3, or 3*4.

[0069] Specifically, during the iterative hierarchical processing, the layout region with the largest area is divided into smaller sub-regions. Each sub-region results in a smaller sub-region, until the area of ​​the sub-region is 4*3, 3*3, or 3*4, where the area is the product of unit lengths. It should be understood that this embodiment, by defining the termination condition of the hierarchical processing, enables the layout region to be quickly divided into 4*3, 3*3, or 3*4 sub-regions.

[0070] Furthermore, the block is a block with a unit length of 1. If the four secondary regions are not equal in the last hierarchical processing, the smaller region will be supplemented with a filler block with an area equal to that of the block, so that the area and side length information of the four secondary regions in the last hierarchical processing are equal.

[0071] It is understandable that, in certain special circumstances, the final grading process may result in the four sub-regions having unequal areas, such as... Figure 4a As shown, the layout area, with sides of 6*7, will actually be divided into four 4*3, 4*3, 3*3, and 3*3 regions. The area of ​​the 3*3 region is significantly smaller than the area of ​​the 4*3 region specified in the termination condition, and the areas of the 4*3, 4*3, 3*3, and 3*3 regions are also unequal. Therefore, in the final hierarchical processing, a column of fill blocks will be added to the 3*3 region, making it four equal-sized 4*3 secondary regions. Finally, the buffer placement position is set at the center point of each 4*3 secondary region.

[0072] It should be understood, for example... Figure 5a As shown, the layout area is a 5x5 region on each side, which will actually be divided into 3x3, 2x3, 3x2, and 2x2 regions. The areas of the 2x3, 3x2, and 2x2 regions are significantly smaller than the 3x3 region specified in the termination condition, and the areas of the 3x3, 2x3, 3x2, and 2x2 regions are also unequal. If the buffer is placed at the center point of each of these regions, the distance between the upper-level buffer and the lower-level buffer will inevitably be unequal. Therefore, it is advisable to fill the smaller regions to ensure that the areas and side lengths of the four secondary regions in the last hierarchical processing are equal. Figure 5b This is a cache placement diagram, where 5oA is the center of the layout area and the placement position of the highest-level cache. 5o1, 5o2, 5o3, and 5o4 are the placement positions of caches in the secondary areas of the first level, respectively. Figure 5b As shown, the distances from 5oA to 5o1, 5o2, 5o3 and 5o4 are equal.

[0073] Understandably, in this embodiment, a few special cases are addressed by setting a fill block, so that the distance from the center point of the last sub-region to the center point of the previous sub-region is equal.

[0074] When a secondary region with a side length product equal to 4*3, 3*3, or 3*4 is obtained, this embodiment will directly obtain the corresponding sub-region. In order to realize the transfer from the secondary region to the sub-region, and from the sub-region to the unit region, an additional level of buffer can be placed. When dividing the sub-region, the fill block can be set according to different rules.

[0075] In one implementation, dividing a secondary region with an area of ​​3*3 includes: inserting a row and a column of fill blocks in the middle of the secondary region with an area of ​​3*3 to obtain a secondary region with an area of ​​4*4.

[0076] Divide the secondary region with an area of ​​4*4 into four sub-regions with an area of ​​2*2;

[0077] Remove the fill blocks from the 2x2 sub-region to obtain sub-regions with areas of 2x2, 2x1, 1x2, or 1x1.

[0078] Understandably, when dividing a 3x3 secondary region into sub-regions, it is only necessary to insert a row and a column of fill blocks in the middle of the 3x3 secondary region to obtain a 4x4 secondary region, and then obtain... Figure 3a The buffer is divided into four sub-regions: 3A1 (2x2), 3B1 (1x2), 3C1 (1x1), and 3D1 (2x1), with the dashed areas representing filler blocks. When setting the buffer placement, the secondary region of 4x4 is divided into four 2x2 sub-regions, each containing filler blocks. The center points of these 2x2 sub-regions are the buffer placement positions: 3o1, 3o2, 3o3, and 3o4. It should be noted that the 2x2 sub-regions contain filler blocks that are not part of the layout area; therefore, these filler blocks must be removed to obtain the 2x2 sub-regions 3A1, 3B1, 3C1, and 3D1. It should be noted that in 2*2, 2*1, 1*2, or 1*1 sub-regions, the buffer is placed at the center point of the sub-region before the padding block is removed. After the padding block is removed, the buffer's position remains unchanged. For example... Figure 3a As shown, the distances from 3oA to 3o1, 3o2, 3o3, and 3o4 are equal. Furthermore, Figure 3a In this process, there are sub-regions 3A1 (2x2), 3B1 (1x2), 3C1 (1x1), and 3D1 (2x1). Sub-region 3C1 is itself a unit region and cannot be further subdivided. Sub-region 3A1 (2x2) can be divided into four unit regions of 1x1 each. Sub-region 3B1 (1x2) can be divided into two unit regions of 1x1 each. Sub-region 3D1 (2x1) can also be divided into two unit regions of 1x1 each. The location where the buffer is placed on the unit region is the center point of the unit region. Thus, the sub-regions, sub-regions, and unit regions have been sequentially divided, starting with the 3x3 sub-region as the termination condition.

[0079] In one implementation, dividing the secondary region with an area of ​​4*3 includes:

[0080] Insert a row of fill blocks in the middle of a 4*3 area to obtain a secondary region with an area of ​​4*4;

[0081] Divide the secondary region with an area of ​​4*4 into four sub-regions with an area of ​​2*2;

[0082] Remove the fill blocks from the 2x2 sub-region to obtain sub-regions with areas of 2x2, 2x1, and 1x1;

[0083] Alternatively, the secondary region with an area of ​​3*4 can be divided into:

[0084] Insert a column of fill blocks in the middle of a 3*4 area to obtain a secondary region with an area of ​​4*4;

[0085] Divide the secondary region with an area of ​​4*4 into four sub-regions with an area of ​​2*2;

[0086] Remove the fill blocks from the 2x2 sub-region to obtain sub-regions with areas of 2x2, 1x2, and 1x1.

[0087] Understandably, when dividing a 3x4 secondary region into sub-regions, it is only necessary to insert a row of fill blocks in the middle of the 3x4 secondary region to obtain a 4x4 secondary region, and then obtain... Figure 3b The buffer is divided into four sub-regions: 3A2 (2x2), 3B2 (1x2), 3C2 (1x2), and 3D2 (2x2), with the dashed areas representing filler blocks. When setting the buffer placement, the secondary region of 4x4 is divided into four 2x2 sub-regions, each containing filler blocks. The center points of these 2x2 sub-regions are the buffer placement positions: 3O1, 3O2, 3O3, and 3O4. It's important to note that the 2x2 sub-regions contain filler blocks that are not part of the layout area; therefore, these filler blocks must be removed to obtain the 2x2 sub-regions 3A2, 3B2, 3C2, and 3D2. It should be noted that in the 2*2, 1*2, 1*2, and 1*1 sub-regions, the buffer is placed at the center point of the sub-region before the padding block is removed. After the padding block is removed, the buffer's position remains unchanged. For example... Figure 3a As shown, the distances from 3OB to 3O1, 3O2, 3O3 and 3O4 are equal.

[0088] Furthermore, Figure 3aIn this context, sub-regions 3A2 (2x2), 3B2 (1x2), 3C2 (1x2), and 3D2 (2x2) can be divided into four 1x1 unit regions. Sub-region 3A2 (2x2) can be further divided into two 1x1 unit regions, and so on. The center point of each unit region is where the buffer is placed. Thus, the division from sub-regions to unit regions has been completed sequentially, starting with the 3x4 sub-region.

[0089] It should be noted that if the four secondary regions are not of equal size during the final hierarchical processing, fill blocks are usually used to supplement the corresponding secondary regions, forming four secondary regions of equal area and size 4*3, 3*3, or 3*4. For example... Figure 5a As shown, the layout area is a 5x5 region on each side, which is actually divided into a 3x3 region 5A1, a 2x3 region 5B1, a 3x2 region 5D1, and a 2x2 region 5C1. To accommodate the buffers, a row and a column of fill blocks are added, making it four secondary regions with an area of ​​3x3. Figure 5c This diagram illustrates the process of dividing the secondary region 5B1 into subregions. As can be seen, the final result will be subregions 5B11, 5B12, 5B13, and 5B14, each with an area of ​​1*2. The locations for placing buffers in these subregions are 5o11, 5o12, 5o13, and 5o14, respectively. Furthermore, the distances from the buffer placement location 5o1 in the secondary region 5B1 to 5o11, 5o12, 5o13, and 5o14 are equidistant. Figure 5d This diagram illustrates the process of dividing the secondary region 5C1 into subregions. As can be seen, the final result will be subregions 5C11, 5C12, 5C13, and 5C14, each with an area of ​​1*2. The locations for placing buffers in these subregions are 5o21, 5o22, 5o23, and 5o24, respectively. Furthermore, the distances from the buffer placement location 5o2 in the secondary region 5C1 to 5o21, 5o22, 5o23, and 5o24 are equidistant. Figure 5eThis diagram illustrates the process of dividing secondary region 5D1 into subregions. As you can see, the final result will be subregions 5D11, 5D12, 5D13, and 5D14, each with an area of ​​1*2. The locations for placing buffers in these subregions are 5o31, 5o32, 5o33, and 5o34, respectively. Furthermore, the distances from the buffer placement location 5o3 in secondary region 5D1 to 5o31, 5o32, 5o33, and 5o34 are equidistant. Secondary region 5A1 is a 3*3 region; its subregion division can be referenced [reference needed]. Figure 3a I won't go into too much detail again. In other words, whether the fill blocks are added during the final hierarchical processing or during the process of dividing the secondary region into sub-regions, they all need to be removed in the end.

[0090] The second embodiment of the present invention also provides a method for constructing a clock tree, comprising the following steps:

[0091] A1. The layout area is divided using the above-mentioned layout area division method;

[0092] A2, place the buffer for the central area at the center point of the layout area;

[0093] A3, when the layout area is hierarchically processed, the layout area will be hierarchically processed by reducing the area. After each hierarchical processing, four secondary areas will be obtained. After each hierarchical processing, a secondary area cache will be placed at the center point of the four secondary areas after hierarchical processing.

[0094] A4, when the area of ​​the secondary region is equal to the product of its side lengths (4*3, 3*3, or 3*4).

[0095] A5, insert a fill block into the secondary region to obtain a secondary region with an area of ​​4*4, divide the secondary region into four sub-regions with an area of ​​2*2, and place a sub-region buffer at the center point of the sub-region.

[0096] A6. After completing the division of the layout area, obtain the position of the unit area and place the unit area buffer at the center point of the unit area.

[0097] A7 connects the central region cache, the secondary region cache during hierarchical processing, the sub-region cache, and the unit region cache in descending order of their area size to complete the construction of the clock tree.

[0098] It should be understood that after the chip's layout area is divided using the layout area division method in the first embodiment, a cache can be set in each divided area, ensuring that the distance from each level's cache to the next level's cache is equal, thus constructing a zero-skew clock tree. Furthermore, the first embodiment divides the layout area from largest to smallest area; in this embodiment, when constructing the clock tree, the clock tree will form a top-down construction order similar to the hierarchical processing in this embodiment.

[0099] Please combine Figure 1 and Figure 6 The third embodiment of this invention also provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions for causing a computer to execute the layout area division method described above.

[0100] The computer-readable storage medium provided in this embodiment of the invention has the same beneficial effects as the above-described layout area division method, and will not be described in detail here.

[0101] Please combine Figure 1 and Figure 7 The fourth embodiment of this invention also provides a computer device applied to the above-mentioned layout area division method, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the layout area division method.

[0102] The computer device provided in this embodiment of the invention has the same beneficial effects as the above-described method for dividing the layout area, and will not be described in detail here.

[0103] Please combine Figure 1 and Figure 8 The fifth embodiment of this invention also provides a computer program product, including a computer program or instructions, which, when executed by a processor, implement the above-described method for dividing the layout area.

[0104] The computer program product provided in this embodiment of the invention has the same beneficial effects as the above-described layout area division method, and will not be described in detail here.

[0105] The foregoing has provided a detailed description of a layout area partitioning method, a clock tree construction method, a computer media device, and a program product disclosed in the embodiments of the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention. Any modifications, equivalent substitutions, and improvements made within the principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for dividing a layout region, used to divide the layout region and place buffers to construct a clock tree, characterized in that: The method for dividing the layout area includes the following steps: Provides a rectangular layout area, which is then divided into several unit-length, array-distributed squares. Obtain the side length information of two adjacent sides of the layout area; The layout area is processed in multiple hierarchical steps based on the side length information to divide the layout area into four secondary areas with similar areas and composed of squares. The process of iteratively hierarchically processing the obtained secondary areas continues until the area of ​​the secondary area is 4*3, 3*3 or 3*4, where the area is the product of unit lengths. Determine if the area of ​​the secondary region is 3*3; If so, the secondary region with an area of ​​3*3 is divided into sub-regions with areas equal to the product of the side lengths of 2*2, 2*1, 1*2 and 1*1. The sub-regions with areas of 2*2, 1*2 and 2*1 are then divided into unit regions with areas equal to the area of ​​the square to complete the division of the layout area. If not, the secondary area with an area of ​​4*3 is divided into sub-areas with areas equal to the product of the side lengths of 2*2, 1*2, and 1*1, or the secondary area with an area of ​​3*4 is divided into sub-areas with areas equal to the product of the side lengths of 2*2, 2*1, and 1*1. The sub-areas with areas of 2*2 and 1*2 or with areas of 2*2 and 2*1 are then divided into unit areas with areas equal to the area of ​​the square to complete the division of the layout area.

2. The method for dividing the layout area as described in claim 1, characterized in that: The layout area is divided into four secondary areas of similar size, each composed of squares: Determine if all side lengths of the layout region are even numbers; If the side lengths of the layout area are all even numbers, the layout area is divided into four secondary areas with an area of ​​(side length / 2)*(side length*2). If the side length of the layout area is odd, then obtain the side length with odd length, and divide the layout area into two secondary areas with an area of ​​[(odd side length + 1) / 2] * [even side length / 2], and two secondary areas with an area of ​​[(odd side length - 1) / 2] * [even side length / 2]. If all sides of the layout area have odd lengths, then obtain the side lengths with odd lengths and divide the layout area into two secondary areas with an area of ​​[(odd side length + 1) / 2] * [(odd side length + 1) / 2] and an area of ​​two secondary areas with an area of ​​[(odd side length - 1) / 2] * [(odd side length - 1) / 2].

3. The method for dividing the layout area as described in claim 2, characterized in that: When iterating through the hierarchical process, the layout region with the largest area is divided into smaller and smaller sub-regions. Each sub-region will have a smaller area until the area of ​​the sub-region is 4*3, 3*3 or 3*4, where the area is the product of unit lengths.

4. The method for dividing the layout area as described in claim 3, characterized in that: The block is a block with a unit length of 1. If the four secondary regions are not equal in the last hierarchical processing, the smaller area will be supplemented with a filler block with an area equal to that of the block, so that the area and side length information of the four secondary regions in the last hierarchical processing are equal.

5. The method for dividing the layout area as described in claim 4, characterized in that: The division of the secondary region with an area of ​​3*3 includes: Insert a row and a column of fill blocks in the middle of a secondary region with an area of ​​3*3 to obtain a secondary region with an area of ​​4*4; Divide the secondary region with an area of ​​4*4 into four sub-regions with an area of ​​2*2; Remove the fill blocks from the 2x2 sub-region to obtain sub-regions with areas of 2x2, 1x2, and 1x1.

6. The method for dividing the layout area as described in claim 4, characterized in that: The division of the secondary region with an area of ​​4*3 includes: Insert a row of fill blocks in the middle of a 4*3 area to obtain a secondary region with an area of ​​4*4; Divide the secondary region with an area of ​​4*4 into four sub-regions with an area of ​​2*2; Remove the fill blocks from the 2x2 sub-region to obtain sub-regions with areas of 2x2, 2x1, and 1x1; Or, the division of the secondary region with an area of ​​3*4 includes: Insert a column of fill blocks in the middle of a 3*4 area to obtain a secondary region with an area of ​​4*4; Divide the secondary region with an area of ​​4*4 into four sub-regions with an area of ​​2*2; Remove the fill blocks from the 2x2 sub-region to obtain sub-regions with areas of 2x2, 1x2, or 1x1.

7. A method for constructing a clock tree, characterized in that: Includes the following steps: The layout area is divided using the layout area division method described in any one of claims 1-6; Place the buffer for the central region at the center point of the layout area; When the layout region is hierarchically processed, the layout region will be hierarchically processed by reducing the area. After each hierarchical processing, four secondary regions will be obtained. After each hierarchical processing, a secondary region buffer will be placed at the center point of the four secondary regions after hierarchical processing. When the area of ​​the secondary region is equal to the product of its side lengths, which is 4*3, 3*3, or 3*4. Insert a fill block into the secondary region to obtain a secondary region with an area of ​​4*4. Divide the secondary region into four sub-regions with an area of ​​2*2. Place a sub-region buffer at the center point of the sub-region. After completing the division of the layout area, obtain the position of the unit area and place the unit area buffer at the center point of the unit area; The clock tree is constructed by connecting the central region cache, the secondary region cache during hierarchical processing, the sub-region cache, and the unit region cache in descending order of the area where the cache is located.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions for causing the computer to execute the layout region division method according to any one of claims 1 to 6.

9. A computer device, applied to the layout area division method as described in any one of claims 1 to 6, characterized in that: It includes a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the layout region division method.

10. A computer program product, characterized in that: It includes a computer program or instructions that, when executed by a processor, implement the layout region division method as described in any one of claims 1 to 6.

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