Layout wiring optimization method and device, storage medium and product

Abstract

The invention relates to the technical field of integrated circuit design, in particular to a layout wiring optimization method and device, a storage medium and a product. The method comprises the following steps: providing a design rule file, initializing layout information of integrated circuit design, and generating a violation database; performing violation detection on the initial layout to obtain layout violations, and dividing the layout violations into to-be-divided violations and a second type of violations; obtaining violation information of the to-be-divided violation, and dividing the to-be-divided violation into a third type of violation and a first type of violation; performing first-class repair on the first-class violation, and updating layout information and layout violation information; performing second-class repair on the second-class violation, and updating layout information and layout violation information; and repeating the repair step of the first type of violation and the second type of violation until a preset termination condition is met, performing first type repair on the third type of violation, and updating the layout information to obtain an optimized layout. The problem that the existing violation repairing efficiency and effect are poor is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a layout wiring optimization method, device, storage medium and product. Background Art

[0002] During the VLSI chip design process, physical design rules become increasingly complex as manufacturing process nodes advance. If the routing results fail to meet the design rule constraints, a design rule violation will occur, significantly reducing yield. To repair these design rule violations, two approaches are generally used: small-scale repair, which involves local adjustments to the layer where the violation occurred and adjacent layers; and large-scale repair, which involves adjusting routing patterns across multiple layers over a larger area. Considering both routing runtime and violation repair requirements, small-scale repairs are generally prioritized, with large-scale repairs used for violations that cannot be fixed.

[0003] However, in extensive practice, we've found that due to the iteration and increased utilization of design rules, small-scale fixes to some rules will occupy adjacent routing resources, leading to increased congestion in subsequent routing. This leaves insufficient routing resources for large-scale fixes to resolve complex violations, ultimately leading to slow runtimes and inability to fully repair violations when actually fixing them. Summary of the Invention

[0004] In order to solve the technical problem of poor efficiency and effect of existing wiring violation repair, the present invention provides a layout wiring optimization method, device, storage medium and product.

[0005] The solution to the technical problem of the present invention is to provide a layout wiring optimization method, including: providing a design rule file and an initial layout, generating a violation database based on the design rule file and the initial layout, wherein the violation database pre-stores violation information of multiple layout violations, wherein the violation information includes the layer where the violation is located, the violation type, the violation repair range and the violation repair method, wherein the repair method includes the first type of repair and the second type of repair; performing violation detection on the initial layout to obtain layout violations, and dividing the layout violations into violations to be divided and second types of violations based on the size of the violation repair range; obtaining violation information of the violations to be divided, and dividing the violations to be divided that meet the preset constraints into third types of violations. Otherwise, it is classified as a first-class violation, wherein the preset constraints are that the layer where the violation is located is a metal layer, the violation type is a spacing violation and does not violate the angular spacing rule, and the violation repair method is to add metal or cut metal on the edge perpendicular to the preferred wiring direction; the first-class repair is performed on the first-class violation in the current layout, and the layout information and layout violation information are updated; the second-class repair is performed on the second-class violation in the current layout, and the layout information and layout violation information are updated; the repair steps for the first-class violation and the second-class violation are repeated until the preset termination threshold is met, the first-class repair is performed on the third-class violation, and the layout information is updated to obtain an optimized layout.

[0006] Preferably, violation detection is performed on the initial layout to obtain layout violations, and the layout violations are divided into violations to be divided and second-class violations based on the size of the violation repair range, including: violation detection is performed on the initial layout based on the design rule file to obtain layout violations; the violation repair range corresponding to each layout violation is obtained based on the violation database, and the violation repair range includes a repair layer and a repair amplitude; layout violations whose repair layer is the layer where the violation is located and / or the adjacent layer and whose repair amplitude is less than a preset threshold are divided into violations to be divided, otherwise, they are divided into second-class violations.

[0007] Preferably, the preset threshold is the spacing between adjacent wiring tracks perpendicular to the preferred wiring direction; when the repair layer of the layout violation includes non-adjacent layers of the layer where the violation is located, and / or the repair amplitude is greater than or equal to the preset threshold, the layout violation is classified as a second type of violation; the first type of repair is a repair of the layer where the violation is located and / or the adjacent layers, and the repair amplitude is less than the preset threshold; the second type of repair is a repair of non-adjacent layers of the layer where the violation is located, and / or a repair with a repair amplitude greater than or equal to the preset threshold.

[0008] Preferably, before performing the first type of repair on the first type of violations in the current layout, the method includes: dividing the current layout into multiple repair areas.

[0009] Preferably, when repairing the current layout, multiple repair areas can be processed in parallel.

[0010] Preferably, performing a second type of repair on the second type of violation in the current layout includes: detecting whether there is a first type of violation in the current layout, and if so, performing a second type of repair on the first type of violation and the second type of violation in the current layout.

[0011] Preferably, the preset termination threshold includes the number of repeated repairs reaching a preset value, and / or the total number of first-type violations and second-type violations in the current layout reaching a preset value.

[0012] In order to solve the above technical problems, the present invention provides another technical solution as follows: an electronic device, comprising a memory, a processor and a computer program stored in the memory, wherein the processor executes the computer program to implement the layout wiring optimization method as described in any one of the above items.

[0013] In order to solve the above technical problems, the present invention provides another technical solution as follows: a computer storage medium storing computer program instructions, which implement the layout wiring optimization method as described in any one of the above items when executed.

[0014] In order to solve the above technical problems, the present invention provides another technical solution as follows: a computer program product, including a computer program, which implements the layout wiring optimization method as described in any of the above items when executed by a processor.

[0015] Compared with the prior art, the layout and routing optimization method, device, storage medium, and product provided by the present invention have the following advantages: 1. An embodiment of the present invention provides a layout routing optimization method. By dynamically dividing layout violations into three categories and repairing violations of different categories in stages, violations that can be repaired in a small local area are decoupled from violations that require large-scale wiring removal and rerouting. This not only avoids timing disruption and layout oscillation caused by large-scale changes, but also enables the repair process to quickly eliminate a large number of easily repairable violations in the early stage, facilitating the concentration of resources to resolve stubborn violations in the later stage, significantly reducing iterative conflicts in the repair process, and delaying the repair of third-category violations that meet specific constraints and occupy adjacent wiring resources to avoid the impact of early local optimization on global wiring. The repair order of different types of violations is controlled through a phased repair strategy, suppressing the chain reaction of violations caused by local repair in the traditional violation repair process. Secondly, the repair process is controlled in combination with preset termination conditions, shortening the overall convergence time, improving optimization efficiency and wiring success rate while ensuring repair quality, and significantly reducing the number of manual interventions, ultimately generating a highly reliable integrated circuit layout.

[0016] 2. The layout routing optimization method provided by the embodiment of the present invention realizes automatic classification based on the quantitative comparison between the violation repair range and the preset repair range. Specifically, the violation repair range of each layout violation is first obtained from the violation database, and the first division can be completed by comparing the "violation repair range" with the "preset repair range" once. The algorithm complexity is low and the implementation is simple; the layout violations that require large-scale chain modifications are identified and divided into the second type of violations at one time, avoiding repeated judgments in subsequent iterations, and significantly reducing CPU usage and memory peak; by accurately distinguishing "violations to be divided" and "second type violations", the foundation is laid for the subsequent phased repair strategy, improving classification efficiency and accuracy, and reducing computing resource consumption.

[0017] 3. The layout and routing optimization method provided by the embodiments of the present invention uses both the repair layer and the repair amplitude of the violation as criteria for determining pending violations, thereby achieving precise quantification of the dual constraints of modification location and modification amplitude. This prevents the misjudgment of second-type violations (cross-layer coupling or cross-track violations requiring extensive repair) as pending violations requiring only local fine-tuning. This makes the set of pending violations more purified, lays a solid foundation for the subsequent subdivision of first-type and third-type violations, and further reduces the false repair rate. Secondly, two types of repair methods are defined by the size of the "repair range", so that the repair strategy matches the violation classification and the applicable scenarios of the two repair methods are clarified. The first type of repair is used for local fine-tuning, and the second type of repair is used to handle large-scale wiring and routing. The two work together to achieve refined resource allocation and reduce invalid calculations. During the repair process, the appropriate repair method is selected according to the violation classification to improve the accuracy of the repair and avoid secondary violations or incomplete repairs due to improper selection of repair methods.

[0018] 4. The layout routing optimization method provided in the embodiment of the present invention divides the current layout into multiple repair areas, and performs repairs in parallel based on the repair areas when repairing violations, making full use of the parallel capabilities of multi-core processors to accelerate the repair of high-frequency, low-complexity first-class violations. It can complete the repair of a large number of first-class violations in a short time, greatly shortening the total optimization time; and the division of the repair areas makes the repair work more focused, the boundaries between areas are controlled, and the mutual interference between areas is reduced. Local modifications will not immediately spread to the entire chip, maintaining the stability of the early layout and improving the overall optimization efficiency and quality.

[0019] 5. In the layout and wiring optimization method provided by the embodiment of the present invention, the first-class violations that cannot be repaired by the first-class repair or will cause other design rule violations after repair will be temporarily suspended, so that the second-class repair can be carried out together with the second-class violations. In the second-class repair, the first-class violations left over from the above steps are detected and processed synchronously, and the second-class repair strategy is uniformly adopted to repair them at one time, so as to avoid the cross-influence of new graphics introduced by the first-class repair and the second-class violations to be processed, thereby ensuring the comprehensiveness of the repair. By collaboratively repairing related violations, the secondary violations caused by step-by-step repair are reduced, and the layout is improved. Figure 1 Consistency and repair success rate.

[0020] 6. The layout routing optimization method provided in the embodiment of the present invention provides two iterative termination conditions: "number of repetitions" and "total number of violations". Through the coordinated cooperation of these two termination conditions, the optimization depth and computational cost are balanced, ensuring convergence within a controllable time, taking into account both quality and progress, avoiding infinite loops or premature termination, and improving optimization efficiency while ensuring that the repair effect meets the expected conditions, saving optimization time and computing resources.

[0021] 7. An embodiment of the present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the layout and wiring optimization method as described in any one of the above items.

[0022] The electronic device implements the layout and wiring optimization method by executing the corresponding computer program through the processor, converting the method into a practical and operable electronic device function, which is convenient for application in actual integrated circuit design work, improves the work efficiency of designers, and promotes the automation and intelligence of the integrated circuit design process. The electronic device of this embodiment also has the same beneficial effects as the above-mentioned layout and wiring optimization method, which will not be repeated here.

[0023] 8. An embodiment of the present invention further provides a computer storage medium on which computer program instructions are stored. When the computer program instructions are executed, the layout and wiring optimization method as described in any one of the above items is implemented.

[0024] The computer storage medium stores relevant computing program instructions, so that the layout and wiring optimization method can be conveniently stored, transmitted and executed, which facilitates the promotion of the layout and wiring optimization method, lowers the usage threshold and maintains algorithm consistency, and helps more integrated circuit design scenarios adopt the layout and wiring optimization method to improve design quality. The computer storage medium of this embodiment also has the same beneficial effects as the above-mentioned layout and wiring optimization method, which will not be repeated here.

[0025] 9. Embodiments of the present invention further provide a computer program product, comprising a computer program, which, when executed by a processor, implements the layout and routing optimization method described in any of the above items. This computer program has the same beneficial effects as the layout and routing optimization method described above, and is not further described here. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0027] Figure 1 This is a flowchart of the steps of a layout routing optimization method provided by an embodiment of the present invention.

[0028] Figure 2 This is an example diagram of performing small-scale repairs on rule violations in a layout routing optimization method provided by an embodiment of the present invention.

[0029] Figure 3 This is an example of a large-scale repair of design rule violations in the layout routing optimization method provided by an embodiment of the present invention. Figure 1 .

[0030] Figure 4 This is an example of a large-scale repair of design rule violations in the layout routing optimization method provided by an embodiment of the present invention. Figure 2 .

[0031] Figure 5 This is a detailed flow chart of step 2 in the layout and routing optimization method provided in an embodiment of the present invention.

[0032] Figure 6 It is a structural diagram of an electronic device provided by an embodiment of the present invention.

[0033] Figure 7 It is a structural diagram of a computer storage medium provided by an embodiment of the present invention.

[0034] Figure 8 It is a schematic diagram of the structure of a computer program product provided by an embodiment of the present invention.

[0035] Description of the accompanying drawings: 1. Electronic device; 11. Memory; 12. Processor; 2. Computer storage medium; 3. Computer program product. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and implementation examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0037] In the embodiments provided herein, it should be understood that "B corresponding to A" means that B is associated with A and B can be determined based on A. However, it should also be understood that determining B based on A does not mean determining B based solely on A; B can also be determined based on A and / or other information.

[0038] It should be understood that references to "one embodiment" or "an embodiment" throughout this specification mean that specific features, structures, or characteristics associated with the embodiment are included in at least one embodiment of the present invention. Therefore, the appearance of "in one embodiment" or "in an embodiment" throughout this specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Those skilled in the art should also be aware that the embodiments described in this specification are all optional embodiments, and the actions and modules involved are not necessarily required for the present invention.

[0039] In various embodiments of the present invention, it should be understood that the size of the serial numbers of the above-mentioned processes does not necessarily mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0040] The flow charts and block diagrams in the accompanying drawings of the present invention illustrate the possible implementation architecture, functions and operations of the system, method and computer program product according to various embodiments of the present application. In this regard, each box in the flow chart or block diagram can represent a module, program segment or a part of code, and the module, program segment or a part of code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementation schemes, the functions marked in the box can also occur in a different order than those marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which is determined based on the functions involved. It should be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs the specified function or operation, or can be implemented by a combination of dedicated hardware and computer instructions.

[0041] A wiring track refers to a predefined parallel path for laying out metal wires on each metal wiring layer of an integrated circuit chip; the directions of wiring tracks on different metal layers are usually alternating.

[0042] See also Figure 1-4 , an embodiment of the present invention provides a layout routing optimization method, comprising: Step S1: providing a design rule file and an initial layout, and generating a violation database based on the design rule file and the initial layout. The violation database pre-stores violation information of multiple layout violations, including the violation layer, violation type, violation repair scope, and violation repair method. The repair method includes first-class repair and second-class repair. Step S2: Perform violation detection on the initial layout to obtain layout violations, and divide the layout violations into pending violations and second-class violations based on the size of the violation repair range; Step S3: Obtaining violation information of the violations to be classified, classifying the violations to be classified as the third type if they meet the preset constraints, and classifying them as the first type if they do not meet the preset constraints, wherein the preset constraints are that the layer where the violation is located is a metal layer, the violation type is a spacing violation and does not violate the angular spacing rule, and the violation repair method is to add metal or cut metal on the edge perpendicular to the preferred routing direction; Step S4: performing a first type of repair on the first type of violation in the current layout, and updating the layout information and layout violation information; Step S5: performing a second type of repair on the second type of violation in the current layout, and updating the layout information and layout violation information; Step S6: Repeat the steps of repairing the first and second types of violations until a preset termination threshold is met, perform the first type of repair on the third type of violations, and update the layout information to obtain an optimized layout.

[0043] Specifically, the layout routing optimization method provided in this embodiment is used to optimize routing of a multi-layer integrated circuit design.

[0044] It should be understood that updating the layout information and layout violation information in step S3 and step S5 includes updating the wiring status of the current layout, updating the violations existing in the current layout, and the classification corresponding to the violations.

[0045] Specifically, "repeating the steps of repairing the first type of violation and the second type of violation" in step S6 refers to repeatedly executing the operations of step S4 and step S5.

[0046] It should be noted that, based on the size of the violation repair range, the violation repair methods can be roughly divided into two types: small-scale repair and large-scale repair. Small-scale repairs make small changes to the layout, belong to local fine-tuning, are highly efficient, and rarely affect other wiring violations; however, there are some violations that will occupy additional wiring resources after small-scale repairs, resulting in increased congestion in subsequent wiring. If such violations are repaired in the early stages, they may significantly reduce the utilization of wiring resources or increase the difficulty of subsequent repairs. The layout wiring optimization method provided by the present invention intelligently and dynamically divides layout violations into three categories, and performs targeted repairs on violations of different categories in stages to avoid mutual interference during the repair process, thereby effectively improving the compliance and optimization structure of layout wiring and improving the quality of layout design.

[0047] It can be understood that the layout wiring optimization method provided by the present invention first classifies layout violations into violations to be divided and second-class violations according to the size of the violation repair range, decouples the violations that can be repaired in a small local area from the violations that require large-scale wiring removal and rewiring, and then classifies the violations that meet specific constraints and occupy adjacent wiring resources among the violations to be divided into third-class violations, and classifies the violations that only require local fine-tuning and do not affect subsequent wiring into first-class violations; according to the characteristics of different types of violations, specific violations are repaired at different stages: first-class violations with a small repair range are prioritized, and then second-class violations with a large repair range are processed, which not only avoids the timing disturbance and layout oscillation caused by large-scale changes, but also makes the repair The repair process can quickly eliminate a large number of easy-to-repair violations in the early stage, making it easier to concentrate resources on solving stubborn violations in the later stage, significantly reducing iterative conflicts in the repair process, and at the same time delaying the repair of third-type violations that meet specific constraints and occupy adjacent wiring resources, avoiding the impact of early local optimization on global wiring, and controlling the repair order of different types of violations through a phased repair strategy, thereby suppressing the chain violation reaction caused by local repair in the traditional violation repair process; secondly, the repair process is controlled by combining preset termination conditions, shortening the overall convergence time, improving optimization efficiency while ensuring repair quality, increasing the wiring success rate, and significantly reducing the number of manual interventions, ultimately generating a highly reliable integrated circuit layout.

[0048] Furthermore, step S1 also includes pre-processing the design rule file and the information of the initial layout to obtain data information that can be used to construct a violation database, and generating the violation database based on the data information.

[0049] It should be noted that there are multiple wiring templates in the design rule file. For some specific templates, there are violations or they are prone to cause certain violations. By comparing the initial layout with the wiring templates in the design rule file, the possible violations of the initial layout and the corresponding repair methods can be obtained. Based on this information, a violation database can be constructed so that in subsequent steps, the layout violations can be quickly and accurately classified and repaired through the violation database.

[0050] Specifically, the aforementioned data information includes but is not limited to: routing tracks, preferred routing directions, through holes, whether to add graphics to repair violations, violation information, etc.

[0051] See also Figure 5 Step S2: Detect violations on the initial layout to obtain layout violations. Based on the size of the violation repair range, the layout violations are divided into pending violations and second-class violations, including: Step S21: performing violation detection on the initial layout based on the design rule file to obtain layout violations; Step S22: obtaining a violation repair range corresponding to each layout violation based on the violation database, where the violation repair range includes a repair layer and a repair amplitude; Step S23: Classify layout violations whose repair layer is the layer where the violation is located and / or the adjacent layer and whose repair amplitude is less than a preset threshold as violations to be classified; otherwise, classify them as second-class violations.

[0052] Understandably, using the "repair layer and repair range of violations" as the dividing indicators between violations to be divided and second-category violations, through clear scope definition, the division can be quickly completed by comparing the "violation repair range" of the violation in the database with the "preset repair range". The algorithm has low complexity and is simple to implement. It can identify and classify layout violations that require large-scale chain changes as second-category violations at one time, avoiding repeated judgments in subsequent iterations, and significantly reducing CPU usage and memory peaks. By accurately distinguishing "violations to be divided" and "second-category violations", it lays the foundation for subsequent phased repair strategies, avoiding local and ineffective fine-tuning of second-category violations in the early stage, improving classification efficiency and accuracy, and reducing computing resource consumption.

[0053] Specifically, the preset threshold is the spacing between adjacent wiring tracks perpendicular to the preferred wiring direction; when the repair layer of the layout violation includes non-adjacent layers of the layer where the violation is located, and / or the repair amplitude is greater than or equal to the preset threshold, the layout violation is classified as a second type of violation.

[0054] Specifically, the non-adjacent layers of the layer where the violation is located refer to other metal layers or through-hole layers except the layer where the violation is located and its adjacent layers.

[0055] It should be noted that within the same layer, the directions of the wiring tracks are consistent, but the directions of the wiring tracks on different layers may be inconsistent, that is, there are multiple parallel tracks. The spacing between adjacent wiring tracks perpendicular to the preferred wiring direction refers to the distance between the wiring track where the violation to be repaired is located and the adjacent wiring track in its repair direction. The repair direction here refers to the direction perpendicular to the preferred wiring direction.

[0056] Specifically, if the violation repair requires multiple adjustments, the wiring track spacing of the specific layer where the adjustment is made should be used as the judgment standard for the repair extent, that is, the adjustment of the first layer cannot be compared with the wiring track spacing of the second layer.

[0057] For example, in a certain metal layer, the preferred wiring track direction is the X direction, and the direction perpendicular to the preferred wiring direction is the Y direction. Assuming that the violation is repaired by moving a line in the Y direction in the current layer or in an adjacent layer of the layer where the violation is located, and the moving range does not reach the nearest wiring track in its moving direction, then the violation is defined as a violation to be classified; if the repair method is to repair a non-adjacent layer of the layer where the violation is located, and / or the moving range of the line to be moved during the repair is to move to or over its adjacent wiring track, then the violation is defined as a second-class violation.

[0058] It can be understood that if the number of layers that need to be adjusted when repairing a violation is greater than 3 layers, it is a second-class violation; if the number of layers that need to be adjusted when repairing a violation is equal to 3 layers, it is necessary to determine the relationship between the repair layer and the layer where the violation is located. For example, if the repair layer is the two layers above or below the layer where the violation is located, at this time, if one of the repair layers is a non-adjacent layer of the layer where the violation is located, the violation is also determined to be a second-class violation; if the layer above and below the layer where the violation is located needs to be adjusted when repairing the violation, at this time, although the repair adjustment also involves 3 layers, since both repair layers are adjacent layers of the layer where the violation is located, the violation is not necessarily a second-class violation. Only when its repair amplitude is greater than or equal to the adjacent wiring track spacing perpendicular to the preferred wiring direction, the violation is defined as a second-class violation. If its repair amplitude is less than the adjacent wiring track spacing perpendicular to the preferred wiring direction, the violation is defined as a violation to be classified.

[0059] Understandably, the repair layer and repair amplitude of the violation are simultaneously used as the criteria for determining the violations to be divided, thereby achieving accurate quantification of the dual constraints of modification position and modification amplitude, preventing the second type of violations that require large-scale repair due to cross-layer coupling or cross-track from being misjudged as violations to be divided that only require local fine-tuning, making the set of violations to be divided purer, laying a solid foundation for the subsequent further subdivision of the first and third types of violations, and further reducing the false repair rate.

[0060] It should be noted that when the repair range of the layout violation exceeds any one of the first threshold and the second threshold, the layout violation is classified as a second type of violation.

[0061] This embodiment enhances the reliability of violation classification through dual-threshold joint judgment, fully considers the spatial relationship and wiring rules in the multi-layer integrated circuit layout wiring, makes the violation classification more scientific and reasonable, and ensures the stability and reliability of subsequent repair.

[0062] Specifically, the first type of repair is the repair of the layer where the violation is located and / or the adjacent layers, and the repair amplitude is less than the preset threshold; the second type of repair is the repair of non-adjacent layers of the layer where the violation is located, and / or the repair amplitude is greater than or equal to the preset threshold.

[0063] Understandably, two types of repair methods are defined by the size of the "repair range", so that the repair strategy matches the violation classification and the applicable scenarios of the two repair methods are clarified. The first type of repair is used for local fine-tuning, and the second type of repair is used to handle large-scale wiring and routing. The two work together to achieve refined resource allocation and reduce invalid calculations. During the repair process, the appropriate repair method is selected according to the violation classification to improve the accuracy of the repair and avoid secondary violations or incomplete repairs due to improper selection of repair methods.

[0064] Furthermore, before performing the first type of repair on the first type of violation in the current layout, the method includes: dividing the current layout into multiple repair areas.

[0065] Specifically, when repairing the current layout, multiple repair areas can be processed in parallel.

[0066] In some embodiments, by setting the side length, the current layout is divided into multiple rectangular areas of uniform size, and different areas are assigned to different computing threads for parallel computing.

[0067] Specifically, the initial layout can be directly divided into regions, and the subsequent cyclic repair process can directly reference the divided regions of the initial layout for repair calculations, avoiding multiple layout region division operations, simplifying the operation process, and improving calculation efficiency.

[0068] In other embodiments, the division of the repair area can also be based on the amount of calculation, that is, a regional calculation amount is preset, that is, the number of first-class violations that need to be calculated in each area, and the current layout is divided into rectangular areas of different areas, and the number of first-class violations to be calculated in each area is roughly the same, so that the time spent on parallel repair of first-class violations in each area is roughly the same, avoiding the situation where the calculation amount of individual threads is large, causing other calculation threads to wait.

[0069] It should be understood that parallel processing of multiple repair areas can be carried out in different repair stages, and the specific selection can be made according to actual conditions. Each repair stage can be partitioned and processed in parallel, or some repair stages can be partitioned and processed in parallel, while some repair stages are processed globally and uniformly.

[0070] It should be noted that, in this embodiment, after performing the first type of repair on the first type of violation in each repair area, the layout information and layout violation information of the area are updated at the same time, that is, the first type of violation repair and information update calculation are performed on the layout by area, and the calculations in different areas are processed in parallel, thereby improving the calculation efficiency; specifically, when performing the second type of repair on the second type of violation or the first type of repair on the third type of violation, multiple areas are also repaired and updated in parallel based on the repair area.

[0071] Understandably, the current layout is divided into multiple repair areas, and when repairing violations, repairs are performed in parallel based on the repair area. This fully utilizes the parallel capabilities of multi-core processors to accelerate the repair of high-frequency, low-complexity first-class violations. A large number of first-class violations can be repaired in a short time, greatly shortening the total optimization time. The division of the repair area makes the repair work more focused, the boundaries between areas are controlled, and mutual interference between areas is reduced. Local modifications will not immediately spread to the entire chip, maintaining early layout stability and improving overall optimization efficiency and quality.

[0072] Furthermore, performing a second type of repair on the second type of violation in the current layout includes: detecting whether there is a first type of violation in the current layout, and if so, performing a second type of repair on the first type of violation and the second type of violation in the current layout.

[0073] It should be noted that some first-category violations will generate new design rule violations after the first-category repair. Therefore, in the actual repair process, the repair results of such violations will be withdrawn and the violations will be retained to perform the second-category repair together with the second-category violations in the next step.

[0074] Understandably, the first-class violations that cannot be repaired by the first-class repair or will cause other design rule violations after repair will be postponed for repair, and the second-class repair will be carried out together with the second-class violations. In the second-class repair, the first-class violations left over from the previous steps will be detected and processed synchronously, and the second-class repair strategy will be uniformly adopted for repair at one time to avoid the cross-influence of new graphics introduced by the first-class repair and the second-class violations to be processed, thereby ensuring the comprehensiveness of the repair. By collaboratively repairing related violations, the secondary violations caused by step-by-step repairs can be reduced, and the version can be improved. Figure 1 Consistency and repair success rate.

[0075] Furthermore, the preset termination threshold includes the number of repeated repairs reaching a preset value, and / or the total number of first-type violations and second-type violations in the current layout reaching a preset value.

[0076] Optionally, the specific value of the preset termination threshold can be adjusted according to actual usage requirements and is not subject to excessive restrictions here.

[0077] Understandably, controlling the number of loop repairs can prevent infinite iterations, and terminating the loop early when the total number of remaining violations reaches the standard can avoid over-optimization, taking into account both efficiency and quality. Two iteration termination conditions, "number of repetitions" and "total number of violations", are provided. Through the coordinated cooperation of these two termination conditions, the optimization depth and computational cost are balanced, ensuring convergence within a controllable time, taking into account both quality and progress, avoiding infinite loops or premature termination, and improving optimization efficiency while ensuring that the repair effect meets the expected conditions, saving optimization time and computing resources.

[0078] Specifically, Table 1 lists three different violation classification methods and repair timings for an area of ​​614825.16um. 2 , a chip design layout with 1,676,845 standard cells at a 7nm process node was repaired, resulting in different design rule violation results. The three solutions in this embodiment use exactly the same design rule file and layout information, and the termination conditions are all set to either repeat the repair process 20 times or the total number of first and second type violations in the current layout is zero.

[0079]

[0080] Table 1. Effect of different repair solutions on the number of final design rule violations for the same design As shown in Table 1, classifying third-category violations and fixing them after the threshold requirement is met can optimize runtime and significantly reduce the number of violations remaining in the layout. Compared to not classifying third-category violations, runtime is reduced by 14.51%, and the number of violations in the layout is reduced by 99.17%. Furthermore, compared to not classifying third-category violations, classifying third-category violations and not fixing them after the threshold requirement is met reduces the number of violations by 96.81%. This indicates that prematurely fixing third-category violations does indeed occupy a significant amount of routing resources and makes the remaining violations difficult to fix. Delaying the repair of third-category violations effectively reduces routing congestion and improves repair efficiency.

[0081] Please see further Figure 6 An embodiment of the present invention further provides an electronic device 1, comprising a memory 11, a processor 12, and a computer program stored in the memory 11, wherein the processor 12 executes the computer program to implement the layout and wiring optimization method as described in any one of the above items.

[0082] Specifically, the electronic device 1 may be a smart phone, a tablet computer, a computer, a portable computer or other device.

[0083] It should be noted that the processor 12 may include one or more cores and message matrix units for processing data. The processor 12 utilizes various interfaces and circuits to connect various components within the entire electronic device 1. By running or executing instructions, programs, code sets, or instruction sets stored in the memory 11 and accessing data stored in the memory 11, the processor 12 performs various functions of the electronic device 1 and processes data.

[0084] Optionally, the processor 12 may be implemented in hardware using at least one of a digital signal processor, a field programmable gate array, and a programmable logic array. The processor 12 may integrate one or a combination of a central processing unit, an image processor, and a modulation decoder. The modulation decoder may also be implemented independently of the processor 12 via a communication chip.

[0085] It can be understood that the electronic device 1 implements the layout wiring optimization method by executing the corresponding computer program through the processor 12, converting the method into a practical and operable function of the electronic device 1, which is convenient for application in actual integrated circuit design work, improves the work efficiency of designers, and promotes the automation and intelligence of the integrated circuit design process. The electronic device 1 of this embodiment also has the same beneficial effects as the above-mentioned layout wiring optimization method, which will not be repeated here.

[0086] See also Figure 7 An embodiment of the present invention further provides a computer storage medium 2 on which computer program instructions are stored. When the computer program instructions are executed, the layout and wiring optimization method as described in any one of the above items is implemented.

[0087] It can be understood that the computer storage medium 2 stores relevant computing program instructions, so that the layout and wiring optimization method can be conveniently stored, transmitted and executed, which provides convenience for the promotion of the layout and wiring optimization method, lowers the usage threshold and maintains algorithm consistency, and helps more integrated circuit design scenarios to adopt the layout and wiring optimization method to improve design quality. The computer storage medium 2 of this embodiment also has the same beneficial effects as the above-mentioned layout and wiring optimization method, which will not be repeated here.

[0088] See also Figure 8 An embodiment of the present invention further provides a computer program product, comprising a computer program, which implements the layout and routing optimization method as described above when executed by a processor.

[0089] It is understood that the computer program product 3 provided in this embodiment includes computer instructions, which may be stored in a computer storage medium. The processor 12 of the electronic device 1 reads the computer instructions from the storage medium and executes the computer instructions, causing the electronic device 1 to perform the layout and routing optimization methods described in the various optional implementations described above.

[0090] It is understandable that, according to the embodiments disclosed in the present invention, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program contains program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication part, and / or installed from a removable medium. When the computer program is executed by a central processing unit (CPU), the above functions defined in the method of the present application are executed. It should be noted that the computer-readable medium described in the present application can be a computer-readable signal medium or a computer-readable storage medium or any combination of the above. Computer-readable storage media, for example, include but are not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or devices, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to, an electrical connection having one or more conductors, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In this application, a computer-readable storage medium may be any tangible medium containing or storing a program for use by or in conjunction with an instruction execution system, apparatus, or device. In this application, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such a propagated data signal may take a variety of forms, including, but not limited to, electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device. Program code embodied on a computer-readable medium may be transmitted using any suitable medium, including, but not limited to, wireless, wire, optical cable, RF, or any suitable combination thereof.

[0091] The computer program code for performing the operations of the present application may be written in one or more programming languages, or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0092] The above is a detailed introduction to a layout routing optimization method, device, storage medium and product disclosed in an embodiment of the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the ideas of the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on the present invention. Any modifications, equivalent replacements and improvements made within the principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A layout routing optimization method, characterized in that: include: Providing a design rule file and an initial layout, generating a violation database based on the design rule file and the initial layout, wherein the violation database pre-stores violation information of a plurality of layout violations, wherein the violation information includes a layer where the violation is located, a violation type, a violation repair scope, and a violation repair method, wherein the repair method includes a first type of repair and a second type of repair; Performing violation detection on the initial layout to obtain layout violations, and dividing the layout violations into pending violations and second-category violations based on the size of the violation repair range; Obtaining violation information of a violation to be classified, classifying the violation to be classified as a third type violation if it satisfies a preset constraint, and otherwise classifying it as a first type violation, wherein the preset constraint is that the layer where the violation is located is a metal layer, the violation type is a spacing violation and does not violate an angular spacing rule, and the violation repair method is adding metal or cutting metal on an edge perpendicular to a preferred routing direction; Performing the first type of repair on the first type of violation in the current layout, and updating the layout information and layout violation information; Performing the second type of repair on the second type of violation in the current layout, and updating the layout information and layout violation information; Repeat the steps of repairing the first and second types of violations until a preset termination threshold is met, perform the first type of repair on the third type of violations, and update the layout information to obtain an optimized layout.

2. The layout and routing optimization method according to claim 1, wherein: Performing violation detection on the initial layout to obtain layout violations, and dividing the layout violations into pending violations and second-class violations based on the size of the violation repair range, including: Performing violation detection on the initial layout based on the design rule file to obtain layout violations; Acquire a violation repair range corresponding to each of the layout violations based on a violation database, wherein the violation repair range includes a repair layer and a repair amplitude; Layout violations whose repair layer is the layer where the violation is located and / or the adjacent layer and whose repair extent is less than a preset threshold are classified as pending violations; otherwise, they are classified as second-class violations.

3. The layout and routing optimization method according to claim 2, wherein: The preset threshold is the distance between adjacent routing tracks perpendicular to the preferred routing direction; When the repair layer of the layout violation includes a non-adjacent layer of the layer where the violation is located, and / or the repair amplitude is greater than or equal to a preset threshold, the layout violation is classified as a second type of violation; The first type of repair is repairing the layer where the violation is located and / or the adjacent layers, and the repair extent is less than a preset threshold; The second type of repair is repair of a non-adjacent layer to the layer where the violation is located, and / or repair with a repair amplitude greater than or equal to a preset threshold.

4. The layout and routing optimization method according to claim 1, wherein: Before performing the first type of repair on the first type of violations in the current layout, the method includes: dividing the current layout into multiple repair areas.

5. The layout and routing optimization method according to claim 4, wherein: When repairing the current layout, multiple repair areas may be processed in parallel.

6. The layout and routing optimization method according to claim 1, wherein: Perform the second type of repair on the second type of violation in the current layout, including: Check whether there are first-category violations in the current layout. If so, perform second-category repairs on the first-category violations and second-category violations in the current layout.

7. The layout and routing optimization method according to claim 1, wherein: The preset termination threshold includes the number of repeated repairs reaching a preset value, and / or the total number of first-type violations and second-type violations in the current layout reaching a preset value.

8. An electronic device, characterized in that: The method comprises a memory, a processor and a computer program stored in the memory, wherein the processor executes the computer program to implement the layout and wiring optimization method according to any one of claims 1 to 7.

9. A computer storage medium, characterized in that: Computer program instructions are stored thereon, and when the computer program instructions are executed, the layout and wiring optimization method according to any one of claims 1 to 7 is implemented.

10. A computer program product comprising a computer program, characterized in that: When the computer program is executed by a processor, the computer program implements the layout and routing optimization method according to any one of claims 1 to 7.

Images