Hardware-adaptive quantum circuit compilation method, device, equipment, medium and product

Abstract

The application discloses a hardware adaptive quantum circuit compiling method and device, equipment, medium and product, and the method comprises the following steps: performing circuit splitting on an original compiled quantum circuit with a quantum bit mapping as a target to obtain a first quantum circuit; and performing circuit depth compression on the first quantum circuit to obtain a finally compiled quantum circuit; through the quantum circuit splitting with the quantum bit mapping as the target and the automatic adjustment of the depth compression degree of the quantum circuit in the compiling process, the running state of the underlying quantum hardware can be included in the compiling process, the hardware adaptive quantum circuit compiling is realized, the problem that the running result of the compiled quantum circuit is affected by the running state of the quantum hardware can be effectively solved, and the characteristic requirement of the distributed power network is met.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of quantum computing, and in particular to a hardware adaptive quantum circuit compiling method, device, equipment, medium and product. BACKGROUND

[0002] Quantum computing technology can maximize the computing power in the computing network. A quantum program developed by a user using a quantum programming language is compiled into a quantum circuit in the form of a quantum assembly language (such as OpenQASM) to be a necessary means of communication between the user and the quantum hardware device. In a quantum laboratory environment, a user generally uses a quantum hardware device one by one, and in a computing network, a large number of users may use the same quantum hardware device in turn, which is likely to cause a large number of bit mapping tasks on the quantum hardware device, affecting the efficiency. In addition, in the computing network (including quantum computing power and classical computing power), compared with the classical computing system compilation process which is only affected by the architecture (x86, arm, etc.), the quantum computing compilation result is mainly affected by the technical route and the hardware running state.

[0003] In the prior art, the quantum circuit compiled and generated needs to be compiled and processed again on a quantum measurement and control device connected with the quantum hardware before running on the quantum hardware, to complete quantum bit mapping after circuit splitting according to the entangled state of the physical quantum bit, and circuit depth compression processing. However, since the measurement and control device and the quantum hardware device are one-to-one, the compilation at this stage is centralized, which does not meet the distributed characteristics of the computing network. SUMMARY

[0004] To solve the problems in the prior art, the present application provides a hardware adaptive quantum circuit compiling method, device, equipment, medium and product, which can effectively solve the problem that the running result of the compiled quantum circuit is affected by the running state of the quantum hardware, meet the distributed characteristics of the computing network, and improve the execution efficiency of the quantum circuit.

[0005] In a first aspect, the present application provides a hardware adaptive quantum circuit compiling method, comprising:

[0006] Splitting the original compiled quantum circuit to obtain a first quantum circuit, taking quantum bit mapping as a target;

[0007] Compressing the circuit depth of the first quantum circuit to obtain a final compiled quantum circuit.

[0008] As an improvement of the above-mentioned scheme, the splitting of the original compiled quantum circuit to obtain a first quantum circuit, taking quantum bit mapping as a target, comprises:

[0009] Analyzing the original compiled quantum circuit to generate a logical qubit entanglement information matrix required by a gate circuit;

[0010] Mapping qubits according to the physical qubit entanglement information matrix of the target quantum hardware and the logical qubit entanglement information matrix to determine whether the physical qubit entanglement state of the target quantum hardware meets the requirements of the logical qubit entanglement information matrix;

[0011] If not, circuit splitting is performed on the current quantum circuit, and a new logical qubit entanglement information matrix is generated by analyzing the split quantum circuit until the physical qubit entanglement state of the target quantum hardware meets the requirements of the newly generated logical qubit entanglement information matrix;

[0012] If yes, output the quantum circuit corresponding to the corresponding logical qubit entanglement information matrix as the first quantum circuit.

[0013] As an improvement of the above scheme, the analyzing the original compiled quantum circuit to generate a logical qubit entanglement information matrix required by a gate circuit comprises:

[0014] Traversing the quantum circuit to number all logical qubits in the quantum circuit;

[0015] Generating a logical qubit entanglement information matrix required by a gate circuit according to the entanglement state between each logical qubit.

[0016] As an improvement of the above scheme, the mapping qubits according to the physical qubit entanglement information matrix of the target quantum hardware and the logical qubit entanglement information matrix to determine whether the physical qubit entanglement state of the target quantum hardware meets the requirements of the logical qubit entanglement information matrix comprises:

[0017] Multiplying the logical qubit entanglement information matrix by a permutation matrix to obtain a product matrix;

[0018] Subtracting the physical qubit entanglement information matrix from the product matrix to generate a judgment matrix;

[0019] Enumerating all permutation matrices to determine whether there is at least one permutation matrix that makes all elements in the judgment matrix non-negative;

[0020] If yes, it is determined that the physical qubit entanglement state of the target quantum hardware meets the requirements of the logical qubit entanglement information matrix;

[0021] If not, it is determined that the physical qubit entanglement state of the target quantum hardware does not meet the requirements of the logical qubit entanglement information matrix.

[0022] As an improvement of the above scheme, the circuit depth compression on the first quantum circuit to obtain the finally compiled quantum circuit comprises:

[0023] The gate circuit analysis is performed on the first quantum circuit to obtain the circuit depth and the user-specified running times;

[0024] According to the circuit depth, the running times and the quantum circuit volume threshold, the compression level of the first quantum circuit is determined; wherein the quantum circuit volume threshold is adaptively adjusted based on the running result of the target quantum hardware;

[0025] The first quantum circuit is compressed according to the compression operation corresponding to the currently determined compression level to obtain the finally compiled quantum circuit.

[0026] As an improvement of the above scheme, the compression level of the first quantum circuit is determined according to the circuit depth, the running times and the quantum circuit volume threshold, comprising:

[0027] According to the circuit depth and the running times, the circuit volume of the first quantum circuit is calculated;

[0028] The circuit volume is compared with the quantum circuit volume threshold;

[0029] In the case that the circuit volume is not greater than the quantum circuit volume threshold, the compression level of the first quantum circuit is determined as the first level;

[0030] In the case that the circuit volume is greater than the quantum circuit volume threshold, the compression level of the first quantum circuit is determined as the second level;

[0031] The first level corresponds to the compression operation based on gate removal; the second level corresponds to the compression operation based on gate merging.

[0032] As an improvement of the above scheme, the method further comprises:

[0033] For the finally compiled quantum circuit obtained by using the compression operation corresponding to the second level, the finally compiled quantum circuit is run to obtain the running result of this time;

[0034] The finally compiled quantum circuit is simulated to obtain the expected running result;

[0035] According to the running result of this time and the expected running result, the deviation value of this running is calculated;

[0036] The quantum circuit volume threshold is dynamically adjusted according to the deviation value.

[0037] In a second aspect, an embodiment of the present application provides a hardware adaptive quantum circuit compiling device, comprising:

[0038] a circuit splitting module configured to split the original compiled quantum circuit to obtain a first quantum circuit with a quantum bit mapping as a target;

[0039] a circuit depth compression module configured to compress the depth of the first quantum circuit to obtain a final compiled quantum circuit.

[0040] In a third aspect, an embodiment of the present application provides a hardware adaptive quantum circuit compiling device, comprising a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein the processor executes the computer program to implement the hardware adaptive quantum circuit compiling method according to any one of the first aspect.

[0041] In a fourth aspect, an embodiment of the present application provides a computer readable storage medium storing a computer program, wherein the computer program controls a device where the computer readable storage medium is located to execute the hardware adaptive quantum circuit compiling method according to any one of the first aspect when the computer program runs.

[0042] In a fifth aspect, an embodiment of the present application provides a computer program product comprising computer programs / instructions, which, when executed by a processor, implement the hardware adaptive quantum circuit compiling method according to any one of the first aspect.

[0043] Compared with the prior art, the hardware adaptive quantum circuit compiling method, device, equipment, medium and product provided by the embodiment of the present application split the original compiled quantum circuit output by the compiling module to obtain a first quantum circuit with a quantum bit mapping as a target, then compress the depth of the first quantum circuit to obtain a final compiled quantum circuit, and the quantum circuit splitting with a quantum bit mapping as a target and the depth compression of the quantum circuit are automatically adjusted during the compiling process, so that the running state of the underlying quantum hardware can be included in the compiling process to implement the hardware adaptive quantum circuit compiling, and the problem that the running result of the compiled quantum circuit is affected by the running state of the quantum hardware can be effectively solved, and the characteristic requirement of the distributed computing power network is met. BRIEF DESCRIPTION OF DRAWINGS

[0044] In order to more clearly illustrate the technical solutions of the present application, the drawings used in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0045] Figure 1 is a flow chart of a hardware adaptive quantum circuit compiling method provided by an embodiment of the present application;

[0046] Figure 2 is an architecture schematic diagram of quantum circuit compiling provided by an embodiment of the present application;

[0047] Figure 3 is an architecture schematic diagram of hardware adaptive optimization provided by an embodiment of the present application;

[0048] Figure 4 is a flow schematic diagram of circuit splitting provided by an embodiment of the present application;

[0049] Figure 5 is a structural block diagram of a hardware adaptive quantum circuit compiling apparatus provided by an embodiment of the present application;

[0050] Figure 6 is a structural block diagram of a hardware adaptive quantum circuit compiling device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0051] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0052] It can be understood that various numerical numbers involved in the embodiments of the present application are only distinguished for convenience of description, and do not limit the scope of the present application. The size of the serial number of each process does not mean the execution order, and the execution order of each process should be determined according to its function and inherent logic.

[0053] In the embodiments of the present application, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. The terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. The elements defined by the statement "include" without more limitation do not exclude the presence of additional identical elements in the process, method, article or device including the elements.

[0054] Please refer toFigure 1 , Figure 1 is a flowchart of a hardware adaptive quantum circuit compiling method provided by an embodiment of the present application. The hardware adaptive quantum circuit compiling method specifically comprises:

[0055] S11: circuit splitting is performed on the original compiled quantum circuit with quantum bit mapping as the target to obtain a first quantum circuit;

[0056] As shown in the example, Figure 2 a user can pre-allocate a container virtual machine to develop a quantum program through a computing power network, and then the container virtual machine compiles the quantum program through a built-in compiling module (also referred to as a quantum program compiler) to generate an original compiled quantum circuit in the form of quantum assembly language.

[0057] S12: circuit depth compression is performed on the first quantum circuit to obtain a finally compiled quantum circuit.

[0058] As shown in the example, Figure 2 the hardware adaptive optimization module comprises a circuit splitting module and a circuit depth compression module; then the compiling module outputs the original compiled quantum circuit to the circuit splitting module for circuit splitting with quantum bit mapping as the target, automatically adjusts the result (i.e., the first quantum circuit) output by the circuit splitting module through the circuit depth compression module for circuit depth compression, so as to achieve the purpose of hardware adaptation; subsequently, the finally compiled quantum circuit is output to a measurement and control device connected with a pre-selected target quantum hardware, and physical quantum bit entanglement information is kept synchronized from the measurement and control device.

[0059] The embodiment of the present application can complete quantum circuit splitting with quantum bit mapping as the target and automatically adjust the depth compression degree of the quantum circuit during the compiling process, can incorporate the running status of the underlying quantum hardware into the compiling process, implement hardware adaptive quantum circuit compiling, effectively solve the problem that the running result of the compiled quantum circuit is affected by the running state of the quantum hardware, meet the characteristic requirement of the distributed computing power network, improve the execution efficiency of the quantum circuit, and improve the compiling effect.

[0060] In an optional embodiment, S11: circuit splitting is performed on the original compiled quantum circuit with quantum bit mapping as the target to obtain a first quantum circuit, comprising:

[0061] The original compiled quantum circuit is parsed to generate a logical quantum bit entanglement information matrix required by a gate circuit;

[0062] Exemplarily, the circuit splitting module generates a logical qubit entanglement information matrix required by the gate circuit by analyzing a distribution of entangled states of qubits required by the gate circuit of the original compiled quantum circuit output by the compiling module.

[0063] According to the physical qubit entanglement information matrix of the target quantum hardware and the logical qubit entanglement information matrix, qubit mapping is performed to determine whether the physical qubit entanglement state of the target quantum hardware meets the requirement of the logical qubit entanglement information matrix.

[0064] The physical qubit entanglement information matrix P is used to represent the entanglement state between the physical qubits of the quantum hardware, and the physical qubit entanglement information matrix P is a binary matrix held by the compiling module and uploaded by each quantum hardware corresponding to the measurement and control device. The physical qubit entanglement information matrix P is a binary matrix held by the compiling module and uploaded by each quantum hardware corresponding to the measurement and control device. The row and column of the physical qubit entanglement information matrix P are physical qubit numbers, and the element values 0 and 1 in the physical qubit entanglement information matrix P represent whether the physical qubits are in an entangled state, for example, 0 represents that the physical qubits are not in an entangled state, and 1 represents that the physical qubits are in an entangled state.

[0065] By comparing the physical qubit entanglement information matrix of the target quantum hardware and the original compiled logical qubit entanglement information matrix, it is determined whether the physical qubit entanglement state of the target quantum hardware meets the requirement of the logical qubit entanglement information matrix (i.e., the logical qubit requirement of the gate circuit of the quantum circuit, referred to as the gate circuit requirement).

[0066] If not, the current quantum circuit is split, and the split quantum circuit is analyzed to generate a new logical qubit entanglement information matrix, until the physical qubit entanglement state of the target quantum hardware meets the requirement of the newly generated logical qubit entanglement information matrix.

[0067] If yes, the quantum circuit corresponding to the corresponding logical qubit entanglement information matrix is output as the first quantum circuit.

[0068] For the case that the entanglement state of the physical quantum bits of the target quantum hardware meets the requirements of the gate circuit, the quantum circuit corresponding to the requirements of the gate circuit is directly output as the first quantum circuit output by the circuit splitting module; for the case that the entanglement state of the physical quantum bits of the target quantum hardware does not meet the requirements of the gate circuit, the quantum circuit is subjected to gate circuit splitting, and then the new quantum circuit obtained after splitting is input to the circuit splitting module again, the quantum circuit is analyzed again, and it is judged whether the entanglement state of the physical quantum bits of the target quantum hardware meets the requirements of the logical quantum bit entanglement information matrix corresponding to the quantum circuit obtained after splitting, and the above process is repeated until it is judged that the entanglement state of the physical quantum bits of the target quantum hardware meets the requirements of the logical quantum bit entanglement information matrix corresponding to the quantum circuit obtained after splitting, and the corresponding quantum circuit is output, as shown in Figure 3 The embodiment of the present application completes the electronic circuit splitting work according to a set of physical quantum bit entanglement information matrices, and can achieve the purpose of adaptive quantum hardware.

[0069] Specifically, the analysis of the original compiled quantum circuit to generate the logical quantum bit entanglement information matrix required by the gate circuit comprises:

[0070] Traverse the quantum circuit and number all the logical quantum bits in the quantum circuit;

[0071] According to the entanglement state between each logical quantum bit, generate the logical quantum bit entanglement information matrix required by the gate circuit.

[0072] In the process of quantum circuit analysis, the embodiment of the present application traverses the quantum circuit, numbers all the logical quantum bits in the quantum circuit, and then generates the logical quantum bit entanglement information matrix L of the quantum circuit according to the entanglement state between the logical quantum bits.

[0073] The logical quantum bit entanglement information matrix L is used to represent the entanglement state between the logical quantum bits, for example, the logical quantum bit entanglement information matrix L is a binary matrix, wherein, n represents the number of logical quantum bits, the rows and columns in the logical quantum bit entanglement information matrix L are logical quantum bit numbers, and the element values 0 and 1 in the logical quantum bit entanglement information matrix L respectively represent whether the logical quantum bits are in an entangled state, for example, 0 represents that the logical quantum bits are not in an entangled state, and 1 represents that the logical quantum bits are in an entangled state.

[0074] By constructing the logical quantum bit entanglement information matrix L of the quantum circuit, the embodiment of the present application can structure and quantify the logical quantum bit entanglement of the quantum circuit, facilitate the subsequent judgment and analysis of hardware mapping adaptation, improve the processing efficiency of circuit splitting, and reduce the amount of calculation.​

[0075] Specifically, the quantum bit mapping according to the physical quantum bit entanglement information matrix of the target quantum hardware and the logical quantum bit entanglement information matrix comprises:

[0076] Multiplying the logical quantum bit entanglement information matrix by a permutation matrix to obtain a product matrix;

[0077] Subtracting the physical quantum bit entanglement information matrix from the product matrix to generate a judgment matrix;

[0078] Enumerating all permutation matrices to determine whether there is at least one permutation matrix such that all elements in the judgment matrix are non-negative;

[0079] If yes, it is determined that the physical quantum bit entanglement state of the target quantum hardware meets the requirements of the logical quantum bit entanglement information matrix;

[0080] If no, it is determined that the physical quantum bit entanglement state of the target quantum hardware does not meet the requirements of the logical quantum bit entanglement information matrix.

[0081] Exemplarily, for whether the physical quantum bit entanglement state of the target hardware meets the logical quantum bit requirements of the gate circuit of the quantum circuit, the embodiment of the present application sets a judgment standard, that is, to verify whether there is a permutation matrix A such that all elements in the judgment matrix B generated according to the fixed matrix generation formula B=P-A L are non-negative.

[0082] It can be understood that the permutation matrix A is a kind of binary matrix with special structure, and its core feature is that each row and each column contains exactly one 1, and the rest elements are all 0. Through the structure of the permutation matrix A, the rearrangement (i.e. permutation) of elements can be realized.

[0083] The embodiment of the present application traverses all permutation matrices to determine whether there is a permutation matrix A such that all elements in the judgment matrix B generated according to the formula B=P-A L are non-negative; if not, it indicates that the physical quantum bit entanglement state of the target hardware does not meet the logical quantum bit requirements of the gate circuit of the quantum circuit, and the gate circuit of the quantum circuit needs to be split; if yes, it indicates that the physical quantum bit entanglement state of the target hardware meets the logical quantum bit requirements of the gate circuit of the quantum circuit, and the quantum circuit does not need to be split.

[0084] The embodiment of the present application can include the running state of the underlying quantum hardware, i.e., the number of entangled quantum bits meeting the construction of the quantum circuit, into the compilation process by constructing the logical quantum bit entanglement information matrix of the quantum circuit and combining the physical quantum bit entanglement information matrix of the underlying quantum hardware for quantum circuit splitting, so that the final compilation result adapts to the quantum hardware running condition, and the compilation effect for the quantum hardware is improved.

[0085] In an optional embodiment, S12: performing circuit depth compression on the first quantum circuit to obtain a finally-compiled quantum circuit, comprising:

[0086] performing gate circuit analysis on the first quantum circuit to obtain a circuit depth and a user-specified running number;

[0087] determining a compression level of the first quantum circuit according to the circuit depth, the running number and a quantum circuit volume threshold value; wherein the quantum circuit volume threshold value is adaptively adjusted based on a running result of target quantum hardware;

[0088] performing compression on the first quantum circuit according to a compression operation corresponding to the currently determined compression level to obtain a finally-compiled quantum circuit.

[0089] Specifically, the determining of the compression level of the first quantum circuit according to the circuit depth, the running number and the quantum circuit volume threshold value comprises:

[0090] calculating a circuit volume of the first quantum circuit according to the circuit depth and the running number;

[0091] comparing the circuit volume with the quantum circuit volume threshold value;

[0092] in a case where the circuit volume is not greater than the quantum circuit volume threshold value, determining that the compression level of the first quantum circuit is a first level;

[0093] in a case where the circuit volume is greater than the quantum circuit volume threshold value, determining that the compression level of the first quantum circuit is a second level.

[0094] In the embodiment of the present application, the compression strategy of the quantum circuit is divided into two levels, as shown in the following table:

[0095]

[0096] wherein the first level corresponds to a compression operation based on gate removal, and the second level corresponds to a compression operation based on gate merging.

[0097] In order to solve the distortion of the circuit operation result caused by level 2 compression to a certain extent, the embodiment of the present application finds a balance between compressing the circuit depth and maintaining the circuit fidelity of the quantum circuit through the design of the circuit depth compression module, and the specific process is as follows:

[0098] The circuit depth compression module maintains an adaptive and dynamically adjustable quantum circuit volume threshold for each quantum hardware and the connected measurement and control equipment. For example, the target quantum hardware and the connected measurement and control equipment maintain a quantum circuit volume threshold V, which can be dynamically adjusted according to the operation result each time.

[0099] The gate circuit analysis is performed on the first quantum circuit output by the circuit splitting module to obtain the circuit depth d and the running frequency s indicated by the user.

[0100] The product of the circuit depth d and the running frequency s indicated by the user is calculated to obtain the circuit volume of the first quantum circuit If , the compression operation corresponding to level 1 is performed, that is, the compression operation based on gate removal, and if , the compression operation corresponding to level 2 is performed, that is, the compression operation based on gate merging, and the specific process is as follows:

[0101] (1);

[0102] The embodiment of the present application selects different compression strategies for circuit depth compression based on the circuit depth and the running frequency of the quantum circuit, and the adaptive and dynamically adjustable quantum circuit volume threshold V of the target quantum hardware, so as to obtain the finally compiled quantum circuit. Through the above process, the matching degree of the actual circuit depth of the quantum circuit and the hardware capability (i.e. the quantum circuit volume threshold V) can be matched, the strength of the compression depth can be adjusted in a targeted manner, so as to find a balance between compressing the circuit depth and maintaining the circuit fidelity of the quantum circuit, and the circuit depth is compressed as much as possible under the premise that the compressed quantum circuit depth matches the hardware, while reducing the distortion of the operation result of the compressed quantum circuit.

[0103] Further, the method further comprises:

[0104] For the finally compiled quantum circuit obtained by using the compression operation corresponding to the second level, the finally compiled quantum circuit is run to obtain the operation result of this time;

[0105] The finally compiled quantum circuit is simulated to obtain the expected operation result;

[0106] According to the operation result of this time and the expected operation result, the deviation value of this operation is calculated;

[0107] The quantum circuit volume threshold is dynamically adjusted according to the deviation value.

[0108] In the embodiment of the present application, for the final compiled quantum circuit obtained by using level 2 corresponding compression operation (i.e. gate merging), the final compiled quantum circuit is run by using target quantum hardware to obtain the running result of this time, and at the same time, the running result of the final compiled quantum circuit is evaluated and tracked by combining the quantum simulator, and the quantum circuit volume threshold V is dynamically adjusted according to the evaluation result, and the specific process is as follows:

[0109] When the level 2 compression operation is performed, the running result C of the compressed quantum circuit (i.e. the final compiled quantum circuit) is obtained, and the compressed quantum circuit is simulated by using the quantum simulator to obtain the expected running result E;

[0110] The variance between the running result of this time and the expected running result is calculated to obtain the deviation value of this running , and the specific calculation is as follows:

[0111] (2);

[0112] If the deviation value is not greater than the preset reference coefficient , it is indicated that the running result distortion is small, and the quantum circuit volume threshold V is slowly reduced according to the preset reduction step length; if the deviation value is greater than the reference coefficient , it is indicated that the running result distortion is large, and the quantum circuit volume threshold V is quickly increased according to the preset quantum circuit volume threshold V; and the specific process is as follows:

[0113] (3);

[0114] Wherein, denotes the reduction step length, denotes the multiplicative growth factor.

[0115] In the embodiment of the present application, the running result of the final compiled quantum circuit is evaluated and tracked, if it is found that the running result distortion caused by this compression is small, the quantum circuit volume threshold V is reduced by a small amplitude, so as to apply large intensity compression to more quantum circuits; if it is found that the circuit running result distortion caused by this compression is large, the quantum circuit volume threshold V is increased by a large amplitude, so as to apply large intensity compression to less quantum circuits, and by dynamically adjusting the quantum circuit volume threshold V, the purpose of self-adaptive quantum hardware can be achieved.

[0116] Compared with the prior art, the embodiment of the present application introduces the running state of the underlying quantum hardware into the compilation process by appending a hardware adaptive optimization module after the compilation module, increases the two-stage processing of circuit depth compression and circuit splitting for the quantum bit mapping target generated by the compilation module, automatically adjusts the compilation optimization strategy, does not need to be manually specified, can adapt to quantum hardware of different technical routes, reduces the adaptation cost, can reduce the load of the measurement and control equipment, realizes the distributed operation of the computing power network task, makes up for the deficiency of the prior art in the distributed characteristics, improves the execution efficiency of the quantum circuit, and improves the compilation effect for quantum hardware.

[0117] Please refer to Figure 5 , Figure 5 is a structural block diagram of a hardware adaptive quantum circuit compilation device provided by the embodiment of the present application, and the hardware adaptive quantum circuit compilation device comprises:

[0118] A circuit splitting module 11 is configured to perform circuit splitting on the originally compiled quantum circuit for the quantum bit mapping target to obtain a first quantum circuit.

[0119] A circuit depth compression module 12 is configured to perform circuit depth compression on the first quantum circuit to obtain a finally compiled quantum circuit.

[0120] In an optional embodiment, the circuit splitting module 11 comprises:

[0121] A first analysis unit is configured to analyze the originally compiled quantum circuit to generate a logical quantum bit entanglement information matrix required by a gate circuit.

[0122] A judgment unit is configured to perform quantum bit mapping according to the physical quantum bit entanglement information matrix of the target quantum hardware and the logical quantum bit entanglement information matrix, and judge whether the physical quantum bit entanglement state of the target quantum hardware meets the requirement of the logical quantum bit entanglement information matrix.

[0123] A gate circuit splitting unit is configured to, if not, perform circuit splitting on the current quantum circuit, analyze the split quantum circuit to generate a new logical quantum bit entanglement information matrix, and repeat the above process until the physical quantum bit entanglement state of the target quantum hardware meets the requirement of the newly generated logical quantum bit entanglement information matrix.

[0124] A quantum circuit output unit is configured to, if yes, output the quantum circuit corresponding to the corresponding logical quantum bit entanglement information matrix as the first quantum circuit.

[0125] In an optional embodiment, the first analysis unit comprises:

[0126] A numbering subunit is configured to number all logical qubits in the quantum circuit;

[0127] A matrix generating subunit is configured to generate a logical qubit entanglement information matrix required by a gate circuit according to entanglement states between the logical qubits.

[0128] In an optional embodiment, the judging unit comprises:

[0129] A first calculating subunit is configured to multiply the logical qubit entanglement information matrix by a permutation matrix to obtain a product matrix;

[0130] A second calculating subunit is configured to subtract the product matrix from the physical qubit entanglement information matrix to generate a judging matrix;

[0131] A permutation matrix judging subunit is configured to enumerate all permutation matrices and judge whether there is at least one permutation matrix that makes all elements in the judging matrix non-negative; if yes, it is determined that the physical qubit entanglement state of the target quantum hardware meets the requirement of the logical qubit entanglement information matrix; if no, it is determined that the physical qubit entanglement state of the target quantum hardware does not meet the requirement of the logical qubit entanglement information matrix.

[0132] In an optional embodiment, the circuit depth compression module 12 comprises:

[0133] A second parsing unit is configured to parse the first quantum circuit to obtain a circuit depth and a user-specified running number;

[0134] A compression level determining unit is configured to determine a compression level of the first quantum circuit according to the circuit depth, the running number and a quantum circuit volume threshold value; wherein the quantum circuit volume threshold value is adaptively adjusted based on a running result of a target quantum hardware;

[0135] A compression unit is configured to compress the first quantum circuit according to a compression operation corresponding to the currently determined compression level to obtain a finally compiled quantum circuit.

[0136] In an optional embodiment, the compression level determining unit comprises:

[0137] A third calculating subunit is configured to calculate a circuit volume of the first quantum circuit according to the circuit depth and the running number;

[0138] A comparing subunit is configured to compare the circuit volume with the quantum circuit volume threshold value;

[0139] The first determining sub-unit is configured to determine that the compression level of the first quantum circuit is a first level when the circuit volume is not greater than the quantum circuit volume threshold.

[0140] The second determining sub-unit is configured to determine that the compression level of the first quantum circuit is a second level when the circuit volume is greater than the quantum circuit volume threshold.

[0141] The first level corresponds to a compression operation based on gate removal, and the second level corresponds to a compression operation based on gate merging.

[0142] In an optional embodiment, the apparatus further comprises:

[0143] The running module is configured to run the finally compiled quantum circuit obtained by using the compression operation corresponding to the second level to obtain a running result of this time.

[0144] The quantum simulation module is configured to simulate the finally compiled quantum circuit to obtain an expected running result.

[0145] The deviation value calculation module is configured to calculate a deviation value of this time according to the running result of this time and the expected running result.

[0146] The threshold adjustment module is configured to dynamically adjust the quantum circuit volume threshold according to the deviation value.

[0147] It should be noted that the working processes of the various modules in the hardware adaptive quantum circuit compiling apparatus according to the embodiments of the present application can refer to the working processes of the hardware adaptive quantum circuit compiling method according to the embodiments of the present application described above, and the technical effects achieved are the same as those of the hardware adaptive quantum circuit compiling method according to the embodiments of the present application described above, which will not be described here in detail.

[0148] Referring to Figure 6 , Figure 6 is a structural block diagram of the hardware adaptive quantum circuit compiling device provided by the embodiments of the present application. The hardware adaptive quantum circuit compiling device comprises a processor 21, a memory 22, and a computer program stored in the memory 22 and executable on the processor 21. The processor 21 implements the steps in each of the hardware adaptive quantum circuit compiling method embodiments described above when executing the computer program, such as steps S11-S12.

[0149] For example, the computer program can be divided into one or more modules / units, which are stored in the memory 22 and executed by the processor 21 to complete the present application. The one or more modules / units can be a series of computer program instruction segments capable of completing a specific function, which are used to describe the execution process of the computer program in the hardware adaptive quantum circuit compiling device.

[0150] The hardware adaptive quantum circuit compiling device can include, but is not limited to, the processor 21, the memory 22. Those skilled in the art can understand that the schematic diagram is only an example of the hardware adaptive quantum circuit compiling device, and does not constitute a limitation on the hardware adaptive quantum circuit compiling device, and can include more or less components than the diagram, or combine certain components, or different components, for example, the hardware adaptive quantum circuit compiling device can also include an input / output device, a network access device, a bus, etc.

[0151] The processor 21 can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), ready programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. The processor 21 is the control center of the hardware adaptive quantum circuit compiling device, and connects various parts of the hardware adaptive quantum circuit compiling device through various interfaces and lines.

[0152] The memory 22 can be used to store the computer programs and / or modules, and the processor 21 realizes various functions of the hardware-adaptive quantum circuit compiling device by running or executing the computer programs and / or modules stored in the memory 22, and calling the data stored in the memory 22. The memory 22 can mainly include a program storage area and a data storage area, wherein the program storage area can store an operating system, at least one application program required by a function (such as a sound playing function, an image playing function, etc.), and the like; and the data storage area can store data created according to the use of the mobile phone (such as audio data, a phone book, etc.), and the like. In addition, the memory 22 can include a high-speed random access memory, and can also include a non-volatile memory, for example, a hard disk, a memory, a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, at least one disk storage device, a flash memory device, or other volatile solid-state memory devices.

[0153] When the modules / units of the hardware-adaptive quantum circuit compiling device are implemented in the form of software function units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the above-mentioned embodiment methods can also be completed by a computer program instructing related hardware, and the computer program can be stored in a computer-readable storage medium. When the processor 21 executes the computer program, the steps of the above-mentioned various method embodiments can be realized. The computer program includes computer program code, which can be in the form of source code, object code, an executable file, or some intermediate form, etc. The computer-readable medium can include any entity or device capable of carrying the computer program code, a recording medium, a U disk, a mobile hard disk, a magnetic disk, an optical disk, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium, etc.

[0154] It should be noted that the apparatus embodiments described above are merely illustrative, and the units described as separate units can or can not be physically separate, and the units shown as units can or can not be physical units, i.e., can be located in one place, or can be distributed to multiple network units. Part or all of the modules can be selected to achieve the purpose of the embodiment according to actual needs. In addition, the connection relationship between the modules in the apparatus embodiment provided by the present application indicates that there is a communication connection between them, which can be implemented as one or more communication buses or signal lines. Those skilled in the art can understand and implement it without creative labor.

[0155] The above is the preferred embodiment of the present application. It should be noted that those skilled in the art can make various improvements and refinements without departing from the principles of the present application, and these improvements and refinements are also considered within the scope of protection of the present application.

Claims

1. A hardware-adaptive quantum circuit compilation method, characterized by, The method comprises the following steps: circuit decomposition is performed on the original compiled quantum circuit with a target quantum bit mapping, to obtain a first quantum circuit; circuit depth compression is performed on the first quantum circuit, to obtain a final compiled quantum circuit; The circuit decomposition is performed on the original compiled quantum circuit with a target quantum bit mapping, to obtain a first quantum circuit, comprising: parsing the original compiled quantum circuit to generate a logical quantum bit entanglement information matrix required by a gate circuit; performing quantum bit mapping according to a physical quantum bit entanglement information matrix of a target quantum hardware and the logical quantum bit entanglement information matrix, and determining whether the physical quantum bit entanglement state of the target quantum hardware meets the requirements of the logical quantum bit entanglement information matrix; if not, performing circuit decomposition on the current quantum circuit, and parsing the decomposed quantum circuit to generate a new logical quantum bit entanglement information matrix, until the physical quantum bit entanglement state of the target quantum hardware meets the requirements of the newly generated logical quantum bit entanglement information matrix; if yes, outputting the quantum circuit corresponding to the corresponding logical quantum bit entanglement information matrix as the first quantum circuit; The quantum bit mapping according to the physical quantum bit entanglement information matrix of the target quantum hardware and the logical quantum bit entanglement information matrix, and determining whether the physical quantum bit entanglement state of the target quantum hardware meets the requirements of the logical quantum bit entanglement information matrix, comprises: multiplying the logical quantum bit entanglement information matrix by a permutation matrix to obtain a product matrix; subtracting the physical quantum bit entanglement information matrix from the product matrix to generate a judgment matrix; enumerating all permutation matrices, and determining whether there is at least one permutation matrix that makes all elements in the judgment matrix non-negative; if yes, it is determined that the physical quantum bit entanglement state of the target quantum hardware meets the requirements of the logical quantum bit entanglement information matrix; if not, it is determined that the physical quantum bit entanglement state of the target quantum hardware does not meet the requirements of the logical quantum bit entanglement information matrix.

2. The hardware-adaptive quantum circuit compilation method of claim 1, wherein, The parsing of the original compiled quantum circuit to generate a logical quantum bit entanglement information matrix required by a gate circuit comprises: traversing the quantum circuit, and numbering all logical quantum bits in the quantum circuit; generating a logical quantum bit entanglement information matrix required by a gate circuit according to the entanglement state between each logical quantum bit.

3. The hardware-adaptive quantum circuit compilation method of claim 1, wherein, The circuit depth compression on the first quantum circuit to obtain a final compiled quantum circuit comprises: gate circuit analysis is performed on the first quantum circuit to obtain a circuit depth and a user-specified running frequency; determining a compression level of the first quantum circuit according to the circuit depth, the running frequency and a quantum circuit volume threshold value; wherein the quantum circuit volume threshold value is adaptively adjusted based on the running result of a target quantum hardware; performing compression on the first quantum circuit according to the compression operation corresponding to the current determined compression level, to obtain a final compiled quantum circuit.

4. The hardware-adaptive quantum circuit compilation method of claim 3, wherein, The determination of the compression level of the first quantum circuit according to the circuit depth, the running frequency and the quantum circuit volume threshold value comprises: According to the circuit depth and the number of operations, calculate a circuit volume of the first quantum circuit; Compare the circuit volume with a quantum circuit volume threshold; If the circuit volume is not greater than the quantum circuit volume threshold, determine a compression level of the first quantum circuit as a first level; If the circuit volume is greater than the quantum circuit volume threshold, determine the compression level of the first quantum circuit as a second level; The first level corresponds to a compression operation based on gate removal, and the second level corresponds to a compression operation based on gate merging.

5. The hardware-adaptive quantum circuit compilation method of claim 3 or 4, wherein, The method further comprises: For a final compiled quantum circuit obtained by using the compression operation corresponding to the second level, run the final compiled quantum circuit to obtain a current running result; Analog simulate the final compiled quantum circuit to obtain an expected running result; According to the current running result and the expected running result, calculate a deviation value of the current running; According to the deviation value, dynamically adjust the quantum circuit volume threshold.

6. A hardware-adaptive quantum circuit compilation apparatus, comprising: Comprise: A circuit splitting module, configured to split an original compiled quantum circuit to obtain a first quantum circuit, with a quantum bit mapping as a target; A circuit depth compression module, configured to compress a circuit depth of the first quantum circuit to obtain a final compiled quantum circuit; The circuit splitting module comprises: A first analysis unit, configured to analyze the original compiled quantum circuit to generate a logical quantum bit entanglement information matrix required by a gate circuit; A judgment unit, configured to perform quantum bit mapping according to a physical quantum bit entanglement information matrix of a target quantum hardware and the logical quantum bit entanglement information matrix, and determine whether a physical quantum bit entanglement state of the target quantum hardware meets a requirement of the logical quantum bit entanglement information matrix; A gate circuit splitting unit, configured to, if not, split a current quantum circuit, and analyze the split quantum circuit to generate a new logical quantum bit entanglement information matrix, until the physical quantum bit entanglement state of the target quantum hardware meets a requirement of the newly generated logical quantum bit entanglement information matrix; A quantum circuit output unit, configured to, if yes, output a quantum circuit corresponding to the corresponding logical quantum bit entanglement information matrix as the first quantum circuit; The judgment unit comprises: A first calculation subunit, configured to multiply the logical quantum bit entanglement information matrix and a permutation matrix to obtain a product matrix; A second calculation subunit, configured to subtract the physical quantum bit entanglement information matrix from the product matrix to generate a judgment matrix; A permutation matrix judgment subunit, configured to enumerate all permutation matrices, and determine whether there is at least one permutation matrix that makes all elements in the judgment matrix non-negative; if yes, it is determined that the physical quantum bit entanglement state of the target quantum hardware meets the requirement of the logical quantum bit entanglement information matrix; if not, it is determined that the physical quantum bit entanglement state of the target quantum hardware does not meet the requirement of the logical quantum bit entanglement information matrix.

7. A hardware-adaptive quantum circuit compilation device, comprising: Comprise: A processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, the processor implementing the hardware-adaptive quantum circuit compilation method of any one of claims 1 to 5 when executing the computer program.

8. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, wherein the computer program controls the device where the computer readable storage medium is located to execute the hardware-adaptive quantum circuit compilation method of any one of claims 1 to 5 when the computer program runs.

9. A computer program product comprising computer programs / instructions, characterized in that, The computer program / instructions implement the hardware-adaptive quantum circuit compilation method of any one of claims 1 to 5 when executed by the processor.

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