Test method and device, equipment, storage medium and program product

Abstract

The invention discloses a test method and device, equipment, a storage medium and a program product, and the test method comprises the steps: writing first data into a first address of a to-be-tested chip through a first writing command under a first clock frequency; at a second clock frequency, at least one first read command and a second write command are sent to the to-be-tested chip, and the at least one first read command and the second write command meet a preset time sequence requirement, so that the to-be-tested chip writes second data read from the first address back to a second address of the to-be-tested chip; wherein the first read command represents to read data from the first address, and the second write command represents to write data into the second address; under the third clock frequency, third data are read from the second address through the second read command; determining a read-write test result of the to-be-tested chip according to the third data and the first data; wherein the first clock frequency and the third clock frequency are both lower than the second clock frequency. Therefore, the coverage rate of the high-speed test is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit technology, and in particular to a testing method, apparatus, device, storage medium, and program product. Background Art

[0002] With the rapid development of semiconductor technology, memory data speeds have also increased. For example, compared to the fifth-generation Low Power Double Data Rate 5 (LPDDR5), LPDDR5X has a data speed of 9600 megabits per second (Mbps).

[0003] In related technologies, as memory speeds increase, the speed requirements for test equipment are also increasing. However, high-speed test equipment is expensive, and test programs need to be redeveloped and redesigned, resulting in excessively high test costs and hindering the implementation of high-speed memory testing. Summary of the Invention

[0004] The present disclosure provides a testing method, apparatus, device, storage medium, and program product, which can utilize the low-speed port of the testing device to test the high-speed read and write functions of the chip under test, thereby improving the coverage of the high-speed test.

[0005] The technical solution of the present disclosure is achieved as follows:

[0006] In a first aspect, an embodiment of the present disclosure provides a testing method, which is applied to a testing device. The testing method includes:

[0007] At a first clock frequency, writing first data to a first address of the chip under test through a first write command;

[0008] At a second clock frequency, at least one first read command and a second write command are sent to the chip under test, and a preset timing requirement is satisfied between the at least one first read command and the second write command, so that the chip under test writes second data read from the first address back to the second address of the chip under test; wherein the first read command represents reading data from the first address, and the second write command represents writing data to the second address;

[0009] Reading third data from the second address using a second read command at a third clock frequency; and determining a read / write test result of the chip under test based on the third data and the first data;

[0010] The first clock frequency and the third clock frequency are both lower than the second clock frequency.

[0011] In some embodiments, at least one first read command includes a third read command; at least one first read command and a second write command meet a preset timing requirement, including: the time interval between the third read command and the second write command meets the first timing requirement, so that the start time of the chip under test reading data from the first address and the start time of the chip under test writing data back to the second address are synchronized.

[0012] In some embodiments, the time interval between the third read command and the second write command meets the first timing requirement, including: the time interval between the third read command and the second write command is an integer multiple of a clock period of the external clock.

[0013] In some embodiments, the time interval between the third read command and the second write command meets the first timing requirement, including: the time interval between the third read command and the second write command is equal to RL-WL+tWCK2DQO-tWCK2DQI; wherein RL represents the read delay time of the third read command, WL represents the write delay time of the second write command, tWCK2DQI represents the delay time from the data clock to the data input, tWCK2DQO represents the delay time from the data clock to the data output, and tWCK2DQI and tWCK2DQI are adjusted through the test mode inside the chip to be tested.

[0014] In some embodiments, at least one first read command includes a third read command and a fourth read command; at least one first read command and a second write command meet preset timing requirements, including: the time interval between the third read command and the fourth read command meets the second timing requirement, and the time interval between the third read command and the second write command meets the third timing requirement, so that the data written back to the second address by the chip under test is the middle part of all the data read from the first address by the third read command and the fourth read command respectively.

[0015] In some embodiments, at least one first read command includes a third read command and a fourth read command, and the test method further includes: writing fourth data to the third address of the chip to be tested through a third write command at a first clock frequency; reading data from the first address through a third read command and reading data from the third address through a fourth read command at a second clock frequency; wherein the time interval between the third read command and the fourth read command meets the second timing requirement, and the time interval between the third read command and the second write command meets the third timing requirement, so that the data written back to the second address by the chip to be tested is the middle part of all the data read from the first address and the third address by the third read command and the fourth read command respectively.

[0016] In some embodiments, the time interval between the third read command and the fourth read command meets the second timing requirement, including: the time interval between the third read command and the fourth read command is two clock cycles of an external clock.

[0017] In some embodiments, the time interval between the third read command and the second write command satisfies a third timing requirement, including: the time interval between the third read command and the second write command is equal to RL-WL+nCK; wherein RL represents the read delay time of the third read command, WL represents the write delay time of the second write command, and nCK represents n clock cycles of the external clock, where n is an integer.

[0018] In some embodiments, the time interval between the third read command and the second write command satisfies the third timing requirement, and also includes: the sum of nCK and the preset duration is greater than or equal to 0 and less than or equal to 2CK, and 2CK represents 2 clock cycles of the external clock; wherein, the preset duration is tWCK2DQI-tWCK2DQO, tWCK2DQI represents the delay time from the data clock to the data input, and tWCK2DQO represents the delay time from the data clock to the data output.

[0019] In some embodiments, the read and write test results of the chip to be tested are determined based on the third data and the first data, including: when the third data and the first data are the same, determining that the read and write test result is that the read and write function test of the chip to be tested is normal; or, when the third data and the first data are different, determining that the read and write test result is that the read and write function test of the chip to be tested fails.

[0020] In some embodiments, determining the read and write test results of the chip to be tested also includes: reading data from the first address of the chip to be tested through a third read command and a fourth read command, or reading data from the first address and the third address of the chip to be tested respectively; writing fifth data back to the second address of the chip to be tested through a second write command, the fifth data being the middle part of all data read by the third read command and the fourth read command; reading third data from the second address through a second read command; looping through the steps of the third read command, the fourth read command, the second write command and the second read command to obtain the third data read multiple times; when the third data read multiple times are consistent, determining that the read and write test result is that the read and write function test of the chip to be tested is normal; or, when there is inconsistency in the third data read multiple times, determining that the read and write test result is that the read and write function test of the chip to be tested fails.

[0021] In some embodiments, the testing method further includes: sending a column address strobe command before the first clock frequency is switched to the second clock frequency, or before the second clock frequency is switched to the third clock frequency.

[0022] In some embodiments, at the second clock frequency, the testing method further includes: when sending a second write command to the chip under test, keeping the input and output ports of the testing device in a suspended state or a high-impedance state.

[0023] In a second aspect, an embodiment of the present disclosure provides a testing device, the testing device including a reading and writing unit and a determining unit, wherein:

[0024] The read / write unit is configured to write first data to a first address of the chip under test via a first write command at a first clock frequency; send at least one first read command and a second write command to the chip under test at a second clock frequency, and the at least one first read command and the second write command meet a preset timing requirement, so that the chip under test writes the second data read from the first address back to the second address of the chip under test; wherein the first read command represents reading data from the first address and the second write command represents writing data to the second address; and read third data from the second address via the second read command at a third clock frequency;

[0025] The determination unit is configured to determine a read / write test result of the chip under test according to the third data and the first data; wherein the first clock frequency and the third clock frequency are both lower than the second clock frequency.

[0026] In a third aspect, an embodiment of the present disclosure provides a testing device, the testing device including a memory and a processor, wherein:

[0027] a memory for storing computer programs capable of running on the processor;

[0028] A processor is configured to execute the testing method as described in any one of the first aspects when running a computer program.

[0029] In a fourth aspect, an embodiment of the present disclosure provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by at least one processor, it implements the test method as described in any one of the first aspects.

[0030] In a fifth aspect, an embodiment of the present disclosure provides a computer program product, which includes a computer program or instructions. When the computer program or instructions are executed by a processor, the test method as described in any one of the first aspects is implemented.

[0031] The embodiments of the present disclosure provide a test method, apparatus, device, storage medium, and program product. The test method includes: writing first data to a first address of a chip under test via a first write command at a first clock frequency; sending at least one first read command and a second write command to the chip under test at a second clock frequency, wherein the at least one first read command and the second write command meet a preset timing requirement, so that the chip under test writes the second data read from the first address back to the second address of the chip under test; reading third data from the second address via a second read command at a third clock frequency; and determining a read / write test result of the chip under test based on the third data and the first data; wherein the first clock frequency and the third clock frequency are both lower than the second clock frequency. In this way, the test device writes data to the chip under test via a low-speed write command, and then sends high-speed read / write commands to the chip under test and controls the timing between the high-speed read / write commands, so that the chip under test reads the high-speed data from its internal storage unit and writes it back to the storage unit inside the chip under test. Then, the test device reads data from the chip under test via a low-speed read instruction to determine whether the read and write functions of the chip under test are correct. In this way, by writing the high-speed data read by the chip under test back into the chip under test, instead of generating high-speed data for the test equipment, the high-speed read and write functions of the chip under test can be tested using the low-speed port of the test equipment, solving the problem that the low-speed test equipment cannot cover the read and write of the high-speed port, and reducing the port speed requirements for the test equipment; at the same time, without affecting the area of ​​the chip under test and the normal read and write path, it also improves the coverage of high-speed testing, thereby improving the test performance of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 This is a data sampling diagram for write operations;

[0033] Figure 2 This is a data sampling diagram for read operations;

[0034] Figure 3 A flow chart of a testing method provided in an embodiment of the present disclosure Figure 1 ;

[0035] Figure 4 A flow chart of a testing method provided in an embodiment of the present disclosure Figure 2 ;

[0036] Figure 5 A signal timing diagram corresponding to a test method provided in an embodiment of the present disclosure Figure 1 ;

[0037] Figure 6 A schematic diagram of a circuit structure of a testing method provided in an embodiment of the present disclosure;

[0038] Figure 7A second flow diagram of a testing method provided in an embodiment of the present disclosure;

[0039] Figure 8 A signal timing diagram corresponding to a test method provided in an embodiment of the present disclosure Figure 2 ;

[0040] Figure 9 A schematic diagram of an application framework of a testing method provided in an embodiment of the present disclosure;

[0041] Figure 10 A schematic diagram of the structure of a testing device provided in an embodiment of the present disclosure;

[0042] Figure 11 A schematic diagram of the specific hardware structure of a test device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure is described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference only and are not intended to limit the embodiments of the present disclosure.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0045] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0046] It should also be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0047] In addition, references to "embodiments" herein mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present disclosure. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0048] The following is an introduction to the related technologies of the present disclosure.

[0049] Semiconductor memory chips are used in computers, servers, handheld devices such as mobile phones, printers, and many other electronic devices. Semiconductor memory chips include multiple memory cells in a memory array, and the memory cells are used to store data. For example, taking dynamic random access memory (DRAM) as an example, before DRAM chips are packaged or put into use, it is generally necessary to test various performance parameters of the DRAM chip to ensure that the design of the DRAM chip meets the requirements. The chip to be tested in the embodiments of the present disclosure can be a DRAM. Therefore, the following embodiment description is described with reference to DRAM as a non-limiting example.

[0050] With the rapid development of semiconductor technology, DRAM testing utilizes a test machine (or "test equipment") to generate stimulus for DRAM testing. As DRAM speeds increase, the speed requirements for test equipment are also increasing (for example, LPDDR5X has reached 9600Mbps).

[0051] In the related art, the input / output (IO) ports of current test equipment cannot reach 10 Gigabits per second (Gbps). While the write clock (WCK) can reach 10G, it is still desirable to test the 10G functionality of the IO ports. The challenge in overcoming this technical issue is to test the 10G IO ports at the lowest cost, that is, to cover the IO port performance with minimal impact on the normal path and without increasing the area.

[0052] like Figure 1 As shown, during a write operation, the test machine sends data at the rising and falling edges of WCK. The expected data to be sent is 1 unit interval (UI). However, due to the limitations of the test machine (for example, the speed of the test machine cannot reach the sending speed of 1UI), the test machine can only send 2UI of data. During a read operation, due to the limitations of the test machine, the same read command needs to be sent twice to obtain 2UI of data. Figure 2 As shown in the figure, a read command usually reads 16 UIs of data. Figure 2 In the figure, the dotted arrow represents one sampling, the thin solid arrow and the thick solid arrow represent two samplings. If the data output speed of the DRAM is greater than the sampling speed of the machine, then two samplings are required to obtain complete data.

[0053] In other words, as memory speeds increase, high-speed memory testing relies on the development of high-speed automatic test equipment (ATE). However, high-speed test equipment is expensive, and test programs need to be redeveloped and redesigned, resulting in excessively high testing costs and hindering the implementation of high-speed memory testing.

[0054] Based on this, the embodiments of the present disclosure provide a test method, apparatus, device, storage medium and program product. In this test method, the test device writes data into the chip under test through a low-speed write command, and then sends a high-speed read and write command to the chip under test and controls the timing between the high-speed read and write commands, so that the chip under test reads the high-speed data from its internal storage unit and writes it back to the storage unit inside the chip under test. Then, the test device reads the data from the chip under test through a low-speed read instruction to determine whether the read and write function of the chip under test is correct. In this way, by writing the high-speed data read out by the chip under test back to the inside of the chip under test, instead of the test device generating high-speed data, the low-speed port of the test device can be used to test the high-speed read and write function of the chip under test, solving the problem that the low-speed test device cannot cover the read and write of the high-speed port, and reducing the port speed requirements for the test device; at the same time, without affecting the area of ​​the chip under test and the normal read and write path, it also improves the coverage of the high-speed test, thereby improving the test performance of the memory.

[0055] The present disclosure is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0056] In one embodiment of the present disclosure, Figure 3 A flow chart of a testing method provided in an embodiment of the present disclosure Figure 1 .like Figure 3 As shown, the test method may include:

[0057] S301 , writing first data to a first address of a chip under test through a first write command at a first clock frequency.

[0058] It should be noted that this test method can be applied to test equipment to perform read and write function tests on the chip under test. The test equipment can be a chip tester, ATE, or test bench, and the chip under test can be a DRAM, such as a memory chip that meets the LPDDR5 or LPDD5X memory specifications; however, this is not a limitation.

[0059] It should also be noted that in the disclosed embodiments, the test equipment's clock frequency can be set within a range smaller than the clock frequency of the chip under test. This allows for high-speed read and write testing of the chip under test using low-cost, low-frequency test equipment, while addressing the speed limitations of the test equipment's IO ports (or "IO interfaces").

[0060] In the disclosed embodiments, a first write command refers to a write instruction sent by a test device to a chip under test at a low frequency, used to write specified data to a specific address of the chip under test, for example, writing first data to a first address. Here, the first data is arbitrary test data, typically known data to facilitate subsequent comparison and verification. Therefore, the first data can be referred to as test data or raw data. The first address is a pre-set storage unit location, which can be represented by an A address.

[0061] In the disclosed embodiments, the first clock frequency may refer to the test device being in a low-frequency state, and thus the first write command may also be referred to as a low-speed write command. That is, the test device writes first data to the first address of the chip under test in the low-frequency state, preparing for subsequent high-speed reading and writing of the chip under test. Thus, by writing test data to the chip under test in the low-frequency state, the signal transmission speed is slow in the low-frequency state, resulting in better signal integrity, thereby ensuring the correctness of the original data and providing a benchmark for subsequent high-speed path testing of the chip under test.

[0062] S302, at a second clock frequency, sending at least one first read command and a second write command to the chip under test, and the at least one first read command and the second write command meet a preset timing requirement, so that the chip under test writes the second data read from the first address back to the second address of the chip under test.

[0063] In the disclosed embodiments, switching from a first clock frequency to a second clock frequency may refer to switching from a low-frequency state to a high-frequency state. That is, the second clock frequency may be a high-frequency state, for example, set to 8 Gbps or higher, or even 10 Gbps, to simulate the read and write functions of the chip under test under high-speed operating conditions, without any limitation thereto. Therefore, the first read command and the second write command herein may be referred to as high-speed read and write commands.

[0064] In the embodiment of the present disclosure, the first read command indicates reading data from the first address, and the second write command indicates writing data to the second address. There may be multiple first read commands, for example, two first read commands, and data can be read from the first address respectively according to the two first read commands. In this way, in a high-frequency state, after sending at least one read command, the chip under test can send a second write command after a specific time, so that the second write command can just write the data read from the first address by at least one read command to the second address. By performing read and write operations at different addresses, it is possible to subsequently check whether the high-speed read and write functions of the data are normal.

[0065] In addition, in the embodiment of the present disclosure, the process of writing the second data read from the first address of the chip under test back to the second address of the chip under test can be called a loop test or loop read and write. When sending the second write command, the IO port of the test device needs to meet certain conditions (for example, being in a floating or high-impedance state) to ensure that the data read from the internal loop (Loop Read) to the data bus (Data Queue, DQ) will not be overwritten. In other words, in the loop read and write, the second write command can just write back the data read from the first address by at least one read command to the second address.

[0066] It's important to note that during high-speed read and write tests, the test equipment is only responsible for sending control commands, such as read and write commands, and column address strobe (CAS) commands, and does not participate in the actual data transmission process. This avoids misjudgments caused by insufficient I / O port speed of the test equipment and ensures the integrity of the data path during the test.

[0067] In this way, under high-frequency conditions, the high-speed data read from the first address of the chip under test is written back to the second address of the chip under test through the second write command sent after a specific time. That is, through normal read and write commands, a loop self-test is performed inside the chip under test. This can replace the test equipment to generate high-speed data, thereby meeting the high-speed performance test requirements of LPDDR5X.

[0068] S303 , reading third data from the second address through a second read command at a third clock frequency; and determining a read / write test result of the chip under test based on the third data and the first data.

[0069] In the embodiment of the present disclosure, switching from the second clock frequency to the third clock frequency may refer to switching from a high-frequency state to a low-frequency state. That is, the third clock frequency may be in a low-frequency state, so the second read command may be referred to as a low-speed read command. In this way, the test device reads the data written to the chip under test itself in the high-speed path (i.e., high-frequency state) in the low-frequency state, which enables the test device to test the read and write performance of the chip under test under high-speed conditions in the low-frequency state, thereby reducing the IO speed requirements for the test device and improving the coverage of high-speed tests without increasing the chip area or affecting the normal read and write paths.

[0070] In the embodiment of the present disclosure, the first clock frequency and the third clock frequency are both lower than the second clock frequency. The first clock frequency may be equal to the third clock frequency, or the first clock frequency may be different from the third clock frequency, without any limitation.

[0071] In the disclosed embodiments, the low-frequency state and the high-frequency state refer to different clock frequency states of the chip under test during the test process. The low-frequency state means that the chip under test runs at a lower clock frequency during the test, with slower signal transmission speeds and relatively loose timing requirements; the high-frequency state means that the chip under test runs at a higher clock frequency during the test, with faster signal transmission speeds and stricter timing requirements.

[0072] In the disclosed embodiment, the test device can compare the third data bit by bit with the initially written first data to determine the read / write test results, thereby completing the read / write performance test of the chip under test. Based on the read / write test results, it can be determined that the read / write function of the chip under test is normal, i.e., the test has passed (Pass); or it can be determined that the read / write function of the chip under test has failed (Fail).

[0073] For example, if the data read from the second address is consistent with the data originally written, it indicates that there is no problem with the writing process and the reading process, and it can be determined that the read and write function test of the chip to be tested is normal; if the data read from the second address is inconsistent with the data originally written, it indicates that an error may occur in the writing process or the reading process, and it can be determined that the read and write function test of the chip to be tested has failed.

[0074] In some embodiments, the testing method further includes: sending a column address strobe command before the first clock frequency is switched to the second clock frequency, or before the second clock frequency is switched to the third clock frequency.

[0075] In the embodiment of the present disclosure, the column address strobe command is a basic control instruction for DRAM operation, and its main function is to activate and strobe the column address in a read or write operation to access data in a storage unit in the DRAM.

[0076] In the disclosed embodiments, in high-speed testing scenarios (i.e., high-frequency states), when preparing to switch the currently running clock frequency to a higher frequency, if proper synchronization is not performed, the read and write paths may become unstable, leading to data loss or errors. Therefore, sending a CAS command before switching the clock frequency can ensure timing consistency between the memory controller and storage array in the DRAM, preventing signal distortion or delay deviation caused by frequency transitions, thereby ensuring the stability of the read and write paths and data integrity.

[0077] In some embodiments, the testing method may further include: keeping the write clock signal always in an on state.

[0078] In the disclosed embodiment, the write clock signal can also be kept in the always-on (WckAlways On) state. In normal mode, the write clock (WCK) signal is enabled only during write operations to save power consumption; in WckAlwaysOn mode, the WCK signal always remains on and continues to run even when there is no write operation. In this way, the test requires fast and continuous data write and read operations inside the DRAM. At this time, the WckAlwaysOn mode can reduce the delay in clock start and stop and improve test efficiency. Here, the WCK signal is a new clock signal introduced in the LPDDR5 memory standard, which is mainly used for data transmission, and by adding the WCK signal, the data transmission rate is higher. Therefore, the WCK signal can also be called a data clock.

[0079] That is to say, in the embodiment of the present disclosure, the column address selection command can be sent before the first clock frequency is switched to the second clock frequency, or before the second clock frequency is switched to the third clock frequency; or the write clock signal can be enabled to be in the always-on state to replace the column address selection command. In this way, not only the timing stability of the system is improved, but also the risk of data transmission errors caused by frequency changes is reduced. In this way, not only the high-speed test coverage can be improved, but also the dependence on external test equipment can be reduced, and it is no longer limited by the speed of the test equipment, thereby improving the overall test efficiency and cost-effectiveness.

[0080] In some embodiments, at the second clock frequency, the test method may further include: when sending a second write command to the chip under test, keeping the input and output ports of the test device in a suspended state or a high-impedance state.

[0081] In an embodiment of the present disclosure, when the test device sends a second write command to the chip under test, in order to prevent external data from interfering with the data stream read by the internal loop, the IO port of the test device is set to a floating state or a high-impedance state (HiZ). In this state, the test device can avoid the problem of overwriting the data on the data bus read by the internal loop of the chip under test during the writing operation to the second address by the second write command, thereby ensuring that the data on the data bus read by the internal loop of the chip under test is not overwritten. In this way, it can be ensured that the high-speed data read from the chip under test can be correctly written back to the chip under test, thereby maintaining the integrity and accuracy of the data and improving the reliability of the test results.

[0082] In the disclosed embodiments, the floating state may refer to an IO port being completely disconnected, presenting a high impedance characteristic to the outside world, which is equivalent to an electrical open circuit. The high impedance state refers to a state in which the IO port remains connected but has zero drive capability, i.e., it does not actively output high or low levels, nor does it pull down or pull up the signal line. It should be noted that both of these methods can avoid the problem of test equipment overwriting or interfering with data on the external data bus.

[0083] In this way, in the embodiment of the present disclosure, by keeping the IO port of the test device in a floating state or a high-impedance state when sending the second write command to the chip under test, external data can be effectively prevented from interfering with the internal loop read and write operations, so that the read data can be accurately written back to the chip under test, thereby improving the coverage of high-speed testing and solving the problem in related technologies that the test equipment cannot support high-speed ports.

[0084] The disclosed embodiment provides a testing method, in which a test device writes data into a chip under test through a low-speed write command, and then sends a high-speed read and write command to the chip under test and controls the timing between the high-speed read and write commands, so that the chip under test reads high-speed data from its own internal storage unit and writes it back to the storage unit inside the chip under test. The test device then reads data from the chip under test through a low-speed read instruction to determine whether the read and write functions of the chip under test are correct. In this way, by writing the high-speed data read out by the chip under test back to the inside of the chip under test, the test device generates high-speed data instead, so that the high-speed read and write functions of the chip under test can be tested using the low-speed port of the test device, solving the problem that the low-speed test device cannot cover the read and write of the high-speed IO port, and reducing the speed requirements for the IO port of the test device; at the same time, without affecting the area of ​​the chip under test and the normal read and write path, the coverage rate of the high-speed test is also improved.

[0085] In another embodiment of the present disclosure, based on the test method of the aforementioned embodiment, the number of at least one first read command is one, for example, at least one first read command may include a third read command. Figure 4 A flow chart of a testing method provided in an embodiment of the present disclosure Figure 2 .like Figure 4 As shown, the test method may include:

[0086] S401: The time interval between the third read command and the second write command meets the first timing requirement, so that the start time of the chip under test reading data from the first address and the start time of the chip under test writing data back to the second address are synchronized.

[0087] In the embodiment of the present disclosure, the time interval between at least one first read command and a second write command meeting a preset timing requirement may refer to the time interval between a third read command and a second write command meeting the first timing requirement. Furthermore, the start time of reading data from the first address refers to the start time of outputting data from the IO port of the chip under test, and the start time of writing data back to the second address refers to the start time of writing data to the data receiver of the IO port.

[0088] In the embodiment of the present disclosure, the first timing requirement may refer to that a specific time interval requirement must be met between the third read command and the second write command, thereby ensuring that the data read from the first address by the chip under test can be captured and written to the second address in a timely manner.

[0089] In the disclosed embodiment, by setting a first timing requirement between the third read command and the second write command, the read and write functionality of the high-speed IO port of the chip under test can be verified without requiring external test equipment to support high speed. This avoids reliance on high-speed external test equipment, reducing testing costs while also improving test coverage and efficiency. Furthermore, this testing method does not affect the normal read and write paths of the chip under test and does not increase the chip area, thus ensuring good compatibility and practicality of the test equipment.

[0090] In some embodiments, the time interval between the third read command and the second write command meets the first timing requirement, including: the time interval between the third read command and the second write command is an integer multiple of a clock period of the external clock.

[0091] In the disclosed embodiments, the external clock may be represented by "CLK," and the corresponding clock cycle may be represented by "tck" or "ck." The chip under test may receive the external clock, and all commands are synchronized with this clock as a reference. During each clock cycle of the external clock, the chip under test may sample command and address signals to determine whether a corresponding operation needs to be performed.

[0092] In the disclosed embodiments, WCK is the clock reference for data read and write operations, used to synchronize data read and write operations within the chip under test. During a write operation, data is sampled on the rising or falling edge of WCK and written to the corresponding memory address of the chip under test. During a read operation, data is read from the corresponding memory address of the chip under test on a specific edge of WCK and transmitted to an external device via the data bus.

[0093] In the disclosed embodiment, the time interval between the third read command and the second write command is set to an integer multiple of the external clock cycle, which can ensure that the timing relationship between the two operations is aligned, thereby avoiding data sampling errors or write failures caused by non-integer delays, thereby reducing the uncertainty and errors caused by asynchronous operations, and thus improving the accuracy of the test. In addition, by setting the read and write command interval to an integer multiple of the clock cycle of the external clock, it can be ensured that the data read out at high speed can be accurately written back to the storage unit inside the chip under test, thereby achieving test coverage of the high-speed read and write functions of the chip under test by the low-speed IO port of the test machine. In this way, not only can the requirements for the IO port speed of the test equipment be reduced, but also the test requirements of the high-performance chip under test can be completed using lower-cost test equipment, thereby improving test efficiency and reducing costs.

[0094] In some embodiments, the time interval between the third read command and the second write command meets the first timing requirement, including: the time interval between the third read command and the second write command is equal to RL-WL+tWCK2DQO-tWCK2DQI; wherein RL represents the read delay time of the third read command, WL represents the write delay time of the second write command, tWCK2DQI represents the delay time from the data clock to the data input, tWCK2DQO represents the delay time from the data clock to the data output, and tWCK2DQI and tWCK2DQI can be adjusted through the test mode inside the chip to be tested.

[0095] In the disclosed embodiments, read latency (RL) refers to the time interval between sending a read command and starting to read data. Setting the read latency is crucial to ensuring correct data reading, especially at high frequencies where any deviation may lead to data errors. Write latency (WL) refers to the time interval between sending a write command and starting to write data to the storage address. Similar to read latency, write latency affects the stability and reliability of written data. At high frequencies, precise control of write latency is particularly important to ensure that write operations are synchronized with the clock.

[0096] In the disclosed embodiments, the data clock to data input delay (tWCK2DQI) refers to the timing deviation from the data clock edge triggering to the data entering the IO port of the chip under test, that is, the data clock to data input delay. It should be noted that due to the routing differences between the digital clock and the data bus, the timing deviation between the two may occur. If tWCK2DQI is not accurately calculated or compensated, it may cause data sampling errors.

[0097] In the disclosed embodiments, the data clock to data output delay (tWCK2DQO) refers to the timing deviation from the data clock edge triggering to the actual data being sent from the IO interface of the chip under test, that is, the data clock to data output delay. Differences in the routing of the digital clock and data bus may cause timing deviations between the two. If tWCK2DQI is not accurately calculated or compensated, this may lead to data sampling errors.

[0098] For example, Figure 5 A signal timing diagram corresponding to a test method provided in an embodiment of the present disclosure Figure 1 .like Figure 5 As shown in the figure, CLK represents the external clock, CMD represents the command signal (such as CAS command, Write command, Read command, etc.), WCK represents the write clock, Read Data represents reading data, Write Data represents writing data, and CK represents one clock cycle of the external clock. Among them, for the command signal, CAS represents the address selection command, Write (AdrA) represents writing data to the A address (i.e., the first address) of the chip under test, Read (AdrA) represents reading data from the A address of the chip under test, Write (AdrB) represents writing data to the B address (i.e., the second address) of the chip under test, and Read (AdrB) represents reading data from the B address of the chip under test.

[0099] In the embodiment of the present disclosure, Figure 5As shown, first send the CAS command, then send the first write command (i.e., Write (AdrA)) on the rising edge of the CLK clock, and after the delay time WL+tWCK2DQI, the first data begins to be written to the first address of the chip under test; WL here refers to the write delay time of the first write command, and tWCK2DQI represents the delay time from the data clock to the data input; send the CAS command again, and then send the third read command (i.e., Read (AdrA)) on the rising edge of the CLK clock, and after the delay time RL+tWCK2DQI, the first data begins to be written to the first address of the chip under test; After CK2DQO, data begins to be read from the first address of the chip under test. Here, RL is the read delay time of the third read command, and tWCK2DQO represents the delay time from the data clock to the data output. After sending the third read command (i.e., Read(AdrA)), a second write command (i.e., Write(AdrB)) is sent after an interval of RL-WL+tWCK2DQO-tWCK2DQI. After the delay time WL+tWCK2DQI, the second write command begins writing data to the second address of the chip under test. It is important to note that the timing at which the third read command begins reading data from the first address of the chip under test and the second write command begins writing data to the second address of the chip under test is synchronized, so that the second data read from the first address is written back to the second address of the chip under test. Finally, the CAS command is sent, and then the second read command (i.e., Read(AdrB)) is sent on the rising edge of the CLK clock. After the delay time RL+tWCK2DQO, data begins to be read from the second address of the chip under test. It should also be noted that tWCK2DQO refers to the timing deviation from the data clock edge trigger to the data actually being sent out from the IO interface of the chip under test, and tWCK2DQI refers to the timing deviation from the data clock edge trigger to the data entering the IO interface of the chip under test.

[0100] It should be noted that, taking the example of data a1 in which the chip under test writes the read data to the second address via the second write command, data a1 includes 0, 1, 2, ..., 15. Here, 0 represents bit 0 (bit 0), 1 represents bit 1 (bit 1), ..., and 15 represents bit 15 (bit 15). At the rising edge of WCK, the 15 bits of data corresponding to data a1 are sequentially written to the second address of the chip under test.

[0101] In an embodiment of the present disclosure, by setting the time interval between sending the third read command and sending the second write command to RL-WL+tWCK2DQO-tWCK2DQI, the chip under test can write the data read in the first address exactly into the second address, thereby completing the loop read and write function of the chip under test.

[0102] In the embodiment of the present disclosure, since the time interval between the write command and the read command must be an integer multiple of the clock period of the external clock, if tWCK2DQO and tWCK2DQI are not adjusted, then in the embodiment of the present disclosure, the first timing requirement is set so that the time interval between the write command and the read command is not an integer multiple of the clock period of the external clock. Therefore, the values ​​of tWCK2DQO and tWCK2DQI can also be adjusted through the internal test mode here, thereby achieving more flexible timing matching.

[0103] It should be noted that the test mode inside the chip to be tested is a working mode for adjusting internal delay parameters. In the related art, when the data transmission rate is greater than 6400Mbps (i.e., high-speed mode), the range of tWCK2DQI is 250 to 600, and the range of tWCK2DQO is 650 to 1600. However, the values ​​of tWCK2DQI and tWCK2DQO in the related art may not meet the first timing requirement. Therefore, the embodiment of the present disclosure adjusts the values ​​of tWCK2DQI and tWCK2DQO by adding a circuit structure so that the time interval between the third read command and the second write command can meet the first timing requirement.

[0104] For example, Figure 6 A circuit diagram of a test method provided in an embodiment of the present disclosure. Figure 6 As shown, the circuit structure shown here is a new circuit for the test mode, and the existing circuit structure for the test mode in the related art is not illustrated. The circuit structure may include a first inverter 601, a second inverter 602, a first selection module 603, a second selection module 604, a first delay module 605, a second delay module 606, an inversion control module 607 and a resistor R. The connection relationship of each device is as follows Figure 6 As shown, no detailed explanation is given here.

[0105] In the embodiment of the present disclosure, both the first delay module 605 and the second delay module 606 may be implemented by cascading an even number of inverters, for example, data delay may be implemented by cascading two inverters.

[0106] It should be noted that the input end of the first inverter 601 is used to receive the first high-speed test signal, and the output end of the first inverter 601 is used to output the inverted first high-speed test signal. The input end and output end of the first inverter 601 are respectively connected to the two control ends of the first selection module 603; the data is input to the first delay module 605 for delay processing, and the input end and output end of the first delay module 605 are respectively connected to the two input ends of the first selection module 603, and the output end of the first selection module 603 is connected to the input end of the second delay module 606. In this way, the first selection module 603 is used to select a signal from one of the two input ends based on the first high-speed test signal and the inverted first high-speed test signal received by the control end of the first selection module 603, and output it from the output end of the first selection module 603; wherein the signals of the two input ends are the data signal before and after delay by the first delay module 605, respectively. Similarly, the input end of the second inverter 602 is used to receive the second high-speed test signal, and the output end of the second inverter 602 is used to output the inverted second high-speed test signal. The input end and output end of the second inverter 602 are respectively connected to the two control ends of the second selection module 604; the input end of the second delay module 606 is used to receive the data signal output by the first selection module 603, and the input end and output end of the second delay module 606 are respectively connected to the two input ends of the second selection module 604, and then the output end of the second selection module 604 is connected to the input end of the inversion control module 607. In this way, the second selection module 604 is used to select a signal from one of the two input ends based on the second high-speed test signal and the inverted second high-speed test signal received by the control end of the second selection module 604, and output it from the output end of the second selection module 604; wherein the signals at these two input ends are the data signal before and after delay by the second delay module 606, respectively. Furthermore, the input terminal of the inverting control module 607 is used to receive the data signal output by the second selection module 604. The two control terminals of the inverting control module 607 are respectively used to receive the third high-speed test signal and the fourth high-speed test signal. The output terminal of the inverting control module 607 is also connected to the resistor R for outputting data. Thus, through the selection of the first selection module 603 and the second selection module 604, the delay between data input and data output can be adjusted, thereby achieving the aforementioned purpose of adjusting the values ​​of tWCK2DQO and tWCK2DQI.

[0107] In addition, Figure 6The first high-speed test signal can be tested with cm0_ts_HighSpeedTestTrim <0> Indicates that the second high-speed test signal can be used cm0_ts_HighSpeedTestTrim <1> The third high-speed test signal can be represented by fnHighSpeedTestN, and the fourth high-speed test signal can be represented by cm0_ts_HighSpeedTest. Here, the level states of fnHighSpeedTestN and cm0_ts_HighSpeedTest are opposite, for example, the level state of fnHighSpeedTestN is high (or called "logic 1"), and the level state of fnHighSpeedTestN is low (or called "logic 0").

[0108] It should also be noted that according to Figure 6 The circuit structure shown can be used to configure the hardware of the chip under test, namely to adjust tWCK2DQI and tWCK2DQO. In other words, this circuit structure can dynamically adjust the values ​​of tWCK2DQO and tWCK2DQI, thereby achieving more flexible timing matching to meet the timing requirements between read and write commands in relevant regulations.

[0109] By establishing a timing relationship between the third read command, the fourth read command, and the second write command, and dynamically adjusting some parameter values ​​within the timing relationship using the chip's internal test mode, high-speed loop read and write operations can be effectively implemented. This allows for functional verification of the chip under test at 10G speeds without adding additional hardware overhead, thereby improving test coverage and reducing test costs.

[0110] In some embodiments, the read and write test results of the chip to be tested are determined based on the third data and the first data, including: when the third data and the first data are the same, determining that the read and write test result is that the read and write function test of the chip to be tested is normal; or, when the third data and the first data are different, determining that the read and write test result is that the read and write function test of the chip to be tested fails.

[0111] In the embodiment of the present disclosure, the third data is the data read from the second address by the low-speed read instruction (i.e., the second read command) after the chip under test completes the high-speed read and write operation. This data is the output result after reading the internal loop of the chip under test, and can reflect whether the chip under test can correctly write and read data in high-speed mode. Among them, the first data is the original data initially written into the chip under test in a low-frequency state. The third data is compared with the first data to determine whether the read and write function of the chip under test is normal. For example, when the two are consistent, it means that no data loss or error occurs in the high-speed reading and writing process of the chip under test, indicating that its read and write function is normal; on the contrary, if the two are inconsistent, it means that there is a problem of abnormal data transmission or storage during the high-speed reading and writing process, thereby determining that the read and write function test has failed.

[0112] Thus, in the disclosed embodiment, by setting the first timing requirement between the third read command and the second write command, synchronous control of the read and write operations can be achieved, that is, the data read from the first address by the chip under test can be written back to the second address by the chip under test; thus, only the low-speed IO interface of the test equipment is required to complete the verification of the high-speed read and write functions of the chip under test, which can reduce the testing cost and complexity; and it can also ensure the integrity of the data during the loop test, thereby effectively verifying the read and write performance of the chip under test in a high-speed state. In addition, this testing method is not limited by the speed of the test equipment, making the test equipment have good compatibility and scalability.

[0113] In another embodiment of the present disclosure, based on the test method of the aforementioned embodiment, the number of the at least one first read command is two, for example, the at least one first read command may include a third read command and a fourth read command; accordingly, Figure 7 The second process diagram of a testing method provided in the embodiment of the present disclosure is shown in FIG. Figure 7 As shown, the test method may include:

[0114] S701, the time interval between the third read command and the fourth read command meets the second timing requirement, and the time interval between the third read command and the second write command meets the third timing requirement, so that the data written back to the second address by the chip under test is the middle part of all the data read from the first address by the third read command and the fourth read command respectively.

[0115] In the disclosed embodiment, at least one of the first read command and the second write command meets the preset timing requirement, which may mean that the time interval between the third read command and the fourth read command meets the second timing requirement, and the time interval between the third read command and the second write command meets the third timing requirement. In addition, the third read command and the fourth read command refer to two read instructions issued continuously in a high-frequency state, which are used to read data from the same address (such as the first address) inside the chip under test. In other words, the time interval between the third read command and the fourth read command meets the second timing requirement to ensure that there is no data gap or overlap between the two read operations.

[0116] In some embodiments, the time interval between the third read command and the fourth read command satisfies the second timing requirement, which may include: the time interval between the third read command and the fourth read command is two clock cycles of the external clock. In this way, the time interval between the third read command and the fourth read command is 2CK, which ensures that there is no data gap or overlap between the two read operations, thereby avoiding data sampling conflicts and ensuring that the two read data are completely recorded.

[0117] In some embodiments, the time interval between the third read command and the second write command meets a third timing requirement, including: the time interval between the third read command and the second write command is equal to RL-WL+nCK.

[0118] In the embodiment of the present disclosure, RL represents the read delay time of the third read command, WL represents the write delay time of the second write command, and nCK represents n clock cycles of the external clock, where n is an integer.

[0119] It should be noted that RL refers to the time interval between sending the third read command and the start of data reading; WL refers to the time interval between sending the second write command and the start of data writing to the storage address. nCK represents n clock cycles of the external clock and is used to adjust the time interval between read and write commands to ensure that the read data can be correctly captured and written back to the second address of the chip under test. Here, n is an integer, and the value of n can be specifically set according to test conditions and timing relationships. For example, n is equal to 2.

[0120] In the embodiment of the present disclosure, by setting the time interval between the third read command and the second write command to RL-WL+nCK, the chip under test can still ensure correct data transmission and cyclic writing in a high-frequency state, and can also ensure the accuracy of the loop test of the chip under test while adapting to the timing deviation under different process-voltage-temperature corners (PVT corners).

[0121] In some embodiments, the time interval between the third read command and the second write command satisfies the third timing requirement and may further include: the sum of nCK and the preset duration is greater than or equal to 0 and less than or equal to 2CK, and 2CK represents 2 clock cycles of the external clock; wherein the preset duration is tWCK2DQI-tWCK2DQO, tWCK2DQI represents the delay time from the data clock to the data input, and tWCK2DQO represents the delay time from the data clock to the data output.

[0122] In the disclosed embodiments, nCK is an adjustable parameter used to adjust the relative timing between data read and written during loop read and write operations, thereby ensuring that the read data is correctly written back to the chip under test. This parameter can also adapt to timing requirements under different process-voltage-temperature (PVT) conditions without changing the hardware structure, improving test flexibility and stability.

[0123] It should be noted that, in the embodiment of the present disclosure, unlike the aforementioned embodiment in which at least one first read command only includes the third read command, in the case in which at least one first read command includes the third read command and the fourth read command, tWCK2DQI and tWCK2DQO can adopt the adjustment range in the related art, so there is no need to add additional Figure 6 The circuit structure shown.

[0124] In the embodiment of the present disclosure, by limiting the value obtained by adding nCK to the preset duration to between 0 and 2CK, it is possible to ensure that read and write operations are physically synchronized, while avoiding data loss or conflicts due to timing errors. This can effectively cover all possible timing configurations and ensure that read and write operations can maintain the correct logical order and data integrity under various working conditions.

[0125] In addition, in the embodiment of the present disclosure, when the chip under test performs a Loop read and write operation when switching to a high-frequency state, the difference between tWCK2DQI and tWCK2DQO is dynamically calculated according to the current state of the chip under test (such as temperature, voltage, process angle, etc.), and the value range of nCK is adjusted accordingly. For example, in a high-temperature environment, due to the decrease in signal transmission speed, tWCK2DQO may increase. At this time, nCK needs to be appropriately reduced to maintain the sum within a reasonable range. On the contrary, under low temperature or high pressure conditions, nCK can be appropriately increased to provide a more ample timing margin.

[0126] That is to say, in the embodiment of the present disclosure, by setting the sum of nCK and the preset time length in the range of 0 to 2CK, the timing matching of read and write operations can be accurately controlled, thereby improving the test coverage and reliability of the chip under test in high-speed mode.

[0127] In some embodiments, at a first clock frequency, the write command for writing data to the chip under test may include two (e.g., a first write command and a third write command). Correspondingly, the at least one first read command may also include two (e.g., a third read command and a fourth read command). At the first clock frequency, after writing the first data to the first address of the chip under test by the first write command, the test method further includes: at the first clock frequency, writing the fourth data to the third address of the chip under test by the third write command; and at the second clock frequency, reading data from the first address by the third read command and reading data from the third address by the fourth read command; wherein the time interval between the third read command and the fourth read command meets the second timing requirement, and the time interval between the third read command and the second write command meets the third timing requirement, so that the data written back to the second address by the chip under test is the middle part of all the data read from the first address and the third address by the third read command and the fourth read command respectively.

[0128] In an embodiment of the present disclosure, the first clock frequency can be in a low-frequency state, and the second clock frequency can be in a high-frequency state. In the low-frequency state, the test device can send two write commands, namely a first write command and a third write command; the first write command is used to write the first data to the first address of the chip under test, and the third write command is used to write the fourth data to the third address of the chip under test; then the third read command and the fourth read command are used to read the data from the first address and the third address respectively to obtain two data; then a part of the two data is intercepted and written back to the second address of the chip under test through the second write command. It should be noted here that if there are two write commands in the initial stage (for example, the first write command and the third write command), then the third read command and the fourth read command are read from different addresses (for example, the first address and the third address) to obtain two data read from the two addresses. If there is only one write command in the initial stage (for example, the first write command), then the third read command and the fourth read command are read from the same address (for example, the first address) twice.

[0129] For example, Figure 8 A signal timing diagram corresponding to a test method provided in an embodiment of the present disclosure Figure 2 .like Figure 8As shown in the figure, CLK represents the external clock, CMD represents the command signal (such as CAS command, Write command, Read command, etc.), WCK represents the write clock, Read Data represents reading data, and Write Data represents writing data. Among them, for the command signal, CAS represents the address selection command, Write (B0, C0) represents writing data to the first address of the chip under test, Write (B4, C0) represents writing data to the third address of the chip under test, Read (B0, C0) and Read (B4, C0) represent two consecutive read commands (i.e., the third read command and the fourth read command), Read (B0, C0) represents reading data from the first address of the chip under test, and Read (B4, C0) represents reading data from the third address of the chip under test; Write (B0, C1) represents writing data to the second address of the chip under test; Read (B0, C1) represents reading data from the second address of the chip under test.

[0130] In the embodiment of the present disclosure, Figure 8As shown, first send the CAS command, then send the first write command Write(B0, C0) and the third write command Write(B4, C0) on the rising edge of the CLK clock respectively, after the delay time WL+tWCK2DQI, the first data starts to be written to the first address of the chip under test, and the fourth data starts to be written to the third address of the chip under test; here WL refers to the write delay time of the first write command Write(B0, C0) or the third write command Write(B4, C0), tWCK2DQI represents the delay time from the data clock to the data input; send the CAS command again, and then send the third read command Read(B0, C0) and the fourth read command Read(B4, C0) on the rising edge of the CLK clock respectively, after the delay time R After L+tWCK2DQO, the third read command Read(B0,C0) starts to read data from the first address of the chip under test, and the fourth read command Read(B4,C0) starts to read data from the third address of the chip under test; here, RL is the read delay time of the third read command Read(B0,C0) or the fourth read command Read(B4,C0), and tWCK2DQO represents the delay time from the data clock to the data output; wherein, after sending the third read command Read(B0,C0), the second write command Write(B0,C1) is sent at an interval of RL-WL+nCK; the second write command Write(B0,C1) starts to write data to the second address of the chip under test after the delay time WL+tWCK2DQI. Note that the interval between the third read command, Read(B0,C0), and the fourth read command, Read(B4,C0), is set to 2CK. Furthermore, the interval between the start of data reading from the first address of the chip under test by the third read command, Read(B0,C0), and the start of data writing to the second address of the chip under test by the second write command, Write(B0,C1), satisfies nCK + tWCK2DQI - tWCK2DQO. This ensures that the middle portion of the data read from the first and third addresses is written back to the second address of the chip under test. Finally, a CAS command is issued, followed by the second read command, Read(B0,C1), on the rising edge of CLK. After a delay of RL + tWCK2DQO, data reading from the second address of the chip under test begins. It is also important to note that tWCK2DQO refers to the timing deviation from the data clock edge triggering to the actual data being sent out of the I / O interface of the chip under test, while tWCK2DQI refers to the timing deviation from the data clock edge triggering to the data entering the I / O interface of the chip under test.

[0131] It should also be noted that according to Figure 8It can be seen that by setting the time interval between the third read command and the fourth read command to 2CK, there is no gap between the First Read Data read by the third read command and the Second Read Data read by the fourth read command; then by adjusting the value of nCK+tWCK2DQL+WCK2DQO, the data written to the chip under test by the second write command is the middle part of all the data read from the first address by the third read command and the fourth read command respectively, thereby ensuring that the high-speed data read out from the chip under test itself can be correctly written back to the chip under test, maintaining the integrity and accuracy of the data, and improving the reliability of the test results.

[0132] It should also be noted that, in the embodiment of the present disclosure, there are 16 data topologies for the data Write Data written to the chip under test by the second write command, which are affected by factors such as the PVT corner. For example, the starting point of writing from the data number read from the third read command is related to the PVT corner. However, under the same conditions, the data read out by multiple loops should be consistent. For example, taking D1 and D2 among the 16 data topologies as an example, D1 is written from the 0th data bit read from the third read command, and D2 is written from the 1st data bit read from the third read command.

[0133] In addition, it should be noted that the data written to the chip under test through the second write command is determined by the simulation time tWCK2DQI-tWCK2DQO, and tWCK2DQI-tWCK2D is related to the PVT corner of the chip under test. Therefore, by adjusting tWCK2DQI-tWCK2DQO, the data written back to the second address by the chip under test can be the middle part of all the data read from the first address by the third read command and the fourth read command respectively.

[0134] In some embodiments, determining the read / write test result of the chip under test may further include:

[0135] Reading data from the first address of the chip under test or reading data from the first address and the third address of the chip under test respectively through a third read command and a fourth read command;

[0136] Writing back fifth data to the second address of the chip under test through the second write command, where the fifth data is a middle part of all the data read by the third read command and the fourth read command;

[0137] Reading third data from the second address through a second read command;

[0138] cyclically executing the steps of the third read command, the fourth read command, the second write command, and the second read command to obtain third data read multiple times;

[0139] If the third data read multiple times are consistent, the read / write test result is determined to be that the read / write function test of the chip to be tested is normal; or, if the third data read multiple times are inconsistent, the read / write test result is determined to be that the read / write function test of the chip to be tested fails.

[0140] In the embodiment of the present disclosure, the fifth data may be a middle portion of all data read by the third read command and the fourth read command, for example Figure 8 Any of the 16 data topologies shown. Since the PVT corner does not change under the same conditions (because the temperature and voltage do not change during a short test, and the process corner of the same chip under test does not change), then follow the same timing as above, for example, first use the third read command and the fourth read command to perform two reads, then use the second write command to write back, and then read again with the second read command. If the read and write functions are normal, then repeat this operation multiple times according to the same timing, and the third data read multiple times should be consistent.

[0141] For example, Figure 8 Taking D2 in the 16 data topologies shown as an example, assume that the fifth data written to the second address of the chip under test via the second write command is D2; if the read and write functions are normal, then the data read from the second address of the chip under test via the second read command is also D2. Under the same conditions, since the PVT corner does not change, after two reads via the third and fourth read commands, the data written to the second address of the chip under test via the second write command is still D2; if the read and write functions are normal, then the data read again via the second read command is still D2. In this way, the operation is repeated multiple times according to the same timing, for example, reading twice and writing back once, and each time the data written back to the second address should be D2. The data read after multiple write backs is compared to determine whether they are all D2. If the data read after multiple write backs is all D2, then the read and write function test of the chip under test is normal; conversely, if the data read after multiple write backs is not all D2 (there is inconsistency), then the read and write function test of the chip under test has failed.

[0142] An embodiment of the present disclosure provides a testing method, which ensures that the read data can be stably captured and written back in a high-frequency state by setting a second timing requirement between the third read command and the fourth read command, and a third timing requirement between the third read command and the second write command; this can reduce the dependence on the IO interface speed of the test machine, thereby improving the coverage of high-speed testing, and can also achieve low-cost testing of the high-speed read and write performance of the chip to be tested, thereby improving test efficiency.

[0143] In another embodiment of the present disclosure, based on the test method of the aforementioned embodiment, the embodiment of the present disclosure mainly relates to high-speed testing of LP5x. Here, a test method applied to LP5x is proposed. Through normal read and write instructions, a loop self-test is performed inside the chip to be tested (such as DRAM) to meet the high-speed performance test requirements of LP5x.

[0144] In the disclosed embodiment, high-speed serial data read from the DRAM is written back to the DRAM, replacing the high-speed data generated by the ATE machine. Furthermore, by controlling the timing of external read and write commands, the high-speed read data from the DRAM is completed and written back to the storage unit inside the DRAM via the Rx interface. Low-speed read instructions are then used to test the correctness of these read and write functions. This allows the high-speed read and write functions of the DRAM to be tested using a low-speed IO interface, resolving the problem of the machine's inability to cover high-speed IO interface chips. This improves the coverage of current high-speed tests, while maintaining a low impact on the chip area and normal read and write paths, thereby enhancing test performance.

[0145] In the embodiments of the present disclosure, the following description is based on an example in which the test equipment is an ATE machine (or "test machine") and the chip under test is a DRAM, but the present invention is not limited thereto. In one possible implementation, the at least one read command includes only the third read command, and the test method may include the following steps:

[0146] Step 1, low-frequency writing background: The test machine first writes data to address A (ie, the first address) in the DRAM using a normal write instruction (ie, the first write command) in a low-frequency state.

[0147] Step 2, switching frequency: switching the frequency to a high frequency state, and configuring parameters such as read delay time and write delay time accordingly.

[0148] Step 3, Loop read and write: send a normal read command (ie, the third read command), and then send a normal write command (ie, the second write command) to operate on address B at a specific time.

[0149] It should be noted that when sending the third read command, the IO interface of the test machine needs to remain in a floating state or high-impedance state to ensure that the data read by the internal loop on the DQ is not overwritten; and when performing loop reading and writing, it is necessary to send a CAS command before the third read command, or turn on the WckAlwaysOn function for synchronization.

[0150] It should also be noted that the time interval between the third read command and the second write command needs to satisfy the following relationship: RL-WL+tWCK2DQO-tWCK2DQI; and the time interval between the third read command and the second write command is an integer multiple of the clock period of the external clock. In addition, tWCK2DQO-tWCK2DQI can be adjusted through the internal test mode, for example, through the aforementioned Figure 6 The circuit structure shown is adjusted.

[0151] It should also be noted that this can also be used to calculate and adjust the interval time between the third read command and the second write instruction. For example, both methods need to satisfy the requirement that the time interval between the third read command and the second write instruction is an integer multiple of the clock. In addition, the main reason why RL-WL+tWCK2DQO-tWCK2DQI is not an integer multiple is tWCK2DQO-tWCK2DQI, so tWCK2DQO-tWCK2DQI can be adjusted to be equal to 0, so that the time interval between the third read command and the second write instruction is an integer multiple of the clock. In this way, in Loop reading and writing, the data read out can be written back.

[0152] Step 4: The data read from DRAM will be rewritten into DRAM.

[0153] Step 5, switching frequency: switching the frequency to a low frequency state, and configuring parameters such as read delay time and write delay time accordingly.

[0154] Step 6, low-frequency read: perform a normal read operation on address B (i.e., the second address) (i.e., read data through the second read command), and check the correctness of the read data at the same time; if the read data is the data of the initial low-speed write background, it means that the high-speed read and write function of the DRAM particle has passed, otherwise it has failed.

[0155] In a specific embodiment, Figure 9 Schematic diagram of an application framework of a test method provided in an embodiment of the present disclosure. Figure 9As shown, the framework may include test machine low-speed write 901, DRAM loop read and write 902, and test machine low-speed read 903. In test machine low-speed write 901 and test machine low-speed read 903, WCK and IO data are in a low-speed state. In DRAM loop read and write 902, WCK and IO data are in a high-speed state, and the IO data keeps the read command configuration (KeepRD configure).

[0156] It should be noted that if Figure 9 In the test sequence shown, both the test machine low-speed write 901 and the test machine low-speed read 903 are machine low-speed reads and writes, and any speed is acceptable. For DRAM loop reads and writes 902, the test machine only needs to send normal command signals and the high-speed WCK. The data read from the loop is directly written back to the DRAM. Furthermore, the addresses for loop reads and writes are different to verify that the data is written correctly. Synchronization can be achieved by issuing a CAS command before switching speeds, or by enabling the WCK always-on function to replace the CAS command.

[0157] It should also be noted that in Figure 9 In the test machine low-speed write 901, first activate through the activation command (Active), then send the CAS command, and then write the data to the A address through the first write command, that is, Figure 9 In the DRAM Loop Read / Write 902, a CAS command is sent, and then data is read from address A through the third read command, i.e. Figure 9 The RD (AdrA) shown in the figure is then used to write data from the second address through the second write command. At this time, the IO of the test machine is in a high impedance state (HiZ), that is, Figure 9 As shown in WR (AdrB, HiZ), it should be noted that at this time, the write command has no data input (i.e., no external data is required) just like the read command, so that the DRAM writes the read data directly back to the DRAM. In the test machine low-speed read 903, the CAS command is sent first, and then the data is read from address B through the second read command, i.e. Figure 9 The RD (AdrB) shown in the figure is then followed by a precharge command (Precharge, PRE), completing the high-speed read and write test of the DRAM. It should be noted that an Activate command (Active) must be sent before the test begins, and a Precharge command (PRE) must be sent after the test is complete to ensure that the test complies with the relevant technical specifications.

[0158] In the embodiment of the present disclosure, combined with the above Figure 5The signal timing shown in the figure shows that the Read (AdrA) and Write (AdrB) operations represent the internal DRAM loop read and write operations. Write (AdrA) and Read (AdrB) represent normal machine read and write operations for test equipment, providing data for verifying internal loop read and write operations. Here, the time interval between Write (AdrB) and Read (AdrA) is RL - WL + tWCK2DQO - tWCK2DQI. Since tWCK2DQO - tWCK2DQI is a simulation time, and Write (AdrB) is in the external clock domain (CK domain), tWCK2DQO - tWCK2DQI can be adjusted through an internal test mode so that the data read by Read (AdrA) is precisely captured by Write (AdrB), that is, written to the second address.

[0159] In another possible implementation, the at least one read command may include a third read command and a fourth read command. Here, the second read command is sent twice to make up for the Figure 5 The at least one read command shown includes tWCK2DQO-tWCK2DQI in the third read command.

[0160] In the embodiment of the present disclosure, two read commands are issued consecutively, and the time interval between the two read commands (ie, the third read command and the fourth read command) is two clock cycles of the external clock to ensure that there is no gap between the two read data.

[0161] In the disclosed embodiment, nCK can be used to adjust the Loop data. Here, for the value of nCK, it is necessary to ensure that 0<=nCK+tWCK2DQI-tWCK2DQO<=2CK, so as to ensure that the data written by the Loop is the middle segment of the two data corresponding to the two read commands, so as to ensure that the second write command can just capture this segment of data.

[0162] In the embodiment of the present disclosure, the data written by the loop may be Figure 8 This is one of the 16 data topologies shown in the figure. It should be noted that the specific data topology is affected by factors such as the PVT corner; however, under the same conditions, the data topology read out over multiple loops should be consistent. It is important to note that the data written each time is determined by the simulation time tWCK2DQI - tWCK2DQO, which is dependent on the DRAM process, voltage, temperature, and other factors.

[0163] The present disclosure provides a testing method. The above embodiments illustrate the specific implementation of the aforementioned embodiments in detail. According to the technical solutions in the aforementioned embodiments, it can be seen that not only can the low-speed IO interface of the test machine be used to test the high-speed read and write functions of the DRAM, but the problem of the test machine being unable to cover the high-speed IO interface chip can also be solved. This improves the coverage of high-speed testing without affecting the chip area and normal read and write paths.

[0164] In yet another embodiment of the present disclosure, based on the same inventive concept as the above embodiment, Figure 10 This is a schematic diagram of the structure of a test device provided in an embodiment of the present disclosure. Figure 10 As shown, the testing device 100 may include a reading and writing unit 1001 and a determining unit 1002, wherein:

[0165] The read / write unit 1001 is configured to write first data to a first address of a chip under test via a first write command at a first clock frequency; send at least one first read command and a second write command to the chip under test at a second clock frequency, and the at least one first read command and the second write command meet a preset timing requirement, so that the chip under test writes the second data read from the first address back to the second address of the chip under test; wherein the first read command represents reading data from the first address, and the second write command represents writing data to the second address; and read third data from the second address via the second read command at a third clock frequency;

[0166] The determining unit 1002 is configured to determine a read / write test result of the chip under test according to the third data and the first data; wherein the first clock frequency and the third clock frequency are both lower than the second clock frequency.

[0167] In some embodiments, the at least one first read command includes a third read command. Accordingly, the at least one first read command and the second write command meet a preset timing requirement, including: a time interval between the third read command and the second write command meets a first timing requirement, so that the start time of the chip under test reading data from the first address and the start time of the chip under test writing data back to the second address are synchronized.

[0168] In some embodiments, the time interval between the third read command and the second write command meets the first timing requirement, including: the time interval between the third read command and the second write command is an integer multiple of a clock period of the external clock.

[0169] In some embodiments, the time interval between the third read command and the second write command meets the first timing requirement, including: the time interval between the third read command and the second write command is equal to RL-WL+tWCK2DQO-tWCK2DQI; wherein RL represents the read delay time of the third read command, WL represents the write delay time of the second write command, tWCK2DQI represents the delay time from the data clock to the data input, tWCK2DQO represents the delay time from the data clock to the data output, and tWCK2DQI and tWCK2DQI are adjusted through the test mode inside the chip to be tested.

[0170] In some embodiments, the at least one first read command includes a third read command and a fourth read command. Accordingly, the at least one first read command and the second write command meet a preset timing requirement, including: the time interval between the third read command and the fourth read command meets the second timing requirement, and the time interval between the third read command and the second write command meets the third timing requirement, so that the data written back to the second address by the chip under test is the middle portion of all the data read from the first address by the third read command and the fourth read command, respectively.

[0171] In some embodiments, the at least one first read command includes a third read command and a fourth read command. Accordingly, the read / write unit 1001 is further configured to write fourth data to a third address of the chip under test using the third write command at a first clock frequency; read data from the first address using the third read command and read data from the third address using the fourth read command at a second clock frequency; wherein the time interval between the third read command and the fourth read command meets the second timing requirement, and the time interval between the third read command and the second write command meets the third timing requirement, so that the data written back to the second address by the chip under test is the middle portion of all the data read from the first address and the third address by the third read command and the fourth read command, respectively.

[0172] In some embodiments, the time interval between the third read command and the fourth read command meets the second timing requirement, including: the time interval between the third read command and the fourth read command is two clock cycles of an external clock.

[0173] In some embodiments, the time interval between the third read command and the second write command satisfies a third timing requirement, including: the time interval between the third read command and the second write command is equal to RL-WL+nCK; wherein RL represents the read delay time of the third read command, WL represents the write delay time of the second write command, and nCK represents n clock cycles of the external clock, where n is an integer.

[0174] In some embodiments, the time interval between the third read command and the second write command satisfies the third timing requirement, and also includes: the sum of nCK and the preset duration is greater than or equal to 0 and less than or equal to 2CK, and 2CK represents 2 clock cycles of the external clock; wherein, the preset duration is tWCK2DQI-tWCK2DQO, tWCK2DQI represents the delay time from the data clock to the data input, and tWCK2DQO represents the delay time from the data clock to the data output.

[0175] In some embodiments, the determination unit 1002 is further configured to, when the third data and the first data are the same, determine that the read-write test result is that the read-write function test of the chip to be tested is normal; or, when the third data and the first data are different, determine that the read-write test result is that the read-write function test of the chip to be tested fails.

[0176] In some embodiments, the read-write unit 1001 is further configured to read data from the first address of the chip to be tested through a third read command and a fourth read command, or to read data from the first address and the third address of the chip to be tested respectively; to write the fifth data back to the second address of the chip to be tested through a second write command, and the fifth data is the middle part of all the data read by the third read command and the fourth read command; to read the third data from the second address through the second read command; to loop the steps of the third read command, the fourth read command, the second write command and the second read command to obtain the third data read multiple times; the determination unit 1002 is further configured to, when the third data read multiple times are consistent, determine that the read-write test result is that the read-write function test of the chip to be tested is normal; or, when there is inconsistency in the third data read multiple times, determine that the read-write test result is that the read-write function test of the chip to be tested fails.

[0177] In some embodiments, see Figure 10 The test device 100 further includes a sending unit 1003 configured to send a column address strobe command before the first clock frequency is switched to the second clock frequency, or before the second clock frequency is switched to the third clock frequency.

[0178] In some embodiments, see Figure 10 The test apparatus 100 further includes a holding unit 1004 configured to keep the input and output interfaces of the test device in a suspended state or a high-impedance state when sending a second write command to the chip under test at a second clock frequency.

[0179] It should be noted that the description of the above device embodiment is similar to the description of the aforementioned test method embodiment and has similar beneficial effects as the test method embodiment. For technical details not disclosed in the test device embodiment of the present disclosure, please refer to the description of the test method embodiment of the present disclosure for understanding.

[0180] In yet another embodiment of the present disclosure, Figure 11 This is a schematic diagram of the specific hardware structure of a test device provided in an embodiment of the present disclosure. Figure 11 As shown, the test device 110 may include: a communication interface 1101, a memory 1102, and a processor 1103; each component is coupled together via a bus system 1104. It is understood that the bus system 1104 is used to achieve connection and communication between these components. In addition to the data bus, the bus system 1104 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clarity, Figure 11 Various buses are labeled as bus system 1104. Among them, the communication interface 1101 is used to receive and send signals when sending and receiving information with other external network elements;

[0181] Memory 1102, used to store computer programs that can be run on processor 1103;

[0182] Processor 1103 is used to execute, when running the computer program: at a first clock frequency, write first data to a first address of a chip under test through a first write command; at a second clock frequency, send at least one first read command and a second write command to the chip under test, and at least one first read command and the second write command meet a preset timing requirement, so that the chip under test writes the second data read from the first address back to the second address of the chip under test; wherein the first read command represents reading data from the first address, and the second write command represents writing data to the second address; at a third clock frequency, read third data from the second address through a second read command; and determine the read and write test results of the chip under test based on the third data and the first data; wherein the first clock frequency and the third clock frequency are both lower than the second clock frequency.

[0183] It is understood that the memory 1102 in the embodiments of the present disclosure may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDRSDRAM), enhanced synchronous DRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DRRAM). The memory 1102 of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0184] The processor 1103 may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by hardware integrated logic circuits or software instructions in the processor 1103. The above-mentioned processor 1103 may be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The various methods, steps, and logic block diagrams disclosed in the embodiments of the present disclosure can be implemented or executed. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in conjunction with the embodiments of the present disclosure can be directly implemented and executed by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium mature in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, etc. The storage medium is located in the memory 1102 , and the processor 1103 reads the information in the memory 1102 and completes the steps of the above method in combination with its hardware.

[0185] It is understood that the embodiments described herein may be implemented using hardware, software, firmware, middleware, microcode, or a combination thereof. For hardware implementation, the processing unit may be implemented in one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers, microprocessors, other electronic units for performing the functions described in the present disclosure, or a combination thereof.

[0186] For software implementation, the techniques described herein can be implemented by modules (e.g., procedures, functions, etc.) that perform the functions described herein. The software code can be stored in a memory and executed by a processor. The memory can be implemented in the processor or external to the processor.

[0187] Optionally, as another embodiment, the processor 1103 is further configured to execute the steps of the testing method described in any one of the aforementioned embodiments when running the computer program.

[0188] In some embodiments, the present disclosure further provides a testing device 110 , which may include at least the testing apparatus 100 described in any one of the aforementioned embodiments.

[0189] It is understood that in the embodiments of the present disclosure, a "unit" can be a portion of a circuit, a portion of a processor, a portion of a program or software, etc., and can also be a module or a non-modular device. Moreover, the various components in the embodiments of the present disclosure can be integrated into a single processing unit, or each unit can exist physically separately, or two or more units can be integrated into a single unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional modules.

[0190] In the embodiments of the present disclosure, if the integrated unit is implemented in the form of a software functional module and is not sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiments of the present disclosure is essentially or the part that contributes to the existing technology or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, server, or network device, etc.) or a processor to execute all or part of the steps of the method described in the embodiments of the present disclosure. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, and other media that can store program code.

[0191] An embodiment of the present disclosure provides a computer-readable storage medium storing a computer program. When the computer program is executed by at least one processor, the steps of the testing method according to any one of the aforementioned embodiments are implemented.

[0192] An embodiment of the present disclosure further provides a computer program product, including a computer program or instructions, which implements the steps of the testing method as described in any one of the aforementioned embodiments when executed by a processor.

[0193] It should be noted that the descriptions of the above test device, storage medium, and program product embodiments are similar to the descriptions of the aforementioned test method embodiments, and have similar beneficial effects as the test method embodiments. For technical details not disclosed in the test device, storage medium, and program product embodiments of this disclosure, please refer to the descriptions of the test method embodiments of this disclosure for an understanding.

[0194] Those skilled in the art will appreciate that the embodiments of the present disclosure may be provided as methods, apparatuses, devices, or computer program products. Therefore, the present disclosure may take the form of hardware embodiments, software embodiments, or embodiments combining software and hardware. Furthermore, the present disclosure may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage and optical storage, etc.) containing computer-usable program code.

[0195] The present disclosure is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present disclosure. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0196] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0197] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0198] It should be noted that, in this disclosure, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, product, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, product, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, product, or apparatus comprising the element.

[0199] The serial numbers of the above-mentioned embodiments of the present disclosure are for description only and do not represent the advantages or disadvantages of the embodiments.

[0200] The methods disclosed in the several method embodiments provided in this disclosure may be arbitrarily combined, if not in conflict, to produce new method embodiments. The features disclosed in the several product embodiments provided in this disclosure may be arbitrarily combined, if not in conflict, to produce new product embodiments. The features disclosed in the several method or device embodiments provided in this disclosure may be arbitrarily combined, if not in conflict, to produce new method embodiments or device embodiments.

[0201] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present disclosure, and they should all be covered by the protection scope of the present disclosure.

Claims

1. A testing method, characterized in that: Applied to testing equipment, the testing method includes: At a first clock frequency, writing first data to a first address of the chip under test through a first write command; At a second clock frequency, at least one first read command and a second write command are sent to the chip under test, and a preset timing requirement is satisfied between the at least one first read command and the second write command, so that the chip under test writes the second data read from the first address back to the second address of the chip under test; wherein the first read command represents reading data from the first address, and the second write command represents writing data to the second address; reading third data from the second address using a second read command at a third clock frequency; and determining a read / write test result of the chip under test based on the third data and the first data; The first clock frequency and the third clock frequency are both lower than the second clock frequency.

2. The testing method according to claim 1, wherein: The at least one first read command includes a third read command; and the at least one first read command and the second write command meet a preset timing requirement, including: The time interval between the third read command and the second write command meets the first timing requirement, so that the start time of the chip under test reading data from the first address and the start time of the chip under test writing data back to the second address are synchronized.

3. The testing method according to claim 2, wherein: The time interval between the third read command and the second write command meets a first timing requirement, including: the time interval between the third read command and the second write command is an integer multiple of a clock period of an external clock.

4. The testing method according to claim 2, wherein: The time interval between the third read command and the second write command meets the first timing requirement, including: the time interval between the third read command and the second write command is equal to RL-WL+tWCK2DQO-tWCK2DQI; Among them, RL represents the read delay time of the third read command, WL represents the write delay time of the second write command, tWCK2DQI represents the delay time from the data clock to the data input, tWCK2DQO represents the delay time from the data clock to the data output, and tWCK2DQI and tWCK2DQI are adjusted by the test mode inside the chip to be tested.

5. The testing method according to claim 1, wherein: The at least one first read command includes a third read command and a fourth read command; and the at least one first read command and the second write command meet a preset timing requirement, including: The time interval between the third read command and the fourth read command meets the second timing requirement, and the time interval between the third read command and the second write command meets the third timing requirement, so that the data written back to the second address by the chip under test is the middle part of all the data read from the first address by the third read command and the fourth read command respectively.

6. The testing method according to claim 1, wherein: The at least one first read command includes a third read command and a fourth read command; and the testing method further includes: At the first clock frequency, writing fourth data to a third address of the chip under test through a third write command; At a second clock frequency, reading data from the first address by using the third read command, and reading data from the third address by using the fourth read command; Among them, the time interval between the third read command and the fourth read command meets the second timing requirement, and the time interval between the third read command and the second write command meets the third timing requirement, so that the data written back to the second address by the chip under test is the middle part of all the data read from the first address and the third address by the third read command and the fourth read command respectively.

7. The testing method according to claim 5 or 6, characterized in that: The time interval between the third read command and the fourth read command meets the second timing requirement, including: the time interval between the third read command and the fourth read command is two clock cycles of an external clock.

8. The testing method according to claim 5 or 6, characterized in that: The time interval between the third read command and the second write command meets a third timing requirement, including: the time interval between the third read command and the second write command is equal to RL-WL+nCK; Wherein, RL represents the read delay time of the third read command, WL represents the write delay time of the second write command, nCK represents n clock cycles of the external clock, and n is an integer.

9. The testing method according to claim 8, characterized in that: The time interval between the third read command and the second write command meets the third timing requirement, further comprising: a sum of nCK and a preset duration is greater than or equal to 0 and less than or equal to 2CK, and the 2CK represents two clock cycles of the external clock; The preset duration is tWCK2DQI-tWCK2DQO, tWCK2DQI represents the delay time from the data clock to the data input, and tWCK2DQO represents the delay time from the data clock to the data output.

10. The testing method according to claim 2, wherein: Determining the read / write test result of the chip under test according to the third data and the first data includes: In a case where the third data is identical to the first data, determining that the read / write test result indicates that the read / write function test of the chip under test is normal; or When the third data is different from the first data, it is determined that the read / write test result is a read / write function test failure of the chip under test.

11. The testing method according to claim 5 or 6, characterized in that: The step of determining the read and write test result of the chip under test further includes: Reading data from the first address of the chip under test or reading data from the first address and the third address of the chip under test respectively through the third read command and the fourth read command; Writing back fifth data to the second address of the chip under test through the second write command, the fifth data being a middle portion of all data read by the third read command and the fourth read command; reading third data from the second address by using the second read command; cyclically executing the steps of the third read command, the fourth read command, the second write command, and the second read command to obtain third data read multiple times; If the third data read multiple times are consistent, determining that the read / write test result is that the read / write function test of the chip under test is normal; or In a case where the third data read multiple times are inconsistent, it is determined that the read / write test result is a read / write function test failure of the chip to be tested.

12. The testing method according to any one of claims 1 to 11, characterized in that: The test method further comprises: Before the first clock frequency is switched to the second clock frequency, or before the second clock frequency is switched to the third clock frequency, a column address strobe command is sent.

13. The testing method according to any one of claims 1 to 11, characterized in that: At the second clock frequency, the testing method further includes: When sending the second write command to the chip under test, the input and output ports of the test device are kept in a suspended state or a high-impedance state.

14. A testing device, characterized in that: The testing device includes a reading and writing unit and a determining unit, wherein: The read / write unit is configured to write first data to a first address of a chip under test by a first write command at a first clock frequency; send at least one first read command and a second write command to the chip under test at a second clock frequency, and the at least one first read command and the second write command meet a preset timing requirement, so that the chip under test writes the second data read from the first address back to the second address of the chip under test; wherein the first read command represents reading data from the first address, and the second write command represents writing data to the second address; and read third data from the second address by a second read command at a third clock frequency; The determining unit is configured to determine a read / write test result of the chip under test according to the third data and the first data; The first clock frequency and the third clock frequency are both lower than the second clock frequency.

15. A testing device, characterized in that: The testing device includes a memory and a processor, wherein: The memory is used to store a computer program that can be run on the processor; The processor is configured to execute the testing method according to any one of claims 1 to 13 when running the computer program.

16. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the testing method according to any one of claims 1 to 13 is implemented.

17. A computer program product comprising a computer program or instructions, characterized in that When the computer program or instruction is executed by a processor, the testing method according to any one of claims 1 to 13 is implemented.

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