Gene data lookup table coding method and device based on in-memory calculation

Abstract

The invention provides a gene data lookup table coding method and device based on in-memory calculation. The method comprises the following steps: splitting three-dimensional lookup table data, and sequentially storing the split three-dimensional lookup table data into a plurality of SRAM (Static Random Access Memory) arrays; the method comprises the following steps: acquiring an input sequence of gene data with the length of L, and arranging the input sequence into L-2 triads (addr1, addr2, sym) according to the position of a symbol in the input sequence; determining a target array from the plurality of SRAM arrays according to addr1 in the triads, transmitting N triads to the target array of the triads at a time, and determining a to-be-searched data row from all data rows of the target array according to addr2 in the triads; three dimensions of the lookup table respectively correspond to three dimensions of an addr1 one-dimensional array, an addr2 one-dimensional array and a sym one-dimensional array; the target array completes comparison between all symbols of a data row to be searched and sym in the triple in a single period through a single-period byte search operation, and outputs a comparison result vector; and recording positions representing that the comparison results are the same in the comparison result vector to an output buffer area of the target array, and replacing symbols sym of the input sequence with the positions.

Description

Technical Field

[0001] The present invention relates to the technical field of genetic data compression acceleration based on in-SRAM computing in computer system structure design, and in particular to a genetic data lookup table encoding method, device, electronic device, computer-readable storage medium and computer program product based on in-SRAM computing, which are used to accelerate the lookup table encoding (LutC) in the MPEG-G genome data compression process. Background Art

[0002] With the rapid development of genome sequencing technology, the scale of genetic sequencing data is growing exponentially. Storage, transmission, and bandwidth costs have become major bottlenecks in genomic research and applications. The symbols in the genetic data input sequence represent descriptors generated by the MPEG-G genetic compression process, with a fixed bit width, such as 7 bits. Data compression is a common method to alleviate this bottleneck, especially with compression algorithms specifically designed for genetic data, such as the MPEG-G standard. MPEG-G offers higher compression ratios than general-purpose compression tools (such as GZIP), but its performance is relatively low. The LutC algorithm is a popular algorithm in the MPEG-G compression process. Its main function is to first access the corresponding data row in a lookup table using the address of the input symbol. Then, through comparison operations, it finds the unique location of the input symbol in the data row. This location is then used to replace the original symbol for encoding. This encoding method effectively improves the compression ratio of subsequent entropy coding.

[0003] Existing software solutions (such as multi-threaded CPU implementations) cannot fully exploit the high parallelism of the LutC algorithm. Other designs (such as GPU-based accelerators) struggle to effectively improve performance due to the algorithm's inherent low latency requirements. Furthermore, there's the significant energy consumption associated with data movement and computation. Therefore, a new acceleration solution is needed to improve the efficiency of the LutC algorithm. Summary of the Invention

[0004] The purpose of this invention is to provide a LutC algorithm optimization method based on in-memory computation. By performing an in-situ matching operation between the lookup table data stored in a static random access memory (SRAM) array and the input symbol sequence data, the occurrence position of each input symbol in the corresponding data row is found. This method significantly improves the performance of the LutC algorithm in the genetic data compression process by leveraging the inherent high parallelism and low latency characteristics within and between SRAM arrays. Furthermore, because computation and memory access operations are performed within the SRAM, eliminating the need for frequent data transfers to the CPU computing unit, LutC reduces latency and energy consumption.

[0005] Specifically, in view of the shortcomings of existing technologies, such as Figure 6As shown, the present invention proposes a gene data lookup table encoding method based on in-memory calculation, which is characterized by comprising:

[0006] A data arrangement step is to split the three-dimensional lookup table data and store them in multiple SRAM arrays in sequence;

[0007] An input sequence processing step is performed, wherein an input sequence of gene data having a length of L is obtained, and the input sequence is organized into L-2 triplets (addr1, addr2, sym) according to the positions of the symbols in the input sequence, where sym is the current i-th symbol to be encoded, addr1 is the i-2-th symbol, and addr2 is the i-1-th symbol; a target array is determined from the multiple SRAM arrays according to addr1 in the triplet, N triplets are transmitted at a time to the target array of the triplet, and a data row to be searched is determined from all data rows of the target array according to addr2 in the triplet; the three dimensions of the lookup table correspond to the three dimensions of the one-dimensional arrays of addr1, addr2, and sym, respectively;

[0008] In the symbol comparison step, the target array compares all symbols of the data row to be searched with the sym in the triplet in a single cycle through a single-cycle byte search operation, and outputs a comparison result vector;

[0009] The matching position recording step records the position in the comparison result vector representing the same comparison result to the output buffer of the target array, and uses the position to replace the symbol sym of the input sequence to obtain the encoding result of the gene data lookup table.

[0010] The genetic data lookup table encoding method based on in-memory calculation is characterized in that the data arrangement step includes: adopting a multiple copy strategy, or an array merging strategy, or a hybrid solution to store the three-dimensional lookup table data into multiple SRAM arrays;

[0011] The multi-copy strategy: splits the three-dimensional lookup table into multiple two-dimensional lookup tables according to its addr1 dimension. Each addr2 dimension of the two-dimensional lookup table corresponds to a row of the SRAM array, and each two-dimensional lookup table is stored in the corresponding SRAM array. The symbol distribution of the genetic data is calculated, and symbols with a symbol distribution higher than a threshold are selected as hotspot symbols addr1. The SRAM array corresponding to the hotspot symbol addr1 is used as the hotspot array, and the hotspot array is replicated. By increasing the number of hotspot arrays, the processing burden of the hotspot array is reduced.

[0012] The array merging strategy: Split the 3D lookup table into multiple 2D lookup tables according to the addr1 dimension of the 3D lookup table. These multiple 2D lookup tables are evenly divided and grouped and merged into each SRAM array (this reduces the number of SRAM arrays required). Then, each 2D lookup table in each group is stored in the corresponding SRAM array according to the multiple addr2 dimensions of each 2D lookup table.

[0013] This hybrid solution: statistics the symbol distribution of the genetic data, selects symbols with symbol distribution higher than the threshold as hot spot symbols addr1, and uses the lookup table corresponding to the hot spot symbol addr1 as the hot spot table; according to the addr1 dimension of the three-dimensional lookup table, the three-dimensional lookup table is split into multiple two-dimensional lookup tables, and the two-dimensional lookup tables corresponding to the hot spot symbol addr1 are evenly divided and grouped and merged into each SRAM array. At the same time, through scheduling, each hot spot table is allocated to a different SRAM array, and then each two-dimensional lookup table is stored in the corresponding SRAM array according to the multiple addr2 dimensions of each two-dimensional lookup table in each group corresponding to a column of the SRAM array (compared with the array merging strategy, the rows and columns are transposed).

[0014] The genetic data lookup table encoding method based on in-memory calculation is characterized in that each symbol in the input sequence is of fixed length.

[0015] like Figure 7 As shown, the present invention also proposes a gene data lookup table encoding device based on in-memory calculation, which is characterized by comprising:

[0016] The data arrangement module splits the three-dimensional lookup table data and stores them in multiple SRAM arrays in sequence;

[0017] An input sequence processing module obtains an input sequence of genetic data of length NL, and organizes the input sequence into L-2 triplets (addr1, addr2, sym) according to the positions of the symbols in the input sequence, where sym is the current i-th symbol to be encoded, addr1 is the i-2-th symbol, and addr2 is the i-1-th symbol; a target array is determined from the multiple SRAM arrays according to addr1 in the triplet, N triplets are transmitted to the target array of the triplet at a time, and a data row to be searched is determined from all data rows of the target array according to addr2 in the triplet; the three dimensions of the lookup table correspond to the three dimensions of the one-dimensional arrays of addr1, addr2, and sym, respectively;

[0018] The symbol comparison module compares all symbols of the data row to be searched with the sym in the triplet in a single cycle through a single-cycle byte search operation, and outputs a comparison result vector;

[0019] The matching position recording module records the position in the comparison result vector representing the same comparison result to the output buffer of the target array, and uses the position to replace the symbol sym of the input sequence to obtain the encoding result of the gene data lookup table.

[0020] The genetic data lookup table encoding device based on in-memory calculation is characterized in that the data arrangement module is used to: adopt a multi-copy strategy, or an array merging strategy, or a hybrid solution to store the three-dimensional lookup table data into multiple SRAM arrays;

[0021] The multi-copy strategy: splits the three-dimensional lookup table into multiple two-dimensional lookup tables according to its addr1 dimension. Each addr2 dimension of the two-dimensional lookup table corresponds to a row of the SRAM array, and each two-dimensional lookup table is stored in the corresponding SRAM array. The symbol distribution of the genetic data is calculated, and symbols with a symbol distribution higher than a threshold are selected as hotspot symbols addr1. The SRAM array corresponding to the hotspot symbol addr1 is used as the hotspot array, and the hotspot array is replicated. By increasing the number of hotspot arrays, the processing burden of the hotspot array is reduced.

[0022] The array merging strategy: Split the 3D lookup table into multiple 2D lookup tables according to the addr1 dimension of the 3D lookup table. These multiple 2D lookup tables are evenly divided and grouped and merged into each SRAM array (this reduces the number of SRAM arrays required). Then, each 2D lookup table in each group is stored in the corresponding SRAM array according to the multiple addr2 dimensions of each 2D lookup table.

[0023] This hybrid solution: statistics the symbol distribution of the genetic data, selects symbols with symbol distribution higher than the threshold as hot spot symbols addr1, and uses the lookup table corresponding to the hot spot symbol addr1 as the hot spot table; according to the addr1 dimension of the three-dimensional lookup table, the three-dimensional lookup table is split into multiple two-dimensional lookup tables, and the two-dimensional lookup tables corresponding to the hot spot symbol addr1 are evenly divided and grouped and merged into each SRAM array. At the same time, through scheduling, each hot spot table is allocated to a different SRAM array, and then each two-dimensional lookup table is stored in the corresponding SRAM array according to the multiple addr2 dimensions of each two-dimensional lookup table in each group corresponding to a column of the SRAM array (compared with the array merging strategy, the rows and columns are transposed).

[0024] The genetic data lookup table encoding device based on in-memory calculation is characterized in that each symbol in the input sequence is of fixed length.

[0025] The present invention also proposes a client for use with any of the above-mentioned gene data lookup table encoding devices based on in-memory calculation.

[0026] The present invention also proposes an electronic device, characterized in that it includes the aforementioned genetic data lookup table encoding device based on in-memory calculation, and the electronic device may be connected to an information display device, which is used to display the genetic data lookup table encoding results using display parameters and attributes set by the user or through an artificial intelligence model.

[0027] The present invention also proposes a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the genetic data lookup table encoding method based on in-memory calculation are implemented.

[0028] The present invention also proposes a computer program product, including a computer program, characterized in that when the computer program is executed by a processor, the steps of the genetic data lookup table encoding method based on in-memory calculation are implemented.

[0029] From the above scheme, it can be seen that the advantages of the present invention are:

[0030] 1. High throughput: By fully utilizing the parallel computing capabilities of the SRAM array, adopting a multi-issue design, and solving the load balancing problem, the execution throughput of the LutC algorithm is significantly improved.

[0031] 2. Low latency: Since calculations are performed directly in SRAM, the delay in data movement is reduced, and an early stopping mechanism is adopted to reduce the number of calculation operations, the execution delay of the algorithm is significantly reduced.

[0032] 3. Low power consumption: Due to the reduction in data movement (reduced communication energy consumption) and the integrated storage and computing characteristics of In-SRAM design (reduced computing energy consumption), compared with traditional CPU software solutions, the power consumption of this invention is significantly reduced under the same task.

[0033] 4. High resource utilization: By adopting array merging strategy or scheduling array merging strategy, the utilization of SRAM array is significantly improved, reducing the waste of hardware resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 :Basic pseudocode presentation of In-SRAM LutC optimization algorithm.

[0035] Figure 2 : Three arrangements of lookup table data within the SRAM array.

[0036] Figure 3 : Four ways to arrange lookup table data among multiple SRAMs.

[0037] Figure 4 : Distribution of LutC input symbol values ​​in the gene compression process.

[0038] Figure 5 : Figure 3 -I data block in Figure 3 -Mapping rules in IV (from oldID to newID).

[0039] Figure 6 Flow chart of the method of the present invention;

[0040] Figure 7 This is a module diagram of the device of the present invention;

[0041] Figure 8 This is a schematic structural diagram of a first electronic device of the present invention;

[0042] Figure 9 This is a schematic diagram of the application environment structure of the first electronic device of the present invention;

[0043] Figure 10 This is a schematic structural diagram of a second electronic device according to the present invention.

[0044] Reference numerals:

[0045] A-First electronic device;

[0046] B-Gene data lookup table encoding device based on in-memory calculation;

[0047] C-data acquisition equipment;

[0048] D-information display device;

[0049] 1000- second electronic device;

[0050] Ⅰ-computing unit;

[0051] II-ROM;

[0052] III-RAM;

[0053] IV-bus;

[0054] V-interface;

[0055] VI-input unit;

[0056] VII-output unit;

[0057] VIII-Storage medium;

[0058] IX-Communication unit. DETAILED DESCRIPTION

[0059] It should be noted that, in this application, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus.

[0060] Without further constraints, an element defined by the phrase "comprises a..." does not preclude the existence of additional identical elements in the process, method, article or apparatus that includes the element.

[0061] The processor described in the present invention is the control center of an electronic device and can be a single processor or a collective term for multiple processing elements. For example, it can be one or more central processing units (CPUs), an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present invention, such as one or more digital signal processors (DSPs) or one or more field programmable gate arrays (FPGAs).

[0062] Optionally, the processor can perform various functions of the electronic device by running or executing a software program stored in the memory, and calling data stored in the memory.

[0063] In a specific implementation, as an embodiment, the processor may include one or more CPUs. Each of these processors may be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). The processor here may refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions). Electronic devices may include: servers, desktop computers, laptops, smartphones, tablet computers, embedded computers, etc., wherein the embedded computers include vehicles and robots, etc.

[0064] The memory is used to store the software program for executing the solution of the present invention, and the execution is controlled by the processor. The specific implementation method can refer to the above method embodiment and will not be repeated here.

[0065] It should be noted that the structure of the electronic device shown in the drawings of the present invention does not constitute a limitation thereto, and the actual knowledge structure recognition device may include more or fewer components than shown in the drawings, or a combination of certain components, or a different arrangement of components.

[0066] The above embodiments can be implemented in whole or in part through software, hardware (such as circuits), firmware, or any other combination. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer program are loaded or executed on a computer, the processes or functions described in accordance with the embodiments of the present invention are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via a wired method (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains a collection of one or more available media. The available medium can be a magnetic medium (such as a floppy disk, hard disk, or magnetic tape), an optical medium (such as a DVD), or a semiconductor medium. The semiconductor medium can be a solid-state drive.

[0067] It should also be understood that the term "and / or" in this document simply describes an association between related objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A alone, A and B together, or B alone. A and B can be singular or plural. Furthermore, the character " / " in this document generally indicates an "or" relationship between the related objects, but it may also indicate an "and / or" relationship. For specific understanding, please refer to the context.

[0068] In this disclosure, "at least one" means one or more, and "plurality" means two or more. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, "at least one of a, b, or c" can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or plural.

[0069] It should also be understood that in various embodiments of the present invention, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0070] In the several embodiments provided by the present invention, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interface, indirect coupling or communication connection of the device or unit, which can be electrical, mechanical or other forms.

[0071] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0072] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0073] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0074] To achieve the above technical effects, the present invention proposes a LutC acceleration solution based on In-SRAM computing, which specifically includes the following core technical contents:

[0075] 1. Unified guide design: The In-SRAM LutC algorithm design of the present invention is kept as unified as possible with the In-SRAM MatchC algorithm to improve resource utilization. Specifically, the present invention reuses the single-cycle byte search OneCycleByteSearch for symbol search in the lookup table, and the position search FindPos for matching position search. Figure 2 The position of '1' in the result vector (RV) at the bottom (red font). The result vector is obtained by OneCycleByteSearch in one cycle. Since the repeated sym in the lookup table has been eliminated before, there will only be one '1' in a result vector.

[0076] For example, if the one-dimensional symbol array corresponding to addr1=0 and addr2=1 is 0011233, the array after deduplication is 0123. When implementing the software, the value of the symbol can be directly used as its storage address, that is, a[i]=i. In this way, the same symbol will be overwritten when traversing the symbol array to achieve deduplication. At the same time, the number of times each symbol is overwritten is recorded, and then the one-dimensional array after deduplication is sorted from most to least according to the number of times, thus completing the construction of the lookup table. It is worth noting that this is an operation in the process of building the lookup table, and the purpose of this application is to speed up the process of searching the lookup table. The constructed lookup table has been obtained by default before the search begins (because the time for building the lookup table is relatively small and the lookup table can be reused under certain conditions).

[0077] The two atomic operations, OneCycleByteSearch and FindPos, are already defined in the In-SRAM MatchC algorithm. Furthermore, In-SRAM LutC inherits the SRAM array dimension constraints from the MatchC optimization design, namely Sx8 rows and Sx2 columns (where S is the sliding window size). By adopting this unified, guided design, the present invention can switch between the functionality of the two algorithms with only minor software adjustments, including the number of SRAM arrays, data format definition, data arrangement, and search execution mechanism, without requiring additional hardware changes. The lookup table is pre-obtained, and its theoretical size can be 128x128x128 symbols, corresponding to the three dimensions of the addr1, addr2, and sym one-dimensional arrays.

[0078] 2. Data format definition: The present invention defines the input data of In-SRAM LutC as a tuple sequence Tuple(addr1, addr2, sym) containing a 7-bit symbol (sym) and its first two symbols (addr1, addr2). The number of bits of symbol sym is not limited to 7 bits, and those skilled in the art can set it according to actual needs. LutC uses addr1 and addr2 of the input symbol to index its data row (table[addr1][addr2]) and uses the above two atomic operations to find the unique matching position (pos);

[0079] For example, if the input sequence is 11231..., the first triple is (1,1,2), the second is (1,2,3), and the third is (2,3,1). LutC algorithm: For the current triple, first use addr1 and addr2 to jointly index into a one-dimensional array with a maximum length of 128 symbols. Then, search for the position of the symbol that matches sym in this array and replace sym with that position.

[0080] The function of addr1 is to index the SRAM number, and the function of addr2 is to index the row in the SRAM. Figure 2 There are three distributions of the lookup table inside the SRAM array. Figure 3 To find out the four distributions of table data among multiple SRAM arrays, the present invention provides four combination schemes;

[0081] Figure 3 The number of blocks in the image is the number of SRAM arrays, the number in the block is addr1, and the color is the degree of load burden. It should be noted that addr1, addr2 and sym are essentially the same, all come from the input sequence and are adjacent symbols in the input sequence.

[0082] In the multi-copy strategy, the hotspot symbol is both hotspot addr1, hotspot addr2, and hotspot sym. The SRAM array corresponding to hotspot addr1 is the hotspot array ( Figure 3 -I red), instead of an array with a hotspot symbol, after using the multi-copy strategy, the load burden of the hotspot array becomes lighter ( Figure 3 -I red becomes lighter);

[0083] In the array merging strategy, the correct understanding is that the two-dimensional lookup tables corresponding to multiple addr1s are merged into the same SRAM array ( Figure 2 -II Figure 3 -III shows that the eight two-dimensional lookup tables with addr1 values ​​from 0 to 7 are merged into the first array, and then multiple one-dimensional lookup tables corresponding to addr2 are mapped to the same row;

[0084] The changes in the hybrid solution are shown in blue. The key points of this solution are: 1. Storing multiple two-dimensional lookup tables corresponding to addr1 in the same SRAM array; 2. Identifying the two-dimensional lookup tables corresponding to hotspot addr1 and storing them in a distributed manner; 3. Transposing the rows and columns and changing the one-dimensional lookup tables corresponding to addr2 to column-by-column storage to achieve greater parallelism.

[0085] 3. Multi-issue execution mechanism: In each iteration, a single input tuple (addr1, addr2, sym) is first directed to the corresponding symbol row based on its addr1 and addr2. Then, a single-cycle byte search (OneCycleByteSearch) is used to find the position in the row that matches the symbol (sym) within one cycle, and the position information is output. Since there is no data dependency between the search tasks for multiple input tuples, this means that in theory, multiple tuples can be processed simultaneously in a single iteration - this enables multi-issue execution, assuming the number of multi-issue tasks is N. However, due to hardware limitations, each SRAM array can only process one tuple per cycle. If multiple tuples share the same addr1, they must wait. In the best case, if there are M SRAM arrays, up to M tuples can be processed in parallel in one cycle.

[0086] 4. Basic Data Arrangement: The main process of LutC is to use the two addresses of the input symbol (addr1 and addr2) to index the corresponding data row and find the unique position where the input symbol appears in the row. Therefore, the SRAM must store a three-dimensional lookup table. The present invention naturally uses the organizational structure of the SRAM to store this table in a hierarchical manner. addr1 is used as an index between different SRAM arrays, while addr2 is used as an index for different data rows within each SRAM array. In addition, the bit planes of each symbol are stored in rows, and different symbols are arranged in columns. The bit planes are a set of the same bits of different symbols. For example, the first bit plane of the two binary numbers '11' and '01' is '10', and the second bit plane is '11'. The symbol width is 7 bits, so the range of addr1 and addr2 is [0,127]. This design will bring two problems: Problem 1: The SRAM area overhead is too large, and Problem 2: The load between SRAM arrays is unbalanced. To address these two problems, the present invention provides the following three optimized data arrangement solutions: Multi-Copies Strategy (MCS), Array-Combined Strategy (ACS), and a hybrid solution: Scheduled Array-Combined Strategy (Hybrid).

[0087] 5. Number of SRAM arrays: Since the lookup table is a three-dimensional array, the first two dimensions are indexed by addr, corresponding to differently numbered SRAM arrays and different data rows within the same array. Therefore, the number of SRAM arrays is multiple, unlike MatchC, which only requires one. The data in the lookup table is distributed across multiple SRAM arrays based on addr1. In the 7-bit case, solution 1 is distributed across 128 SRAM arrays (i.e., addr1 and array have a one-to-one correspondence), solution 2 is distributed across 144 arrays (copying the heavily loaded data), and solutions 3 and 4 are both distributed across 16 arrays (merging data from multiple arrays into one).

[0088] To illustrate the above-mentioned features and effects of the present invention more clearly and easily, the following embodiments are specifically described below with reference to the accompanying drawings. This specification discloses one or more embodiments incorporating the features of the present invention. The disclosed embodiments are for illustrative purposes only. The scope of protection of the present invention is not limited to the disclosed embodiments; the present invention is defined by the appended claims.

[0089] The specific implementation of the present invention is as follows (S is 256, M is 128, and N is 16):

[0090] 1. Initialization phase

[0091] Basic data arrangement: such as Figure 2 -I and Figure 3 As shown in Figure 1-1, addr1 is used as an index between different SRAM arrays, while addr2 is used as an index to different data rows within each SRAM array. Furthermore, the bit planes of each symbol are stored in rows, with different symbols arranged in columns. Since the symbol width is 7 bits, both addr1 and addr2 range from [0, 127]. This means there are 128 SRAM arrays, each with 128 lookup table rows, and each row containing 128 7-bit symbols. Each symbol is arranged in rows within its own column, occupying 7 rows.

[0092] This design will bring two problems.

[0093] Problem 1: SRAM area overhead is too large. Due to the highly parallel multi-layer memory layout design, a large number of SRAM arrays are required, specifically 128 arrays (because sym is 7 bits and the value range is 0 to 127). To make matters worse, for the sake of unified design, the size of the SRAM array is set to 256x8 rows and 256x2 columns, but LutC's lookup table only occupies a small part of each SRAM array, with a utilization rate of only 12.5%, which exacerbates the area overhead problem. Figure 2 -I shown.

[0094] Problem 2: Unbalanced load between SRAM arrays. Despite the adoption of a multi-transmit design, the number of tuples received by each SRAM array is extremely unbalanced, resulting in a significant performance degradation due to the delay of a few overloaded SRAM arrays. This imbalance occurs because most of LutC's input symbols come from the quality scores in the gene sequencing Fastq file, rather than from the intermediate descriptors and some other metadata generated by the base sequence (Seq) field in the Fastq file. These quality scores usually follow the following formula: Figure 4 As shown in the distribution. Since addr1, addr2 and sym in the tuple all follow this distribution, the possibility of conflict within the same iteration is quite high. That is, in the descriptors (input symbols) generated by the genetic data, Figure 4 It can be seen that a large number of descriptors are concentrated in the range of 28 to 43. If the one-to-one mapping method in the basic solution is adopted, the load of the 28th to 43rd SRAM arrays will be significantly heavier than that of other arrays.

[0095] In order to address these two problems, the present invention proposes three optimized data arrangement schemes in addition to the basic arrangement strategy.

[0096] Option 1 is the basic arrangement strategy, that is Figure 2 -I and Figure 3 The disadvantage of the -I combination is that the space utilization rate inside the SRAM array is low (the gray area with no valid data accounts for a high proportion), and the load between the SRAM arrays is very unbalanced. This is because the probability of addr1 being 28 to 43 is very high (a characteristic of genetic data), and the probability of indexing the corresponding SRAM array during parallel search is naturally also high. For example, Figure 3 - As shown in I, red represents heavy load burden;

[0097] Three optimized data layout solutions:

[0098] Solution 2 Multi-copy strategy (MCS): Figure 3 As shown in Figure 2-II, this method replicates 16 hotspot SRAM arrays based on data distribution. Although this strategy can alleviate Problem 2 by distributing the tasks of K hotspot arrays into 32 arrays, it exacerbates Problem 1 due to the increase in the total number of SRAM arrays.

[0099] This solution can alleviate the load imbalance problem because addr1 in the range of 28 to 43 can index both the original array and the replica array. This reduces the array load burden and makes the red color fade. However, this strategy does not solve the problem of internal utilization of the SRAM array and requires increasing the number of SRAM arrays.

[0100] Array Merge Strategy (ACS): Option 3, such as Figure 2-II, the present invention merges the lookup table data originally distributed in too many arrays into fewer arrays. This strategy overcomes problem 1 by filling each array with valid data, but it exacerbates problem 2 ( Figure 3 -III).

[0101] Solution 3 is the array merging strategy, namely Figure 2 -II and Figure 3 -III combination, merge the lookup table data in multiple arrays into one array, fill Figure 2 The gray part in -I will make multiple addr1 index into the same SRAM array. The main method is to change the original one addr2 corresponding to one row of the SRAM array to multiple addr2 corresponding to one row, such as Figure 2 -II, 4 addr2s correspond to one row. This solution can significantly improve the space utilization inside the SRAM array (almost no gray part) and reduce the number of SRAM arrays. Figure 3 As shown in Scheme 3-III, the number of addr1s is reduced from 128 in the basic scheme to 16. However, this strategy increases the probability that multiple addr1s will be indexed into the same SRAM array in parallel, thereby increasing the load on each array. The search process is basically the same as in Schemes 1 and 2, except that the mapping between addr1 and the SRAM array must be calculated. If multiple addr2s are mapped to the same row in the same array, the search can be performed simultaneously and the results obtained.

[0102] Solution 4: Hybrid solution - scheduling array merging strategy: Figure 2 -III and Figure 3 -IV combination uses the merging method in solution 3, but instead of simply merging in sequence, it disperses the lookup table data of the original hotspot array into different new arrays, such as Figure 3 As shown in Figure -IV, the bold numbers 28 to 43 are distributed to different SRAM arrays. This can reduce the load burden on each array. The search process is basically the same as the previous solution, except that it is transposed. If multiple addr2s are mapped to the same column of the same array, they can be searched and the results obtained at the same time. In addition, the data in the original SRAM array number (oldID) will be replaced by the data in the new array number (newID). The mapping relationship is as follows: Figure 5 shown.

[0103] (i) Utilize the row-level parallelism within the SRAM array. For problem 1, the present invention first inherits the merging method of ACS. However, the present invention utilizes the row-level parallelism within each SRAM array to compensate for the loss of parallelism. Specifically, when multiple input tuples share the same addr1 and sym, and the value of addr2 is in the range of [4N, 4(N+1)-1], they can be processed in parallel, that is, a single-cycle search is performed on four addr2s in the same row, as shown in Figure 2. Figure 2 -II.

[0104] (ii) Rearrange the data in the array. Then, the present invention re-arranges the 16 hotspot addr1 data blocks (such as Figure 3 -I) are distributed into 16 SRAM arrays (as shown in Figure 3 -IV), follow Figure 5 The old address and new address mapping rules described in the formula are used to alleviate the workload imbalance problem.

[0105] (iii) Array Transposition. To further enhance the parallelism within the SRAM array, the present invention transposes the array by swapping rows and columns (e.g., Figure 2 -III), increasing the parallelism of each SRAM array from 4 (rows) to 16 (columns), further improving performance.

[0106] Option 4: Hybrid solution, i.e. Figure 2 -III and Figure 3 -IV combination, this scheme has three key points: (i) using the third strategy, only 16 arrays are needed; (ii) addr1 (28 to 43) with high probability of occurrence is distributed to each array, such as Figure 3 - As shown in the numbers in the IV blocks, the load burden (iii) is reduced as Figure 2 -III, the original 4 addr2s corresponding to one row are changed to 16 addr2s corresponding to one column to obtain greater addr2 search parallelism.

[0107] Each triplet first uses addr1 to determine which SRAM array to search next. Each SRAM array can only process a limited number of search requests for different addr2 in one cycle. Schemes 1 and 2 can only process a maximum of 1 (only 1 addr2 in the same row), scheme 3 can process a maximum of 4 (4 addr2 in the same row), and scheme 4 can process a maximum of 16 (16 addr2 in the same column). When the limit is exceeded, other parallel search requests must wait until the corresponding array is processed before they can be responded to.

[0108] 2. Search process

[0109] The core of the LutC algorithm of the present invention is to find the position of each input symbol in the corresponding data row by performing in-situ matching operations on the lookup table data stored in the SRAM array and the input symbol sequence data. The In-SRAM optimized LutC can process N search encoding tasks in parallel and find the position of the symbol in each task in the data row within one shot. Figure 1 The specific steps are as follows:

[0110] Input sequence processing: The input sequence is organized into triples of Tuple (addr1, addr2, sym), and N such triples are emitted at a time. Based on addr1 and addr2 in each triple, the row in the SRAM array is determined as the data row to be searched.

[0111] Symbol comparison: sym compares all the symbols (bytes) of the above data row in a single cycle through the OneCycleByteSearch operation and outputs a matching result vector RV (1 indicates a match, 0 indicates a mismatch).

[0112] Match result processing: The FindPos operation searches for the rightmost 1 in each result vector to determine the matching position. The FindPos operation is implemented using a tree-like combinational logic circuit, which can complete the position search in a single cycle.

[0113] Match position record: record the matching position (pos) and write the result to the output buffer (an SRAM array specifically used to store output results). Use this position to replace the original input symbol (sym) as the encoded output and write it to DRAM.

[0114] To sum up, the lookup table of the present invention can be abstracted as a three-dimensional array. The first two dimensions are determined by addr1 and addr2 in the input symbol sequence triplet. Sym is stored in the third dimension and sorted from high to low according to the frequency of sym, and repeated sym is eliminated. Therefore, the address (position) of sym with high frequency of occurrence is smaller, and there are many repeated sym in the input symbol sequence. Most of the positions obtained by looking up the table will be concentrated in a very small range close to 0. Such position data is more suitable for entropy coding than the original symbol sequence data; the lookup table in the present invention is obtained in advance and is fixed during the lookup process. It is a prerequisite and is not included in the design. This application involves the accelerated design of the lookup process.

[0115] The following is a system embodiment corresponding to the above method embodiment. This embodiment can be implemented in conjunction with the above embodiment. The relevant technical details mentioned in the above embodiment are still valid in this embodiment and will not be repeated here to reduce repetition. Accordingly, the relevant technical details mentioned in this embodiment can also be applied to the above embodiment.

[0116] like Figure 7 As shown, the present invention also proposes a gene data lookup table encoding device based on in-memory calculation, which is characterized by comprising:

[0117] The data arrangement module splits the three-dimensional lookup table data and stores them in multiple SRAM arrays in sequence;

[0118] An input sequence processing module obtains an input sequence of genetic data of length NL, and organizes the input sequence into L-2 triplets (addr1, addr2, sym) according to the positions of the symbols in the input sequence, where sym is the current i-th symbol to be encoded, addr1 is the i-2-th symbol, and addr2 is the i-1-th symbol; a target array is determined from the multiple SRAM arrays according to addr1 in the triplet, N triplets are transmitted to the target array of the triplet at a time, and a data row to be searched is determined from all data rows of the target array according to addr2 in the triplet; the three dimensions of the lookup table correspond to the three dimensions of the one-dimensional arrays of addr1, addr2, and sym, respectively;

[0119] The symbol comparison module compares all symbols of the data row to be searched with the sym in the triplet in a single cycle through a single-cycle byte search operation, and outputs a comparison result vector;

[0120] The matching position recording module records the position in the comparison result vector representing the same comparison result to the output buffer of the target array, and uses the position to replace the symbol sym of the input sequence to obtain the encoding result of the gene data lookup table.

[0121] The genetic data lookup table encoding device based on in-memory calculation is characterized in that the data arrangement module is used to: adopt a multi-copy strategy, or an array merging strategy, or a hybrid solution to store the three-dimensional lookup table data into multiple SRAM arrays;

[0122] The multi-copy strategy: splits the three-dimensional lookup table into multiple two-dimensional lookup tables according to its addr1 dimension. Each addr2 dimension of the two-dimensional lookup table corresponds to a row of the SRAM array, and each two-dimensional lookup table is stored in the corresponding SRAM array. The symbol distribution of the genetic data is calculated, and symbols with a symbol distribution higher than a threshold are selected as hotspot symbols addr1. The SRAM array corresponding to the hotspot symbol addr1 is used as the hotspot array, and the hotspot array is replicated. By increasing the number of hotspot arrays, the processing burden of the hotspot array is reduced.

[0123] The array merging strategy: Split the 3D lookup table into multiple 2D lookup tables according to the addr1 dimension of the 3D lookup table. These multiple 2D lookup tables are evenly divided and grouped and merged into each SRAM array (this reduces the number of SRAM arrays required). Then, each 2D lookup table in each group is stored in the corresponding SRAM array according to the multiple addr2 dimensions of each 2D lookup table.

[0124] This hybrid solution: statistics the symbol distribution of the genetic data, selects symbols with symbol distribution higher than the threshold as hot spot symbols addr1, and uses the lookup table corresponding to the hot spot symbol addr1 as the hot spot table; according to the addr1 dimension of the three-dimensional lookup table, the three-dimensional lookup table is split into multiple two-dimensional lookup tables, and the two-dimensional lookup tables corresponding to the hot spot symbol addr1 are evenly divided and grouped and merged into each SRAM array. At the same time, through scheduling, each hot spot table is allocated to a different SRAM array, and then each two-dimensional lookup table is stored in the corresponding SRAM array according to the multiple addr2 dimensions of each two-dimensional lookup table in each group corresponding to a column of the SRAM array (compared with the array merging strategy, the rows and columns are transposed).

[0125] The genetic data lookup table encoding device based on in-memory calculation is characterized in that each symbol in the input sequence is of fixed length.

[0126] The present invention also proposes a client for use with any of the above-mentioned gene data lookup table encoding devices based on in-memory calculation.

[0127] like Figure 7 As shown, the present invention further proposes, in another embodiment, a first electronic device A including the aforementioned gene data lookup table encoding device based on in-memory calculation.

[0128] like Figure 8 As shown, the first electronic device A can also be connected to the data acquisition device C and the information display device D through a wired or wireless information transmission scheme. The data acquisition device C is used to collect and obtain videos to be identified and classified, such as the sorting videos described in the embodiment of the present invention, and the information display device D is used to display the video classification results obtained by the analysis of the present invention.

[0129] The information display device D can organize and process the data output by the first electronic device A based on the information display mechanism to improve the readability of the data output by the first electronic device A. The information display mechanism can be manually preset, for example, the data output by the first electronic device A is visually displayed, which can be based on the display parameters and / or attributes set by the user. The display parameters can be, for example, the display data range, and the display attributes can be, for example, the display font, color, whether to scroll, etc. The user is presented with the key information specified by the user, and the user can understand this information more promptly without having to access the secondary page or scroll the page, saving the user's operation. Or the information display mechanism can be an artificial intelligence AI display model, which can learn the user's key information based on the user's previous usage habits, such as viewing time, number of clicks, number of edits, etc., and then automatically present the user with rich and necessary key information.

[0130] The present invention also provides a computer program product, which includes a computer program. The computer program can be stored on a readable storage medium. When the computer program is executed by a processor, the computer can execute the genetic data lookup table encoding method based on in-memory calculation provided by the above methods.

[0131] In another embodiment, the present invention further proposes a storage medium VIII for storing a computer program for executing the genetic data lookup table encoding method based on in-memory calculation. It should be understood that the storage medium in the embodiment of the present invention can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM), and direct RAM bus RAM (DR RAM).

[0132] Figure 10 A schematic block diagram of a second electronic device 1000 that can be used to implement an embodiment of the present invention is shown. The second electronic device 1000 electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The second electronic device 1000 can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein. The second electronic device 1000 may be the same as or different from the first electronic device A.

[0133] The second electronic device 1000 includes a computing unit I, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory II (ROM) or a computer program loaded from a storage medium VIII into a random access memory (RAM) III. Various programs and data required for the operation of the device 1000 can also be stored in the RAM III. The computing unit I, ROM II, and RAM III are connected to each other via a bus IV. An input / output (I / O) interface V is also connected to the bus IV.

[0134] Multiple components in the second electronic device 1000 are connected to the I / O interface V, including: an input unit VI, such as a keyboard and mouse; an output unit VII, such as various types of displays and speakers; a storage medium VIII, such as a magnetic disk and optical disk; and a communication unit IX, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit IX allows the second electronic device 1000 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0135] Computing unit I can be various general and / or special processing components with processing and computing capabilities. Some examples of computing unit I include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units that run machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. Computing unit I performs the various methods and processes described above, such as method steps S1-S4. For example, in some embodiments, the method can be implemented as a computer software program that is tangibly contained in a machine-readable medium, such as a storage medium VIII. In some embodiments, part or all of the computer program can be loaded and / or installed on the device 1000 via ROM II and / or communication unit IX. When the computer program is loaded into RAM III and executed by computing unit I, one or more steps of the method described above can be performed. Alternatively, in other embodiments, computing unit I can be configured to execute the method in any other appropriate manner (e.g., by means of firmware).

[0136] Although the embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the description and implementation methods. They can be fully applied to various fields suitable for the present invention. For those familiar with the art, additional modifications can be easily implemented. Therefore, without departing from the general concept defined by the claims and the scope of equivalents, the present invention is not limited to the specific details and illustrations shown and described herein.

Claims

1. A gene data lookup table encoding method based on in-memory calculation, characterized in that: include: A data arrangement step is to split the three-dimensional lookup table data and store them in multiple SRAM arrays in sequence; An input sequence processing step is performed, wherein an input sequence of gene data having a length of L is obtained, and the input sequence is organized into L-2 triplets (addr1, addr2, sym) according to the positions of the symbols in the input sequence, where sym is the current i-th symbol to be encoded, addr1 is the i-2-th symbol, and addr2 is the i-1-th symbol; a target array is determined from the multiple SRAM arrays according to addr1 in the triplet, N triplets are transmitted at a time to the target array of the triplet, and a data row to be searched is determined from all data rows of the target array according to addr2 in the triplet; the three dimensions of the lookup table correspond to the three dimensions of the one-dimensional arrays of addr1, addr2, and sym, respectively; In the symbol comparison step, the target array compares all symbols of the data row to be searched with the sym in the triplet in a single cycle through a single-cycle byte search operation, and outputs a comparison result vector; The matching position recording step records the position in the comparison result vector representing the same comparison result to the output buffer of the target array, and uses the position to replace the symbol sym of the input sequence to obtain the encoding result of the gene data lookup table.

2. The method for encoding a gene data lookup table based on in-memory calculation according to claim 1, wherein: The data arrangement step includes: adopting a multiple copy strategy, or an array merging strategy, or a hybrid solution to store the three-dimensional lookup table data into multiple SRAM arrays; The multi-copy strategy: splits the three-dimensional lookup table into multiple two-dimensional lookup tables according to its addr1 dimension. Each addr2 dimension of the two-dimensional lookup table corresponds to a row of the SRAM array, and each two-dimensional lookup table is stored in the corresponding SRAM array. The symbol distribution of the genetic data is calculated, and symbols with a symbol distribution higher than a threshold are selected as hotspot symbols addr1. The SRAM array corresponding to the hotspot symbol addr1 is used as the hotspot array, and the hotspot array is replicated. By increasing the number of hotspot arrays, the processing burden of the hotspot array is reduced. The array merging strategy: Split the 3D lookup table into multiple 2D lookup tables according to the addr1 dimension of the 3D lookup table. These multiple 2D lookup tables are evenly divided and grouped and merged into each SRAM array (this reduces the number of SRAM arrays required). Then, each 2D lookup table in each group is stored in the corresponding SRAM array according to the multiple addr2 dimensions of each 2D lookup table. This hybrid solution: statistics the symbol distribution of the genetic data, selects symbols with symbol distribution higher than the threshold as hot spot symbols addr1, and uses the lookup table corresponding to the hot spot symbol addr1 as the hot spot table; according to the addr1 dimension of the three-dimensional lookup table, the three-dimensional lookup table is split into multiple two-dimensional lookup tables, and the two-dimensional lookup tables corresponding to the hot spot symbol addr1 are evenly divided and grouped and merged into each SRAM array. At the same time, through scheduling, each hot spot table is allocated to a different SRAM array, and then each two-dimensional lookup table is stored in the corresponding SRAM array according to the multiple addr2 dimensions of each two-dimensional lookup table in each group corresponding to a column of the SRAM array (compared with the array merging strategy, the rows and columns are transposed).

3. The method for encoding a gene data lookup table based on in-memory calculation according to claim 1, wherein: Each symbol in the input sequence is of fixed length.

4. A gene data lookup table encoding device based on in-memory calculation, characterized in that: include: The data arrangement module splits the three-dimensional lookup table data and stores them in multiple SRAM arrays in sequence; An input sequence processing module obtains an input sequence of genetic data of length NL, and organizes the input sequence into L-2 triplets (addr1, addr2, sym) according to the positions of the symbols in the input sequence, where sym is the current i-th symbol to be encoded, addr1 is the i-2-th symbol, and addr2 is the i-1-th symbol; a target array is determined from the multiple SRAM arrays according to addr1 in the triplet, N triplets are transmitted to the target array of the triplet at a time, and a data row to be searched is determined from all data rows of the target array according to addr2 in the triplet; the three dimensions of the lookup table correspond to the three dimensions of the one-dimensional arrays of addr1, addr2, and sym, respectively; The symbol comparison module compares all symbols of the data row to be searched with the sym in the triplet in a single cycle through a single-cycle byte search operation, and outputs a comparison result vector; The matching position recording module records the position in the comparison result vector representing the same comparison result to the output buffer of the target array, and uses the position to replace the symbol sym of the input sequence to obtain the encoding result of the gene data lookup table.

5. The gene data lookup table encoding device based on in-memory calculation according to claim 4, characterized in that: The data arrangement module is used to: store the three-dimensional lookup table data into multiple SRAM arrays using a multiple copy strategy, an array merging strategy, or a hybrid solution; The multi-copy strategy: Split the 3D lookup table into multiple 2D lookup tables according to the addr1 dimension of the 3D lookup table. Each addr2 dimension of the 2D lookup table corresponds to a row of the SRAM array, and each 2D lookup table is stored in the corresponding SRAM array. Count the symbol distribution of the gene data, select the symbol with a symbol distribution higher than the threshold as the hotspot symbol addr1, use the SRAM array corresponding to the hotspot symbol addr1 as the hotspot array, copy the hotspot array, and reduce the processing burden of the hotspot array by increasing the number of hotspot arrays; The array merging strategy: Split the 3D lookup table into multiple 2D lookup tables according to the addr1 dimension of the 3D lookup table. These multiple 2D lookup tables are evenly divided and grouped and merged into each SRAM array (this reduces the number of SRAM arrays required). Then, each 2D lookup table in each group is stored in the corresponding SRAM array according to the multiple addr2 dimensions of each 2D lookup table. The hybrid solution: count the symbol distribution of the gene data, select the symbol with a symbol distribution higher than the threshold as the hotspot symbol addr1, and use the lookup table corresponding to the hotspot symbol addr1 as the hotspot table; According to the addr1 dimension of the three-dimensional lookup table, the three-dimensional lookup table is split into multiple two-dimensional lookup tables. The two-dimensional lookup tables corresponding to the hotspot symbol addr1 are evenly divided and grouped and merged into each SRAM array. At the same time, each hotspot table is allocated to a different SRAM array through scheduling. Then, according to the multiple addr2 dimensions of each two-dimensional lookup table in each group corresponding to a column of the SRAM array (compared with the array merging strategy, the rows and columns are transposed), each two-dimensional lookup table is stored in the corresponding SRAM array.

6. The gene data lookup table encoding device based on in-memory calculation according to claim 4, characterized in that: Each symbol in the input sequence is of fixed length.

7. A client, used for any one of the in-memory computing-based gene data lookup table encoding devices described in claims 4-6.

8. An electronic device, characterized in that: It includes a genetic data lookup table encoding device based on in-memory calculation as described in claims 4-6, and the electronic device is connected to an information display device, which is used to display the genetic data lookup table encoding results according to display parameters and attributes set by the user or through an artificial intelligence model.

9. A computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the computer program implements the steps of the genetic data lookup table encoding method based on in-memory calculation according to any one of claims 1 to 3.

10. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the gene data lookup table encoding method based on in-memory calculation described in any one of claims 1 to 3 are implemented.

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