Method for manufacturing superimposed mark

Abstract

The invention provides a manufacturing method of a superimposed mark. A first mask ring is formed on the target layer. A first dielectric layer is formed on the first mask ring. Forming a second mask ring on the first dielectric layer; in the first direction, the length of the first mask ring is greater than the length of the second mask ring. In the second direction, the length of the first mask ring is smaller than the length of the second mask ring. A patterning process is performed on the second mask ring, the first dielectric layer and the first mask ring to form a third mask ring on the target layer corresponding to an overlapping region of the first mask ring and the second mask ring. A second dielectric layer is formed on the target layer and the third mask ring. A mask pattern layer is formed on the second dielectric layer, the mask pattern layer is provided with an opening, and the inner side wall of the opening is aligned with the inner side wall of the third mask ring; taking the mask pattern layer as a mask, and removing a part of the second dielectric layer and a part of the target layer; removing the mask pattern layer, the second dielectric layer and the third mask ring;

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a mark used in semiconductor processes, and in particular to a method for manufacturing an overlay mark. Background Art

[0002] In semiconductor processing, overlay marks are used to check the alignment between the previous layer and the current layer. Generally, overlay marks can be formed in the peripheral area of ​​the substrate (such as the scribe line), and the overlay mark formation step is usually integrated with the device formation step in the device area.

[0003] For example, when forming a pad array on a substrate in the device region, an overlay mark with the same pattern can be formed on the substrate in the peripheral region. However, when performing alignment measurement using an optical instrument, this type of overlay mark often lacks a clear optical image and has low contrast, leading to misalignment measurements. Summary of the Invention

[0004] The present invention is directed to a method for manufacturing a superimposed mark, which can form a superimposed mark with high optical image contrast.

[0005] The method for manufacturing an overlay mark of the present invention includes the following steps: forming a target layer on a substrate; forming a first mask ring on the target layer; forming a first dielectric layer on the first mask ring; forming a second mask ring on the first dielectric layer, wherein the length of the first mask ring in a first direction is greater than the length of the second mask ring in the first direction, the length of the first mask ring in a second direction is less than the length of the second mask ring in the second direction, and the first direction and the second direction are staggered; performing a patterning process on the second mask ring, the first dielectric layer, and the first mask ring to form a third mask ring on the target layer corresponding to the overlapping area of ​​the first mask ring and the second mask ring; forming a second dielectric layer on the target layer and the third mask ring; forming a mask pattern layer on the second dielectric layer, wherein the mask pattern layer has an opening, and the inner sidewall of the opening is aligned with the inner sidewall of the third mask ring; using the mask pattern layer as a mask, removing a portion of the second dielectric layer and a portion of the target layer; removing the mask pattern layer, the second dielectric layer, and the third mask ring.

[0006] Based on the above, a block-shaped overlay mark is formed on the substrate by forming two partially overlapping mask rings, the mask rings defined by the overlapping portions, and the mask pattern layer located thereon. As a result, the overlay mark can have a high optical image contrast, and the overlay mark formation step can be integrated with the formation step of the semiconductor device in the device region. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figures 1A to 1HA top view schematically shows the manufacturing process of a superimposed mark according to an embodiment of the present invention;

[0008] Figures 2A to 2H For the Figures 1A to 1H Schematic diagram of the manufacturing process cross section along the AA section line;

[0009] Figures 3A to 3H For the Figures 1A to 1H Schematic diagram of the manufacturing process cross-section along the BB section line. DETAILED DESCRIPTION

[0010] First, refer to Figure 1A 、 Figure 2A as well as Figure 3A , providing a substrate 100. In this embodiment, the substrate 100 includes a peripheral region 100a and a device region 100b. The substrate 100 includes a silicon base and a dielectric layer formed on the silicon base. In the device region 100b, semiconductor components such as transistors, interconnect structures, and circuit patterns may be formed on the silicon base, and the dielectric layer covers these semiconductor components. The peripheral region 100a may be an area for providing an overlay mark. The device region 100b may be provided as a portion of the entire device region or the entire device region.

[0011] A conductive layer 102 is formed on the substrate 100. The conductive layer 102 may be a metal layer, such as a tungsten layer, but the present invention is not limited thereto. Specifically, in the peripheral region 100a, the conductive layer 102 may be used to form a target layer for forming an overlay mark, while in the device region 100b, the conductive layer 102 may be used to form a device material layer for a semiconductor device. For example, the conductive layer 102 in the device region 100b may be used to form a pad array, and thus the conductive layer 102 may be considered a pad material layer. In this embodiment, the target layer in the peripheral region 100a corresponds to the device material layer in the device region 100b.

[0012] As semiconductor technology advances, the size of semiconductor devices continues to shrink. Therefore, various self-aligned multiple patterning processes can be used to form semiconductor devices. In the present invention, a self-aligned double patterning (SADP) process is used to form the devices in device region 100b. In other embodiments, a self-aligned triple patterning (SATP) process and a self-aligned quadruple patterning (SAQP) process can also be used.

[0013] After forming the conductive layer 102, a first block pattern layer 104 is formed on the conductive layer 102 in the peripheral region 100a, and a plurality of first stripe pattern layers 204 extending along the Y direction and arranged parallel to each other are formed on the conductive layer 102 in the device region 100b. In this embodiment, the first block pattern layer 104 and the first stripe pattern layer 204 are simultaneously defined using a single photomask. This means that no additional photomask or process steps are required to form the first block pattern layer 104 in the peripheral region 100a.

[0014] Next, refer to Figure 1B 、 Figure 2B as well as Figure 3B , a first mask material layer 106 is formed on the substrate 100. In the peripheral region 100a, the first mask material layer 106 is formed on the sidewalls of the first block pattern layer 104 to surround the first block pattern layer 104. Furthermore, in the device region 100b, the first mask material layer 106 is formed on the sidewalls of the first stripe pattern layer 204 to surround the first stripe pattern layer 204.

[0015] The method for forming the first mask material layer 106 includes the following steps. First, a layer of mask material is conformally formed on the substrate 100. Then, an anisotropic etching process is performed to remove a portion of the mask material. After the anisotropic etching process, the first mask material layer 106 located at the ends of the first strip pattern layer 204 in the device region 100b can be further removed. Strips of the first mask material layer 106 extending along the Y direction and arranged parallel to each other are formed on both sides of the first strip pattern layer 204.

[0016] Also refer to Figure 1C 、 Figure 2C as well as Figure 3C , the first block pattern layer 104 and the first strip pattern layer 204 are removed. A first mask ring 106a (first mask material layer 106) remains on the conductive layer 102 in the peripheral region 100a, and a plurality of first mask strips 206 (first mask material layer 106) remain on the conductive layer 102 in the device region 100b. In this embodiment, the first mask ring 106a and the first mask strips 206 are formed using a well-known self-aligned double patterning process.

[0017] A first dielectric layer 110 is formed on the substrate 100. The first dielectric layer 110 covers the conductive layer 102, the first mask ring 106a, and the first mask strip 206. Subsequently, a second block pattern layer 112 is formed on the first dielectric layer 110 in the peripheral region 100a, and a plurality of second strip pattern layers 212 extending along the X-direction and arranged parallel to each other are formed on the first dielectric layer 110 in the device region 100b. The second block pattern layer 112 and the second strip pattern layer 212 are simultaneously defined using a single photomask. In other words, no additional photomask or process steps are required to form the second block pattern layer 112 in the peripheral region 100a.

[0018] The second block pattern layer 112 is located at Figure 1B 、 Figure 2B as well as Figure 3B As shown, above the first block pattern layer 104, the second block pattern layer 112 has a shorter length in the X direction than the first block pattern layer 104, and a longer length in the Y direction than the first block pattern layer 104. The first block pattern layer 104 and the second block pattern layer 112 partially overlap.

[0019] A second mask material layer 114 is formed on the substrate 100. In the peripheral region 100a, the second mask material layer 114 is formed on the sidewalls of the second block pattern layer 112 to surround the second block pattern layer 112. In the device region 100b, the second mask material layer 114 is formed on the sidewalls of the second strip pattern layer 212 to surround the second strip pattern layer 212. The second mask material layer 114 is formed using the same method as the first mask material layer 106. Strips of the second mask material layer 114 extending along the X-direction and arranged parallel to each other are formed on both sides of the second strip pattern layer 212.

[0020] Also refer to Figure 1D 、 Figure 2D as well as Figure 3D , the second block pattern layer 112 and the second strip pattern layer 212 are removed. As a result, the second mask ring 114a (second mask material layer 114) remains on the first dielectric layer 110 in the peripheral region 100a, and a plurality of second mask strips 214 (second mask material layer 114) remain on the first dielectric layer 110 in the device region 100b. In this embodiment, the second mask ring 114a and the second mask strips 214 are formed using a well-known self-aligned double patterning process.

[0021] The position of the first block pattern layer 104 partially overlaps with the position of the second block pattern layer 112. The first block pattern layer 104 has a larger length in the X direction, and the second block pattern layer 112 has a larger length in the Y direction. Figure 1D 、 Figure 2D as well as Figure 3D As shown, the first mask ring 106a partially overlaps the second mask ring 114a, the first mask ring 106a may have a greater length in the X direction, and the second mask ring 114a may have a greater length in the Y direction.

[0022] A patterning process is performed on the second mask ring 114a, the first dielectric layer 110, and the first mask ring 106a to form a third mask ring on the conductive layer 102 in the peripheral region 100a corresponding to the overlapping area between the first mask ring 106a and the second mask ring 114a.

[0023] Reference Figure 1E 、 Figure 2E as well as Figure 3E An anisotropic etching process is then performed using the second mask ring 114a and the second mask strip 214 as masks to remove the exposed first dielectric layer 110. This exposes a portion of the first mask ring 106a and a portion of the conductive layer 102 in the peripheral region 100a, while exposing a portion of the first mask strip 206 and a portion of the conductive layer 102 in the device region 100b. The second mask ring 114a and the second mask strip 214 are then removed. At this point, a ring-shaped first dielectric layer 110 is formed in the peripheral region 100a at a location corresponding to the second mask ring 114a, and a strip-shaped first dielectric layer 110 is formed in the device region 100b at a location corresponding to the second mask strip 214.

[0024] Also refer to Figure 1F 、 Figure 2F as well as Figure 3F An anisotropic etching process is performed using the annular first dielectric layer 110 in the peripheral region 100a and the strip-shaped first dielectric layer 110 in the device region 100b as masks to remove and expose the first mask ring 106a and the first mask strips 206. The annular first dielectric layer 110 and the strip-shaped first dielectric layer 110 are then removed. A third mask ring 116 formed from the remaining first mask ring 106a is formed in the peripheral region 100a, and an array of multiple mask blocks 216 formed from the remaining first mask strips 206 is formed in the device region 100b.

[0025] The third mask ring 116 is substantially a rectangular ring and has two inner sidewalls 116X extending in the X direction and two inner sidewalls 116Y extending in the Y direction. In addition, each mask block 216 has two sidewalls 216X extending in the X direction and two sidewalls 216Y extending in the Y direction.

[0026] The sidewalls of the first block pattern layer 104 define the inner sidewalls of the first mask ring 106a extending in the Y direction, and the inner sidewalls of the first mask ring 106a extending in the Y direction define the inner sidewalls 116Y of the third mask ring 116. Furthermore, the sidewalls of the first strip pattern layer 204 extending in the Y direction define the sidewalls 216Y of the mask block 216 extending in the Y direction. Because the first block pattern layer 104 and the first strip pattern layer 204 are simultaneously formed using a single photomask, the inner sidewalls 116Y of the third mask ring 116 correspond to the sidewalls 216Y of the mask block 216, defining the Y-direction alignment line used during alignment measurement.

[0027] The sidewalls of the second block pattern layer 112 define the inner sidewalls of the second mask ring 114a extending in the X-direction, and the inner sidewalls of the second mask ring 114a extending in the X-direction define the inner sidewalls 116X of the third mask ring 116. Furthermore, the sidewalls of the second strip pattern layer 212 extending in the X-direction define the sidewalls 216Y of the mask block 216 extending in the X-direction. Because the second block pattern layer 112 and the second strip pattern layer 212 are simultaneously formed using a single photomask, the inner sidewalls 116X of the third mask ring 116 correspond to the sidewalls 216X of the mask block 216, defining the X-direction alignment line used during alignment measurement.

[0028] Also refer to Figure 1G 、 Figure 2G as well as Figure 3G A second dielectric layer 118 is formed on the substrate 100. The second dielectric layer 118 covers the conductive layer 102 and the third mask ring 116 in the peripheral region 100a, and exposes the device region 100b. A mask pattern layer 120 is formed on the second dielectric layer 118. In this embodiment, the mask pattern layer 120 may be a metal layer, such as a tungsten layer, but the present invention is not limited thereto. The mask pattern layer 120 has an opening 122, and the inner sidewall of the opening 122 is aligned with the inner sidewall of the third mask ring 116. The inner sidewall 122X of the opening 122 extending in the X direction is aligned with the inner sidewall 116X of the third mask ring 116, and the inner sidewall 122Y of the opening 122 extending in the Y direction is aligned with the inner sidewall 116Y of the third mask ring 116. The mask pattern layer 120 may be formed simultaneously with the circuit layer in the area outside the device region 100b, but the present invention is not limited thereto.

[0029] Also refer to Figure 1H 、 Figure 2H as well as Figure 3HAn anisotropic etching process is performed using the mask pattern layer 120 as a mask to remove the second dielectric layer 118 exposed by the opening 122. Next, the mask pattern layer 120 is removed. An anisotropic etching process is performed using the remaining second dielectric layer 118 and the mask block 216 as masks to remove the exposed conductive layer 102. Overlay marks 124 defined by the mask pattern layer 120 are formed on the substrate 100 in the peripheral region 100a, and pads 218 defined by the mask block 216 are formed on the substrate 100 in the device region 100b. Subsequently, the mask pattern layer 120, the second dielectric layer 118, the third mask ring 116, and the mask block 216 are removed.

[0030] Since the inner sidewalls of the opening 122 of the mask pattern layer 120 are aligned with the inner sidewalls of the third mask ring 116, the inner sidewalls 124X and 124Y of the overlap mark 124 defined by the mask pattern layer 120 can respectively correspond to the sidewalls 218X and 218Y of the pad 218 defined by the mask module 216, so that the inner sidewalls 124X and 124Y of the overlap mark 124 can serve as the X-direction alignment lines and the Y-direction alignment lines, respectively, during the alignment measurement process.

[0031] In the prior art, when forming a pad array in the device region, an overlay mark with the same pattern as the pad array is formed in the peripheral region. This type of overlay mark does not produce a clear optical image when performing alignment measurement using an optical instrument, and the contrast of the optical image is low. In this embodiment, overlay mark 124 is larger than pads 218 and is block-shaped. Therefore, it can produce a clear optical image when performing alignment measurement using an optical instrument, and the contrast of the optical image can be effectively improved. This effectively reduces or even eliminates the problem of alignment measurement errors.

[0032] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing a superimposed mark, characterized in that: include: forming a target layer on a substrate; forming a first mask ring on the target layer; forming a first dielectric layer on the first mask ring; forming a second mask ring on the first dielectric layer, wherein a length of the first mask ring in a first direction is greater than a length of the second mask ring in the first direction, a length of the first mask ring in a second direction is less than a length of the second mask ring in the second direction, and the first direction and the second direction are staggered; performing a patterning process on the second mask ring, the first dielectric layer, and the first mask ring to form a third mask ring on the target layer corresponding to an overlapping area of ​​the first mask ring and the second mask ring; forming a second dielectric layer on the target layer and the third mask ring; forming a mask pattern layer on the second dielectric layer, wherein the mask pattern layer has an opening, and an inner sidewall of the opening is aligned with an inner sidewall of the third mask ring; Using the mask pattern layer as a mask, removing a portion of the second dielectric layer and a portion of the target layer; as well as The mask pattern layer, the second dielectric layer and the third mask ring are removed.

2. The method for manufacturing a superimposed mark according to claim 1, wherein: The method for forming the first mask ring includes: forming a first block pattern layer on the target layer; forming a first mask material layer on sidewalls of the first block pattern layer; and The first block pattern layer is removed.

3. The method for manufacturing a superimposed mark according to claim 2, wherein: The method for forming the second mask ring includes: forming a second block pattern layer on the first dielectric layer, wherein the second block pattern layer is located above the first block pattern layer, a length of the second block pattern layer in the first direction is smaller than a length of the first block pattern layer in the first direction, and a length of the second block pattern layer in the second direction is greater than a length of the first block pattern layer in the second direction; forming a second mask material layer on sidewalls of the second block pattern layer; and The second block pattern layer is removed.

4. The method for manufacturing a superimposed mark according to claim 3, wherein: The method for forming the third mask ring includes: Using the second mask ring as a mask, removing a portion of the first dielectric layer; removing the second mask ring; using the remaining first dielectric layer as a mask to remove a portion of the first mask ring; and The remaining first dielectric layer is removed.

5. The method for manufacturing a superimposed mark according to claim 4, characterized in that: The substrate has a device region and a peripheral region, and the target layer is located on the substrate in the peripheral region.

6. The method for manufacturing a superimposed mark according to claim 5, characterized in that: When forming the target layer, a first device material layer is formed on the substrate in the device region, and the target layer corresponds to the device material layer.

7. The method for manufacturing a superimposed mark according to claim 6, wherein: The component material layer is a pad material layer.

8. The method for manufacturing a superimposed mark according to claim 6, wherein: When forming the first block pattern layer, a plurality of first strip pattern layers extending along the second direction are formed above the first element material layer, and the first block pattern layer and the plurality of first strip pattern layers are defined simultaneously by a photomask; The first mask material layer is also formed on sidewalls of the plurality of first stripe pattern layers; and When removing the first block pattern layer, the plurality of first strip pattern layers are removed.

9. The method for manufacturing a superimposed mark according to claim 8, wherein: When forming the second block pattern layer, a plurality of second strip pattern layers extending along the first direction are formed above the plurality of first strip pattern layers, and the second block pattern layer and the plurality of second strip pattern layers are simultaneously defined by a photomask; The second mask material layer is also formed on sidewalls of the plurality of second stripe pattern layers; and When removing the second block pattern layer, the plurality of second strip pattern layers are removed.

10. The method for manufacturing a superimposed mark according to claim 5, wherein: The mask pattern layer and the second dielectric layer expose the device region.

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