Battery management system and battery box

Abstract

The invention discloses a battery management system and a battery box, and relates to the technical field of battery management, the battery management system comprises a master control module and at least one group of slave control modules; the master control module comprises an STM32 single-chip microcomputer, a relay control unit, a CAN communication unit and a daisy chain communication conversion unit. The STM32 single-chip microcomputer is connected with the relay control unit, the CAN communication unit and the daisy chain communication conversion unit. The slave control module comprises a slave control AFE unit, a temperature acquisition unit, a reinforced communication unit, a passive equalization unit and a filtering unit; the slave control AFE unit is respectively connected with the temperature acquisition unit, the enhanced communication unit, the passive equalization unit and the filtering unit, the passive equalization unit and the filtering unit are respectively connected with the battery pack, and the enhanced communication unit is connected with the daisy chain communication conversion unit; the slave control modules are connected in series through the enhanced communication unit. The battery box layout and the battery management system are optimized, and the suitability and the sampling frequency of the battery box are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of battery management, and more particularly to a battery management system and a battery box. Background Art

[0002] Sustainable development of transportation energy and energy conservation and emission reduction in the transportation sector have been prioritized by governments worldwide. Against this backdrop, electric vehicles, due to their significant energy-saving and environmentally friendly advantages, have received strong policy support and promotion, becoming a key area of ​​technological innovation in the global automotive industry. This trend has not only accelerated the rise of the electric vehicle industry but also directly driven the rapid development of power battery technology and its management systems, providing crucial technical support for achieving green transportation and sustainable energy development.

[0003] The Battery Management System (BMS) is an indispensable core component of modern new energy vehicle technology. BMS topologies include integrated and master-slave configurations. The advantages of an integrated BMS are lower cost, smaller footprint within the battery system, and easier maintenance. However, the voltage platform of current electric vehicles is mostly above 300V, and the voltage monitoring chips of integrated BMSs cannot meet such high voltage ratings. Therefore, the current mainstream approach is to use a master-slave architecture to decompose the high-voltage acquisition task into low-voltage acquisition tasks. A master-slave BMS is primarily composed of two modules: the master control module and the slave control module. The master control module is responsible for data processing, communication, and diagnostics, while the slave control module is responsible for data acquisition, monitoring, and balancing. Due to factors such as mass production requirements and modular design, mainstream BMS products on the market have poor compatibility between the slave control module and the battery module, resulting in complex wiring harnesses and the risk of disconnection between the wiring harness and connectors due to the manufacturing process. Furthermore, when the slave control acquisition channels do not match the number of battery cells, problems such as redundant BMS slave control channels can occur, resulting in wasted space and volume, ultimately increasing costs. In addition to poor adaptability, many BMS products have problems such as slow data sampling rates. When battery cells are damaged due to individual differences, if the BMS cannot respond quickly to cut off the high-voltage output, the battery pack may be damaged, causing safety accidents.

[0004] Therefore, how to improve the adaptability and sampling frequency of the master-slave battery management system is an urgent problem that those skilled in the art need to solve. Summary of the Invention

[0005] In view of this, the present invention provides a battery management system and a battery box, which optimize the battery box layout and the battery management system and improve the adaptability and sampling frequency of the battery box.

[0006] In order to achieve the above object, the present invention adopts the following technical solutions:

[0007] A battery management system includes a master control module and at least one group of slave control modules;

[0008] The main control module includes an STM32 single-chip microcomputer, a relay control unit, a CAN communication unit, and a daisy-chain communication conversion unit; the STM32 single-chip microcomputer is connected to the relay control unit, the CAN communication unit, and the daisy-chain communication conversion unit respectively;

[0009] The slave control module includes a slave control AFE unit, a temperature acquisition unit, an enhanced communication unit, a passive balancing unit and a filtering unit; the slave control AFE unit is respectively connected to the temperature acquisition unit, the enhanced communication unit, the passive balancing unit and the filtering unit, the passive balancing unit and the filtering unit are respectively connected to the battery pack, and the enhanced communication unit is connected to the daisy chain communication conversion unit; multiple groups of slave control modules are connected in series through the enhanced communication unit.

[0010] Preferably, the slave-controlled AFE unit includes a chip U1 of model LTC6804-1, and an LDO (low-dropout linear regulator) component is provided in the chip U1. The first pin V+ of the chip U1 is connected to the positive pole of the battery pack, and the 31st pin V- is connected to the negative pole of the battery pack. The circuit voltage is reduced by the LDO component, and the reduced power supply is output to the 38th pin DRVE (output Drive1 signal).

[0011] Preferably, the enhanced communication unit includes two external resistors, two terminal resistors, two capacitors, an external transformer U2 and an isoSPI interface; the first pin TD+ of the external transformer U2 is connected to the IPA pin of the chip U1, the third pin TD- is connected to the IMA pin of the chip U1, and a first terminal resistor is connected between the first pin TD+ and the third pin TD-, the sixth pin RD+ is connected to the IPB pin of the chip U1, the eighth pin RD- is connected to the IMB pin of the chip U1, and a second terminal resistor is connected between the sixth pin RD+ and the eighth pin RD-, and the second pin TCT is connected to the first capacitor , the 7th pin RCT is connected to the second capacitor, and the other ends of the two capacitors are grounded respectively, the 14th pin TX- and the 16th pin TX+ are respectively connected to the RX- pin and RX+ pin of the external transformer U2 of the enhanced communication unit in the next-level slave control module, and the 9th pin RX- and the 11th pin RX+ are respectively connected to the TX- pin and TX+ pin of the external transformer U2 of the enhanced communication unit in the previous-level slave control module; the 1st pin of the isoSPI interface is connected to the 37th pin Vreg1 of the chip U1, the 2nd pin is connected to the 40th pin ISOMD of the chip U1, and the 3rd pin is grounded for mode selection.

[0012] Preferably, the daisy chain communication conversion unit includes a chip U4 of model LTC6820HMS, a connector CN5, a connector CN2, two decoupling capacitors and a single-channel daisy chain circuit; the single-channel daisy chain circuit includes two external resistors, a terminal resistor, an external transformer and two capacitors; the chip U4 is connected to the SPI pin of the STM32 microcontroller through the connector CN5, the 6th pin VDDS, the 7th pin POL, the 8th pin PHA and the 9th pin VDD of the chip U4 are connected to VCC, and two decoupling capacitors are connected, the 10th pin IM of the chip U4 is connected to the terminal resistor and the 3rd pin of the external transformer, and the 11th pin IP is connected to the SPI pin of the STM32 microcontroller. Connected to the other end of the terminal resistor and the 1st pin of the external transformer, the 15th pin ICMP is grounded through the second external resistor and connected to one end of the first external resistor, and the 16th pin IBIAS is connected to the other end of the first external resistor; the 2nd and 5th pins of the external transformer are grounded through a capacitor respectively, the 4th pin is connected to the 2nd pin of the connector CN2, and the 6th pin is connected to the 1st pin of the connector CN2; the 1st pin of the connector CN2 is connected to the TX+ pin of the external transformer U2 in the enhanced communication unit, and the 2nd pin is connected to the TX- pin of the external transformer U2 in the enhanced communication unit, which is used to connect the slave control module in series for isoSPI communication.

[0013] Preferably, the passive balancing unit includes several groups of balancing modules, each group of balancing modules includes a field effect transistor P-MOS, a first current limiting resistor, a second current limiting resistor, a discharge resistor and a light-emitting diode; the source (pin 2) of the field effect transistor P-MOS is connected to the positive electrode of a battery in the battery pack, the gate (pin 1) is connected to one end of the first current limiting resistor, the other end of the first current limiting resistor is connected to a balancing pin of the chip U1 (the balancing pins include pins S1-S12), the drain (pin 3) is connected to the anode of the light-emitting diode and one end of the discharge resistor, the other end of the discharge resistor is connected to the positive electrode of another battery in the battery pack, the cathode of the light-emitting diode is connected to one end of the second current limiting resistor, and the other end of the second current limiting resistor is connected to the positive electrode of another battery in the battery pack.

[0014] Preferably, the filtering circuit includes several groups of grounded capacitors and several groups of RC low-pass filters composed of filter resistors and filter capacitors; one end of the filter resistor is connected to the positive pole of a battery in the battery pack, and the other end is connected to an acquisition pin of the chip U1 (the power pins include C1-C12 pins), and the other end is simultaneously connected to one end of the grounded capacitor and one end of the filter power supply, the other end of the filter capacitor is connected to one end of the filter capacitor in another group of RC low-pass filters, and the other end of the grounded capacitor is grounded.

[0015] Preferably, the temperature acquisition unit includes several groups of temperature acquisition probes and voltage divider resistors; one end of the voltage divider resistor is connected to the 34th pin VREF2 of the chip U1, and the other end is respectively connected to the built-in GPIO1 pin of the chip U1 and one end of the temperature acquisition probe, and the other end of the temperature acquisition probe is grounded.

[0016] Preferably, the slave control module also includes a debugging section, which sets the measurement points Vref1 (TP1), Vref2 (TP2), and IBIAS1 (TP3). When Vref1 = 3V, the chip U1 core enters the Measure state; when Vref2 = 3V, the chip U1 auxiliary measurement channel is turned on; when IBIAS1 = 2V, isoSPI in the chip U1 is enabled.

[0017] Preferably, the slave control module further includes a fuse unit, including a plurality of fuses, one end of each fuse is connected to a collection pin (C0-C12 pin) of the chip U1, and the other end is connected to the battery pack.

[0018] A battery box, applying the above-mentioned battery management system, comprises a box body, a battery pack, a main control PCB board, and a slave control PCB board, wherein the main control module is integrated on the main control PCB board, and the slave control module is integrated on the slave control PCB board; the battery pack is placed in the box body, and the main control PCB board and the slave control PCB board are fixed above the battery pack, wherein the slave control PCB board further comprises a spring, one end of the spring is fixed to the side of the slave control PCB board facing the battery pack and connected to the passive balancing unit, and the other end contacts the battery pack; temperature acquisition probes of the temperature acquisition unit are spaced apart and distributed on the side of the slave control PCB board facing the battery pack.

[0019] Preferably, the battery box is further provided with a module cover plate adapted to the opening of the top surface of the box body, so as to seal the main control PCB board, the slave control PCB board and the battery pack in the box body.

[0020] Preferably, the module cover plate, the main control PCB board, the slave control PCB board and the box body are fixedly connected by bolts and studs.

[0021] Preferably, an electrode sheet with good conductivity is provided at one end of the spring, which contacts the positive electrode or negative electrode of each battery in the battery pack.

[0022] It can be seen from the above technical solution that compared with the prior art, the present invention discloses a battery management system and a battery box. The present invention is suitable for battery modules with flat electrodes. In view of the problems of poor adaptability of the existing battery management system to the battery box, redundant wiring, and limited design size of the battery box, the layout of the battery box is designed, the battery pack is simple to assemble, the acquisition board and the BMS slave control are integrated into one, and spring collection and NTC probe direct contact collection are used to solve the complex wiring problem in the battery box under high voltage. It has strong adaptability to racing cars and reduces the weight of the overall battery device. It can reduce the height of the battery box by 20mm and the weight by 5kg, effectively reducing the design and production costs and expanding the design space of racing cars. In addition, the present invention can disconnect the safety circuit within 0.5s after detecting an abnormality, which complies with the rules of the Formula Student battery box and can be applied to the Formula Student battery box. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0024] Figure 1 A schematic diagram of the battery management system provided by the present invention;

[0025] Figure 2 A schematic diagram of the circuit structure of a daisy chain communication conversion unit provided by the present invention;

[0026] Figure 3 A schematic diagram of the structure of the slave control module provided by the present invention;

[0027] Figure 4 A schematic diagram of the circuit structure of the slave control AFE unit provided by the present invention;

[0028] Figure 5 A schematic diagram of the circuit structure of the enhanced communication unit provided by the present invention;

[0029] Figure 6 A schematic diagram of the passive balancing unit circuit structure provided by the present invention;

[0030] Figure 7 A schematic diagram of the filter unit circuit structure provided by the present invention;

[0031] Figure 8 This is a schematic diagram of the circuit structure of the temperature acquisition unit provided by the present invention;

[0032] Figure 9 A schematic diagram of the circuit structure of the debugging module provided by the present invention;

[0033] Figure 10 A schematic diagram of the circuit structure of the insurance unit provided by the present invention;

[0034] Figure 11 A schematic diagram of the battery pack structure provided by the present invention;

[0035] Figure 12 A schematic diagram of the PCB structure of the slave control module provided by the present invention;

[0036] Figure 13 This is a schematic diagram of the battery box structure provided by the present invention.

[0037] In the attached figure: 1-module cover plate, 2-slave control PCB board, 3-battery cell, 4-box, 5-ear support plate, 6-spring, 7-NTC temperature probe. DETAILED DESCRIPTION

[0038] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0039] An embodiment of the present invention discloses a battery management system, comprising a master control module and at least one group of slave control modules;

[0040] The main control module includes an STM32 microcontroller, a relay control unit, a CAN communication unit, and a daisy-chain communication conversion unit. The STM32 microcontroller is connected to the relay control unit, the CAN communication unit, and the daisy-chain communication conversion unit respectively. The CAN communication unit is connected to an external host computer and an electronic control unit (ECU) via a CAN bus. The relay control unit is connected to an external safety circuit and relay.

[0041] The slave control module includes a slave control AFE unit, a temperature acquisition unit, an enhanced communication unit, a passive balancing unit, and a filter unit; the slave control AFE unit is connected to the temperature acquisition unit, the enhanced communication unit, the passive balancing unit, and the filter unit respectively, the passive balancing unit and the filter unit are connected to the battery pack respectively, and the enhanced communication unit is connected to the daisy chain communication conversion unit; multiple groups of slave control modules are connected in series through the enhanced communication unit; isoSPI communication is achieved between the slave control AFE unit and the daisy chain communication conversion unit. The structure of the slave control module is as follows Figure 3 shown.

[0042] The relay control unit uses the STM32 microcontroller pin to determine its status based on the slave control parameters collected. The pin outputs a voltage signal to control the opening and closing of the relay's field-effect transistor (P-MOS) for low-side drive. The CAN communication unit's main function is to complete the conversion between logical levels and the physical levels of the CAN bus. Furthermore, the slave control AFE unit includes a chip U1, model LTC6804-1. Chip U1 is equipped with an LDO (low-dropout linear regulator) component. Pin 1 V+ of chip U1 is connected to the positive terminal of the battery pack, and pin 31 V- is connected to the negative terminal of the battery pack. The circuit is stepped down by the LDO component, and the stepped-down power supply is output to pin 38 DRVE (output Drive1 signal).

[0043] Furthermore, the communication unit is strengthened to include two external resistors, two terminal resistors, two capacitors, an external transformer U2 and an isoSPI interface; the first pin TD+ of the external transformer U2 is connected to the 42nd pin IPA of the chip U1, the third pin TD- is connected to the 41st pin IMA of the chip U1, and the first terminal resistor is connected between the first pin TD+ and the third pin TD-, the sixth pin RD+ is connected to the 48th pin IPB of the chip U1, the eighth pin RD- is connected to the 47th pin IMB of the chip U1, and the second terminal resistor is connected between the sixth pin RD+ and the eighth pin RD-, and the second pin TCT is connected to the Connect to the first capacitor, pin 7 RCT is connected to the second capacitor, the other ends of the two capacitors are grounded respectively, pin 14 TX- and pin 16 TX+ are respectively connected to the RX- pin and RX+ pin of the external transformer U2 of the enhanced communication unit in the next-level slave control module, pin 9 RX- and pin 11 RX+ are respectively connected to the TX- pin and TX+ pin of the external transformer U2 of the enhanced communication unit in the previous-level slave control module; pin 1 of the isoSPI interface is connected to pin 37 (Vreg1) of chip U1, pin 2 is connected to pin 40 (ISOMD) of chip U1, and pin 3 is grounded for mode selection.

[0044] Furthermore, the daisy chain communication conversion unit includes a chip U4 of model LTC6820HMS, a connector CN5, a connector CN2, two decoupling capacitors and a single daisy chain circuit; the single daisy chain circuit includes two external resistors, a terminal resistor, an external transformer and two capacitors; the chip U4 is connected to the SPI pin of the STM32 microcontroller through the connector CN5, the 6th pin VDDS, the 7th pin POL, the 8th pin PHA and the 9th pin VDD of the chip U4 are connected to VCC, and two decoupling capacitors are connected, the 10th pin IM of the chip U4 is connected to the terminal resistor and the 3rd pin of the external transformer, and the 11th pin IP is connected to Connected to the other end of the terminal resistor and the 1st pin of the external transformer, the 15th pin ICMP is grounded through the second external resistor and connected to one end of the first external resistor, and the 16th pin IBIAS is connected to the other end of the first external resistor; the 2nd and 5th pins of the external transformer are grounded through a capacitor respectively, the 4th pin is connected to the 2nd pin of the connector CN2, and the 6th pin is connected to the 1st pin of the connector CN2; the 1st pin of the connector CN2 is connected to the TX+ pin of the external transformer U2 in the enhanced communication unit, and the 2nd pin is connected to the TX- pin of the external transformer U2 in the enhanced communication unit, which is used to connect the slave control module in series for isoSPI communication.

[0045] Furthermore, the passive balancing unit includes several groups of balancing modules, each group of balancing modules includes a field effect transistor P-MOS, a first current limiting resistor, a second current limiting resistor, a discharge resistor and a light-emitting diode; the source (pin 2) of the field effect transistor P-MOS is connected to the positive electrode of a battery in the battery pack, the gate (pin 1) is connected to one end of the first current limiting resistor, the other end of the first current limiting resistor is connected to a balancing pin of the chip U1 (the balancing pins include pins S1-S12), the drain (pin 3) is connected to the anode of the light-emitting diode and one end of the discharge resistor, the other end of the discharge resistor is connected to the positive electrode of another battery in the battery pack, the cathode of the light-emitting diode is connected to one end of the second current limiting resistor, and the other end of the second current limiting resistor is connected to the positive electrode of another battery in the battery pack.

[0046] Furthermore, the filtering circuit includes several groups of grounded capacitors and several groups of RC low-pass filters composed of filter resistors and filter capacitors; one end of the filter resistor is connected to the positive pole of a battery in the battery pack, and the other end is connected to a power pin of the chip U1 (the power pins include C1-C12 pins), and the other end is simultaneously connected to one end of the grounded capacitor and one end of the filter power supply, the other end of the filter capacitor is connected to one end of the filter capacitor in another group of RC low-pass filters, and the other end of the grounded capacitor is grounded.

[0047] Furthermore, the temperature acquisition unit includes several groups of temperature acquisition probes and voltage divider resistors; one end of the voltage divider resistor is connected to the 34th pin VREF2 of the chip U1, and the other end is connected to the GPIO1 pin built into the chip U1 and one end of the temperature acquisition probe, and the other end of the temperature acquisition probe is grounded.

[0048] Furthermore, the slave control module also includes a debugging section, setting the indicator unit, measurement points Vref1 (TP1), Vref2 (TP2) and IBIAS1 (TP3). When Vref1 = 3V, the chip U1 core enters the Measure state. When Vref2 = 3V, the chip U1 auxiliary measurement channel is turned on. When IBIAS1 = 2V, the isoSPI in the chip U1 is enabled. Figure 9 As shown, the indicator unit includes a transistor U3, a bypass capacitor C6, a light-emitting diode D2, and a resistor R20. Pins 1B, 2C, and 4C of transistor U3 are connected to chip U1, respectively. Pin 3E is connected to pin 37 VREG of chip U1. The anode of light-emitting diode D2 is connected to pin 37 VREG of chip U1, and the cathode is connected to resistor R20. The other end of resistor R20 is grounded. One end of bypass capacitor C6 is connected to pin 37 VREG of chip U1, and the other end is grounded. The circuit status is indicated by the light-emitting diode, and a 10KΩ resistor R20 is used for current limiting, and a 1uF bypass capacitor is used to reduce power supply ripple. Transistor U3 is an NPN transistor model CZT5551 TR PBFREE. Pin 1 is connected to the drive signal Drive1, pins 2 and 4 are connected to the power supply V1+, and pin 3 is connected to one end of bypass capacitor C6 and the anode of light-emitting diode D2.

[0049] Furthermore, the slave control module also includes a fuse unit, including several fuses (F1-F24), one end of each fuse is connected to the acquisition pin (C0-C12 pin) of the chip U1, and the other end is connected to the battery pack, such as Figure 10 shown.

[0050] In a specific embodiment, the circuit structure of the slave-controlled AFE unit and the peripheral circuit is as follows: Figure 4As shown; the LDO component is integrated in the chip U1, and its related circuit structure is: the 38th pin DRIVE of the chip U1 is connected to the pin 1 of the transistor U3 (CZT5551) of the debugging board, and the voltage is stepped down to 5V and output to the 37th pin VREG of the chip U1; the pin 1 of the chip U1 is connected to the positive electrode Cell_12+ of the 12th battery, and the pin 31 is connected to the negative electrode Cell_1- of the first battery; the 1st pin B of the transistor U3 is connected to the 38th pin DRIVE of the chip U1, the 2nd pin C and the 4th pin C are both connected to one end of the capacitor C3 and one end of the resistor R13, the other end of the capacitor C3 is grounded, and the other end of the resistor R13 is connected to the positive electrode of the 12th battery.

[0051] In a specific embodiment, Figure 5 As shown, the enhanced communication unit adopts a two-wire isolated interface and a simple twisted pair to realize the cascade of chip U1, which effectively realizes the expansion of the acquisition channel. This communication method encodes the standard SPI into differential pulse isoSPI, and sets the pulse strength and receiver threshold through external resistors. Through an external transformer, it is beneficial to improve the low packet error rate. The daisy chain conversion unit of the present invention compromises power consumption and communication robustness, and uses two 1kΩ external resistors (R17, R18) to set the pulse strength and receiver threshold. 120Ω resistors (R14, R16) are used as terminal resistors. In order to optimize common-mode noise suppression, an HX1188NL external transformer (U2) with its own center tap is used, and two 100pf capacitors (C4, C5) are also provided. The specific connection relationship is: Pin 1 of U2 is connected to the IPA of the LTC6804-1 chip U1, Pin 3 is connected to the IMA of U1, and a terminal resistor R14 is connected between Pin 1 and Pin 3; Pin 6 and Pin 8 of U2 are connected to the IPB and IMB of U1, and R16 is connected between Pin 6 and Pin 8; Pin 2 and Pin 7 of U2 are connected to capacitors C4 and C5 to ground respectively; Pin 16 and Pin 14 of U2 are connected to the RX+ and RX- of the next-level slave control (or to the IP pin and IM pin of the CAN communication unit); Pin 11 and Pin 9 of U2 are connected to the TX+ and TX- of the previous-level slave control; Pin 4, Pin 5, Pin 12, and Pin 13 of U2 are left floating; Pin 1 of the isoSPI interface is connected to Vreg1 of chip U1, Pin 2 is connected to ISOMD of chip U1, and Pin 3 is grounded.

[0052] In a specific embodiment, the daisy chain communication conversion unit converts standard SPI to differential isoSPI through an LTC6820 chip to achieve the connection of multiple LTC6804-1, thereby minimizing the wiring harness and components in the layout of the battery management system. Figure 2As shown, the daisy-chain communication conversion unit includes the LTC6820 chip U4, connectors (CN2, CN3, CN5, H10, H11, H12, H13), decoupling capacitors (C1, C4), and a single daisy-chain circuit. The single daisy-chain circuit includes two 1K external resistors (R2, R3) to set the pulse strength and receiver threshold, 120Ω (R1) as a terminal resistor, an external transformer (L1) of model HM2103NLT, and 100pF capacitors (C2, C3) connected to the center tap to reduce electromagnetic interference. The specific connection relationship is: U4 is connected to the SPI interface of the STM32 microcontroller through CN5 (MOSI, MISO, SCK, CS), H10 is reserved for the logic analyzer connection interface to facilitate code debugging and SPI timing analysis, the VDDS pin and VDD are connected to the external power supply VCC, and VCC and GND are connected to the external power supply through H13; the EN, MSTR, and SLOW pins in U4 are reserved for mode settings. When EN is connected to VCC, the chip will always enter the enabled state. When EN is connected to GND, the chip will Sleep within 5.5ms when CS is inactive or IP / IM has no signal. When the SPI communication rate is above 200Kps, the SLOW pin of U4 must be connected to GND. When the MSTR pin is connected to VCC, U4 converts SPI to isoSPI. When the MSTR pin is connected to GND, U4 converts isoSPI to SPI. H13 is a jumper pin. The EN pin is connected to the pin 1EN of U4 to enable the chip. The SPI1 interface of the STM32 microcontroller is connected to H10 and connected to U4 accordingly. The MOSI pin of 10 is connected to the pin 2MOSI of U4, the MISO pin is connected to the pin 3MISO of U4, the SCK pin is connected to the pin 4SCK of U4, and the CS pin is connected to the pin 5CS of U4; the pin 6VDDS, pin 7POL, pin 8PHA, and pin 9VDD of U4 are connected to the VCC5V power supply, and two decoupling capacitors are connected; the two ends of the terminal resistor R1 are connected to the U4 pin 10IM and pin 11IP, and are connected to the L1 input pins 1 and 3; H12 is a jumper pin, and the MSTR pin Connect to pin 12MSTR of U4; H11 is a jumper pin, and the SLOW pin is connected to pin 13SLOW of U4; the GND terminal of U4 is grounded, pin 15ICMP of U4 is connected to ground through a 1k resistor R3 and connected to one end of a 1k resistor R2, and pin 16IBIAS of U4 is connected to the other end of R2; the center tap end of L1, i.e. pin 2 and pin 5, are grounded through a 100pf capacitor, and pin 4 and pin 6 of L1 are connected to pin 2 and pin 1 of CN2 respectively, for serial slave communication.

[0053] In a specific embodiment, Figure 6The passive balancing unit shown is adapted to 12 batteries in the battery pack and is provided with 12 field-effect transistors P-MOS (Q1-Q12), 12 first current-limiting resistors (R23-R26, R39-R42, R55-R58), 12 second current-limiting resistors (R30, R32, R34, R36, R46, R48, R50, R52, R62, R64, R66, R68), 12 discharge resistors (R29, R31, R33, R35, R45, R47, R49, R51, R61, R63, R65, R67) and 12 light-emitting diodes. The first current-limiting resistor uses a 3.3KΩ resistor as the balancing pin current-limiting resistor, the second current-limiting resistor uses a 475Ω resistor as the LED circuit current-limiting resistor, and the discharge resistor uses a 33Ω resistor. The BSS84 P-MOS field-effect transistor (FET) uses an external MOSFET for cell balancing, controlled by the source pin. Balancing is achieved by configuring the DCC bit in the configuration register. A 2512-package discharge resistor limits the power consumed by the MOSFET, effectively dissipating heat and preventing damage to the chip due to excessive heat. For example, the specific connection relationship is as follows: Q1's pin 2 source is connected to the positive terminal of the 12th cell, Cell_12+; Q1's pin 1 gate is connected to one end of the balancing pin current-limiting resistor R23, the other end of which is connected to S12 of chip U1; Q1's pin 3 drain is connected to the anode of the light-emitting diode (LED) and one end of the discharge resistor R29. The other end of the discharge resistor R29 is connected to the positive terminal of the 11th cell, Cell_11+; the cathode of the light-emitting diode (LED) is connected to one end of the LED circuit current-limiting resistor R30, the other end of which is connected to the positive terminal of the 11th cell, Cell_11+. The other balancing circuit connections are the same.

[0054] In a specific embodiment, Figure 7The filter circuit shown is adapted to the 12 cells of the battery pack, and 12 groups of RC low-pass filters and 12 grounding capacitors (C7-C18) are set. The RC low-pass filters are used to reduce transient noise, and the grounding capacitors are used to reduce high-frequency noise. The 12 groups of RC low-pass filters include 12 100Ω resistors (R21, R22, R27, R28, R37, R38, R43, R44, R53, R54, R59, and R60) and 11 10nF capacitors (C19-C29). The specific connection relationship is as follows: the positive electrode Cell_1+ of the first battery is connected to the resistor R21, the other end of the resistor R21 is connected to the 24th pin 1+ of the chip U1, and is connected to capacitors C7 and C19. The other end of C7 is grounded, and the other end of C19 is connected to the 22nd pin 2+ of chip U1; Cell_2+ is connected to resistor R27, the other end of resistor R27 is connected to 2+, and capacitors C9 and C20 are connected, the other end of C9 is grounded, and the other end of C20 is connected to 3+; Cell_3+ is connected to resistor R37, the other end of resistor R37 is connected to 3+, and capacitors C11 and C21 are connected, the other end of C11 is grounded, and the other end of C21 is connected to 4+; Cell_4+ is connected to resistor R43, the other end of resistor R43 is connected to 4+, and capacitors C13 and C22 are connected, the other end of C13 is grounded, and the other end of C22 is connected to 5+; 5+ is connected to resistor R53, the other end of resistor R53 is connected to 5+, and capacitors C15 and C23 are connected. The other end of C15 is grounded, and the other end of C23 is connected to 6+; Cell_6+ is connected to resistor R59, the other end of resistor R59 is connected to 6+, and capacitors C17 and C29 are connected. The other end of C17 is grounded, and the other end of C29 is connected to 7+; Cell_7+ is connected to resistor R22, the other end of resistor R22 is connected to 7+, and capacitors C8 and C28 are connected. The other end of C8 is grounded, and the other end of C28 is connected to 8+; Cell_8+ is connected to resistor R28, the other end of resistor R28 is connected to 8+, and capacitors C10 and C29 are connected. C27, the other end of C10 is grounded, and the other end of C27 is connected to 9+; Cell_9+ is connected to resistor R38, the other end of resistor R38 is connected to 9+, and is also connected to capacitor C12 and capacitor C26, the other end of C12 is grounded, and the other end of C26 is connected to 10+; Cell_10+ is connected to resistor R44, the other end of resistor R44 is connected to 10+, and is also connected to capacitor C14 and capacitor C25, the other end of C14 is grounded, and the other end of C25 is connected to 11+; Cell_11+ is connected to resistor R54, the other end of resistor R54 is connected to 11+, and is also connected to capacitor C16 and capacitor C24, the other end of C16 is grounded, and the other end of C24 is connected to 12+;Cell_12+ is connected to resistor R60, the other end of which is connected to 12+, and to capacitor C18, the other end of which is grounded.

[0055] In a specific embodiment, Figure 8 As shown, the temperature acquisition unit is adapted to the 12 batteries of the battery pack, and is equipped with 5 temperature acquisition probes (TH1, TH2, TH3, TH4, TH5) and 5 voltage divider resistors (R1, R2, R4, R5, R7); the temperature acquisition probes use TH1-TH5 thermistors (NTCs) with a resistance of 100KΩ and a B value of 4130 at a temperature of 25°C. The chip U1 has a built-in Vref2 output to provide bias current for the NTC used. The 5 GPIO ports of the chip U1 are used for ADC measurement, and the current temperature value is obtained through the built-in function; the specific connection relationship is: Vref2 in the chip U1 is connected to the resistor R1 , R2, R4, R5, R7; the other end of resistor R1 is connected to GPIO1 in chip U1, and is connected to the thermistor TH1, and the other end of the thermistor TH1 is grounded; the other end of resistor R2 is connected to GPIO2, and is connected to the thermistor TH2, and the other end of the thermistor TH2 is grounded; the other end of resistor R4 is connected to GPIO3, and is connected to thermistor TH3, and the other end of the thermistor TH3 is grounded; the other end of resistor R5 is connected to GPIO4, and is connected to thermistor TH4, and the other end of the thermistor TH4 is grounded; the other end of resistor R7 is connected to GPIO5, and is connected to thermistor TH5, and the other end of the thermistor TH5 is grounded.

[0056] On the other hand, in a specific embodiment, a battery box, using the above-mentioned battery management system, includes a box body, a battery pack, a main control PCB board and a slave control PCB board, wherein the main control module is integrated on the main control PCB board, and the slave control module is integrated on the slave control PCB board; the battery pack is placed in the box body, and the main control PCB board and the slave control PCB board are fixed on the top of the battery pack in sequence from top to bottom, wherein the slave control PCB board also includes a spring, one end of the spring is fixed on the side of the slave control PCB board facing the battery pack and connected to the passive balancing unit, and the other end contacts the battery pack; the temperature acquisition probes of the temperature acquisition unit are spaced apart and distributed on the side of the slave control PCB board facing the battery pack. Figure 11-13 shown.

[0057] Furthermore, the battery box is also provided with a module cover plate adapted to the opening of the top surface of the box body, so as to seal the main control PCB board, the slave control PCB board and the battery pack in the box body.

[0058] Furthermore, the module cover plate, the main control PCB board, the slave control PCB board and the box body are fixedly connected by bolts and studs.

[0059] Furthermore, an electrode sheet with good conductivity is provided at one end of the spring, which contacts the positive electrode or negative electrode of each battery in the battery pack.

[0060] In a specific embodiment, the battery box adopts an elastic collection structure, the slave PCB directly contacts the battery cell through the spring, and uses the NTC temperature probe to closely contact the battery cell to achieve accurate measurement of the battery cell voltage and temperature, thereby replacing the traditional wire collection method. Figure 12 As shown, the slave control PCB module 2 integrates the acquisition spring 6, NTC temperature probe 7, battery cell overcurrent protection and AFE analog front-end acquisition circuit, which reduces the number of complex acquisition wiring harnesses and PCBs from a structural perspective, making the module acquisition solution more concise and efficient. At the same time, it optimizes the internal space layout of the battery box and reduces the overall weight of the system. For weight-sensitive applications (such as racing cars), it helps to lightweight the battery box design. Figure 13 As shown, the battery box adopts a modular fastening method to ensure the stable installation of the PCB board. The fasteners M3×5 studs are fixed to the tab support plate 5 by bonding. The battery tabs of the battery pack are bent and placed in the grooves of the tab support plate and fixed by laser welding of copper sheets. The slave control PCB board 2 is fastened to the M3×5 studs by four M3×6 bolts, thereby achieving stable support for the PCB board; NTC temperature probes 7 are distributed at intervals on the bottom surface of the slave control PCB board 2, close to the battery cells 3 to collect their temperatures.

[0061] In addition, to further enhance structural reliability and ensure safe insulation coverage of high-voltage components, a module cover plate 1 made of ABS material (compliant with UL94-2013 fire protection rating, insulation level V0) is used. This cover plate is prepared using a 3D printing additive manufacturing process and is fastened to the lifting lugs of the box body 4 using M4×12 bolts and M4 nuts to prevent the PCB board from detaching from the battery cell tabs due to excessive elastic force of the spring 6, thereby providing double compression protection and ensuring the long-term stable operation of the acquisition system.

[0062] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Reference can be made to the common and similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method description.

[0063] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A battery management system, characterized in that: It includes a master control module and at least one group of slave control modules; The main control module includes an STM32 single-chip microcomputer, a relay control unit, a CAN communication unit, and a daisy-chain communication conversion unit; the STM32 single-chip microcomputer is connected to the relay control unit, the CAN communication unit, and the daisy-chain communication conversion unit respectively; The slave control module includes a slave control AFE unit, a temperature acquisition unit, an enhanced communication unit, a passive balancing unit and a filtering unit; the slave control AFE unit is respectively connected to the temperature acquisition unit, the enhanced communication unit, the passive balancing unit and the filtering unit, the passive balancing unit and the filtering unit are respectively connected to the battery pack, and the enhanced communication unit is connected to the daisy chain communication conversion unit; multiple groups of slave control modules are connected in series through the enhanced communication unit.

2. A battery management system according to claim 1, characterized in that: The slave-controlled AFE unit includes a chip U1, which is equipped with an LDO component. The V+ pin of the chip U1 is connected to the positive electrode of the battery pack, and the V- pin is connected to the negative electrode of the battery pack. The power supply after being stepped down by the LDO component is output to the DRVE pin.

3. A battery management system according to claim 2, characterized in that: The enhanced communication unit includes two external resistors, two terminal resistors, two capacitors, an external transformer U2 and an isoSPI interface; the TD+ pin of the external transformer U2 is connected to the IPA pin of the chip U1, the TD- pin is connected to the IMA pin of the chip U1, and a first terminal resistor is connected between the TD+ pin and the TD- pin, the RD+ pin is connected to the IPB pin of the chip U1, the RD- pin is connected to the IMB pin of the chip U1, and a second terminal resistor is connected between the RD+ pin and the RD- pin, the TCT pin is connected to the first capacitor, the RCT pin is connected to the second capacitor, and the other ends of the two capacitors are grounded respectively, the TX- pin and TX+ pin are respectively connected to the next-level slave control module, and the RX- pin and RX+ pin are respectively connected to the previous-level slave control module; the 1st pin of the isoSPI interface is connected to the Vreg1 pin of the chip U1, the 2nd pin is connected to the ISOND pin of the chip U1, and the 3rd pin is grounded.

4. A battery management system according to claim 3, characterized in that: The daisy chain communication conversion unit includes a chip U4 model LTC6820HMS, a connector CN5, a connector CN2, two decoupling capacitors and a single daisy chain circuit; the single daisy chain circuit includes two external resistors, a terminal resistor, an external transformer and two capacitors; the chip U4 is connected to the SPI pin of the STM32 microcontroller through the connector CN5, the VDDS pin, POL pin, PHA pin and VDD pin of the chip U4 are connected to VCC, and two decoupling capacitors are connected, the IM pin of the chip U4 is connected to the terminal resistor and the third pin of the external transformer, and the IP pin is connected to the terminal resistor The other end and the 1st pin of the external transformer, the ICMP pin is grounded through a second external resistor and connected to one end of the first external resistor, and the IBIAS pin is connected to the other end of the first external resistor; the 2nd and 5th pins of the external transformer are grounded through a capacitor respectively, the 4th pin is connected to the 2nd pin of the connector CN2, and the 6th pin is connected to the 1st pin of the connector CN2; the 1st pin of the connector CN2 is connected to the TX+ pin of the external transformer U2 in the enhanced communication unit, and the 2nd pin is connected to the TX- pin of the external transformer U2 in the enhanced communication unit, which is used to connect the slave control module in series for isoSPI communication.

5. A battery management system according to claim 2, characterized in that: The passive balancing unit includes several groups of balancing modules, each group of balancing modules includes a field effect transistor P-MOS, a first current limiting resistor, a second current limiting resistor, a discharge resistor and a light-emitting diode; the source of the field effect transistor P-MOS is connected to the positive electrode of a battery in the battery pack, the gate is connected to one end of the first current limiting resistor, the other end of the first current limiting resistor is connected to a balancing pin of the chip U1, the drain is connected to the anode of the light-emitting diode and one end of the discharge resistor, the other end of the discharge resistor is connected to the positive electrode of another battery in the battery pack, the cathode of the light-emitting diode is connected to one end of the second current limiting resistor, and the other end of the second current limiting resistor is connected to the positive electrode of another battery in the battery pack.

6. A battery management system according to claim 2, characterized in that: The filtering circuit includes several groups of grounded capacitors and several groups of RC low-pass filters composed of filter resistors and filter capacitors; one end of the filter resistor is connected to the positive pole of a battery in the battery pack, the other end is connected to an acquisition pin of the chip U1, and the other end is simultaneously connected to one end of the grounded capacitor and one end of the filter power supply. The other end of the filter capacitor is connected to one end of the filter capacitor in another group of RC low-pass filters, and the other end of the grounded capacitor is grounded.

7. A battery management system according to claim 2, characterized in that: The temperature acquisition unit includes several groups of temperature acquisition probes and voltage divider resistors; one end of the voltage divider resistor is connected to the VREF2 pin of the chip U1, and the other end is connected to the GPIO1 pin built into the chip U1 and one end of the temperature acquisition probe, and the other end of the temperature acquisition probe is grounded.

8. A battery management system according to claim 2, characterized in that: The slave control module also includes a debugging section to set the measurement points Vref1, Vref2 and BIAS1. When Vref1 = 3V, the chip U1 core enters the Measure state. When Vref2 = 3V, the chip U1 auxiliary measurement channel is turned on. When IBIAS1 = 2V, isoSPI in chip U1 is enabled.

9. A battery management system according to claim 2, characterized in that: The slave control module further includes a fuse unit, which includes a plurality of fuses. One end of each fuse is connected to a collection pin of the chip U1, and the other end is connected to the battery pack.

10. A battery box, characterized in that: A battery management system according to any one of claims 1 to 9 is applied, comprising a housing, a battery pack, a main control PCB board and a slave control PCB board, wherein the main control module is integrated on the main control PCB board and the slave control module is integrated on the slave control PCB board; the battery pack is placed in the housing, and the main control PCB board and the slave control PCB board are fixed above the battery pack, wherein the slave control PCB board further comprises a spring, one end of the spring is fixed on a side of the slave control PCB board facing the battery pack and connected to a passive balancing unit, and the other end contacts the battery pack; the temperature acquisition units are spaced apart on the side of the slave control PCB board facing the battery pack.

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