Inverter device

Abstract

The invention discloses an inverter device. The inverter device includes a wiring substrate having a wiring layer, a wiring layer, and a wiring layer, transistors arranged in an intermediate layer of the wiring substrate, and having a source region and a drain region surrounding the source region on one surface of each of the transistors, and a capacitor. The first power supply wiring extends in the first direction from one terminal of the capacitor, and is connected to the drain of the transistor in a drain region of the transistor closer to the first direction side than the source region. An output wiring connected to the source of the transistor extends in the second direction, and is connected to the drain of the transistor in a drain region of the transistor closer to the first direction side than the source region. The second power supply wiring extends in the second direction from the other terminal of the capacitor and is connected to the source of the transistor. The purpose of the present invention is to reduce the inductance of an inverter device.

Description

Technical Field

[0001] The technology disclosed in this specification belongs to the technical field related to inverter devices. Background Art

[0002] As the power density of inverter devices increases, higher output is being promoted, and therefore, a technology for reducing the inductance of the inverter devices is required.

[0003] Patent Document 1 discloses a technique for reducing wiring inductance in a DC-AC inverter by arranging two wiring conductors close to each other and in parallel, allowing currents to flow in different directions through the wiring conductors, thereby utilizing mutual inductance to reduce wiring inductance.

[0004] Patent Document 1: Japanese Patent Application Laid-Open No. 2003-259656 Summary of the Invention

[0005] -Technical problem to be solved by the invention-

[0006] Conventional inverter devices are constructed by mounting transistors on the surface of a substrate. However, mounting transistors on the surface of a substrate presents a problem in that the self-inductance cannot be sufficiently reduced due to the influence of the bonding wires connecting the transistors to the substrate.

[0007] The technology disclosed in this specification is developed to solve the above-mentioned problem, and its purpose is to provide an inverter device with reduced inductance.

[0008] -Technical solutions for solving technical problems-

[0009] To solve the above-mentioned technical problems, the technology disclosed in this specification is directed to an inverter device. The inverter device includes a wiring substrate, a first transistor, a second transistor, and a capacitor. The wiring substrate has a first wiring layer, a second wiring layer, and a third wiring layer arranged in a stacked state. The first transistor and the second transistor each have a source region and a drain region surrounding the source region on one surface. The first transistor and the second transistor are arranged in an intermediate layer between the second wiring layer and the third wiring layer with the one surface facing the second wiring layer. One terminal of the capacitor is connected to a first power supply wiring line in the first wiring layer, and the other terminal of the capacitor is connected to a second power supply wiring line in the first wiring layer. The first power supply wiring line extends from the one terminal of the capacitor in a first direction in the first wiring layer and is connected to the drain of the first transistor. An output wiring line connected to the source of the first transistor extends in a second direction opposite to the first direction in the second wiring layer and is connected to the drain of the second transistor. The second power supply wiring line extends from the other terminal of the capacitor in the second direction in the first wiring layer and is connected to the source of the second transistor.

[0010] By adopting such a structure, a physically narrow loop can be achieved, focusing on the loop circuit formed by the capacitor, the first transistor, and the second transistor, thereby reducing the self-inductance. Moreover, the direction of the current flowing through the first power supply wiring of the first wiring layer can be made opposite to the direction of the current flowing through the output wiring. Similarly, the direction of the current flowing through the output wiring can be made opposite to the direction of the current flowing through the second power supply wiring of the first wiring layer. Thus, the mutual inductance is subtracted from the self-inductance, thereby reducing the composite inductance value. Thus, by adopting the structure of this embodiment, it is possible to achieve both low inductance and high thermal conductivity of the inverter device.

[0011] -Effects of the Invention-

[0012] As described above, according to the technology disclosed in this specification, the inductance of the inverter device can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a circuit diagram of an inverter device;

[0014] Figure 2 is a side sectional view showing an example of the structure of an inverter device;

[0015] Figure 3 is a top view of the inverter device as viewed from above the second wiring layer;

[0016] Figure 4is a bottom view of the inverter device as viewed from below the fifth wiring layer;

[0017] Figure 5 is a diagram for explaining the flow of current in an inverter device;

[0018] Figure 6 This is another example of the configuration of the inverter device 1. Figure 2 A side sectional view of

[0019] Figure 7 This is another example of the configuration of the inverter device 2. Figure 2 A side sectional view of

[0020] Figure 8 is a top view of the inverter device as viewed from above the first wiring layer;

[0021] Figure 9 It is along Figure 8 Cross-sectional view taken along line IX-IX.

[0022] - Explanation of symbols -

[0023] 1 - inverter device; 11 - first power supply wiring; 12 - second power supply wiring; OUT - output wiring; L1 - wiring layer (first wiring layer); L2 - wiring layer (second wiring layer); L5 - wiring layer (third wiring layer); Q - transistor; Q1 - transistor (first transistor); Q2 - transistor (second transistor). DETAILED DESCRIPTION

[0024] Below, exemplary embodiments are described in detail with reference to the accompanying drawings. It should be noted that the description of the following embodiments is essentially only an example, and the description is centered on the structure related to the subject of the technology to be disclosed. In addition, technical elements that are different from the subject of the technology to be disclosed are sometimes simplified in illustration or description, or the description is omitted, but there is no intention to limit the scope of the technology to be disclosed. In this disclosure, the term "connection" is used as a concept that broadly includes electrical connection. For example, in addition to the case where there is direct connection between each other, it also includes the case where there is indirect connection between each other via vias, etc.

[0025] Figure 1 This is a circuit diagram of an inverter device according to an embodiment. Figure 2 is a side sectional view showing the structure of the inverter device (for example, along Figure 3 sectional view taken along line II-II).

[0026] like Figure 1As shown, in this example, the inverter device 1 is a two-level inverter that outputs DC power from a DC power source such as a battery (not shown) into three-phase (U-phase, V-phase, and W-phase) AC power. The inverter device 1 can be used for any purpose, including, for example, driving a vehicle or starting an engine (e.g., an integrated starter generator (ISG)).

[0027] like Figure 1 and Figure 2 As shown, inverter device 1 includes a wiring board 2, transistors Q1 to Q6, and capacitors C1 to C3. It should be noted that in the following description, when transistors Q1 to Q6 are not distinguished, they may be referred to as "transistors Q." Similarly, when capacitors C1 to C3 are not distinguished, they may be referred to as "capacitors C."

[0028] - Wiring substrate -

[0029] The wiring substrate 2 is, for example, a multilayer wiring substrate (eg, a printed circuit board) having six wiring layers. Figure 2 As shown, the thickness direction of the wiring substrate is defined as the vertical direction, and the wiring layer (first wiring layer) on the main surface (topmost) where capacitors C1 to C3 are arranged is called wiring layer L1. Furthermore, wiring layers L2 to L6 (second to sixth wiring layers) are formed in sequence downward from wiring layer L1, with an insulating layer (e.g., a layer formed of resin) sandwiched between each wiring layer. To improve heat dissipation performance, the insulating layer 4 between wiring layers L5 and L6 is preferably made of glass epoxy resin or a highly thermally conductive resin. Figure 2 The example in which an insulating TIM (Thermal Interface Material) is used as the insulating layer 4 between the wiring layer L5 and the wiring layer L6 is shown. In addition, a heat sink 5 is attached to the lower surface of the wiring layer L6.

[0030] -capacitance-

[0031] Capacitors C1 to C3 are provided between first power supply wiring 11, which is supplied with a positive power supply voltage P(+) from a battery (not shown), and second power supply wiring 12, which is supplied with a negative power supply voltage N(-) from a battery (not shown). Capacitor C1 is a capacitor for the U phase and is provided in parallel with the series circuit of transistors Q1 and Q2 connected in series. Capacitor C2 is a capacitor for the V phase and is provided in parallel with the series circuit of transistors Q3 and Q4 connected in series. Capacitor C3 is a capacitor for the W phase and is provided in parallel with the series circuit of transistors Q5 and Q6 connected in series.

[0032] -transistor-

[0033] Figure 3 is a top view of the inverter device 1 as viewed from above the wiring layer L2. Figure 4 This is a bottom view of the inverter device 1 as viewed from below the wiring layer L5 . Figure 8 This is a plan view of the inverter device 1 as viewed from above the wiring layer L1. Figure 9 It is along Figure 8 The cross-sectional view taken along the IX-IX line. Figure 3 、 Figure 4 as well as Figure 8 In FIG, the positions of transistors Q1 to Q6 are indicated by dotted lines. Figure 3 、 Figure 4 as well as Figure 8 As shown in FIG, the X direction and the Y direction are defined as directions perpendicular to the up and down directions, and the X direction and the Y direction are perpendicular to each other. Figure 3 The direction on the left of the figure is called X1 direction, and the direction in the X direction is Figure 3 The direction on the right of the figure is called X2 direction, and the direction in the Y direction is Figure 3 The direction above the figure is called Y1 direction, and the direction in the Y direction is Figure 3 The direction below the accompanying drawings is referred to as the Y2 direction for explanation.

[0034] like Figures 2 to 4 、 Figure 8 、 Figure 9 As shown, transistors Q1 to Q6 for the U-phase, V-phase, and W-phase are arranged in the middle layer between wiring layer L2 and wiring layer L5. In this example, wiring layer L3, wiring layer L4, and the insulating layer X3 between L3 and L4 constitute the "middle layer." Specifically, when viewed from above, transistors Q1 to Q6 are arranged in the X-Y direction in the middle layer. In this example, transistors Q1 and Q2 for the U-phase are arranged in the X-direction, transistors Q3 and Q4 for the V-phase are arranged in the X-direction, and transistors Q5 and Q6 for the W-phase are arranged in the X-direction. The group of transistors Q1 and Q2 for the U-phase, the group of transistors Q3 and Q4 for the V-phase, and the group of transistors Q5 and Q6 for the W-phase are arranged in the order of U-phase, V-phase, and W-phase in the Y2 direction.

[0035] The transistor Q is a vertically structured N-type power MOSFET. In this example, the transistor Q is composed of a semiconductor chip Qa (referred to simply as "chip" in the accompanying drawings) and a lead frame Qb. A source electrode is provided on one surface of the semiconductor chip Qa, and a drain electrode is provided on the other surface of the semiconductor chip Qa. The lead frame Qb is made of, for example, copper and is arranged to cover the other surface (drain electrode) of the semiconductor chip Qa (see FIG. 1 ). Figure 2) is formed into a U-shape in a side cross-sectional view and is connected to the drain of the semiconductor chip Qa. That is, the lead frame Qb and the drain of the semiconductor chip Qa have the same potential.

[0036] In other words, one side of the transistor Q includes a source region S with a source terminal and a drain region D with a drain terminal surrounding the source region S. The drain terminal is formed entirely on the other side of the transistor Q. It should be noted that in this disclosure, a "terminal" refers to an outlet for current flow, and the specific form or method of the terminal is not particularly limited. For ease of explanation, the source terminal will sometimes be referred to simply as "source," and the drain terminal will sometimes be referred to simply as "drain."

[0037] In this example, the source region S is rectangular, and the drain region D is arranged as a rectangular frame to surround the source region S. However, the shape of the source region S is not limited to a rectangle. Similarly, the drain region D does not have to surround the entire circumference of the source region, and the drain region D may be partially interrupted. In the following description, one surface is referred to as the "source-drain surface" and the other surface is referred to as the "drain surface." It should be noted that the gate of the transistor Q is provided on the source-drain surface, but this is omitted from the illustration because it is different from the subject matter of the disclosed technology.

[0038] In addition, the source or drain of the transistor Q is connected to each wiring formed in the wiring layer L2 and the wiring layer L5 through a plurality of vias V or lead frames Qb. However, in the following description, for the sake of convenience, the description indicating the connection via vias V or lead frames Qb is sometimes omitted. The same is true for the connection between the wirings of each wiring layer. The diagram and / or the description indicating the connection via vias V or lead frames Qb are sometimes omitted. It should be noted that in Figure 2 and Figure 9 In order to facilitate understanding of the drawings, wirings to which common signals or voltages are applied are marked with common hatching. Figure 2 and Figure 9 In the figure, wirings with common hatching are connected to each other via vias (including vias not shown).

[0039] Next, transistors Q1 to Q6 will be described. It should be noted that the structure of the transistors is common to the U-phase, V-phase, and W-phase, and here, the transistors of one phase (the U-phase) will be described.

[0040] like Figure 2 or Figure 9As shown, the source-drain surface of transistor Q1 is arranged opposite to wiring layer L2, and the drain surface of transistor Q1 is arranged opposite to wiring layer L5. In other words, transistor Q1 is arranged with its source-drain surface facing upward. The source of transistor Q1 is connected to output wiring OUT of wiring layer L2. In addition, the drain of transistor Q1 on the source-drain surface is connected to first power supply wiring 11 on wiring layer L2, and the drain of transistor Q1 on the drain surface is connected to first power supply wiring 11 on wiring layer L5. In addition, transistor Q1 is arranged so that the source region S of the source-drain surface is located closer to the X1 side than terminal C11 (the terminal on the X1 side) of capacitor C1.

[0041] The source-drain surface of transistor Q2 is arranged opposite wiring layer L2, and the drain surface of transistor Q2 is arranged opposite wiring layer L5. In other words, transistor Q2 is arranged with its source-drain surface facing upward. The source of transistor Q2 is connected to second power supply wiring 12 of wiring layer L2. Furthermore, the drain of transistor Q2 on its source-drain surface is connected to output wiring OUT on wiring layer L2, and the drain of transistor Q2 on its drain surface is connected to output wiring OUT on wiring layer L5. Furthermore, transistor Q2 is arranged so that the source region S of its source-drain surface is located closer to the X2 side of terminal C12 (the terminal on the X2 side) of capacitor C1 in the X2 direction.

[0042] It should be noted that the V-phase transistors Q3 and Q4 are configured similarly to the U-phase transistors Q1 and Q2, and detailed description thereof is omitted. Similarly, the W-phase transistors Q5 and Q6 are configured similarly to the U-phase transistors Q1 and Q2.

[0043] -wiring-

[0044] The first power supply wiring 11 is connected to a terminal C11 of the capacitor C1 in the wiring layer L1, and extends from the terminal C11 in the X1 direction (equivalent to the first direction). Specifically, the length of the first power supply wiring 11 extends from the terminal C11 of the capacitor C1 to a position exceeding the end of the transistor Q1 on the X1 direction side. In addition, the first power supply wiring 11 is a wiring having a width wider than the width of the transistor Q1, and the first power supply wiring 11 is arranged in a manner covering the transistor Q1 when viewed from above. Furthermore, the first power supply wiring 11 of the wiring layer L1 is connected to the first power supply wiring 11 of the wiring layer L2 via the via V1 at a position closer to the X1 direction side than the source region S of the transistor Q1. The first power supply wiring 11 of the wiring layer L2 is connected to the drain of the transistor Q1 at the drain region D of the transistor Q1 on the X1 direction side than the source region S. Specifically, at Figure 3 or Figure 8In the top view of FIG, the first power supply wiring 11 is connected to the drain region D of the transistor Q1 in the region where the first power supply wiring 11 and the drain region D of the transistor Q1 overlap. As a result, a current in the X1 direction flows through the first power supply wiring 11 of the first wiring layer L1 (see FIG. Figure 5 ).

[0045] In addition, the first power supply wiring 11 of the wiring layer L2 is connected to the first power supply wiring 11 of the wiring layer L5 via the via V2 that penetrates the wiring layers. Furthermore, the first power supply wiring 11 of the wiring layer L5 is connected to the drain of the transistor Q1 at the drain surface of the transistor Q1. Specifically, Figure 4 In the bottom view of FIG, the first power supply wiring 11 is connected to the drain of the transistor Q1 in a region where the first power supply wiring 11 overlaps with the drain region D of the transistor Q1.

[0046] The same applies to the relationship between the first power supply wiring 11 and the V-phase transistor Q3 and the relationship between the first power supply wiring 11 and the W-phase transistor Q5 , and detailed descriptions thereof are omitted.

[0047] The output wiring OUT is formed in the wiring layer L2 and the wiring layer L5, and the output of each phase of the inverter device 1 is output from the output wiring OUT. Figure 3 As shown, the output wiring is arranged in a manner overlapping with the source region S of the transistor Q1 in a top view, and is connected to the source of the transistor Q1 in the overlapping region. Moreover, the output wiring OUT of the wiring layer L2 extends from the position overlapping with the source region S of the transistor Q1 in the X2 direction (equivalent to the second direction), and is connected to the drain of the transistor Q2 at the drain region D of the transistor Q2 which is closer to the X1 direction side than the source region. Specifically, Figure 3 In a top view, the output wiring OUT extends to the drain region D on the X1 side of transistor Q2 and is connected to the drain of transistor Q2 in an area overlapping with the drain region D of transistor Q2. Furthermore, in a top view, the first power supply wiring 11 of wiring layer L1 and the output wiring OUT of wiring layer L2 overlap vertically and run parallel to each other. Furthermore, the overlap width in the Y direction between the first power supply wiring 11 of wiring layer L1 and the output wiring OUT of wiring layer L2 is maximized. This maximizes the effectiveness of reducing inductance by leveraging mutual inductance.

[0048] Furthermore, the output wiring OUT of the wiring layer L2 is connected to the output wiring OUT of the wiring layer L5 via the via V3 penetrating the wiring layer. Furthermore, the output wiring OUT of the wiring layer L5 is connected to the drain of the transistor Q2 at the drain surface of the transistor Q2. Specifically, Figure 4In the bottom view of , the output wiring OUT of the wiring layer L5 is connected to the drain of the transistor Q2 in a region where the output wiring OUT of the wiring layer L5 overlaps with the drain region D of the transistor Q2.

[0049] Note that the same applies to the relationship between the second power supply wiring 12 and the output wiring OUT and the V-phase transistor Q4 , and the relationship between the second power supply wiring 12 and the output wiring OUT and the W-phase transistor Q6 , and detailed descriptions thereof are omitted.

[0050] The second power supply wiring 12 is connected to the other terminal C12 of the capacitor C1 in the wiring layer L1 and extends from the terminal C12 in the X2 direction. It is also provided in the wiring layer L2 through the via V. The second power supply wiring 12 of the wiring layer L2 is connected to the source of the transistor Q2 at the source region S of the transistor Q2. Specifically, Figure 3 or Figure 8 In the top view, the second power wiring 12 is connected to the source of transistor Q2 in the area where it overlaps with the source region S of transistor Q2. Consequently, current in the X1 direction flows through the second power wiring 12 of wiring layer L1. It should be noted that, in a top-down view, the second power wiring 12 of wiring layer L1 and the output wiring OUT of wiring layer L2 overlap vertically and have a parallel section. Furthermore, the overlap width in the Y direction between the first power wiring 11 of wiring layer L1 and the output wiring OUT of wiring layer L2 is ensured to be the maximum possible width. This enhances the effect of reducing inductance by utilizing mutual inductance.

[0051] -Effects of the implementation method-

[0052] As described above, the inverter device 1 of this embodiment includes a wiring substrate 2, multiple transistors Q and a capacitor C, wherein the wiring substrate 2 has a wiring layer L1 (equivalent to the first wiring layer), a wiring layer L2 (equivalent to the second wiring layer) and a wiring layer L5 (equivalent to the third wiring layer), and the multiple transistors Q are arranged in the middle layer between the wiring layer L2 and the wiring layer L5 of the wiring substrate 2.

[0053] When focusing on the U phase, the first power supply wiring 11 extends in the first direction from one terminal C11 of capacitor C1 in wiring layer L1 and is connected to the drain of transistor Q1 at the drain region D on the X1 side of transistor Q1's source region S. The output wiring OUT connected to the source of transistor Q1 extends in the X2 direction in wiring layer L2 and is connected to the drain of transistor Q2 at the X1 side of transistor Q2's source region S. The second power supply wiring 12 extends in the second direction from the other terminal C12 of capacitor C1 in wiring layer L1 and is connected to the source of transistor Q2. By adopting this structure, when focusing on the loop circuit formed by capacitor C1, transistor Q1, and transistor Q2, a physically narrow loop can be achieved, thereby reducing self-inductance.

[0054] Furthermore, the first power supply wiring 11 of wiring layer L1, through which current flows in the X1 direction, runs in parallel with the output wiring OUT of wiring layer L2, through which current flows in the X2 direction. Similarly, the output wiring OUT of wiring layer L2, through which current flows in the X2 direction, runs in parallel with the second power supply wiring 12 of wiring layer L1, through which current flows in the X1 direction. In other words, the directions of current flowing in parallel wiring on wiring layers L1 and L2 can be made opposite. This subtracts the mutual inductance from the self-inductance, thereby reducing the combined inductance of inverter device 1.

[0055] Thus, by adopting the structure of this embodiment, it is possible to achieve both low inductance and high thermal conductivity in the inverter device 1. As described above, the V phase and the W phase are also configured in the same manner as the U phase, and the same effects can be obtained.

[0056] Furthermore, by adopting the configuration of this embodiment, the first power supply wiring 11 , the second power supply wiring 12 , and the output wiring OUT can be made wider while the inverter device 1 can be compactly configured, thereby achieving miniaturization of the inverter device 1 .

[0057] <Other implementation methods>

[0058] As mentioned above, the above embodiments are merely examples and should not be interpreted as limiting the scope of the present disclosure. The scope of the present disclosure is defined by the scope of the claims, and modifications and variations that fall within the equivalent scope of the claims are included within the scope of the present disclosure.

[0059] For example, in the above embodiment, if Figure 2 As shown, the transistor Q includes a U-shaped lead frame Qb in a side cross-sectional view, but is not limited thereto. Figure 6As shown in (Variation 1), the shape of the lead frame Qb may be a rectangle whose sides in the X direction are longer than the sides in the X direction of the semiconductor chip Qa in a side cross-sectional view. In this case, as in the above-described embodiment, the width of the lead frame Qb in the Y direction may be wider than the sides in the Y direction of the semiconductor chip Qa, or may be the same as the width of the semiconductor chip Qa.

[0060] exist Figure 6 In the structure of, for example, the drain (lead frame Qb) of the drain-source surface of the transistor Q1 and the first power supply wiring 11 of the wiring layer L2 are also connected through the via V. Similarly, the drain (lead frame Qb) of the drain-source surface of the transistor Q2 and the output wiring OUT of the wiring layer L5 are connected through the via V. The other structures are the same as Figure 2 same.

[0061] In addition, if Figure 7 As shown in (Variation 2), a structure in which the transistor Q2 is reversed can also be adopted. In this case, the difference from the above embodiment lies in the connection between the output wiring OUT and the transistor Q2, and the connection between the transistor Q2 and the second power supply wiring 12. It should be noted that Figure 7 is equivalent to the second variant Figure 2 The cross-sectional view of Figure 5 Similarly, the direction of current flow is represented by a dotted line.

[0062] Specifically, the output wiring OUT extends in the X2 direction from transistor Q1 to the drain region D of transistor Q2 in wiring layer L2. When viewed from above, the output wiring OUT is connected to the drain of transistor Q2 in a region overlapping with the drain region D of transistor Q2. In this second variation, when viewed from above, the first power supply wiring 11 of wiring layer L1 and the output wiring OUT of wiring layer L2 also overlap vertically and are provided in parallel.

[0063] Furthermore, the source of transistor Q2 is connected to second power supply wiring 12 provided in wiring layer L5, and is also connected to second power supply wiring 12 in wiring layer L1 via a via or the like at a location closer to the X2 direction than the source region of transistor Q2. Similar to the above embodiment, second power supply wiring 12 in wiring layer L1 extends in the second direction from the other terminal C12 of capacitor C1 in wiring layer L1. In other words, the output wiring OUT of wiring layer L2 overlaps vertically with the second power supply wiring 12 in wiring layer L1, with a parallel section provided.

[0064] The same effects as those of the above-described embodiment can also be obtained in the configurations of Modifications 1 and 2. That is, both low inductance and high thermal conductivity of the inverter device 1 can be achieved.

[0065] Industrial Applicability

[0066] The technology disclosed in this specification can reduce the inductance of an inverter device and is therefore extremely useful.

Claims

1. An inverter device, characterized in that: The inverter device includes a wiring substrate, a first transistor, a second transistor, and a capacitor. The wiring substrate is provided with a first wiring layer, a second wiring layer, and a third wiring layer arranged in a stacked state. The first transistor and the second transistor each have a source region and a drain region surrounding the source region on one surface thereof, and the first transistor and the second transistor are arranged in an intermediate layer between the second wiring layer and the third wiring layer with the one surface thereof facing the second wiring layer. One terminal of the capacitor is connected to the first power supply wiring of the first wiring layer, and the other terminal of the capacitor is connected to the second power supply wiring of the first wiring layer. The first power supply wiring extends in the first wiring layer from one terminal of the capacitor in a first direction, and the first power supply wiring is connected to the drain of the first transistor at the drain region of the first transistor that is closer to the first direction than the source region. An output wiring connected to the source of the first transistor extends in a second direction opposite to the first direction in the second wiring layer and is connected to the drain of the second transistor on the first direction side relative to the source region. The second power supply wiring extends from the other terminal of the capacitor in the first wiring layer toward the second direction, and the second power supply wiring is connected to the source of the second transistor.

2. The inverter device according to claim 1, wherein: The first power supply wiring is connected to each other through a via connecting the second wiring layer and the third wiring layer, and the first power supply wiring is connected to the drain of the first transistor in the third wiring layer.

3. The inverter device according to claim 1, wherein: The output wiring is connected to each other through a via connecting the second wiring layer and the third wiring layer, and the output wiring is connected to the drain of the second transistor in the third wiring layer.

4. An inverter device, characterized in that: The inverter device includes a wiring substrate, a first transistor, a second transistor, and a capacitor. The wiring substrate is provided with a first wiring layer, a second wiring layer, and a third wiring layer arranged in a stacked state. A source region is provided on one surface of each of the first transistor and the second transistor, and a drain region is provided on the other surface of each of the first transistor and the second transistor. The first transistor and the second transistor are arranged in an intermediate layer between the second wiring layer and the third wiring layer. One terminal of the capacitor is connected to the first power supply wiring of the first wiring layer, and the other terminal of the capacitor is connected to the second power supply wiring of the first wiring layer. The one surface of the first transistor is arranged opposite to the second wiring layer, and the other surface of the second transistor is arranged opposite to the second wiring layer. The first power supply wiring extends from one terminal of the capacitor in the first wiring layer in a first direction and is connected to the drain of the first transistor. an output wiring connected to the source of the first transistor extending in a second direction opposite to the first direction in the second wiring layer and connected to the drain of the second transistor; The second power supply wiring extends from the other terminal of the capacitor in the first wiring layer toward the second direction and is connected to the source of the second transistor.

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