Ultra-wideband small-size low-insertion-loss reconfigurable radio frequency delay line

Abstract

The application provides a kind of ultra-wideband small size low insertion loss reconfigurable radio frequency delay ware, it is related to the technical field of delay ware chip, including two switchable adjustable attenuation units and multiple adjustable delay units connected together;The input end of the first switchable adjustable attenuation unit is the radio frequency input end, and the output end of the second switchable adjustable attenuation unit is the radio frequency output end, and multiple adjustable delay units are connected between the first switchable adjustable attenuation unit and the second switchable adjustable attenuation unit;The switchable adjustable attenuation unit adopts MOS tube switch array, and the MOS tube switch array includes n MOS tubes with different widths in parallel, and the adjustment of attenuation and impedance is realized by switching the MOS tube switch array;The adjustable delay unit adopts T type Π type combination LC network.The application has the advantages of expanding the working frequency band, reducing the insertion loss of large delay and reducing the area.

Description

Technical Field

[0001] This invention relates to the field of delay chip technology, and more specifically, to an ultra-wideband, small-size, low-insertion-loss reconfigurable radio frequency delay. Background Technology

[0002] In fields such as radar phased arrays, delay chip is used to provide precise time delay control to achieve true time-delay beamforming, thereby meeting the requirements of broadband beamforming. This ensures that the beam can maintain a stable pointing and shape over a wide frequency band, avoids beam squint effect, and improves the pointing accuracy and target positioning capability of the radar.

[0003] In the existing technology, delay chips are divided into active delay and passive delay. Active delay circuits use inverters and other active devices to achieve controllable group delay. Their bandwidth is affected by the amplifier and is therefore relatively narrow. Passive delay chips are composed of passive devices such as switches and inductor-capacitor groups. They have a wider bandwidth, but their chip area is larger. Meanwhile, existing technologies also have the following drawbacks: RF switches have capacitive parasitic capacitance due to the MOSFETs. To achieve a fixed delay across the entire bandwidth, an inductor needs to be added to offset the capacitance within the switch band, which occupies a large area. Furthermore, conventional switch-switching delay circuits have two paths—delay state and reference state—and the matching inductor and wiring increase the vertical dimension, thus increasing the delay unit area. Using switches to switch between the delay and reference states introduces two additional insertion losses per delay unit, resulting in significant link insertion losses. Conventional delay circuits using LCL networks to widen bandwidth have a simpler structure and can achieve a fixed delay within a certain frequency band, but their delay curve decreases with increasing frequency, limiting high-frequency performance and resulting in insufficient bandwidth. Traditional switch-switching chips lack internal passive switching components, making performance tuning impossible during testing. Actual chip performance often differs from simulation, potentially leading to poor performance.

[0004] Therefore, how to expand the operating frequency band, reduce the insertion loss of large delays, and reduce the area has become an urgent problem to be solved. Summary of the Invention

[0005] The purpose of this invention is to provide an ultrawideband, small-size, low-insertion-loss reconfigurable radio frequency delay that can expand the operating frequency band, reduce the insertion loss of large delays, and reduce the area.

[0006] This invention is achieved through the following technical solution:

[0007] An ultrawideband, small-size, low-insertion-loss reconfigurable radio frequency delay includes two switchable adjustable attenuation units and multiple adjustable delay units connected in series.

[0008] The first switch-adjustable attenuation unit's input is the RF input, the second switch-adjustable attenuation unit's output is the RF output, and multiple adjustable delay units are connected in series between the first switch-adjustable attenuation unit and the second switch-adjustable attenuation unit.

[0009] The adjustable attenuation unit with switching capability uses a MOSFET switching array, which consists of n MOSFETs of different widths connected in parallel. The attenuation and impedance are adjusted by switching the MOSFET switching array.

[0010] The adjustable delay unit adopts a T-type / Π-type combined LC network.

[0011] Preferably, among the n parallel MOS transistors of different widths, the width of the i-th MOS transistor is... , .

[0012] Preferably, the method for adjusting the attenuation and impedance by switching the MOSFET array is as follows:

[0013] By controlling the on / off state of n MOS transistors with high and low voltage levels respectively, the conduction of MOS transistors with different numbers of transistors is achieved, forming a configuration other than all being turned off. Different combinations of values ​​can be used to achieve Adjustment of the attenuation value.

[0014] Preferably, the MOS transistor switch array comprises four MOS transistors of different widths connected in parallel.

[0015] Preferably, the T-type / Π-type combined LC network includes multiple variable capacitors and multiple inductors;

[0016] The first terminal of the third inductor is grounded. The second terminal of the third inductor is connected to the first terminal of the first variable capacitor and the first terminal of the second variable capacitor. The second terminal of the first variable capacitor is connected to the first terminal of the third variable capacitor and the first terminal of the fourth inductor and serves as the input terminal of the adjustable delay unit. The second terminal of the second variable capacitor is connected to the first terminal of the fourth variable capacitor and the first terminal of the fifth inductor and serves as the output terminal of the adjustable delay unit. The second terminals of the third and fourth variable capacitors are grounded. The second terminals of the fifth and fourth inductors are connected to the first terminal of the fifth variable capacitor. The second terminal of the fifth variable capacitor is grounded.

[0017] Preferably, the third inductor, the fourth inductor, and the fifth inductor are arranged in a stacked manner.

[0018] Preferably, the stacking arrangement is as follows:

[0019] The third inductor is a figure-eight shaped inductor;

[0020] The fourth inductor and the fifth inductor share a single coupled spiral inductor.

[0021] The figure-eight inductor is stacked with the coupled spiral inductor.

[0022] Preferably, the coupled spiral inductor comprises a balun made of three turns of metal.

[0023] Preferably, both the coupled spiral inductor and the figure-eight inductor are made of high-layer metal, and the balun is octagonal.

[0024] Preferably, the number of adjustable delay units is eight.

[0025] The technical solution of the present invention has at least the following advantages and beneficial effects:

[0026] This invention replaces the switch-switching delay unit used in conventional large delays with an adjustable delay unit, eliminating the need for one reference state, saving the balancing inductor and trace area for another reference state, and reducing the overall chip area.

[0027] This invention eliminates the need for switches by switching the delay unit. Each delay unit can save the insertion loss of two switch modules, which greatly reduces the overall insertion loss of the chip and reduces the overall loss of the delay chip.

[0028] This invention can compensate for insertion loss errors under different delays by switching the attenuation value of the adjustable attenuation unit, thereby reducing RMS delay parasitic amplitude errors.

[0029] The adjustable delay unit designed in this invention improves the delay flatness at high frequencies, so that the delay at high frequencies can maintain a small change, widening the bandwidth by more than double, increasing its application scenarios, and greatly reducing the area of ​​the delay unit by stacking figure-eight inductors in the delay unit.

[0030] This invention uses adjustable capacitors and adjustable attenuation, allowing the chip to still modify its internal capacitance and attenuation values ​​via SPI configuration during the testing phase, thereby improving latency performance errors and RMS delay parasitic amplitude errors between simulation tests. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the ultrawideband, small-size, low-insertion-loss reconfigurable radio frequency delay provided in Embodiment 1 of the present invention.

[0032] Figure 2 This is a schematic diagram of the principle of the switch-adjustable attenuation unit provided in Embodiment 2 of the present invention;

[0033] Figure 3This is a schematic diagram of the adjustable delay unit provided in Embodiment 2 of the present invention;

[0034] Figure 4 A schematic diagram illustrating the principle of the delay module and high-order Π-type LC network used in the conventional delay unit provided in Embodiment 2 of the present invention;

[0035] Figure 5 A comparison diagram of the delay curves of the adjustable delay unit provided in Embodiment 2 of the present invention and the traditional solution;

[0036] Figure 6 This is a schematic diagram of the inductor of the adjustable delay unit provided in Embodiment 2 of the present invention;

[0037] Figure 7 This is a schematic diagram of the structure of the balun provided in Embodiment 2 of the present invention;

[0038] Figure 8 The delay curve and RMS delay parasitic amplitude error curve provided in Embodiment 2 of the present invention;

[0039] Icons: C1 - First variable capacitor, C2 - Second variable capacitor, C3 - Third variable capacitor, C4 - Fourth variable capacitor, C5 - Fifth variable capacitor, L3 - Third inductor, L4 - Fourth inductor, L5 - Fifth inductor. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0041] Example 1

[0042] This embodiment provides an ultrawideband, small-size, low-insertion-loss reconfigurable radio frequency delay. (See also...) Figure 1 It includes two switchable adjustable attenuation units connected in series and multiple adjustable delay units;

[0043] The first switch-adjustable attenuation unit's input is the RF input, the second switch-adjustable attenuation unit's output is the RF output, and multiple adjustable delay units are connected in series between the first switch-adjustable attenuation unit and the second switch-adjustable attenuation unit.

[0044] The adjustable attenuation unit with switching capability uses a MOSFET switching array, which consists of n MOSFETs of different widths connected in parallel. The attenuation and impedance are adjusted by switching the MOSFET switching array.

[0045] The adjustable delay unit adopts a T-type / Π-type combined LC network.

[0046] In traditional designs, the signal from a switch-type delay chip is input at the RF input terminal and then output after passing through six delay units to achieve the function of delaying the input signal. Each delay unit consists of three parts: a switching module, a delay state module, and a reference state module. The signal is switched between an LCL delay state composed of an inductor and capacitor or a reference state composed of a Π-type resistor, achieving either time delay or pass-through of the input signal. However, this structure suffers from significant insertion loss due to the two switching modules in each delay unit. Furthermore, because the parasitic capacitance of the MOSFET within the RF switch is capacitive, an external inductor is required to offset the parasitic capacitance within the switching band if a fixed delay is desired across the entire bandwidth, further increasing the delay circuit area.

[0047] Compared with conventional switch-type delay chip, the technical solution of this embodiment uses a reconfigurable delay link that only uses one delay path, eliminating the need for an inductor and trace area for another reference state. By switching the capacitance value of the capacitor array under different delays, the delay amount is changed, and the attenuation value of the adjustable attenuation unit is switched to improve the insertion loss error of different delay states. This eliminates the insertion loss caused by two switches in each unit of a conventional delay unit, as well as the vertical dimension caused by the resistor and inductor of the reference state, reducing the overall loss and area of ​​the delay chip. Furthermore, the reconfigurable structure allows the internal capacitance and attenuation value to be modified via SPI configuration during the testing phase, reducing simulation test differences and achieving good delay performance and RMS delay parasitic amplitude.

[0048] Example 2

[0049] This embodiment is based on the technical solution of embodiment 1, and mainly makes further improvements to the settings of the switch-adjustable attenuation unit and the adjustable delay unit.

[0050] In this embodiment, refer to Figure 2 Among the n parallel MOS transistors of different widths, the widths increase by a factor of two in succession. For example, the width of the i-th MOS transistor is... , In a preferred embodiment, the MOSFET switch array includes four MOSFETs of different widths connected in parallel.

[0051] Based on this, the method for adjusting the attenuation and impedance by switching the MOS transistor array is as follows: The on / off state of n MOS transistors is controlled by high and low levels respectively, so that the conduction of MOS transistors with different numbers of transistors is achieved, forming a state other than all being turned off. Different combinations of values ​​can be used to achieve Adjustment of the attenuation value.

[0052] The above scheme primarily utilizes switching to turn different MOSFETs on or off, enabling MOSFETs of varying bit lengths to conduct and altering their internal resistance. This is equivalent to a resistor network of different resistors connected in parallel across the adjustable attenuation unit. By changing the resistance values, different attenuation levels are achieved, and the impedance at both the input and output terminals also changes, thus realizing different attenuation levels and input / output impedances. Adjusting the attenuation level compensates for the different insertion losses under different delay states, reducing the parasitic amplitude of the chip's RMS delay. Changing the input and output impedances mitigates the characteristic impedance changes of the adjustable delay unit caused by variations in the variable capacitor's capacitance. Furthermore, a mismatch between the load impedances Zin and Zout and the characteristic impedance of the adjustable delay unit can negatively impact the delay flatness within the bandwidth.

[0053] As a preferred embodiment, the number of adjustable delay units can be adjusted according to requirements. In the schematic diagram of this embodiment, the number of adjustable delay units is 8. (See attached diagram) Figure 3 The adjustable delay unit includes multiple variable capacitors and multiple inductors;

[0054] The first terminal of the third inductor L3 is grounded. The second terminal of the third inductor L3 is connected to the first terminal of the first variable capacitor C1 and the first terminal of the second variable capacitor C2. The second terminal of the first variable capacitor C1 is connected to the first terminal of the third variable capacitor C3 and the first terminal of the fourth inductor L4 and serves as the input terminal of the adjustable delay unit. The second terminal of the second variable capacitor C2 is connected to the first terminal of the fourth variable capacitor C4 and the first terminal of the fifth inductor L5 and serves as the output terminal of the adjustable delay unit. The second terminals of the third variable capacitor C3 and the fourth variable capacitor C4 are grounded. The second terminals of the fifth inductor L5 and the fourth inductor L4 are connected to the first terminal of the fifth variable capacitor C5. The second terminal of the fifth variable capacitor C5 is grounded.

[0055] In the adjustable delay unit, each variable capacitor is an n-bit binary capacitor array composed of n capacitors, and the equivalent capacitance value of the q-th variable capacitor is... Let q = 1, 2, ..., 5:

[0056]

[0057] in, For the j-th binary address bit, This indicates the capacitance value adjusted to by the qth variable capacitor. Figure 3 The diagram shows the equivalent capacitance of the fourth variable capacitor.

[0058] Among them, the values ​​of the first variable capacitor C1 and the second variable capacitor C2 are the same, denoted by C3var; the values ​​of the third variable capacitor C3 and the fourth variable capacitor C4 are the same, denoted by C1var; and the value of the fifth variable capacitor C5 is denoted by C2var.

[0059] The delay modules used in traditional delay units can be referenced. Figure 4 The delay is achieved by using an LCL network consisting of a coupled inductor and a parallel capacitor. (See reference...) Figure 4 b) This circuit is a higher-order Π-type LC network with a wider bandwidth. It is composed of parallel capacitors and series inductors with mutual coupling. Through the higher-order LC network, the delay bandwidth is further improved.

[0060] In each adjustable delay unit of this embodiment, a Π-type LC network is formed by the fourth inductor L4, the fifth inductor L5, and the third to fifth variable capacitors C3 to C5, and a T-type LC network is formed by the third inductor L3, the first variable capacitor C1, and the second variable capacitor C2. Since the delay is determined by both the L and C values ​​within the adjustable delay unit, different delays can be achieved by switching C1var, C2var, and C3var in the capacitor array while keeping L constant. This combination of T-type and Π-type LC networks effectively widens the bandwidth.

[0061] For a comparison of the delay curves of the adjustable delay unit in this embodiment with those of traditional solutions, please refer to [link / reference needed]. Figure 5 As can be seen, conventional LCL networks, due to their simpler structure, can achieve fixed delay within a certain frequency band under matching conditions, but their delay curve decreases with increasing frequency. Higher-order Π-type LC networks, while offering slightly wider bandwidth, experience a rise in high-frequency delay, still limiting high-frequency performance. The solution in this embodiment, however, maintains relatively small delay variations at high frequencies, more than doubling the bandwidth compared to conventional LCL networks.

[0062] In addition, to reduce the chip area, the inductors in the adjustable delay unit are stacked, that is, the third, fourth and fifth inductors are stacked.

[0063] Specifically, the stacking arrangement is as follows:

[0064] participate Figure 6Because the figure-eight inductor has a point field and a cross field in its upper and lower coils, respectively, with equal magnetic field magnitudes and opposite directions, it exhibits extremely low coupling with surrounding inductors, approaching zero. Therefore, the third inductor is a figure-eight inductor. The fourth and fifth inductors share a coupled spiral inductor with a coupling coefficient of k. The figure-eight inductor is stacked with the coupled spiral inductor. This design significantly reduces the area of ​​the delay unit without altering the performance of each inductor.

[0065] Also see Figure 7 The coupled spiral inductor includes a balun made of three metal turns. A top metal tap in the middle of the balun connects to a capacitor array C2var (the fifth variable capacitor) and then to ground. This, along with the variable parallel-to-ground capacitors C1var (the third and fourth variable capacitors) at the input and output terminals, forms a Π-type LC network. This network is then combined with two variable capacitor arrays C3var (the first and second variable capacitors) connected in series with the figure-eight-shaped ground inductor (the third inductor) to form a T-type LC network.

[0066] On the other hand, both the coupled spiral inductor and the figure-eight inductor are made of high-layer metal, and the balun is octagonal to reduce insertion loss.

[0067] Figure 8 The left side of the graph shows the delay curve of the technical solution in this embodiment. It can be seen that by adjusting the values ​​of C1var, C2var and C3var in different delay states, an ultra-wideband delay of 1-20GHz can be obtained with a step of 10ps. A total of 18 states were selected, covering a range of 10-180ps. Figure 8 The right side of the graph shows the RMS delay parasitic amplitude error curve of this embodiment. It can be seen that after adding an adjustable attenuation unit to adjust the attenuation, the amplitude error of different delay states becomes smaller, and the overall error is within 1.2dB.

[0068] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An ultrawideband, small-size, low-insertion-loss reconfigurable radio frequency delay, characterized in that, It includes two switch-adjustable attenuation units connected in series and multiple adjustable delay units; The first switch-adjustable attenuation unit's input is the RF input, the second switch-adjustable attenuation unit's output is the RF output, and multiple adjustable delay units are connected in series between the first switch-adjustable attenuation unit and the second switch-adjustable attenuation unit. The adjustable attenuation unit with switching capability uses a MOSFET switching array, which consists of n MOSFETs of different widths connected in parallel. The attenuation and impedance are adjusted by switching the MOSFET switching array. The adjustable delay unit uses a T-type / Π-type combined LC network; The T-type / Π-type combined LC network includes a third inductor, a fourth inductor, a fifth inductor, a first variable capacitor, a second variable capacitor, a third variable capacitor, a fourth variable capacitor, and a fifth variable capacitor; The first terminal of the third inductor is grounded. The second terminal of the third inductor is connected to the first terminal of the first variable capacitor and the first terminal of the second variable capacitor. The second terminal of the first variable capacitor is connected to the first terminal of the third variable capacitor and the first terminal of the fourth inductor and serves as the input terminal of the adjustable delay unit. The second terminal of the second variable capacitor is connected to the first terminal of the fourth variable capacitor and the first terminal of the fifth inductor and serves as the output terminal of the adjustable delay unit. The second terminals of the third and fourth variable capacitors are grounded. The second terminals of the fifth and fourth inductors are connected to the first terminal of the fifth variable capacitor. The second terminal of the fifth variable capacitor is grounded.

2. The ultra-wideband, small-size, low-insertion-loss reconfigurable radio frequency delay according to claim 1, characterized in that, Among the n parallel MOS transistors of different widths, the width of the i-th MOS transistor is , .

3. The ultra-wideband, small-size, low-insertion-loss reconfigurable radio frequency delay according to claim 2, characterized in that, The method for adjusting attenuation and impedance by switching the MOSFET array is as follows: By controlling the on / off state of n MOS transistors with high and low voltage levels respectively, the conduction of MOS transistors with different numbers of transistors is achieved, forming a configuration other than all being turned off. Different combinations of values ​​can be used to achieve Adjustment of the attenuation value.

4. The ultrawideband, small-size, low-insertion-loss reconfigurable radio frequency delay according to claim 3, characterized in that, The MOS transistor switch array comprises four MOS transistors of different widths connected in parallel.

5. The ultra-wideband, small-size, low-insertion-loss reconfigurable radio frequency delay according to claim 1, characterized in that, The third inductor, the fourth inductor, and the fifth inductor are arranged in a stacked manner.

6. The ultra-wideband, small-size, low-insertion-loss reconfigurable radio frequency delay according to claim 5, characterized in that, The stacking arrangement is as follows: The third inductor is a figure-eight shaped inductor; The fourth inductor and the fifth inductor share a single coupled spiral inductor. The figure-eight inductor is stacked with the coupled spiral inductor.

7. The ultra-wideband, small-size, low-insertion-loss reconfigurable radio frequency delay according to claim 6, characterized in that, The coupled spiral inductor comprises a balun made of three turns of metal.

8. The ultra-wideband, small-size, low-insertion-loss reconfigurable radio frequency delay according to claim 7, characterized in that, Both the coupled spiral inductor and the figure-eight inductor are made of high-layer metal, and the balun is octagonal.

9. The ultra-wideband, small-size, low-insertion-loss reconfigurable radio frequency delay according to claim 1, characterized in that, The number of adjustable delay units is 8.

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