Improved level conversion circuit capable of automatically detecting transmission direction

Abstract

The invention discloses an improved level conversion circuit capable of automatically detecting a transmission direction, and relates to the technical field of chip power supply, the structure of the level conversion circuit is two groups of transmission circuits which are symmetrically arranged, and the two groups of transmission circuits can perform two-way transmission of signals; the first transmission circuit comprises a port, and the port sends a signal to the second transmission circuit through the level translator and receives a signal of the second transmission circuit through the impedance driver and the edge acceleration control module; the level converter converts an input signal into a signal of a corresponding level domain; a high-impedance path is arranged in the impedance driver; a low-impedance path is arranged in the edge acceleration control module, and the matching problem of different levels of the main control chip and the interface chip is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip power supply, and in particular to an improved level conversion circuit capable of automatically detecting transmission direction. Background Art

[0002] The development of modern electronic technology has led to a gradual decrease in the supply voltage and core voltage of main control chips such as CPUs / MCUs. However, in conventional applications, the signals of the main control chip are generally not used directly. Instead, different interface chips are used to meet the corresponding application environment. In this case, there is the problem of matching the different voltage levels of the main control chip and the interface chip.

[0003] At the same time, due to the promotion of intelligent equipment, the number of IOs of the main control chip is also relatively tight. Summary of the Invention

[0004] In view of this, the present application provides an improved level conversion circuit for automatically detecting the transmission direction to solve the problem of matching different levels of the main control chip and the interface chip.

[0005] The present application provides an improved level conversion circuit for automatically detecting transmission direction, wherein the level conversion circuit includes two symmetrically arranged groups of transmission circuits, and the two groups of transmission circuits can perform bidirectional signal transmission; the port of the first transmission circuit is set to end A, and the end A sends a signal to the second transmission circuit through the level converter A, and receives the signal of the second transmission circuit through the impedance driver A and the edge acceleration control module A; the port of the second transmission circuit is set to end B, and the end B sends a signal to the first transmission circuit through the level converter B, and receives the signal of the first transmission circuit through the impedance driver B and the edge acceleration control module B; wherein: the level converter A and the level converter B are the same device, which can convert the input signal into a signal of the corresponding level domain; the impedance driver A and the impedance driver B are the same device, set a high impedance path, and provide static driving capability for the output signal; the edge acceleration control module A and the edge acceleration control module B are the same device, set a low impedance path, and are closed after the signal conversion is completed For example, in the level conversion circuit provided in at least one embodiment of the present disclosure, the edge acceleration control module A includes two signal input terminals and two signal output terminals; the first signal input terminal receives the signal from the A terminal, and the second signal input terminal receives the signal from the B terminal; the first signal output terminal sends the signal to the A terminal through the MOS transistor PM1, and the second signal output terminal sends the signal to the A terminal through the MOS transistor NM1; the edge acceleration control module B includes two signal input terminals and two signal output terminals; the first signal input terminal receives the signal from the B terminal, and the second signal input terminal receives the signal from the A terminal; the first signal output terminal sends the signal to the B terminal through the MOS transistor PM2, and the second signal output terminal sends the signal to the B terminal through the MOS transistor NM2.

[0006] For example, in the level conversion circuit provided in at least one embodiment of the present disclosure, the MOS transistor PM1 is configured as follows: the gate is connected to the first signal output terminal of the acceleration control module A, the source is connected to the power supply VCC1, and the drain is connected to the drain of the MOS transistor NM1; the MOS transistor NM1 is configured as follows: the gate is connected to the second signal output terminal of the acceleration control module A, the source is grounded; the common end of the drains of the MOS transistor PM1 and the MOS transistor NM1 is connected to the A end.

[0007] For example, in the level conversion circuit provided in at least one embodiment of the present disclosure, the MOS transistor PM2 is configured as follows: the gate is connected to the first signal output terminal of the acceleration control module B, the source is connected to the power supply VCC2, and the drain is connected to the drain of the MOS transistor NM2; the MOS transistor NM2 is configured as follows: the gate is connected to the second signal output terminal of the acceleration control module B, the source is grounded; and the common terminal of the drains of the MOS transistor PM2 and the MOS transistor NM2 is connected to the B terminal.

[0008] For example, in the level conversion circuit provided in at least one embodiment of the present disclosure, the level converter A includes a signal input terminal and two signal output terminals; the signal input terminal receives the signal from the A terminal; the first signal output terminal sends the processed signal to the edge acceleration control module B, and the second signal output terminal sends the processed signal to the impedance driver B; the level converter B includes a signal input terminal and two signal output terminals; the signal input terminal receives the signal from the B terminal; the first signal output terminal sends the processed signal to the edge acceleration control module A, and the second signal output terminal sends the processed signal to the impedance driver A.

[0009] For example, in the level conversion circuit provided in at least one embodiment of the present disclosure, the level converter A is connected to the power supply VCC2 in the second transmission circuit; and the level converter B is connected to the power supply VCC1 in the first transmission circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0011] Figure 1 is a schematic diagram of a level conversion circuit provided by at least one embodiment of the present disclosure; Figure 2 is a circuit diagram of a level converter provided by at least one embodiment of the present disclosure; Figure 3 is a circuit diagram of an impedance driver provided by at least one embodiment of the present disclosure; Figure 4 is a circuit diagram of an edge acceleration control module provided by at least one embodiment of the present disclosure; Figure 5 is a waveform diagram of an N_SPDUP signal provided by at least one embodiment of the present disclosure; Figure 6 This is a P_SPDUP signal waveform diagram provided by at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0012] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0013] In this application, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

[0014] Example In the prior art, the problem of matching different levels between the main control chip and the interface chip is mainly solved by the solution described in the open document CN118100905A, a level conversion circuit that automatically detects the transmission direction. However, the main problem of this structure is the possibility of burning the chip or increasing system power consumption.

[0015] The newly designed circuit in this disclosure mainly includes an impedance driver, a level converter, and an edge acceleration control module. The main function of the level converter is to convert the input signal into a signal of the corresponding level domain; the main function of the impedance driver is to provide a high-impedance path to facilitate the high-low level conversion of the input signal without generating additional power consumption or burning the chip, and to provide static driving capability for the output signal; the main function of the edge acceleration control module is to provide a low-impedance path to accelerate the signal conversion during the signal conversion process from low to high or from high to low, and shut down after the signal conversion is completed to avoid conflicts with the input signal. Since the circuit structure is symmetrical, the working process inside the chip is similar regardless of whether the signal is transmitted from end A to end B or from end B to end A. Therefore, this disclosure uses end A as the input signal for analysis, and the situation where end B is the input can be obtained by mirroring.

[0016] Signal changes can be categorized into two types: from a low level to a high level, and from a high level to a low level. A complete signal transition can be divided into four phases, defined here as PHASE1, PHASE2, PHASE3, and PHASE4. PHASE1 is defined as the phase before the transition, when end A is low and end B is low. PHASE2 is defined as the phase during the transition, when end A is high and end B is low. PHASE3 is defined as the phase after the transition is complete, when end A is high and end B is high. PHASE4 is defined as the phase during the transition, when end A is low and end B is high. By defining these four phases, the signal will always be in one of these four states.

[0017] Phase 1 of the first round: like Figure 1 When a signal source is connected to terminal A and the signal is at a low level, level conversion module A converts the input signal into signals in the corresponding level domain, generating a logical in-phase signal A2 and a logical inverted signal A2_n corresponding to power supply VCC2. The logical inverted signal A2_n sets the voltage level at terminal B to a low level through impedance driver B. When the voltage level at terminal B is set to a low level, level converter B similarly generates a logical in-phase signal B1 and a logical inverted signal B1_n corresponding to power supply VCC1. The logical inverted signal B1_n drives impedance driver A, still keeping terminal A at a low level. During this process, because the internal resistance of the two impedance drivers A is much greater than that of the signal source, the signal at terminal A remains low, and power consumption does not increase significantly.

[0018] Preferably, Figure 4 This is a circuit diagram of an edge acceleration control module provided by at least one embodiment of the present disclosure. Since the edge acceleration control module A and the edge acceleration control module B are the same device, the present disclosure uses a Figure 4 express; It should be noted that: Figure 4 The power supply VCC in is a general representation. Figure 4 When the edge acceleration control module A is indicated, the power supply VCC value is the power supply VCC1. Otherwise, if Figure 4 When the edge acceleration control module B is indicated, the power supply VCC value is the power supply VCC2; Similarly, the power supply VCC that appears in other circuit diagrams has the same explanation.

[0019] The more important signal states in the edge acceleration control module B are as follows: NET1 is 1, NET2 is 0, NET3 is 0, NET4 is 1, NET5 is 0, and NET6 is 0.

[0020] NET1 is 1, resulting in the OR gate output P_SPDUP being high, and NET6 is 0, resulting in the AND gate output N_SPDUP being low. Since the power supplies VCC1 and VCC2 use the same edge acceleration control module, the input logic is also the same; Therefore, in Figure 1 In the level conversion circuit shown, the output N_SPDUP of the AND gate AND, which serves as the second signal output terminal of the edge acceleration control module A and the edge acceleration control module B, is logically low, represented by N_SPDUP_A and N_SPDUP_B respectively; the output P_SPDUP of the OR gate OR, which serves as the first signal output terminal of the edge acceleration control module A and the edge acceleration control module B, is logically high, represented by P_SPDUP_A and P_SPDUP_B respectively, so that the MOS transistors PM1, NM1, PM2 and NM2 are turned off.

[0021] Phase 2 of the first round: When the signal at terminal A transitions from a low level to a high level, level converter A generates a logic inversion signal A2_n. This logic inversion signal A2_n transitions from a high level to a low level, causing the output of impedance driver B to transition from a low level to a high level. However, due to the insufficient driving capability of impedance driver B, the signal speed is insufficient, resulting in a state where the level at terminal A is high and the level at terminal B is low. In this case, edge acceleration control module B is required to drive MOS transistor PM2 to accelerate the edge of the signal at terminal B, thereby increasing the signal conversion speed.

[0022] The working process of edge acceleration control module B is as follows: In this case, the states of the various signals are as follows: NET1 becomes 0, NET2 becomes 1 after a delay, NET3 becomes 1 after a delay, NET4 remains 1, NET5 remains 0, and NET6 remains 0.

[0023] like Figure 4 As shown in the figure, based on the above signal conditions, after NET1 changes from 1 to 0, NET3 is NET1, and it changes from 0 to 1 only after a delay t1 through MOS transistor PM1, resistor R1, and inverters INV1 and INV2. Therefore, the input of the OR gate OR is 0 during the t1 period, causing the P_SPDUP output to be 0, thereby turning on MOS transistor PM2 and accelerating the rise of the signal at terminal B. After the t1 period, NET3 changes to 1, causing the output of the OR gate OR, P_SPDUP, to switch to 1, thus autonomously turning off MOS transistor PM2. The same situation occurs at terminal A, but the signal at terminal A has already reached high, and the turning on of MOS transistor PM1 does not affect the signal at terminal A.

[0024] During this process, NET6 remains at 0, so that the output N_SPDUP of the AND gate remains low. Since the acceleration modules at ends A and B have the same logic, N_SPDUP_A and N_SPDUP_B are low, ensuring that MOS tubes NM1 and NM2 remain in the off state.

[0025] Phase 3 of the first round: When the signal at terminal B passes through the PHASE1 and PHASE2 stages, the low-to-high conversion is completed, and the impedance driver B is responsible for maintaining the high level state.

[0026] In the edge acceleration control module B, the signal changes are as follows: NET1 remains 0, NET2 remains 1, NET3 remains 1, NET4 becomes 0, NET5 becomes 1, and NET6 becomes 1 after a delay.

[0027] NET3 is 1, causing the output P_SPDUP of the OR gate to remain 1. Since the acceleration module logics of ends A and B are the same, P_SPDUP_A and P_SPDUP_B are high, making the MOS tubes PM1 and PM2 both in the off state.

[0028] After NET4 becomes 0, NET6 is generated after a delay of t2 from NET4 through MOS transistor PM2, inverter INV3, and inverter INV4. Therefore, there may be a time when NET4 and NET6 are both 1. However, by adjusting the width-to-length ratio of MOS transistor PM2, the rising edge speed of NET5 can be increased to minimize high-level spikes at the output of the AND gate, thus preventing incorrect signal conversion. This adjustment ensures that the output N_SPDUP of the AND gate remains 0. Because the acceleration modules on the A and B sides share the same logic, the low values ​​of N_SPDUP_A and N_SPDUP_B turn off MOS transistors NM1 and NM2.

[0029] Phase 4 of the first round: When the signal at terminal A transitions from a high level to a low level, level converter A generates a logic inversion signal A2_n. This logic inversion signal A2_n transitions from a low level to a high level, causing the output of impedance driver B to transition from a high level to a low level. However, due to the insufficient driving capability of impedance driver B, the signal speed is insufficient, resulting in a state where the level at terminal A is low and the level at terminal B is high. In this case, edge acceleration control module B is required to drive MOS transistor NM2 to accelerate the edge of the signal at terminal B, thereby increasing the signal conversion speed.

[0030] The working process of edge acceleration control module B is as follows: In this case, the states of the various signals are as follows: NET1 remains 0, NET2 remains 1, NET3 remains 1, NET4 becomes 1, NET5 becomes 0 after a delay, and NET6 becomes 0 after a delay.

[0031] like Figure 4 As shown in the figure, based on the above signal conditions, after NET4 changes from 0 to 1, NET6 is NET4, and it changes from 1 to 0 only after a delay t3 through MOS transistor NM2, resistor R2, inverter INV3, and inverter INV4. Therefore, the input of the NAND gate AND is 1 during the t3 period, causing the N_SPDUP output to be 1, thereby turning on MOS transistor NM2 and accelerating the decline of the signal at terminal B. After the t3 period, NET6 changes to 0, causing the output N_SPDUP of the AND gate to change to 0, thereby automatically turning off MOS transistor NM2. The same situation occurs at terminal A, but the signal at terminal A has already turned low at this time, and the turning on of MOS transistor NM1 does not affect the signal at terminal A.

[0032] NET3 remains at 1, causing the output signal P_SPDUP of the OR gate OR to remain at 1. Since the acceleration modules at ends A and B have the same logic, P_SPDUP_A and P_SPDUP_B are high, causing the MOS tubes PM1 and PM2 to be in the off state.

[0033] Phase 1 of the second round: When the signal at terminal B passes through PHASE3 and PHASE4, the high-to-low conversion is completed, and the impedance driver B is responsible for maintaining the low level state.

[0034] In the edge acceleration control module B, the signal changes are as follows: NET1 becomes 1, NET2 becomes 0 after a delay, NET3 becomes 0 after a delay, NET4 remains 0, NET5 remains 1, and NET6 remains 1.

[0035] NET4 is 0, causing the output N_SPDUP of AND1 to remain 0. Since the acceleration module logics of ends A and B are the same, N_SPDUP_A and N_SPDUP_B are low, causing MOS tubes NM1 and NM2 to be in the off state.

[0036] After NET1 becomes 1, NET3 is generated after a delay of t4 from NET1 through NM1, inverter INV1, and inverter INV2. Therefore, there may be a time when both NET1 and NET3 are 0 simultaneously. However, by adjusting the width-to-length ratio of MOS transistor NM1, the speed of NET2's falling edge can be increased to minimize low-level spikes at the output of the OR gate, thus preventing erroneous signal conversion. This adjustment ensures that the output P_SPDUP of the OR gate remains 1. Because the acceleration modules on both ends A and B share the same logic, the low values ​​of P_SPDUP_A and P_SPDUP_B turn off MOS transistors PM1 and PM2.

[0037] Combine Figure 5 is a waveform diagram of an N_SPDUP signal provided by at least one embodiment of the present disclosure; Figure 6This is a waveform diagram of a P_SPDUP signal provided by at least one embodiment of the present disclosure. It can be seen that regardless of whether the signal transitions from a low level to a high level or vice versa, the circuit remains in one of four operating states: PHASE 1, PHASE 2, PHASE 3, and PHASE 4. Furthermore, due to the symmetry of the circuit, the aforementioned analysis process is not affected by swapping the input signals when transmitting from A to B or vice versa, thus fully enabling automatic signal conversion. In the level conversion circuit provided by at least one embodiment of the present disclosure, the circuit configuration of the edge acceleration control module A or the edge acceleration control module B is as follows: the first signal input terminal is connected to the first input terminal of the NOR gate NOR and the first input terminal of the NAND gate NAND, the second signal input terminal is connected to the second input terminal of the NOR gate NOR and the second input terminal of the NAND gate NAND; the output terminal of the NOR gate NOR is connected to the second input terminal of the OR gate OR and the gates of the MOS transistors NM3 and PM3, and the output terminal of the OR gate OR is connected to the first signal output terminal; the MOS transistor PM3 is configured such that: the source terminal is connected to the power supply VCC, the drain terminal is connected to the source terminal of the MOS transistor NM3 through the resistor R1, and the drain terminal of the MOS transistor NM3 is grounded; and the MOS transistor PM3 is configured such that: the source terminal is connected to the power supply VCC, the drain terminal is connected to the source terminal of the MOS transistor NM3 through the resistor R1, and the drain terminal of the MOS transistor NM3 is grounded; and The common end of the source of transistor NM3 and resistor R1 is connected to inverter INV1 and inverter INV2 in sequence; the output of inverter IVN2 is connected to the first input of OR gate OR; the output of NAND gate NAND is connected to the first input of AND gate AND, the gates of MOS transistors NM4 and PM4, and the output of AND gate AND is connected to the second signal output terminal; MOS transistor PM4 is configured as follows: the source is connected to power supply VCC, the drain is connected to the source of MOS transistor NM4 through resistor R2, and the drain of MOS transistor NM4 is grounded; the drain of MOS transistor PM4 and the common end of resistor R2 are connected to inverters INV3 and INV4 in sequence; the output of inverter INV4 is connected to the second input of AND gate AND.

[0038] In the level conversion circuit provided in at least one embodiment of the present disclosure, Figure 2 As shown, Figure 2 is a circuit diagram of a level converter provided by at least one embodiment of the present disclosure; The circuit configuration of the level converter A or the level converter B is as follows: the signal input terminal IN is connected to the input terminal of the inverter INV5 and the gate of the MOS transistor NM6; the output terminal of the inverter INV5 is connected to the gate of the MOS transistor NM5; the MOS transistor NM5 is configured such that: its drain is grounded; its source is sequentially connected to the first signal output terminal OUT and the drain of the MOS transistor PM5; and the common terminal of the first signal output terminal OUT and the drain of the MOS transistor PM5 is connected to the gate of the MOS transistor PM6; the MOS transistor NM6 is configured such that: its drain is grounded; its source is sequentially connected to the second signal output terminal OUT_n and the drain of the MOS transistor PM6; and the common terminal of the second signal output terminal OUT_n and the drain of the MOS transistor PM6 is connected to the gate of the MOS transistor PM5; and the sources of the MOS transistors PM5 and PM6 are both connected to the power supply VCC.

[0039] In the level conversion circuit provided in at least one embodiment of the present disclosure, Figure 3 As shown, Figure 3 is a circuit diagram of an impedance driver provided by at least one embodiment of the present disclosure; The circuit of the impedance driver is configured as follows: comprising MOS transistors PM7 and NM7, wherein the gates of the MOS transistors PM7 and NM7 are interconnected, and the common end of the gates is connected to the signal input end IN; wherein the drains of the MOS transistors PM7 and NM7 are interconnected, and the common end of the drains is connected to the signal output end OUT via a resistor R3; the source of the MOS transistor PM7 is connected to the power supply VCC , the source of the MOS tube NM7 is grounded. The resistance of the resistor R3 is greater than the internal resistance of the signal source; In summary, the beneficial effects of this solution can be clearly seen in the process. This circuit does not need to use additional control pins to control the transmission direction of the signal, and can realize automatic detection and transmission of the signal. Professionals can further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, computing software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0040] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0041] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. An improved level conversion circuit for automatically detecting transmission direction, characterized in that: The level conversion circuit includes two sets of transmission circuits that are symmetrically arranged, and the two sets of transmission circuits can perform bidirectional signal transmission; The port of the first transmission circuit is set to terminal A, and the terminal A sends a signal to the second transmission circuit through the level converter A, and receives the signal of the second transmission circuit through the impedance driver A and the edge acceleration control module A; The port of the second transmission circuit is set to terminal B, which sends a signal to the first transmission circuit through the level converter B and receives the signal from the first transmission circuit through the impedance driver B and the edge acceleration control module B; wherein: The level converter A and the level converter B are the same device, which can convert the input signal into a signal of the corresponding level domain; The impedance driver A and the impedance driver B are identical devices, setting a high impedance path and providing static driving capability for the output signal; The edge acceleration control module A and the edge acceleration control module B are identical devices, set up a low impedance path, and are closed after the signal conversion is completed.

2. The improved level conversion circuit for automatically detecting transmission direction according to claim 1, characterized in that: The edge acceleration control module A includes two signal input terminals and two signal output terminals; The first signal input terminal receives the signal from terminal A, and the second signal input terminal receives the signal from terminal B; the first signal output terminal sends the signal to terminal A through MOS transistor PM1, and the second signal output terminal sends the signal to terminal A through MOS transistor NM1; The edge acceleration control module B includes two signal input terminals and two signal output terminals; The first signal input terminal receives the signal from terminal B, and the second signal input terminal receives the signal from terminal A; the first signal output terminal sends the signal to terminal B through MOS transistor PM2, and the second signal output terminal sends the signal to terminal B through MOS transistor NM2.

3. The improved level conversion circuit for automatically detecting transmission direction according to claim 2, characterized in that: The MOS transistor PM1 is configured as follows: a gate connected to the first signal output terminal of the acceleration control module A, a source connected to the power supply VCC1, and a drain connected to the drain of the MOS transistor NM1; The MOS tube NM1 is configured as follows: the gate is connected to the second signal output terminal of the acceleration control module A and the source is grounded; The common end of the drain of the MOS transistor PM1 and the drain of the MOS transistor NM1 is connected to the A end.

4. The improved level conversion circuit for automatically detecting transmission direction according to claim 2, characterized in that: The MOS transistor PM2 is configured as follows: a gate connected to the first signal output terminal of the acceleration control module B, a source connected to the power supply VCC2, and a drain connected to the drain of the MOS transistor NM2; The MOS tube NM2 is configured as follows: the gate is connected to the second signal output terminal of the acceleration control module B and the source is grounded; The common end of the drain of the MOS transistor PM2 and the drain of the MOS transistor NM2 is connected to the B end.

5. The improved level conversion circuit for automatically detecting transmission direction according to claim 2, characterized in that: The circuit configuration of the edge acceleration control module A or the edge acceleration control module B is as follows: The first signal input terminal is connected to the first input terminal of the NOR gate NOR and the first input terminal of the NAND gate NAND, and the second signal input terminal is connected to the second input terminal of the NOR gate NOR and the second input terminal of the NAND gate NAND; The output end of the NOR gate NOR is connected to the second input end of the OR gate OR and the gates of the MOS transistors NM3 and PM3, and the output end of the OR gate OR is connected to the first signal output end; The MOS transistor PM3 is configured as follows: a source terminal is connected to the power supply VCC, a drain terminal is connected to the source terminal of the MOS transistor NM3 via the resistor R1, and the drain terminal of the MOS transistor NM3 is grounded; and a common terminal of the source terminal of the MOS transistor NM3 and the resistor R1 is connected to the inverter INV1 and the inverter INV2 in sequence; the output terminal of the inverter IVN2 is connected to the first input terminal of the OR gate OR; The output end of the NAND gate NAND is connected to the first input end of the AND gate AND and the gates of the MOS transistors NM4 and PM4, and the output end of the AND gate AND is connected to the second signal output end; The MOS transistor PM4 is configured as follows: a source terminal is connected to the power supply VCC, a drain terminal is connected to the source terminal of the MOS transistor NM4 via the resistor R2, and the drain terminal of the MOS transistor NM4 is grounded; and a common terminal of the drain terminal of the MOS transistor PM4 and the resistor R2 is connected to the inverter INV3 and the inverter INV4 in sequence; and an output terminal of the inverter INV4 is connected to the second input terminal of the AND gate AND.

6. The improved level conversion circuit for automatically detecting transmission direction according to claim 1, characterized in that: The level converter A includes a signal input terminal and two signal output terminals; the signal input terminal receives the signal from terminal A; the first signal output terminal sends the processed signal to the edge acceleration control module B, and the second signal output terminal sends the processed signal to the impedance driver B; The level converter B includes a signal input terminal and two signal output terminals; the signal input terminal receives the B terminal signal; the first signal output terminal sends the processed signal to the edge acceleration control module A, and the second signal output terminal sends the processed signal to the impedance driver A.

7. The improved level conversion circuit for automatically detecting transmission direction according to claim 6, characterized in that: The level converter A is connected to the second transmission circuit power supply VCC2; The level converter B is connected to the power supply VCC1 in the first transmission circuit.

8. The improved level conversion circuit for automatically detecting transmission direction according to claim 7, characterized in that: The circuit configuration of the level converter A or the level converter B is as follows: The signal input terminal IN is connected to the input terminal of the inverter INV5 and the gate of the MOS transistor NM6; the output terminal of the inverter INV5 is connected to the gate of the MOS transistor NM5; The MOS transistor NM5 is configured as follows: the drain is grounded, the source is sequentially connected to the first signal output terminal OUT and the drain of the MOS transistor PM5, and the common terminal of the first signal output terminal OUT and the drain of the MOS transistor PM5 is connected to the gate of the MOS transistor PM6; The MOS transistor NM6 is configured as follows: the drain is grounded, the source is sequentially connected to the second signal output terminal OUT_n and the drain of the MOS transistor PM6, and the common terminal of the second signal output terminal OUT_n and the drain of the MOS transistor PM6 is connected to the gate of the MOS transistor PM5; the sources of the MOS transistors PM5 and PM6 are both connected to the power supply VCC.

9. The improved level conversion circuit for automatically detecting transmission direction according to claim 1, characterized in that: The circuit configuration of the impedance driver is: The MOS transistors PM7 and NM7 are included, wherein the gates of the MOS transistors PM7 and NM7 are interconnected, and the common end of the gates is connected to the signal input end IN; wherein the drains of the MOS transistors PM7 and NM7 are interconnected, and the common end of the drains is connected to the signal output end OUT via a resistor R3; the source of the MOS transistor PM7 is connected to the power supply VCC, and the source of the MOS transistor NM7 is grounded.

10. The improved level conversion circuit for automatically detecting transmission direction according to claim 9, characterized in that: The resistance of the resistor R3 is greater than the internal resistance of the signal source.

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