Dual-slope analog-to-digital converter and method

Abstract

The invention discloses a dual-slope analog-to-digital converter and method, the dual-slope analog-to-digital converter comprises an integrating capacitor, a current source, a coarse-fine quantization comparator, a coarse-fine quantization counter and a control logic module, and the control logic module switches the discharge slope according to the comparison result of the coarse-fine quantization comparator; an input voltage is sampled to an integrating capacitor through a sampling switch, a sampling and holding node discharges through two parallel constant current sources, and a coarse quantization comparator with a reference voltage of Vref and a fine quantization comparator with a reference voltage of VT are respectively connected into the sampling and holding node; the output Vc1 of the coarse quantization comparator controls the latching of the M-bit counter and outputs an M-bit coarse quantization result Nc, and the output Vc2 of the fine quantization comparator controls the latching of the N-bit counter and outputs an N-bit fine quantization result Nf to form M + N-bit data required by two steps. The invention overcomes the problems of high clock frequency requirement, clock delay, high circuit power consumption and the like of the SS ADC, and is suitable for reading circuits of high-performance image sensors and infrared focal plane detectors.

Description

Technical Field

[0001] The present invention relates to a high-resolution, low-power, small-area analog-to-digital converter (ADC) for array applications such as image sensors, and in particular to a dual-slope (DS) ADC and a method thereof. Background Art

[0002] Image sensors typically use column-level ADCs to quantize photoelectric signals. Commonly used circuit structures for column-level ADCs include single-slope ADCs (SS ADCs), successive approximation ADCs (SAR ADCs), and circular ADCs.

[0003] The SS ADC's conversion is essentially from the voltage domain to the time domain and then to the digital domain. Each column uses a comparator and counter, and the entire array shares a ramp signal generation circuit. The circuit is simple, so it occupies a small area and is an ADC architecture suitable for array applications such as image sensors.

[0004] The conversion speed and accuracy of traditional SS-ADC are limited by the counting frequency. High-performance image sensors and infrared detectors have a large dynamic range, requiring the ADC resolution to be above 14 bits. As the image sensor array size and frame rate continue to increase, the ADC conversion speed requirements are also increasing. For traditional N-bit SSADC, the conversion cycle is 2 N For example, a 14-bit traditional SS-ADC with a sampling rate of 100 kS / s has a conversion time of 10 μs and requires a counting clock signal with a frequency of up to 1.64 GHz, which leads to transmission delay of the high-speed clock signal and power consumption issues of the circuit.

[0005] Unlike traditional one-step ADCs, which directly convert input signals, two-step ADCs perform M-bit coarse quantization and N-bit fine quantization on the input signal, combining the two quantization results to achieve an (M+N)-bit ADC quantization bit count. Compared to a one-step ADC with the same quantization bit count, a two-step ADC improves conversion speed and reduces power consumption. However, due to device parameter mismatch, the two-step ADC architecture often introduces errors in the transfer between the coarse quantization residual voltage and the fine quantization reference voltage. Conventional two-step ADCs with variable reference voltages place high demands on the power consumption and accuracy of the reference voltage generation circuitry, and matching the coarse and fine quantization reference voltages is difficult. For applications such as image sensor arrays, this leads to poor consistency between different ADC input reference voltages and high drive capability requirements. Device parameter and reference voltage mismatch can cause ADC code omissions or duplicate codes, severely impacting image sensor image quality. These code omissions and duplicate codes in two-step ADCs can be addressed through calibration, but this inevitably introduces complex circuitry and calibration procedures, increasing circuit overhead. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to overcome the above-mentioned shortcomings and provide a dual-slope analog-to-digital converter and method suitable for array applications, which has the characteristics of small area, low power consumption, high resolution and no need for correction, and is suitable for application in high-performance image sensors and infrared focal plane detector readout circuits.

[0007] The dual-slope ADC of the present invention is essentially a two-step integrating ADC. It uses a constant-current discharge circuit for the integrating capacitor, combined with a high-precision comparator, to achieve voltage-to-time conversion, and a corresponding counter to achieve time-to-digital conversion. By switching between different discharge currents to achieve different discharge slopes, it achieves M-bit coarse quantization and N-bit fine quantization. Together, these two steps achieve analog-to-digital conversion with (M+N)-bit quantization accuracy.

[0008] Specifically, a dual-slope analog-to-digital converter of the present invention includes integrating capacitors electrically connected in sequence, and the discharge currents are I0 and (2 N -1) a fine quantization current source and a coarse quantization current source of I0, a coarse quantization comparator and a fine-coarse quantization comparator, a coarse quantization counter and a fine quantization counter corresponding to the coarse quantization comparator and the fine-coarse quantization comparator, and a control logic module, wherein the control logic module switches the discharge slope according to the comparison result of the coarse quantization comparator and the fine-coarse quantization comparator.

[0009] The dual-slope analog-to-digital converter converts the input voltage V in The sampling is done to the integration capacitor, and the sampling and holding node passes through two discharge currents, I0 and (2 N-1) The fine quantization current source and the coarse quantization current source of I0 are discharged and connected to the reference voltage V ref The coarse quantization comparator and the reference voltage are V T The output V of the coarse quantization comparator is c1 Control the M-bit counter to latch and output the M-bit coarse quantization result N c , the output of the precision comparator V c2 Control the N-bit counter to latch and output the N-bit precision result N f , constituting the M+N bit data required for the two steps.

[0010] Furthermore, the sampling switch is used as a sampling input voltage V in The lower plate of the integrating capacitor is grounded, and the upper plate is the ADC real-time quantization voltage V int .

[0011] Furthermore, the fine quantization current source and the coarse quantization current source are set at the ADC real-time quantization voltage V int and ground potential; the switch is located between the ADC real-time quantization voltage V int Between the quantization node and the coarse quantization current source.

[0012] Furthermore, the integration capacitor is directly connected to the input terminals of the coarse quantization comparator and the fine coarse quantization comparator.

[0013] Furthermore, the output of the coarse quantization comparator is connected to the coarse quantization counter, the output of the fine quantization comparator is connected to the fine quantization counter, and both the fine quantization comparator and the coarse quantization counter are controlled by a control logic module. When quantization starts, the control logic module controls the sampling switch to be turned off.

[0014] Furthermore, the dual-slope two-step ADC converts 2 (M+N) The clock cycle is reduced to 2 M +2 N The DS ADC can realize the design of small area, low power consumption and high precision by increasing the conversion speed and reducing the power consumption. It also reduces the limitation of high precision on the counting clock of a single SS ADC and gives full play to the advantages of small area and low power consumption of SS ADC.

[0015] The specific circuit working process of the present invention is as follows:

[0016] 1. The first step is the M-bit coarse quantization process

[0017] 1.1 Input signal voltage V in Range > V ref , through the Samp sampling switch to V in The signal is stored in the sampling capacitor Cint After that, coarse quantization begins. int The voltage passes through the constant current source I c and I f At the same time, the effect starts to decrease with the slope of k1, I c with I f The ratio is (2 N -1)∶1, and at the same time control the M-bit coarse quantization counter to start counting with CLK;

[0018] 1.2 If V int Less than V ref , then the result of triggering the coarse quantization comparator flips to 1, and the counter is locked according to the output result of the comparator, and the coarse quantization result N is obtained. c . N c M-bit digital value D COARSE [M-1:0]. At the same time, the control signal MSB en Set the constant current source I c Disconnected from the sampling and protection node, at this time V int Less than V ref and greater than V T , and start the comparison in the subsequent refinement stage.

[0019] 2. The second step of quantification process:

[0020] 2.1 Constant current source I c After disconnection, V int The voltage is only determined by the constant current source I f The effect continues to decrease with the slope of k2, and the precision begins. c with I f The ratio is (2 N -1)∶1, so we have:

[0021]

[0022] 2.2 If V int drops to less than V T , then the output signal V C2 Flip to 1, trigger the latch value of the precision counter according to the output result of the comparator, and get the precision result N f . N f is the N-bit digital value D FINE [N-1:0].

[0023] 3. The coarse quantization value D COARSE [M-1:0] and the quantized value D of the fine quantization FINE [N-1:0] are combined into the final quantized value D[M+N-1, 0] and can be output to the outside of the chip via a high-speed digital serial interface, where:

[0024] D[M+N-1,0]={D COARSE [M-1],…,D COARSE [0],D FINE [N-1],…,D FINE [0]}.

[0025] The beneficial effects of the present invention include:

[0026] (1) The DS ADC of the present invention can realize the analog-to-digital converter function with high precision (above 14 bits), small area, and low power consumption, and is suitable for application in high-performance image sensors and infrared detectors;

[0027] (2) The DS ADC of the present invention achieves different discharge slopes by matching current sources, and cooperates with corresponding comparators and counters to form a single-slope ADC for coarse quantization and fine quantization. The fine quantization start time of each DS ADC in the entire array depends on the end time of its own coarse quantization. There is no need for synchronization between the two conversion steps, which shortens the overall conversion time, greatly improves the conversion speed, and reduces power consumption.

[0028] (3) The DS ADC of the present invention does not need to transfer the coarse quantization residual voltage between different circuits, thus avoiding the mismatch between the coarse quantization residual voltage and the fine quantization reference voltage caused by CMOS process deviations and the non-ideal characteristics of the residual voltage transfer circuit. It also avoids the occurrence of missing and repeated codes in the traditional two-step ADC structure. Therefore, the DS ADC does not need a correction circuit, further saving circuit overhead.

[0029] (4) The DS ADC of the present invention uses a sampling capacitor and a current source to realize local ramp voltage generation, eliminating the need for an additional ramp voltage generation circuit and corresponding signal buffering and distribution circuits. The circuit area is small and the layout is easy. It can be effectively applied to high-performance image sensors with small pixel pitch and large arrays.

[0030] (5) The DS ADC of the present invention provides flexibility for the two-step bit selection. By properly selecting the coarse quantization bit M and the fine quantization bit N, different sensor imaging system requirements can be met. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 This is a schematic diagram of the dual-slope integrating ADC circuit of the present invention, in which:

[0032] 101 - sampling switch, 102 - integrating capacitor, 103 - fine quantization current source, 104 - coarse quantization current source, 105 - switch, 106 - coarse quantization comparator, 107 - fine-coarse quantization comparator, 108 - coarse quantization counter, 109 - fine quantization counter, 110 - control logic module.

[0033] Figure 2 This is a working timing diagram of the dual-slope integrating ADC of the present invention. DETAILED DESCRIPTION

[0034] The present invention will be further described in detail below through embodiments in conjunction with the accompanying drawings, but the protection scope of the present invention is not limited to the following embodiments.

[0035] like Figure 1 The dual slope ADC structure is shown as follows: the sampling switch 101 is used to sample the input voltage V in The switch has a capacity of C int The lower plate of the integrating capacitor 102 is grounded, and the upper plate is the ADC real-time quantization voltage V int When the signal is fully established, V int With V in Equal, the sampling switch 101 is disconnected and the quantization process begins. int The rate of decrease is set by two groups at V int The fine quantization current source 103 and the coarse quantization current source 104 between the ground potential and the ground potential are precisely controlled: the fine quantization current source 103 is controlled by a constant current I f (i.e. I0) discharges the charge stored in the integrating capacitor 102 with a capacity of Cint to the ground; the current I of the coarse quantized current source 104 c is I0's (2 N -1) times, switch 105 is V int The switch between the quantization node and the coarse quantization current source 104 is controlled by the logic control module. The ADC real-time quantization voltage node is connected to the input of the coarse quantization comparator 106 and the fine coarse quantization comparator 107. The reference voltage of the coarse quantization comparator 106 is V ref , the reference voltage of the precision comparator 107 is V T , and respectively at V int The voltage drops to V ref and V T Output comparison result flip signal V c1 and V c2 The output of the coarse quantization comparator 106 is connected to the M bit coarse quantization counter 108, and the output of the fine quantization comparator 107 is connected to the N bit fine quantization counter 109. Both counters are controlled by the control logic module 110. When quantization starts, the control logic module 110 controls the sampling switch 101 to be disconnected, and the coarse quantization counter 108 starts counting. V int By V in The voltage starts to decrease at a rate of k1. The voltage drops to V ref When the coarse quantization comparator 106 flips, the coarse quantization counter 108 latches the coarse quantization result. The control logic module 110 controls the switch 105 to close at the next clock edge, and V intThe falling rate is reduced from k1 to k2, and the N bit precision counter 109 starts counting. int Lower than V T When the precision comparator 107 outputs the flip signal V c2 , driving the N bit fine quantization counter 109 to latch the fine quantization result.

[0036] like Figure 2 The figure shows the timing diagram of the dual slope ADC operation. A conversion cycle depends on the input starting voltage. The worst case is 2 M +2 N Within CLK. Input signal voltage V in Range > V ref Before the conversion starts, close the Samp switch to set V in The signal is stored in the sampling capacitor C int , disconnect the Samp switch at t0 to ensure V int The voltage is not affected by the state of the front-end circuit and begins to be coarsely quantized. en Enable state is high, I c The current source acts on the sampling and protection node, V int The voltage passes through the constant current source I c and I f The combined effect starts to decrease with the slope of k1, and the downward slope is

[0037]

[0038] At the same time, the M-bit coarse quantization counter is controlled to start counting in conjunction with CLK.

[0039] If V int Less than V ref , then the result V of the coarse quantization comparator is triggered at time t1 c1 Flip to 1, according to the output result of the comparator, trigger the coarse quantization counter value triggered by the previous CLK rising edge of the latch, and obtain the coarse quantization result N c . N c M-bit digital value D COARSE [M-1:0]. At the same time, the control signal MSB en At the next rising edge of CLK following t1, it jumps to low, and the constant current source I c Disconnected from the sampling and protection node, at this time V int Less than V ref and greater than V T , and start the comparison in the subsequent refinement stage.

[0040] The second step of the quantization process is to control the logic LSB with t1 en The signal jumps high and starts. c After disconnection, Vint The voltage is only determined by the constant current source I f The effect continues to decrease at a slope of k2, and the slope of the decrease is

[0041]

[0042] If at time t2 V int Less than V T , then the output signal V C2 Flip to 1, according to the output result of the comparator, trigger the latch to latch the value of the precision counter triggered by CLK at time t2, and obtain the precision result N f . N f is the N-bit digital value D FINE [N-1:0], where the coarse quantization is the high M bits and the fine quantization is the low N bits, and the final transformation result can be obtained.

[0043] The above descriptions are only some specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with this technical field within the technical scope disclosed by the present invention should be covered by the scope of protection of the present invention.

Claims

1. A dual-slope analog-to-digital converter, characterized in that: Comprising electrically connected in sequence: Integrating capacitor (102), The discharge currents are I0 and (2 N -1) a fine quantization current source (103) and a coarse quantization current source (104) of I0, a coarse quantization comparator (106) and a fine coarse quantization comparator (107), a coarse quantization counter (108) and a fine quantization counter (109) corresponding to the coarse quantization comparator (106) and the fine coarse quantization comparator (107), and A control logic module (110), wherein the control logic module (110) switches the discharge slope according to a comparison result between the coarse quantization comparator (106) and the fine coarse quantization comparator (107); The dual slope analog-to-digital converter converts the input voltage V in The sampling is done to the integration capacitor (102), and the sampling and holding node passes through two discharge currents, I0 and (2 N -1) The fine quantization current source (103) and the coarse quantization current source (104) of I0 are discharged and connected to the reference voltage V ref The coarse quantization comparator (106) and the reference voltage V T The output V of the coarse quantization comparator (106) is c1 Control the M-bit counter to latch and output the M-bit coarse quantization result N c , the output V of the precision comparator (107) c2 Control the N-bit counter to latch and output the N-bit precision result N f , constituting the M+N bit data required for the two steps.

2. The dual-slope analog-to-digital converter according to claim 1, characterized in that: The sampling switch (101) is used as a sampling input voltage V in The lower plate of the integrating capacitor (102) is grounded, and the upper plate is the ADC real-time quantization voltage V int .

3. The dual-slope analog-to-digital converter according to claim 1, characterized in that: The fine quantization current source (103) and the coarse quantization current source (104) are set at the ADC real-time quantization voltage V int Between and ground potential; The switch (105) is located at the ADC real-time quantization voltage V int Between the quantization node and the coarse quantization current source (103).

4. The dual-slope analog-to-digital converter according to claim 1, characterized in that: The integration capacitor (102) is directly connected to the input terminals of the coarse quantization comparator (106) and the fine coarse quantization comparator (107).

5. The dual-slope analog-to-digital converter according to claim 1, characterized in that: The output of the coarse quantization comparator (106) is connected to a coarse quantization counter (108), and the output of the fine quantization comparator (107) is connected to a fine quantization counter (109). Both the fine quantization comparator (107) and the coarse quantization counter (108) are controlled by a control logic module (110).

6. The dual-slope analog-to-digital converter according to claim 5, characterized in that: When quantization starts, the control logic module (110) controls the sampling switch (101) to be turned off.

7. The dual-slope analog-to-digital converter according to any one of claims 1 to 6, characterized in that: The analog-to-digital converter converts 2 (M+N) The clock cycle is reduced to 2 M +2 N clock cycles, which is used to increase conversion speed, reduce power consumption, and reduce the limitation of high precision on the counting clock of a single SS ADC.

8. An analog-to-digital conversion method of a dual-slope analog-to-digital converter according to any one of claims 1 to 7, characterized in that: It includes the first step of M-bit coarse quantization and the second step of fine quantization; The first step of M-bit coarse quantization includes: (1) Input signal voltage V in Range > V ref , through the Samp switch to V in The signal is stored in the sampling capacitor C int After that, coarse quantization begins; V int The voltage passes through the constant current source I c and I f At the same time, the effect starts to decrease with the slope of k1, I c with I f The ratio is (2 N -1):1, simultaneously control the M-bit coarse quantization counter to start counting with CLK; (2) If V int Less than V ref , then the result of triggering the coarse quantization comparator flips to 1, and the counter is locked according to the output result of the comparator, and the coarse quantization result N is obtained. c ; N c M-bit digital value D COARSE [M-1:0]; At the same time, the control signal MSB en Set the constant current source I c Disconnected from the sampling and protection node, at this time V int Less than V ref and greater than V T , start the comparison of the subsequent refinement stage; The second step of quantification includes: (1) Constant current source I c After disconnection, V int The voltage is only determined by the constant current source I f The effect continues to decrease with the slope of k2, and the precision begins; c with I f The ratio is (2 N -1):1 to get: (2) If V int drops to less than V T , then the output signal V C2 Flip to 1, trigger the latch value of the precision counter according to the output result of the comparator, and get the precision result N f , where N f is the N-bit digital value D FINE [N-1:0]; (3) The coarse quantization value D COARSE [M-1:0] and the quantized value D of the fine quantization FINE [N-1:0] are combined into the final quantized value D[M+N-1, 0] and output to the outside of the chip via the high-speed digital serial interface, where: D[M+N-1,0]={D COARSE [M-1],…,D COARSE [0],D FINE [N-1],…,D FINE [0]}。

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