Semiconductor structure and manufacturing method of semiconductor structure

Abstract

A semiconductor structure includes a semiconductor wafer, a device layer, and a dummy static random access memory (PSRAM) die. The device layer is disposed on a surface of the semiconductor wafer, wherein the device layer includes an organic layer. The PSRAM die is disposed on a surface of the semiconductor wafer and electrically connected to the semiconductor wafer. The invention further provides a manufacturing method of the semiconductor structure. The semiconductor structure provided by the invention has a smaller size and / or better performance, and has relatively low power consumption.

Description

Technical Field

[0001] The invention relates to a semiconductor structure and a method for manufacturing the semiconductor structure. Background Art

[0002] A system on chip (SoC) is an integrated circuit that integrates multiple electronic components with different functions into a single chip. Therefore, electronic products including this SoC can provide high performance while being relatively small in size.

[0003] To improve computing efficiency, static random access memory (SRAM) or dynamic random access memory (DRAM) circuits are often embedded in SoCs to form embedded memory. However, forming embedded memory in SoCs not only increases process cost and complexity, but also limits the area and / or performance of the integrated circuits in the original SoC.

[0004] For example, see Figure 6A as well as Figure 6B , Figure 6A as well as Figure 6B A conventional light-emitting device module 1000 is shown, in which an embedded memory 4 and a light-emitting device 2 are integrated into a SoC 1. The embedded memory 4 is an SRAM, and the light-emitting device 2 is covered by a passivation layer 3. SRAM is a type of memory with 6, 8, 10, or more transistors. Its relatively large area compresses the size of the integrated circuits in the original SoC, potentially reducing performance. If the size of the integrated circuits in the original SoC is retained, the final electronic product will be larger and have higher manufacturing costs.

[0005] Furthermore, SRAM and DRAM also have problems such as relatively high power consumption, which degrades the user experience when using electronic products including SRAM and / or DRAM. Summary of the Invention

[0006] The present invention provides a semiconductor structure with smaller size and / or better performance and relatively low power consumption.

[0007] The semiconductor structure provided by the present invention includes a semiconductor wafer, a device layer, and a virtual static random access memory (PSRAM) die. The device layer is disposed on a surface of the semiconductor wafer, wherein the device layer includes an organic layer. The PSRAM die is disposed on the surface of the semiconductor wafer and is electrically connected to the semiconductor wafer.

[0008] The present invention provides a method for manufacturing a semiconductor structure, wherein the semiconductor structure has a smaller size and / or better performance and relatively low power consumption.

[0009] The present invention provides a method for manufacturing a semiconductor structure, comprising the following steps: providing a virtual static random access memory (PSRAM) wafer; dicing the PSRAM wafer to form a plurality of PSRAM dies; and bonding the PSRAM dies to the surface of a semiconductor die, wherein the surface of the semiconductor die has a component layer and a passivation layer disposed thereon, and the component layer includes an organic layer.

[0010] Based on the above, by attaching a PSRAM die to a semiconductor die, the size and / or performance of the integrated circuit within the semiconductor die are not limited by the PSRAM die. In other words, the semiconductor structure provided by the present invention can have a relatively small size and / or relatively good performance. Furthermore, the memory integrated within the semiconductor structure provided by the present invention is PSRAM, which combines the advantages of DRAM's low cost and large capacity with the user interface of SRAM, thereby reducing the power consumption of the semiconductor structure provided by the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 FIG. 1 is a schematic partial cross-sectional view of a semiconductor structure according to a first embodiment of the present invention.

[0012] Figure 2 FIG. 1 is a schematic partial cross-sectional view of a semiconductor structure according to a second embodiment of the present invention.

[0013] Figure 3 FIG. 1 is a schematic flow chart of a method for manufacturing a semiconductor structure according to a first embodiment of the present invention.

[0014] Figure 4 FIG. 1 is a schematic flow chart of a method for manufacturing a semiconductor structure according to a second embodiment of the present invention.

[0015] Figure 5A Based on Figure 1 A schematic top view of an embodiment of a semiconductor structure is shown.

[0016] Figure 5B Based on Figure 1 A schematic top view of another embodiment of a semiconductor structure is shown.

[0017] Figure 6A A schematic partial cross-sectional view of a conventional semiconductor structure including an embedded memory is shown.

[0018] Figure 6B Based on Figure 6A A schematic top view of a known semiconductor structure is shown.

[0019] Figure 7 A schematic diagram illustrating one embodiment of the definition of the front side and the back side of a semiconductor die or semiconductor wafer. DETAILED DESCRIPTION

[0020] The following examples are listed and described in detail with reference to the accompanying drawings. However, the examples provided are not intended to limit the scope of protection of the present invention. In addition, the drawings are for illustrative purposes only and are not drawn to their original size. For ease of understanding, the same elements will be marked with the same symbols in the following description.

[0021] Figure 1 FIG. 1 is a schematic partial cross-sectional view of a semiconductor structure according to a first embodiment of the present invention.

[0022] Please refer to Figure 1 , Figure 1 The semiconductor structure 10 of this embodiment is shown. In this embodiment, the semiconductor structure 10 includes a semiconductor die 100 , a device layer 200 , a passivation layer 300 , and a pseudo static random-access memory (PSRAM) die 400 .

[0023] In this embodiment, the semiconductor die 100 includes a display driver integrated circuit (DDIC) to drive the light-emitting element disposed thereon. That is, the semiconductor structure 10 of this embodiment may, for example, integrate a light-emitting element and a memory element. Based on this, the semiconductor structure 10 may be used, for example, in augmented reality glasses and / or virtual reality glasses, but the present invention is not limited thereto. In other embodiments, the semiconductor die 100 may include a microcontroller unit (MCU), true wireless Bluetooth, edge artificial intelligence (Edge-AI), or other suitable electronic components. The material of the semiconductor die 100 may include, for example, silicon, silicon germanium, silicon-on-insulator (SOI), or other suitable semiconductor materials, but the present invention is not limited thereto. In this embodiment, a plurality of pads 110 are further disposed on the surface 100S of the semiconductor die 100. The plurality of pads 110 may, for example, be used to bond the semiconductor die 100 to another die (such as the PSRAM die 400 described later).

[0024] The device layer 200 is, for example, disposed on the surface 100S of the semiconductor die 100. In this embodiment, the device layer 200 includes an organic layer. Specifically, the device layer 200 includes, for example, a micro organic light-emitting diode (micro OLED). For example, the device layer 200 may include an organic light-emitting layer (not shown), a first electrode (not shown), and a second electrode (not shown). The organic light-emitting layer may, for example, include a light-emitting layer, an electron injection layer, an electron transport layer, a hole transport layer, and / or a hole injection layer, but the present invention is not limited thereto. The first electrode may, for example, be disposed on the surface of the organic light-emitting layer close to the semiconductor die 100, and the second electrode may, for example, be disposed on the surface of the organic light-emitting layer away from the semiconductor die 100. In some embodiments, the device layer 200 may further include at least one insulating layer for electrical isolation, wherein these insulating layers may comprise organic materials, inorganic materials, or a combination thereof.

[0025] The passivation layer 300 is, for example, disposed on the device layer 200 and, for example, covers the device layer 200. In some embodiments, the material of the passivation layer 300 may include glass, metal, metal oxide, or a combination thereof. In this embodiment, the material of the passivation layer 300 includes glass. The passivation layer 300 can, for example, be used to block oxygen and / or moisture from the outside from entering the device layer 200, thereby inhibiting oxidation of the organic light-emitting layer and / or electrodes, and reducing the possibility of dark spots appearing in the light-emitting area of ​​the device layer 200.

[0026] The PSRAM die 400 is, for example, disposed on the surface 100S of the semiconductor die 100. PSRAM is a memory that provides an interface similar to static random-access memory (SRAM) to a dynamic random-access memory (DRAM)-based memory. Specifically, the PSRAM die 400 has an interface protocol similar to that of SRAM, which allows access by providing an address, read commands, and / or write commands, without the need for a controller in DRAM to control the memory cells for periodic data refresh. Furthermore, the core of the PSRAM adopts the architecture of DRAM, that is, the memory cells in the PSRAM are composed of, for example, a transistor and a capacitor. Based on this, compared to SRAM, which includes at least six transistors, PSRAM has a relatively small size and / or a relatively large storage capacity. Therefore, PSRAM combines the advantages of both SRAM and DRAM.

[0027] In this embodiment, a PSRAM die 400 is externally mounted on the semiconductor die 100. Specifically, the PSRAM die 400 can be bonded to the surface 100S of the semiconductor die 100 via an adhesive layer AL disposed on a surface 400S1 of the PSRAM die 400. Furthermore, the PSRAM die 400 can be bonded to the pads 110 on the semiconductor die 100 via pads 410 disposed on a surface 400S2 of the PSRAM die 400. The surface 400S1 of the PSRAM die 400 faces the surface 100S of the semiconductor die 100, while the surface 400S2 of the PSRAM die 400 faces away from the surface 100S of the semiconductor die 100. The surface 400S2 of the PSRAM die 400 is, for example, the active surface of the PSRAM die 400. In other words, a plurality of pads 410 and / or other connecting components can be disposed on the surface 400S2 of the PSRAM die 400. It is worth noting that the "active surface" (also called the front side) of the PSRAM die 400 is the surface on which the back-end-of-line (BEOL) process is formed, and the opposite side of the "active surface" is the back side of the semiconductor die 100. For ease of understanding, Figure 7 1 shows the definition of the front and back sides of a semiconductor die or semiconductor wafer, which will be described in the following embodiments. The adhesive layer AL may be, for example, a die attach film (DAF), AA glue, or other suitable adhesive layer, but the present invention is not limited thereto. In this embodiment, the pads 410 on the surface 400S2 of the PSRAM die 400 are bonded (electrically connected) to the pads 110 on the semiconductor die 100 via a wire bonding process. Specifically, the pads 410 of the PSRAM die 400 and the corresponding pads 110 of the semiconductor die 100 may be bonded to each other via metal wires L. In this manner, the PSRAM die 400 may be electrically connected to the semiconductor die 100 and / or components in the device layer 200. In this embodiment, the semiconductor die 100 includes a DDIC, and the DDIC is configured to drive the device layer 200 using the PSRAM die 400. For example, the semiconductor die 100 is configured to access the PSRAM die 400 via the metal wires L. In some embodiments, the device layer 200 includes micro organic light emitting diodes, and the semiconductor die 100 is configured to control the micro organic light emitting diodes by accessing the PSRAM die 400 .

[0028] In this embodiment, a keep-out zone (KOZ) is formed between the PSRAM die 400 and the device layer 200 to isolate the PSRAM die 400 from the device layer 200. Specifically, the keep-out zone (KOZ) is a region without semiconductor devices and is used to isolate the device layer 200 from the PSRAM die 400 through air.

[0029] In some embodiments, the semiconductor structure 10 may further include an encapsulant layer 500. The encapsulant layer 500, for example, covers the pads 110 of the semiconductor die 100 and the pads 410 of the PSRAM die 400 and surrounds the metal wires L to provide a sealed and protective seal. The encapsulant layer 500 may be made of, for example, potting paste or other suitable materials, but the present invention is not limited thereto.

[0030] Figure 2 FIG2 is a partial cross-sectional view of a semiconductor structure according to a second embodiment of the present invention. Figure 2 The embodiments can be used Figure 1 The component numbers and partial contents of the embodiments are the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted.

[0031] Please refer to Figure 2 The main difference between the semiconductor structure 20 of this embodiment and the aforementioned semiconductor structure 10 is that the pad 410 on the surface 400S2 of the PSRAM die 400 is bonded to the pad 110 on the semiconductor die 100 through a re-crystal bonding process.

[0032] Specifically, in this embodiment, the semiconductor structure 20 further includes a conductive film 600 and a bump BP. The conductive film 600 is, for example, disposed between the PSRAM die 400 and the semiconductor die 100, and the bump BP is, for example, disposed on the surface 400S2 of the PSRAM die 400. In this embodiment, the surface 400S2 (active surface) of the PSRAM die 400 faces the semiconductor die 100. Therefore, the conductive film 600 may, for example, contact the bump BP on the surface 400S2 of the PSRAM die 400 and the pad 110 of the semiconductor die 100, thereby electrically connecting the bump BP of the PSRAM die 400 and the pad 110 of the semiconductor die 100 through the conductive film 600.

[0033] In this embodiment, the conductive film 600 comprises an anisotropic conductive film, wherein the anisotropic conductive film includes conductive particles and an insulating material. Because the conductive particles are included in the anisotropic conductive film, when the PSRAM die 400 and the semiconductor die 100 are bonded (electrically connected) to each other through a recrystallization bonding process, the anisotropic conductive film between the PSRAM die 400 and the semiconductor die 100 is squeezed, causing the conductive particles to deform and abut against the bump BP and the pad 110, thereby forming an electrical path between the PSRAM die 400 and the semiconductor die 100. Furthermore, the insulating material in the anisotropic conductive film can be used to secure the PSRAM die 400 to the semiconductor die 100.

[0034] In addition, in this embodiment, the semiconductor structure 20 further includes an encapsulation layer 700. The encapsulation layer 700 is disposed on the semiconductor die 100 and surrounds the PSRAM die 400 and the bump BP to provide a sealed and protective seal. Furthermore, the encapsulation layer 700, for example, exposes the surface 400S1 of the PSRAM die 400. The encapsulation layer 700 may be made of, for example, epoxy resin or other suitable materials, but the present invention is not limited thereto.

[0035] Figure 3 FIG1 is a flow chart of a method for manufacturing a semiconductor structure according to a first embodiment of the present invention. Figure 3 The embodiments can be used Figure 1 The component numbers and partial contents of the embodiments are the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted.

[0036] Please refer to Figure 3 First, a PSRAM wafer 400a is provided, which includes a plurality of PSRAM dies 400 to be cut. The introduction of the PSRAM dies 400 can be referred to the above embodiment and will not be repeated here.

[0037] Next, the PSRAM wafer 400a is placed on the dicing tape DT, with the surface 400S1 of the PSRAM die 400 to be diced facing the dicing tape DT. The PSRAM wafer 400a can be secured to the dicing tape DT, for example, via an adhesive layer AL. The adhesive layer AL is described in detail in the previous embodiment and will not be further described here. In this embodiment, a dicing frame DF can be provided surrounding the dicing tape DT to secure the dicing tape DT.

[0038] Next, the PSRAM wafer 400a is diced to form a plurality of PSRAM dies 400. In this embodiment, the PSRAM wafer 400a can be diced using a wafer dicing device (not shown), but the present invention is not limited thereto. Because the PSRAM wafer 400a is secured to the dicing tape DT, the plurality of PSRAM dies 400 can still be neatly arranged on the dicing tape DT after the PSRAM wafer 400a is diced.

[0039] Then, the PSRAM die 400 and the dicing tape DT are separated. The PSRAM die 400 and the dicing tape DT can be separated by performing a suitable separation process, but the present invention is not limited thereto. In this embodiment, after the PSRAM die 400 and the dicing tape DT are separated, an adhesive layer AL is disposed on the surface 400S1 of the PSRAM die 400.

[0040] Next, a wire bonding process is performed to bond the pads 410 on the surface 400S2 of the PSRAM die 400 to the pads 110 on the semiconductor die 100. The wire bonding process may include the following steps, but the present invention is not limited thereto.

[0041] (1) The surface 400S1 of the PSRAM chip 400 opposite to the active surface is placed facing the surface 100S of the semiconductor chip 100, and the PSRAM chip 400 is bonded to the semiconductor chip 100 using an adhesive layer AL. The surface 400S2 of the PSRAM chip 400 is, for example, the active surface of the PSRAM chip 400. That is, a plurality of pads 410 and / or other connecting components can be, for example, disposed on the surface 400S2 of the PSRAM chip 400. It is worth noting that the "active surface" (also referred to as the front side) of the PSRAM chip 400 is the surface on which the back-end-of-line (BEOL) process is formed, and the opposite side of the "active surface" is the back side of the semiconductor chip 100, which will be Figure 7 Described in the embodiments shown below. In some embodiments, the adhesive layer AL is cured at a temperature below 100°C to bond the PSRAM die 400 to the semiconductor die 100. In this embodiment, a device layer 200 and a passivation layer 300 are provided on the semiconductor die 100. The description of the device layer 200 and the passivation layer 300 can be referred to the aforementioned embodiments and will not be repeated here. In addition, in this embodiment, a prohibited area KOZ is formed between the PSRAM die 400 and the device layer 200 to isolate the PSRAM die 400 from the device layer 200. It is worth noting that the thermal budget generated by bonding the PSRAM die 400 to the semiconductor die 100 can be reduced by using an ion fan or introducing gas, but the present invention is not limited to this.

[0042] (2) Forming a metal wire L electrically connected to the pad 410 of the PSRAM die 400 and the corresponding pad 110 of the semiconductor die 100, so that the PSRAM die 400 and the semiconductor die 100 can be bonded to each other through the metal wire L. Based on this, the PSRAM die 400 can be electrically connected to the semiconductor die 100 and / or the devices in the device layer 200.

[0043] Then, a sealing layer 500 is formed to cover the pads 110 of the semiconductor die 100 and the pads 410 of the PSRAM die 400. The sealing layer surrounds the metal wires L to provide a sealing and protective effect. In some embodiments, the sealing layer 500 is formed by curing the sealing material layer at a temperature below 100°C.

[0044] At this point, the fabrication of the semiconductor structure 10 is completed. Although the fabrication method of the semiconductor structure 10 of this embodiment is described using the above method as an example, the fabrication method of the semiconductor structure of the present invention is not limited thereto.

[0045] Figure 4 FIG2 is a flow chart of a method for manufacturing a semiconductor structure according to a second embodiment of the present invention. Figure 4 The embodiments can be used Figure 2 The component numbers and partial contents of the embodiments are the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted.

[0046] Please refer to Figure 4 First, a PSRAM wafer 400a is provided, which includes a plurality of PSRAM dies 400 to be cut. The introduction of the PSRAM dies 400 can be referred to the above embodiment and will not be repeated here.

[0047] Next, a bump BP is formed on each of the plurality of PSRAM dies 400 to be cut. The bump BP can be formed, for example, by electroplating, but the present invention is not limited thereto. In this embodiment, the bump BP is disposed on the surface 400S2 of the PSRAM dies 400 to be cut.

[0048] Thereafter, the PSRAM wafer 400 a is placed on the dicing tape DT, wherein the surfaces 400S1 of the PSRAM dies 400 to be diced face the dicing tape DT and are fixed on the dicing tape DT.

[0049] The PSRAM wafer 400a is then cut to form a plurality of PSRAM dies 400. In this embodiment, the PSRAM wafer 400a can be cut using a wafer cutting device (not shown), but the present invention is not limited thereto. Since the PSRAM wafer 400a is secured to the dicing tape DT, the plurality of PSRAM dies 400 can still be neatly arranged on the dicing tape DT after the PSRAM wafer 400a is cut.

[0050] Then, the PSRAM die 400 and the dicing tape DT are separated. The PSRAM die 400 and the dicing tape DT can be separated by performing a suitable separation process, but the present invention is not limited thereto.

[0051] Next, multiple PSRAM dies 400 are placed on a temporary substrate TS, with surfaces 400S1 of the PSRAM dies 400 facing the temporary substrate TS. In other words, the PSRAM dies 400 are placed face-up on the temporary substrate TS. In some embodiments, the PSRAM dies 400 may be bonded to the temporary substrate TS via a die adhesive film (not shown), but the present invention is not limited thereto.

[0052] Then, an encapsulation layer 700 is formed on the temporary substrate TS to form an encapsulation structure ES. The encapsulation structure ES includes multiple PSRAM dies 400 and the encapsulation layer 700, wherein the encapsulation layer 700 surrounds the multiple PSRAM dies 400 and exposes a portion of the bumps BP. The method for forming the encapsulation layer 700 may, for example, include the following steps. First, an encapsulation material layer (not shown) is formed on the temporary substrate TS to surround and cover the multiple PSRAM dies 400. The encapsulation material layer may, for example, be formed using a molding process or other suitable process, but the present invention is not limited thereto. Next, the encapsulation material layer is planarized (e.g., polished) until the bumps BP are exposed, thereby forming the encapsulation layer 700. The material of the encapsulation layer 700 may, for example, be epoxy resin, but the present invention is not limited thereto.

[0053] Then, the encapsulated structure ES and the temporary substrate TS are separated by performing a suitable separation process, but the present invention is not limited thereto.

[0054] Then, the encapsulation structure ES is cut to form a plurality of PSRAM dies 400 surrounded by the encapsulation layer 700. In this embodiment, the encapsulation structure ES can be cut by performing a suitable cutting process, but the present invention is not limited thereto.

[0055] Next, in this embodiment, a re-crystal bonding process is performed to bond the bump BP on the surface 400S2 of the PSRAM die 400 to the pad 110 on the semiconductor die 100. The re-crystal bonding process may include the following steps, but the present invention is not limited thereto.

[0056] (1) A conductive film 600 covering the pad 110 is formed on the semiconductor die 100. (2) The PSRAM die 400 and the conductive film 600 are pressed together at a temperature of approximately 140° C. for several seconds so that the PSRAM die 400 can be bonded to the semiconductor die 100 through the conductive film 600. Specifically, in this embodiment, the conductive film 600 includes an anisotropic conductive film. Since the anisotropic conductive film includes conductive particles, when the PSRAM die 400 and the semiconductor die 100 are bonded to each other through the recrystallization bonding process, the anisotropic conductive film between the PSRAM die 400 and the semiconductor die 100 is squeezed, causing the conductive particles to deform and abut against the bump BP and the pad 110, thereby forming an electrical path between the PSRAM die 400 and the semiconductor die 100.

[0057] In this embodiment, a device layer 200 and a passivation layer 300 are disposed on the semiconductor die 100 . The description of the device layer 200 and the passivation layer 300 can be referred to the above embodiments and will not be repeated here.

[0058] At this point, the fabrication of the semiconductor structure 20 is completed. Although the fabrication method of the semiconductor structure 10 of this embodiment is described using the above method as an example, the fabrication method of the semiconductor structure of the present invention is not limited thereto.

[0059] Figure 5A Based on Figure 1 A schematic top view of an embodiment of a semiconductor structure is shown, and Figure 5B Based on Figure 1 FIG1 is a top view schematic diagram of another embodiment of a semiconductor structure shown in FIG1. Figure 5A as well as Figure 5B The embodiments can be used separately Figure 1 The component numbers and partial contents of the embodiments are the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted.

[0060] Please refer to Figure 5A as well as Figure 5B , which each show a semiconductor structure 10a ( Figure 1 An embodiment of a semiconductor structure shown) and a semiconductor structure 10b ( Figure 1 Another embodiment of the semiconductor structure shown further includes a plurality of pads CP formed on the semiconductor die 100.

[0061] Specifically, the surface 100S of the semiconductor die 100 includes a plurality of pads CP formed thereon, and when viewed from the top of the PSRAM die 400 , the PSRAM die 400 and the plurality of pads CP substantially form a straight line L on the edge 100E of the semiconductor structure 10 .

[0062] When with Figure 6B When compared with the conventional semiconductor structure 1 shown, the semiconductor structure 10a can have a relatively large glass area (on which the device layer 200 is disposed), and the semiconductor structure 10b can have a relatively small size. This is because the PSRAM die 400 is externally mounted on the semiconductor die 100 rather than embedded in the semiconductor die 100.

[0063] In summary, by attaching a PSRAM die externally to a semiconductor die, the size and / or performance of the integrated circuit within the semiconductor die are not limited by the PSRAM die. In other words, the semiconductor structure provided by the present invention can have a relatively small size and / or relatively good performance. Furthermore, the memory integrated within the semiconductor structure provided by the present invention is PSRAM, which combines the advantages of DRAM's low cost and large capacity with the user interface of SRAM, thereby reducing the power consumption of the semiconductor structure provided by the present invention.

[0064] It is worth noting that in the description of the above embodiments, the "active surface" (also called the front side) of the die is the surface on which the back-end process is formed, and the opposite side of the "active surface" is the surface of the semiconductor substrate (the back side of the die). For ease of understanding, Figure 7 The definition of the front and back sides of a semiconductor die or semiconductor wafer is shown. Figure 1 PSRAM die 400 in the semiconductor wafer (e.g. Figure 3 Referring to the PSRAM wafer 400a in FIG. 1 , the semiconductor structure 80 may include a semiconductor substrate 83 and a back-end-of-line (FEOL) structure 85, wherein a front-end-of-line (FEOL) structure 84 is formed in and / or on the semiconductor substrate 83. A memory device or a semiconductor device may be formed on the semiconductor substrate 83. According to some embodiments of the present invention, a surface of the back-end-of-line (FEOL) structure 85 may be a front side 81 of the semiconductor structure 80, and a surface of the semiconductor substrate 83 opposite to the surface of the back-end-of-line (FEOL) structure 85 may be a back side 82 of the semiconductor structure 80. However, the present invention is not limited to this embodiment, and the definitions of the front side and the back side of the semiconductor structure 80 may be interchangeable.

[0065] Those skilled in the art will appreciate that modifications may be made to the technical solutions described in the aforementioned embodiments and their variations without departing from the scope or spirit of the present invention. Based on the contents described in the aforementioned embodiments, the present invention is intended to cover modifications and variations that fall within the scope of the appended claims and their equivalents.

Claims

1. A semiconductor structure, characterized in that include: semiconductor grains; an element layer disposed on a surface of the semiconductor crystal grain, wherein the element layer comprises an organic layer; and The virtual static random access memory crystal grain is disposed on the surface of the semiconductor crystal grain and is electrically connected to the semiconductor crystal grain. 2 . The semiconductor structure of claim 1 , wherein the semiconductor die comprises a display driver integrated circuit, and the display driver integrated circuit is configured to drive the device layer by utilizing the virtual static random access memory die. 3 . The semiconductor structure according to claim 1 , wherein a keep-out zone is formed between the virtual SRAM die and the device layer, so as to isolate the device layer from the virtual SRAM die by air. 4 . The semiconductor structure according to claim 1 , wherein the device layer comprises a micro organic light emitting diode, and the semiconductor die is configured to control the micro organic light emitting diode by accessing the virtual static random access memory die.

5. The semiconductor structure of claim 1 , wherein the virtual SRAM die comprises a first surface and a second surface, the first surface of the virtual SRAM die is attached to the surface of the semiconductor die, the surface of the semiconductor die has a plurality of first pads formed thereon, and the second surface of the virtual SRAM die has a plurality of second pads formed thereon, and the semiconductor structure further comprises: A plurality of metal wires are configured to connect the plurality of second pads to the plurality of first pads. 6 . The semiconductor structure according to claim 5 , further comprising a sealing layer, wherein the sealing layer covers the first pads of the semiconductor die and the second pads of the virtual static random access memory die, and surrounds the metal wire. 7 . The semiconductor structure of claim 5 , wherein the semiconductor die is configured to access the virtual static random access memory die through the metal wire.

8. The semiconductor structure according to claim 1 , wherein the surface of the semiconductor die has a plurality of first pads formed thereon, and the semiconductor structure further comprises: a plurality of bumps formed on the surface of the virtual static random access memory die; as well as A conductive film is formed on the plurality of first pads, The virtual static random access memory die and the semiconductor die are electrically connected to each other through the plurality of bumps and the conductive film. 9 . The semiconductor structure according to claim 8 , further comprising an encapsulation layer, wherein the encapsulation layer is disposed on the semiconductor die and surrounds the virtual SRAM die and the plurality of bumps.

10. The semiconductor structure of claim 1 , wherein a surface of the semiconductor die further comprises a plurality of pads formed thereon, and when viewed from a top of the virtual SRAM die, the virtual SRAM die and the plurality of pads substantially form a straight line on an edge of the semiconductor structure.

11. A method for manufacturing a semiconductor structure, comprising: Provide virtual static random access memory wafers; cutting the virtual static random access memory wafer to form a plurality of virtual static random access memory dies; as well as The virtual static random access memory die is bonded to the surface of a semiconductor die, wherein a device layer and a passivation layer are disposed on the surface of the semiconductor die, and the device layer includes an organic layer.

12. The method for manufacturing a semiconductor structure according to claim 11, further comprising: A wire bonding process is performed to bond a plurality of second pads disposed on the virtual static random access memory die to a plurality of first pads disposed on the surface of the semiconductor die.

13. The method for manufacturing a semiconductor structure according to claim 12, wherein performing the wire bonding process comprises: bonding the dummy SRAM die to the semiconductor die via an adhesive layer disposed on a first surface of the dummy SRAM die, wherein the first surface of the dummy SRAM die is opposite to an active surface of the dummy SRAM die, and the adhesive layer is cured at a temperature below 100° C.; and A plurality of metal wires are formed, wherein the plurality of metal wires are electrically connected to the plurality of second pads of the virtual static random access memory die and to corresponding first pads of the semiconductor die.

14. The method for manufacturing a semiconductor structure according to claim 13, further comprising, after forming the plurality of metal wires: A sealing layer is formed to cover the first pads of the semiconductor die and the second pads of the virtual static random access memory die, and the sealing layer surrounds the metal wires, wherein the sealing layer is cured at a temperature below 100° C.

15. The method for manufacturing a semiconductor structure according to claim 11, further comprising: Before dicing the virtual SRAM wafer, a plurality of bumps are formed on the active surface of the virtual SRAM die, wherein the active surface of the virtual SRAM die is opposite to the first surface of the virtual SRAM die.

16. The method for manufacturing a semiconductor structure according to claim 15, further comprising: A re-bonding process is performed to bond the plurality of bumps disposed on the virtual static random access memory die to a plurality of first pads disposed on the surface of the semiconductor die.

17. The method for manufacturing a semiconductor structure according to claim 16, wherein performing the re-crystal bonding process comprises: forming a conductive film to cover the plurality of first pads disposed on the surface of the semiconductor die; as well as The virtual SRAM die and the conductive film are pressed together at a temperature of about 140° C., wherein the active surface of the virtual SRAM die faces the surface of the semiconductor die.

18. The method for manufacturing a semiconductor structure according to claim 16, further comprising: after dicing the virtual SRAM wafer and before performing the re-bonding process; Disposing the plurality of virtual SRAM dies on a temporary substrate, wherein the first surfaces of the plurality of virtual SRAM dies face the temporary substrate; forming an encapsulation layer on the temporary substrate to form an encapsulation structure, wherein the encapsulation structure includes the plurality of virtual static random access memory dies and the encapsulation layer, and the encapsulation layer surrounds the plurality of virtual static random access memory dies and exposes portions of the plurality of bumps; separating the encapsulated structure from the temporary substrate; as well as The encapsulation structure is cut to form a plurality of virtual SRAM dies surrounded by the encapsulation layer. 19 . The method for manufacturing a semiconductor structure according to claim 11 , wherein the semiconductor die comprises a display driver integrated circuit, and the device layer comprises a micro organic light emitting diode.

20. The method for manufacturing a semiconductor structure according to claim 11, further comprising: A keep-out area is formed between the virtual static random access memory die and the device layer.

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