Dynamic random access memory and preparation method thereof
By adopting a Z-channel structure and an embedded ferroelectric layer design in dynamic random access memory, the problems of insufficient sensing margin and retention time after device size reduction are solved, and efficient data storage performance and low power consumption characteristics are achieved.
Patent Information
- Application Number
- CN202511153905.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-18
- Publication Date
- 2025-09-30
AI Technical Summary
Existing TFET-based 1T-DRAMs find it difficult to achieve both high sensing margin and long retention time while reducing device size. Traditional methods cannot achieve a response time of seconds at room temperature and also suffer from the problem of low on-state current.
A Z-type channel structure is adopted, combined with the design of the first and second dielectric electrode layers, source electrode, drain electrode, source region, channel region, storage window and drain region. By extending the vertical tunneling channel length and expanding the lateral gate-source overlap area, the gate's electrostatic control ability of the channel is enhanced, and a ferroelectric layer and a multi-gate structure are embedded to regulate the electric field and tunneling efficiency.
Without increasing the device area, the line tunneling probability and on-state current are improved, the sensing margin and retention time are optimized, the device power consumption is reduced, and efficient data storage performance is achieved.
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Figure CN120730734A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor storage technology, and in particular to a dynamic random access memory and a preparation method thereof. Background Art
[0002] Dynamic random access memory (DRAM), the core hardware unit responsible for data storage in electronic products, is widely used in fields such as cloud computing, smart devices, and artificial intelligence. Traditional DRAM, composed of metal-oxide-semiconductor field-effect transistors (MOSFETs) and capacitors, boasts simple configuration, high chip density, and low power consumption. However, with the scaling of technology nodes, 1T1C-DRAM faces the problem that the capacitor area cannot be scaled down proportionally with the transistors, resulting in a large chip area occupied by the capacitors, which has restricted the development of this type of memory. Although new structures such as three-dimensional storage capacitors and trench capacitors have been proposed to address this issue, these approaches increase process costs and face significant challenges in manufacturing and yield. Capacitor-free single-transistor DRAM (1T-DRAM) overcomes these capacitor scaling limitations and offers higher data rates and storage density, attracting considerable research attention. 1T-DRAM utilizes a floating body effect and silicon-on-insulator (SOI) structure to achieve its storage characteristics. Compared to 1T1C-DRAM, 1T-DRAM employs different charge storage mechanisms, including impact ionization, bipolar transport, band-to-band tunneling, and gate tunneling. However, 1T-DRAM based on MOSFET has the problem of short charge storage time (generally less than 64ms). In order to save data for a long time, the refresh frequency of 1T-DRAM needs to be increased, which will also increase dynamic power consumption. In addition, the high off-state leakage of MOSFET also makes it difficult to reduce the static power consumption of 1T-DRAM based on it. off ), high on / off ratio (I on / I off ) and steep subthreshold swing (SS avg ) and other advantages, it is expected to replace MOSFET in the low power consumption field. For 1T-DRAM, high I on / I off Helps improve its sensing margin (SM), low I off It can reduce its read "0" current (I R0 ) and static power consumption. Therefore, research on 1T-DRAM based on TFET has been developed in recent years, with a focus on improving the sensing margin (SM) and retention time (RT).
[0003] Under the existing technical background, although 1T-DRAM based on TFET has made some progress in improving the sensing margin (SM) and retention time (RT), it still has bottlenecks: First, a 1T-DRAM with an asymmetric gate structure is proposed, which can pass N + The doping layer structure increases SM to 1.11μA / μm; secondly, the gate-drain underlap structure, double-gate structure and triple-gate structure are used to increase RT. Although the RT can be increased to 1.8s, the gate of this 1T-DRAM is as long as 600nm, which cannot reduce the device size. Moreover, when the storage area is scaled to below 100nm, the above methods cannot achieve a response time of seconds at room temperature. In addition, SM is a key parameter in the design of peripheral circuits. Traditional TFET-based 1T-DRAM will increase the RT due to the on-state current (I on ) is relatively low, resulting in a low SM. Therefore, achieving both high SM and RT while reducing device size is the focus of current research. Summary of the Invention
[0004] The present invention aims to provide a dynamic random access memory and a preparation method thereof to solve the above-mentioned technical problems and increase the effective line tunneling area without increasing the device area, thereby being more conducive to device scaling.
[0005] To solve the above technical problems, the present invention provides a dynamic random access memory device comprising a second dielectric electrode layer, a source electrode, a drain electrode, a source region, a channel region, a memory window, a drain region, and a first dielectric electrode layer. The source electrode, drain electrode, source region, channel region, memory window, and drain region are disposed on the upper surface of the second dielectric electrode layer; the first dielectric electrode layer covers the upper surfaces of the channel region, the memory window, and the drain region; the channel region is Z-shaped and includes a first lateral region, a first longitudinal region, and a second lateral region connected in sequence; the upper surface of the source region contacts the lower surface of the first lateral region; one side surface of the source region contacts the source electrode, and the other side surface of the source region contacts one side surface of the first longitudinal region; one side surface of the memory window contacts one side surface of the second lateral region; one side surface of the drain region contacts the drain electrode, and the other side surface of the drain region contacts another side surface of the memory window.
[0006] In the above scheme, by setting the channel area in a Z shape, the effective line tunneling area can be increased by extending the tunneling channel length in the vertical direction without increasing the overall area of the device; by expanding the lateral gate-source overlap area, the electrostatic control ability of the gate on the channel is enhanced, the formation of the electron-hole double layer is promoted, and the line tunneling probability can be increased, which is more conducive to the scaling of the device.
[0007] Furthermore, the first dielectric electrode layer includes a first dielectric layer and a first tunneling gate electrode; wherein the lower surface of the first dielectric layer contacts the upper surface of the channel region, the upper surface of the storage window and the upper surface of the drain region, and the upper surface of the first dielectric layer contacts the lower surface of the first tunneling gate electrode.
[0008] In the above scheme, by directly contacting the lower surface of the first dielectric layer with the channel region, storage window, and drain region, the first tunneling gate electrode is physically isolated from the underlying semiconductor structure, preventing direct electrical conduction between the first tunneling gate electrode and the semiconductor and shorting between the first tunneling gate electrode and the channel or drain region, thus ensuring electrical isolation of the device. The first dielectric layer also converts the voltage signal on the first tunneling gate electrode into an electric field perpendicular to the channel region and storage window, ensuring that the electric field precisely acts on the electron-hole double layer induced by the first tunneling gate electrode in the channel region and the band structure of the storage window, providing a physical basis for controlling line tunneling. The first tunneling gate electrode, through electrical connection to the first dielectric layer, can induce an electron region in the Z-shaped channel region below the first dielectric layer. This electron region forms an electron-hole double layer with the source region, providing a carrier source for line tunneling. Furthermore, by adjusting the voltage of the first tunneling gate electrode, the electron concentration in the electron-hole double layer can be dynamically controlled, thereby controlling the on and off of line tunneling and optimizing the sensing margin.
[0009] Furthermore, the first dielectric electrode layer further includes a ferroelectric layer; wherein the ferroelectric layer is located on the lower surface of the first tunneling gate electrode, and the lower surface of the ferroelectric layer is in contact with the upper surface of the first dielectric layer.
[0010] In the above scheme, by embedding a ferroelectric layer in the first dielectric layer and the first tunneling gate electrode, the negative capacitance characteristics of the ferroelectric material can be utilized to induce a "gate voltage amplification effect," which amplifies the voltage signal applied to the first tunneling gate electrode, thereby enhancing the surface potential of the channel region and exacerbating the band bending, thereby promoting electron tunneling between the electron-hole double layer in the channel region and increasing the on-state current. The embedded ferroelectric layer can also reduce the subthreshold swing, achieving efficient tunneling at low voltages and reducing device power consumption. The coercive electric field and remanent polarization strength in the ferroelectric layer can also be adjusted to control the intensity of the electric field effect on the electron-hole double layer in the channel region, thereby regulating the linear tunneling efficiency in the electron-hole double layer. This can both increase the on-state current and suppress the off-state current, thereby improving the read current ratio (read current ratio = on-state current / off-state current) and the sensing margin.
[0011] Furthermore, the second dielectric electrode layer includes a second dielectric layer, a second tunneling gate electrode and a storage gate electrode; wherein the second tunneling gate electrode and the storage gate electrode are embedded in the second dielectric layer; and the storage gate electrode corresponds to the storage window in the vertical direction.
[0012] In the above scheme, by utilizing the high work function characteristics of the second tunneling gate electrode, a hole layer is induced in the channel region, which forms an electron-hole double layer with the electron layer induced by the first tunneling gate electrode, further expanding the effective line tunneling area and improving the on-state current. In addition, a three-dimensional control structure is provided in which the second tunneling gate electrode and the first tunneling gate electrode form upper and lower gates, which can accurately control the opening and closing of line tunneling through the voltage difference, avoiding an increase in the off-state current and improving the read current ratio. By embedding the storage gate electrode in the second dielectric layer, multi-gate coordinated control can be achieved without increasing the device size, solving the problem of performance degradation under traditional structural size scaling. In addition, the storage gate electrode is directly opposite the storage window above, which can improve the tunneling gate electrode's control sensitivity to carriers, ensuring that the sensing margin and read current ratio can be improved even at low voltages.
[0013] Furthermore, the storage window is a SiGe structure.
[0014] In the above scheme, the bandgap width of the SiGe material used is lower than that of the Si material, which can reduce the barrier height for inter-band tunneling, thereby promoting the tunneling of electrons from the Z-shaped channel to the storage window and increasing the on-state current. At the same time, the use of narrow-bandgap SiGe material enables the device to achieve efficient tunneling even at low operating voltages, reducing energy consumption and solving the problem of insufficient tunneling current at low voltages in traditional structures. Moreover, by adjusting the Ge component of the SiGe material, the band structure of the storage window can also be controlled, allowing the device to achieve both a high read current ratio and a high sensing margin at low bias voltages, thereby improving data reading accuracy.
[0015] The present invention provides a method for preparing a dynamic random access memory, comprising the following steps:
[0016] Determining a silicon-on-insulator wafer with a substrate;
[0017] Fabricating a storage window on the insulator silicon wafer to obtain a first silicon wafer;
[0018] Growing an intrinsic silicon epitaxial layer on the first silicon wafer and forming a source region to obtain a second silicon wafer;
[0019] The intrinsic silicon epitaxial layer of the second silicon wafer is etched to form a Z-shaped channel region, thereby obtaining a third silicon wafer; wherein the Z-shaped channel region includes a first lateral region, a first longitudinal region, and a second lateral region connected in sequence; a lower surface of the first lateral region contacts an upper surface of the source region; a side surface of the first longitudinal region contacts a side surface of the source region; and a side surface of the second lateral region contacts a side surface of the storage window;
[0020] preparing a drain region on the third silicon wafer so that the drain region contacts the storage window, thereby obtaining a fourth silicon wafer;
[0021] forming a first dielectric electrode layer, a source electrode, and a drain electrode on the fourth silicon wafer, such that the source electrode contacts one side of the source region, and the drain electrode contacts one side of the drain region, to obtain a fifth silicon wafer;
[0022] A substrate is etched from the fifth silicon wafer, and a second dielectric electrode layer is prepared to obtain a dynamic random access memory.
[0023] This solution provides a method for preparing a dynamic random access memory. In practical applications, it only requires etching the intrinsic silicon epitaxial layer to form a Z-shaped channel region. Without increasing the device area, it can extend the vertical tunneling path and expand the lateral gate-source overlap area, thereby increasing the effective line tunneling area, improving the line tunneling probability and enhancing the gate's electrostatic control ability of the channel, thereby promoting the formation of an electron-hole double layer and increasing the on-state current, which is more conducive to device scaling.
[0024] Furthermore, the step of fabricating a storage window on the insulator silicon wafer to obtain a first silicon wafer comprises:
[0025] depositing a first mask layer on the silicon-on-insulator wafer;
[0026] Defining a storage window area on the insulator silicon wafer and a first etching area on the first mask layer, removing the first etching area and growing SiGe in the storage window area to obtain a storage window and a second mask layer;
[0027] The second mask layer is removed to obtain a first silicon wafer.
[0028] In this approach, the first etched area is removed to expose the storage window region on the surface of the silicon-on-insulator wafer, ensuring that SiGe grows only in the designated storage window region. The narrow bandgap characteristics of the formed SiGe storage window are then utilized to form a deep potential well through the Si / SiGe heterojunction, enhancing hole storage capacity, thereby extending retention time and improving band-to-band tunneling efficiency to optimize sensing margin.
[0029] Furthermore, the step of growing an intrinsic silicon epitaxial layer on the first silicon wafer and forming a source region to obtain a second silicon wafer comprises:
[0030] growing a first intrinsic silicon epitaxial layer on the first silicon wafer to obtain a first silicon wafer to be operated;
[0031] depositing a third mask layer on the first silicon wafer to be operated;
[0032] Delimiting a second etching region on the first silicon wafer to be operated, and delimiting a third etching region on the third mask layer, removing the second etching region and the third etching region to obtain a second silicon wafer to be operated and a fourth mask layer;
[0033] Demarcating a source region on the second silicon wafer to be operated, and performing doping in the source region to obtain a source region; wherein the lower surface of the source region is in contact with the substrate;
[0034] A second intrinsic silicon epitaxial layer is grown on the source region and the fourth mask layer is removed to obtain a second silicon wafer.
[0035] In the above scheme, the target area for preparing the source region is exposed by removing the second and third etched areas, and the unetched third mask layer is retained as the fourth mask layer to continue to protect other areas, providing a precise spatial boundary for subsequent source region doping, ensuring that doping occurs only within the demarcated source region. Subsequently, doping is performed in the source region to form a source region. This source region serves as the hole supply end for line tunneling and can form the first electron-hole double layer with the electron layer induced in the subsequent Z-type channel. As the core carrier source for line tunneling, its hole concentration directly affects the magnitude of the on-state current. A second intrinsic silicon epitaxial layer is then grown on the source region, which not only fills the surface defects of the source region after doping, but also forms a complete channel substrate together with the remaining first intrinsic silicon epitaxial layer, ensuring the structural continuity of the subsequent Z-type channel during etching, and providing stable channel support for the efficient transmission of line tunneling electrons.
[0036] Furthermore, the first dielectric electrode layer, the source electrode, and the drain electrode are prepared on the fourth silicon wafer so that the source electrode contacts one side of the source region, and the drain electrode contacts one side of the drain region, to obtain a fifth silicon wafer; comprising:
[0037] Depositing a first dielectric layer, a ferroelectric layer, and a first tunneling gate electrode in sequence on the fourth silicon wafer to prepare a first dielectric electrode layer; wherein the lower surface of the first dielectric layer contacts the upper surface of the first lateral region, the upper surface of the first longitudinal region, the upper surface of the second lateral region, the upper surface of the storage window, and the upper surface of the drain region; the lower surface of the ferroelectric layer contacts the upper surface of the first dielectric layer; and the upper surface of the ferroelectric layer contacts the lower surface of the first tunneling gate electrode;
[0038] A source electrode and a drain electrode are deposited on the fourth silicon wafer so that the source electrode contacts one side of the source region and the drain electrode contacts one side of the drain region, thereby obtaining a fifth silicon wafer.
[0039] In the above scheme, by depositing a ferroelectric layer on the first dielectric layer, the negative capacitance characteristics of the ferroelectric layer can be used to induce a "gate voltage amplification effect," enhancing the surface potential and band bending of the channel region, promoting electron tunneling between the electron-hole double layer, and thus increasing the on-state current. At the same time, the thickness, coercive electric field, and residual polarization of the ferroelectric layer can be adjusted to optimize the subthreshold swing and capacitance matching, achieving efficient regulation at low voltages and effectively reducing device power consumption. Then, a first tunneling gate electrode is deposited on the ferroelectric layer. The specific work function of the first tunneling gate electrode can induce an electron region in the Z-shaped channel. This electron region forms the first electron-hole double layer with the source region, providing an electron source for line tunneling. At the same time, by adjusting the voltage on the first tunneling gate electrode, the electron concentration can be dynamically controlled, thereby controlling the on and off of line tunneling, directly affecting the on-state current and the sensing margin. Finally, source and drain electrodes are deposited on both sides of the wafer. The source electrode is in contact with one side of the source region, serving as the external lead-out terminal of the source region, providing a stable hole supply path for line tunneling, ensuring the effective connection between the source region and the external circuit, and ensuring the continuous supply of carriers during read and write operations; the drain electrode is in contact with one side of the drain region, serving as the external lead-out terminal of the drain region, responsible for collecting line tunneling electrons transmitted through the Z-type channel, forming an on-state current, and transmitting the current signal to the external circuit to realize data reading and recognition.
[0040] Furthermore, the process of etching a substrate from the fifth silicon wafer and preparing a second dielectric electrode layer to obtain a dynamic random access memory comprises:
[0041] etching a substrate from the fifth silicon wafer;
[0042] A second dielectric electrode layer is prepared in the original substrate area of the fifth silicon wafer to obtain a dynamic random access memory, specifically:
[0043] depositing an initial dielectric layer on the fifth silicon wafer;
[0044] Defining a fourth etched region and a fifth etched region in the initial dielectric layer, and removing the fourth etched region and the fifth etched region to obtain a second dielectric layer; wherein the upper surface of the second dielectric layer is in contact with the lower surface of the source electrode, the lower surface of the drain electrode, the lower surface of the source region, the lower surface of the channel region, the lower surface of the storage window, and the lower surface of the drain region;
[0045] Depositing metal in the fourth etched region to form a second tunneling gate electrode; wherein the second tunneling gate electrode is embedded in the second dielectric layer;
[0046] Depositing metal in the fifth etched region to form a storage gate electrode; wherein the storage gate electrode is embedded in the second dielectric layer;
[0047] The second tunneling gate electrode, the storage gate electrode and the second dielectric layer form a second dielectric electrode layer.
[0048] In the above scheme, metal is deposited in the fourth etched region to form a second tunneling gate electrode. The specific work function of the second tunneling gate electrode can induce a hole layer in the Z-shaped channel. This layer, combined with the electron layer induced by the first tunneling gate electrode, forms a second electron-hole double layer, thereby expanding the effective line tunneling area and increasing the on-state current. Furthermore, the second tunneling gate electrode and the first tunneling gate electrode form a "top-bottom gate" structure, which can precisely control the on and off of line tunneling through a voltage difference, avoiding an abnormal increase in the off-state current caused by false activation of line tunneling in the off state, thereby improving the read current ratio. Finally, metal is deposited in the fifth etched region to form a storage gate electrode. This can regulate the hole concentration within the storage window through electrostatic induction, optimizing the hole storage capacity and improving the retention time. Furthermore, by matching the work function of the storage gate electrode with the energy band of the storage window, efficient control can be achieved at low bias voltages, reducing programming voltage, and enhancing the hole binding ability, reducing hole leakage, and extending the retention time. BRIEF DESCRIPTION OF THE DRAWINGS
[0049] Figure 1 A structural diagram of a dynamic random access memory provided by one embodiment of the present invention;
[0050] Figure 2 A schematic flow chart of a method for manufacturing a dynamic random access memory according to an embodiment of the present invention;
[0051] Figure 3 A schematic diagram of a method for manufacturing a first silicon wafer provided by one embodiment of the present invention;
[0052] Figure 4 A schematic diagram of a method for manufacturing a second silicon wafer provided by one embodiment of the present invention;
[0053] Figure 5 A schematic diagram of a method for manufacturing a third silicon wafer provided by one embodiment of the present invention;
[0054] Figure 6 A schematic diagram of a method for manufacturing a fourth silicon wafer provided by one embodiment of the present invention;
[0055] Figure 7 A schematic diagram of a method for manufacturing a fifth silicon wafer provided by one embodiment of the present invention;
[0056] Figure 8 A schematic diagram of a method for manufacturing a dynamic random access memory provided by one embodiment of the present invention;
[0057] in:
[0058] 1. Second dielectric electrode layer; 11. Second dielectric layer; 12. Second tunneling gate electrode; 13. Storage gate electrode; 2. Source electrode; 3. Drain electrode; 4. Drain region; 5. Channel region; 6. Storage window; 7. Source region; 8. First dielectric electrode layer; 81. First dielectric layer; 82. Ferroelectric layer; 83. First tunneling gate electrode; 9. Substrate; 10. Second intrinsic silicon epitaxial layer. DETAILED DESCRIPTION
[0059] The following will provide a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.
[0060] See Figure 1 This embodiment provides a dynamic random access memory, comprising a second dielectric electrode layer 1, a source electrode 2, a drain electrode 3, a source region 7, a channel region 5, a storage window 6, a drain region 4, and a first dielectric electrode layer 8. The source electrode 2, drain electrode 3, source region 7, channel region 5, storage window 6, and drain region 4 are disposed on the upper surface of the second dielectric electrode layer 1. The first dielectric electrode layer 8 covers the upper surfaces of the channel region 5, the storage window 6, and the drain region 4. The channel region 5 is Z-shaped and includes a first lateral region, a first longitudinal region, and a second lateral region connected in sequence. The upper surface of the source region 7 contacts the lower surface of the first lateral region, one side of the source region 7 contacts the source electrode 2, and the other side of the source region 7 contacts one side of the first longitudinal region. One side of the storage window 6 contacts one side of the second lateral region. One side of the drain region 4 contacts the drain electrode 3, and the other side of the drain region 4 contacts another side of the storage window 6.
[0061] In this embodiment, the dynamic random access memory (DRAM) consists of a tunneling field-effect transistor (FET) and a memory cell. The source electrode 2 is made of platinum, and the drain electrode 3 is made of hafnium. By arranging the channel region 5 in a Z-shape, with the bulk material being Si and a thickness of 10 nm, the effective linear tunneling area can be increased by extending the vertical tunneling channel length without increasing the overall device area. This is because linear tunneling electrons are primarily concentrated in the electron layers at the top and sides of the source region 7. The structural design of the Z-shaped channel region 5 in this embodiment provides these electrons with a longer tunneling path and a larger contact area with the channel region 5, effectively expanding the effective area for tunneling. The channel sensing margin in the first lateral region between the source region 7 and the first dielectric electrode layer 8 gradually decreases with increasing channel thickness. When the channel thickness of the first lateral region is greater than 4 nm, the sensing margin decreases by an order of magnitude. This is because the increased channel thickness in the first lateral region reduces the control of the first dielectric electrode layer 8 over the channel in the first lateral region, resulting in reduced linear tunneling. However, the off-state current is insensitive to changes in the channel thickness of the first lateral region. In addition, the threshold voltage will shift to the left and tend to saturation as the channel thickness of the first lateral region decreases. It can be seen that the narrower the thickness of the channel region 5, the more conducive it is to turning on the device. After comprehensive compromise, it can be concluded that when the thickness of the channel in the first lateral region is 3nm, the optimal device performance can be obtained. The increase in the effective tunneling area directly increases the on-state current of the device. Since the sensing margin is the on-state current (I R1 ) and the off-state current (I R0 ) difference, the reading current ratio is the on-state current (I R1 ) and the off-state current (I R0 ), therefore, the increase in on-state current can simultaneously improve the sensing margin and read current ratio. At the same time, these line tunneling electrons can be efficiently collected by the drain end (drain region 4 and drain electrode 3) through the Z-shaped channel region 5. This is essentially because the Z-shaped channel region 5 provides a larger effective tunneling area, resulting in more carriers participating in the tunneling. This directly reflects the effect of increasing the effective line tunneling area on I R1 Furthermore, the potential gradient at the tunneling junction bends the energy band. The higher electric field formed by the potential gradient can further enhance the tunneling efficiency of electrons between the electron-hole double layer, thereby further increasing the on-state current. Preferably, the Z-shaped channel region 5 of this embodiment also expands the lateral gate-source overlap area, broadening the range of control that the tunneling gate electrode can exert on the electron layer or hole layer in the channel region 5. This increases the physical area where line tunneling can occur, promotes the formation of the electron-hole double layer, and enables the device to maintain sufficient tunneling efficiency even when the device is reduced in size, thereby further facilitating device scaling.
[0062] Furthermore, the first dielectric electrode layer 8 includes a first dielectric layer 81 and a first tunneling gate electrode 83; wherein, the lower surface of the first dielectric layer 81 contacts the upper surface of the channel region 5, the upper surface of the storage window 6 and the upper surface of the drain region 4, and the upper surface of the first dielectric layer 81 contacts the lower surface of the first tunneling gate electrode 83.
[0063] In this embodiment, there are two electron-hole double layers in the Z-shaped channel region 5, which can help improve the sensing margin of the device. Specifically, the first dielectric layer 81 uses HfO2 gate dielectric, and the first tunneling gate electrode 83 is made of metal aluminum. Whether the electron zone in the Z-shaped channel region 5 is formed is mainly controlled by the metal work function (φ M1 ), when φ M1 =4.2eV, an electron region can be induced in the Z-channel region 5, and when φ M1 = 4.6eV, the Z-type channel region 5 is in the intrinsic state. M1 As the sensing margin decreases, the sensing margin will gradually increase. This is because φ M1 The smaller the value, the more electrons are induced in the Z-type channel region 5 close to the first tunneling gate electrode, thereby increasing the linear tunneling rate between the electron-hole double layer between the first tunneling gate electrode and the source region 7, and ultimately resulting in an on-state current I R1 As for the off-state current I R0 As φM1 decreases, it will remain unchanged at first. However, when φM1 decreases to 4.1eV, the off-state current I R0 The value will increase by four orders of magnitude. This phenomenon is because when φ M1 = 4.1eV, wire tunneling is turned on during the off-state operation, making the off-state current I R0A sudden increase in the change trend appears. In addition, by directly contacting the lower surface of the first dielectric layer 81 with the channel region 5, the storage window 6, and the drain region 4, the first tunneling gate electrode 83 can be physically isolated from the underlying semiconductor structure, avoiding direct conduction between the first tunneling gate electrode 83 and the semiconductor, and preventing the first tunneling gate electrode 83 from forming a short circuit with the channel region 5 or the drain region 4, thereby ensuring the electrical isolation of the device. The use of the first dielectric layer 81 can also convert the voltage signal on the first tunneling gate electrode 83 into an electric field perpendicular to the channel region 5 and the storage window 6, ensuring that the electric field can accurately act on the electron-hole double layer induced by the first tunneling gate electrode 83 in the channel region 5 and the band structure of the storage window 6, providing a physical basis for line tunneling control. The first tunneling gate electrode 83, through electrical connection with the first dielectric layer 81, can induce an electron region in the Z-shaped channel region 5 below the first dielectric layer 81. This electron region and the source region 7 will form an electron-hole double layer, providing a carrier source for line tunneling. Furthermore, by adjusting the voltage of the first tunneling gate electrode 83 , the electron concentration in the electron-hole double layer can be dynamically controlled, thereby controlling the on and off of the line tunneling, thereby optimizing the sensing margin.
[0064] Furthermore, the first dielectric electrode layer 8 further includes a ferroelectric layer 82 ; wherein the ferroelectric layer 82 is located on the lower surface of the first tunneling gate electrode 83 , and the lower surface of the ferroelectric layer 82 contacts the upper surface of the first dielectric layer 81 .
[0065] In this embodiment, by embedding a ferroelectric layer 82 (the material is HZO, and the thickness is selected to be 3nm) in the first dielectric layer 81 and the first tunneling gate electrode 83, the negative capacitance characteristics of the ferroelectric material can be used to induce a "gate voltage amplification effect", that is, amplifying the voltage signal transmitted by the first tunneling gate electrode 83, thereby enhancing the surface potential of the channel region 5 and intensifying the degree of band bending, thereby promoting electron tunneling between the electron-hole double layer in the channel region 5, and increasing the on-state current; in addition, as the thickness of the ferroelectric layer 82 increases, the degree of capacitance matching is gradually optimized. When a stable negative capacitance effect is formed, it can not only significantly increase the on-state current of the device, but also effectively reduce the subthreshold swing. This characteristic plays a key role in improving the performance of the device and reducing the device supply voltage in this embodiment, because the gate voltage amplification effect can be controlled by changing the thickness of the ferroelectric layer 82. When the thickness of the ferroelectric layer 82 is ≤1nm, the subthreshold swing of the device will initially stabilize at 40mV / decade and then show an upward trend. When the thickness of the ferroelectric layer 82 is ≥1nm, the subthreshold swing begins to decrease before the gate voltage reaches 0.5V. As the thickness of the ferroelectric layer 82 increases, the subthreshold swing decreases more, and the gate voltage threshold corresponding to its initial decrease gradually decreases. Although the subthreshold swing can be reduced to approximately 10mV / decade when the ferroelectric layer 82 is 5nm thick, based on the analysis of semiconductor surface potential characteristics, the device will cause capacitance mismatch due to the excessive thickness of the ferroelectric layer 82, resulting in an unstable hysteresis state. Therefore, although a too small thickness of the ferroelectric layer 82 can ensure capacitance matching, the device performance improvement is limited; a too large thickness can easily lead to hysteresis effect. After comprehensive optimization, the thickness of the ferroelectric layer 82 is controlled in the range of 1-3nm. The device in this embodiment can achieve the best balance between subthreshold swing characteristics and working stability. Finally, the coercive electric field and residual polarization intensity in the ferroelectric layer 82 can also be adjusted. As the coercive electric field increases, the off-state current will gradually increase; and as the residual polarization intensity continues to decrease, the sensing margin will gradually increase, but when the residual polarization intensity value is reduced to 0.6μC / cm 2 Therefore, in order to balance high sensing margin and low off-state current, the optimal values of coercive electric field and remanent polarization intensity are set to 1.5MV / cm and 0.6μC / cm respectively. 2 , which can both increase the on-state current and suppress the off-state current, ultimately improving the read current ratio and sensing margin.
[0066] Furthermore, the second dielectric electrode layer 1 includes a second dielectric layer 11, a second tunneling gate electrode 12 and a storage gate electrode 13; wherein the second tunneling gate electrode 12 and the storage gate electrode 13 are embedded in the second dielectric layer 11; and the storage gate electrode 13 corresponds to the storage window 6 in the vertical direction.
[0067] In this embodiment, based on the charge plasma principle, an electron layer can be induced in the Z-shaped channel region 5 near the first tunneling gate electrode 83. This electron layer can establish two electron-hole double layers with the hole layer induced in the source region 7 and the hole layer induced in the second tunneling gate electrode 12, thereby greatly improving the linear tunneling probability of the device and ultimately improving the storage performance of the device. The second dielectric layer 11 uses HfO2 gate dielectric, and the second tunneling gate electrode 12 is made of metal palladium. The metal work function (φ M2 ) has the following effects on the device: R0 ), when φM2 increases, I R0 First, it will slowly increase with φM2; and when φM2>5.6eV, I R0 will increase dramatically (this is due to the unexpected activation of line tunneling in the off state); secondly, for the on-state current (I R1 ), it will first increase with the increase of φM2. When φM2>5.5eV, I R1 Maintained at the same order of magnitude; further, as φM2 increases, the read current ratio and subthreshold swing (SS avg ) will show an opposite trend, and when φM2=5.6eV, the read current ratio and subthreshold swing can simultaneously obtain the optimal value. In addition, φ M1 and φ M2 It will affect the electron concentration in the electron layer and the hole concentration in the hole layer respectively. By adjusting φ M1 and φ M2 The value of can adjust the energy band structure of the channel between the first tunneling gate electrode 83 and the second tunneling gate electrode 12, so as to control the opening and closing of the line tunneling. M1 =4.2eV and φ M2 = 5.6eV, the device can achieve the best storage performance - at this time, a lower I R0 with subthreshold swing, and higher I R1The high work function characteristics of the second tunneling gate electrode 12 induce a hole layer in the channel region 5, which forms an electron-hole double layer with the electron layer induced by the first tunneling gate electrode 83, thereby expanding the effective line tunneling area and increasing the on-state current. Furthermore, the three-dimensional upper and lower gate control structure formed by the second tunneling gate electrode 12 and the first tunneling gate electrode 83 can precisely control the on and off of line tunneling through the voltage difference, avoiding an increase in the off-state current and improving the read current ratio. The memory cell consists of a storage window 6 and a storage gate electrode 13 made of metallic silver. By embedding the storage gate electrode 13 in the second dielectric layer 11, multi-gate coordinated control can be achieved without increasing the device size, solving the problem of performance degradation during traditional structural scaling. Furthermore, the storage gate electrode 13 directly faces the storage window 6 above, which can improve the control sensitivity of carriers, ensuring that the device can still achieve an improved sensing margin and a higher read current ratio at low voltages.
[0068] Furthermore, the storage window 6 is a SiGe structure.
[0069] In this embodiment, the material of the SiGe storage window 6 is Si 0.6 Ge 0.4The SiGe storage window 6 has a width of 50nm and a thickness of 10nm. Using SiGe as the storage window 6 offers multiple advantages, specifically as follows: The SiGe material has a lower bandgap than Si, effectively improving the device's band-to-band tunneling and enabling it to store more holes even at low operating voltages, thereby promoting electron tunneling from the Z-shaped channel to the storage window 6 and increasing the on-state current. Furthermore, the Si material in the Z-shaped channel and the SiGe material in the SiGe storage window 6 form a Si / SiGe heterojunction. The energy band discontinuity within the heterojunction causes a shift in the high-valence band, enabling the dynamic random access memory to obtain a deeper potential well in the SiGe storage region, enhancing the storage region's hole storage capacity and achieving a higher retention time. Furthermore, the narrow bandgap enables efficient tunneling even at low operating voltages, reducing energy consumption and resolving the problem of insufficient tunneling current at low voltages in traditional structures. Secondly, by adjusting the Ge content of the SiGe material, the band structure of memory window 6 can be manipulated, enabling the device to achieve both a high read current ratio and a high sensing margin at low bias voltages, improving data reading accuracy. Specifically, this is because as the Ge content increases, the read current ratio first increases and then decreases, reaching a peak at a Ge content of 0.4; whereas the sensing margin first increases with the Ge content, reaching saturation at a Ge content of 0.6. The reason for this phenomenon is that when the device is in the off-state, as the Ge composition increases, the valence band in the SiGe storage window 6 bends upward. When the Ge composition is greater than 0.4, the valence band bending brings the valence band energy level of the storage window 6 closer to the conduction band energy level of the drain region 4, making it easier for electrons to tunnel from the storage window 6 to the drain region 4. At the same time, the increased valence band bending slightly expands the energy matching range, meaning that more electrons of different energies meet the tunneling condition, resulting in an increase in the off-state current. When the device is in the on-state, as the Ge composition increases, the conduction band in the SiGe storage window 6 bends downward, and the barrier height here first decreases, reaching saturation when the Ge composition reaches 0.6. The reduced barrier height allows more linear tunneling electrons to drift across the barrier to the drain region 4, increasing the on-state current and ultimately saturating the on-state current at a Ge composition of 0.6. Furthermore, the variation trend of the retention time (RT) is consistent with the sensing margin, as the retention time is closely related to the degradation of the sensing margin. On the other hand, the width of the SiGe storage window 6 significantly affects the device performance of this embodiment: both the read current ratio and the retention time decrease as the width of the SiGe storage window 6 decreases. This is because a reduction in the width of the SiGe storage window 6 leads to a decrease in the hole concentration in the storage region, which in turn reduces the on-state current and increases the off-state current.Furthermore, when the window width is lower, the read current ratio and retention time are reduced, but they are still higher than the corresponding recommended values in the International Semiconductor Technology Development Roadmap. Therefore, the device in this embodiment has good scalability.
[0070] This embodiment provides a method for preparing a dynamic random access memory, comprising the following steps:
[0071] Determine a silicon-on-insulator wafer with a substrate 9;
[0072] Manufacturing a storage window 6 on the insulator silicon wafer to obtain a first silicon wafer;
[0073] Growing an intrinsic silicon epitaxial layer on the first silicon wafer and forming a source region 7 to obtain a second silicon wafer;
[0074] The intrinsic silicon epitaxial layer of the second silicon wafer is etched to form a Z-shaped channel region 5, thereby obtaining a third silicon wafer; wherein the Z-shaped channel region 5 includes a first lateral region, a first longitudinal region, and a second lateral region connected in sequence; the lower surface of the first lateral region contacts the upper surface of the source region 7; a side surface of the first longitudinal region contacts a side surface of the source region 7; and a side surface of the second lateral region contacts a side surface of the storage window 6;
[0075] preparing a drain region 4 on the third silicon wafer so that the drain region 4 contacts the storage window 6 to obtain a fourth silicon wafer;
[0076] A first dielectric electrode layer 8, a source electrode 2, and a drain electrode 3 are formed on the fourth silicon wafer, so that the source electrode 2 contacts one side of the source region 7, and the drain electrode 3 contacts one side of the drain region 4, to obtain a fifth silicon wafer.
[0077] The substrate 9 is etched from the fifth silicon wafer, and a second dielectric electrode layer 1 is prepared to obtain a dynamic random access memory.
[0078] This embodiment provides a method for preparing a dynamic random access memory. A SiO2 mask layer can be deposited on a second silicon wafer, and the SiO2 mask layer and the intrinsic silicon epitaxial layer are etched to form a Z-shaped channel region 5. The position of the left source electrode 2 and the right drain electrode 3 are etched using RIE etching technology. Further, N + The drain region 4 and the Z-shaped channel region 5 are made of Si with a thickness of 10 nm. This allows for the extension of the vertical tunneling path and the expansion of the lateral gate-source overlap area without increasing the device area. This increases the effective line tunneling area, improves the line tunneling probability, and enhances the gate's electrostatic control of the channel, thereby promoting the formation of an electron-hole double layer and increasing the on-state current, thus facilitating device scaling.
[0079] Furthermore, the step of manufacturing a storage window 6 on the insulator silicon wafer to obtain a first silicon wafer comprises:
[0080] depositing a first mask layer on the silicon-on-insulator wafer;
[0081] Defining a storage window 6 region on the insulator silicon wafer and a first etching region on the first mask layer, removing the first etching region and growing SiGe in the storage window 6 region to obtain the storage window 6 and the second mask layer;
[0082] The second mask layer is removed to obtain a first silicon wafer.
[0083] In this embodiment, a SiO2 hard mask layer (first mask layer) is deposited on an insulator silicon wafer using plasma enhanced chemical vapor deposition (PE-CVD) technology; then, diluted hydrofluoric acid is used to etch away the mask layer (first etching area) on the storage window 6, and SiGe is grown in the storage window 6 area with a width of 50 nm using Ge condensation method, and P is implanted in the storage window 6 area using ion implantation technology. + doping, the concentration is 1×10 19 cm -3 By removing the first etched area, the storage window 6 area on the surface of the insulator silicon wafer can be exposed, ensuring that SiGe is grown only in the designated storage window 6 area. The SiGe storage window 6 material is Si 0.6 Ge 0.4 The SiGe storage window 6 has a width of 50nm and a thickness of 10nm. The narrow bandgap characteristics of the SiGe storage window 6 are then utilized to form a deep potential well through the Si / SiGe heterojunction, enhancing hole storage capacity, thereby extending retention time and improving inter-band tunneling efficiency to optimize sensing margin.
[0084] Furthermore, the process of growing an intrinsic silicon epitaxial layer on the first silicon wafer and forming a source region 7 to obtain a second silicon wafer comprises:
[0085] growing a first intrinsic silicon epitaxial layer on the first silicon wafer to obtain a first silicon wafer to be operated;
[0086] depositing a third mask layer on the first silicon wafer to be operated;
[0087] Delimiting a second etching region on the first silicon wafer to be operated, and delimiting a third etching region on the third mask layer, removing the second etching region and the third etching region to obtain a second silicon wafer to be operated and a fourth mask layer;
[0088] Demarcating a source region 7 on the second silicon wafer to be operated, and performing doping in the source region 7 to obtain the source region 7; wherein the lower surface of the source region 7 is in contact with the substrate 9;
[0089] A second intrinsic silicon epitaxial layer 10 is grown on the source region 7 and the fourth mask layer is removed to obtain a second silicon wafer.
[0090] In this embodiment, after the second mask layer is stripped off, a first intrinsic silicon epitaxial layer is first grown on the first silicon wafer using molecular beam epitaxy, followed by the deposition of a SiO2 mask layer (third mask layer) using PE-CVD. A selective etching process is used to etch away the mask layer and intrinsic silicon above the source region 7, and the source region 7 is doped using boron implantation. Finally, intrinsic silicon is regrown above the source region 7 and the SiO2 mask layer is deposited. In this embodiment, the source region 7 and the drain region 4 are heavily doped with P-type and N-type, respectively, with doping concentrations of 1×10 20 cm -3 . By removing the second etching area and the third etching area, the target area for preparing the source region 7 is exposed, and the unetched third mask layer is retained as the fourth mask layer to continue to protect other areas, providing a precise spatial boundary for the subsequent doping of the source region 7, ensuring that doping only occurs within the demarcated source region 7 area. Subsequently, doping is performed in the source region 7 to form the source region 7. The source region 7 serves as the hole supply end for line tunneling and can form a first electron-hole double layer with the electron layer induced in the subsequent Z-type channel. As the core carrier source for line tunneling, its hole concentration directly affects the magnitude of the on-state current. A second intrinsic silicon epitaxial layer 10 is then grown on the source region 7, which not only fills the surface defects of the source region 7 after doping, but also forms a complete channel substrate together with the remaining first intrinsic silicon epitaxial layer, ensuring the structural continuity of the subsequent Z-type channel during etching, and providing stable channel support for the efficient transmission of line tunneling electrons.
[0091] Furthermore, a first dielectric electrode layer 8, a source electrode 2, and a drain electrode 3 are formed on the fourth silicon wafer so that the source electrode 2 contacts one side of the source region 7, and the drain electrode 3 contacts one side of the drain region 4, to obtain a fifth silicon wafer; comprising:
[0092] A first dielectric layer 81, a ferroelectric layer 82, and a first tunneling gate electrode 83 are sequentially deposited on the fourth silicon wafer to prepare a first dielectric electrode layer 8; wherein the lower surface of the first dielectric layer 81 contacts the upper surface of the first lateral region, the upper surface of the first longitudinal region, the upper surface of the second lateral region, the upper surface of the storage window 6, and the upper surface of the drain region 4; the lower surface of the ferroelectric layer 82 contacts the upper surface of the first dielectric layer 81; and the upper surface of the ferroelectric layer 82 contacts the lower surface of the first tunneling gate electrode 83;
[0093] A source electrode 2 and a drain electrode 3 are deposited on the fourth silicon wafer so that the source electrode 2 contacts one side of the source region 7 and the drain electrode 3 contacts one side of the drain region 4 to obtain a fifth silicon wafer.
[0094] In this embodiment, a 2 nm thick HfO2 first dielectric layer 81 is deposited on a fourth silicon wafer using atomic layer deposition (ALD). A 1-3 nm thick HZO ferroelectric layer 82 is selectively deposited on the HfO2 first dielectric layer 81 using ALD. The hafnium and zirconium compositions in the ferroelectric layer 82 are determined by the coercive field and remanent polarization. Platinum, hafnium, and aluminum are then deposited using ALD to form the source electrode 2 on the left side of the device, the drain electrode 3 on the right side, and the first tunneling gate electrode 83 at the top. By depositing a ferroelectric layer 82 (made of HZO with a thickness of 1-3nm) on the first dielectric layer 81, the negative capacitance characteristics of the ferroelectric layer 82 can be used to induce a "gate voltage amplification effect", thereby enhancing the surface potential and band bending of the channel region 5, promoting the tunneling of electrons between the electron-hole double layer, and thus increasing the on-state current; at the same time, the thickness, coercive electric field and residual polarization strength of the ferroelectric layer 82 can be adjusted to optimize the subthreshold swing and capacitance matching, achieve high-efficiency regulation under low voltage, and effectively reduce device power consumption. Then, a first tunneling gate electrode 83 is deposited on the ferroelectric layer 82. The material of the first tunneling gate electrode 83 is metallic aluminum. Aluminum with a work function of 4.2eV is selected as the first tunneling gate electrode 83, which can induce an electron region on the upper surface of the first lateral region, part of the first longitudinal region and part of the second lateral region, thereby interacting with P + The source region 7 forms an electron-hole double layer, providing an electron source for line tunneling. At the same time, by adjusting the voltage on the first tunneling gate electrode 83, the electron concentration can be dynamically controlled, thereby controlling the opening and closing of line tunneling, directly affecting the size of the on-state current and the sensing margin. Finally, the source electrode 2 and the drain electrode 3 are deposited on both sides of the wafer. The source electrode 2 is made of platinum metal and contacts one side of the source region 7, serving as an external lead-out terminal of the source region 7. This provides a stable hole supply path for line tunneling, ensuring effective connection between the source region 7 and the external circuit, and ensuring a continuous supply of carriers during read and write operations. The drain electrode 3 is made of hafnium metal and contacts one side of the drain region 4, serving as an external lead-out terminal of the drain region 4. It is responsible for collecting line tunneling electrons transmitted through the Z-channel, forming an on-state current, and transmitting the current signal to the external circuit to achieve data reading and recognition.
[0095] Furthermore, the process of etching the substrate 9 from the fifth silicon wafer and preparing the second dielectric electrode layer 1 to obtain a dynamic random access memory comprises:
[0096] Etching a substrate 9 from the fifth silicon wafer;
[0097] A second dielectric electrode layer 1 is prepared in the original substrate 9 region of the fifth silicon wafer to obtain a dynamic random access memory, specifically:
[0098] depositing an initial dielectric layer on the fifth silicon wafer;
[0099] Defining a fourth etched region and a fifth etched region in the initial dielectric layer, and removing the fourth etched region and the fifth etched region to obtain a second dielectric layer 11; wherein the upper surface of the second dielectric layer 11 is in contact with the lower surface of the source electrode 2, the lower surface of the drain electrode 3, the lower surface of the source region 7, the lower surface of the channel region 5, the lower surface of the storage window 6, and the lower surface of the drain region 4;
[0100] Depositing metal in the fourth etched region to form a second tunneling gate electrode 12; wherein the second tunneling gate electrode 12 is embedded in the second dielectric layer 11;
[0101] Depositing metal in the fifth etched region to form a storage gate electrode 13; wherein the storage gate electrode 13 is embedded in the second dielectric layer 11;
[0102] The second tunneling gate electrode 12 , the storage gate electrode 13 and the second dielectric layer 11 form a second dielectric electrode layer 1 .
[0103] In this embodiment, the substrate 9 of the fifth silicon wafer (substrate 9 includes a Si substrate 9 and a SiO2 dielectric layer) is etched away using RIE etching technology, and then the HfO2 second dielectric layer 11 is deposited using atomic layer deposition (ALD). Next, RIE etching technology is used to etch out the positions of the second tunneling gate electrode 12 and the storage gate electrode 13 at the bottom, and palladium and silver metals are deposited using ALD technology to form the second tunneling gate electrode 12 and the storage gate electrode 13. A second tunneling gate electrode 12 is formed by depositing metal in the fourth etched area. The material of the second tunneling gate electrode 12 is metal palladium. Metal palladium with a work function of 5.6 eV is selected as the second tunneling gate electrode 12. The specific work function of the second tunneling gate electrode 12 can induce a hole layer in the Z-type channel, and form a second electron-hole double layer with the electron layer induced by the first tunneling gate electrode 83, thereby expanding the effective line tunneling area and increasing the on-state current; on the other hand, the second tunneling gate electrode 12 and the first tunneling gate electrode 83 form a "upper and lower gate" structure, which can accurately control the opening and closing of the line tunneling through the voltage difference, avoiding the abnormal increase of the off-state current caused by the false activation of the line tunneling in the off state, thereby improving the read current ratio. Finally, metal is deposited in the fifth etched area to form a storage gate electrode 13, which can adjust the hole concentration in the storage window 6 through electrostatic induction, optimize the hole storage capacity and increase the retention time; at the same time, the material of the storage gate electrode 13 is metallic silver, and metallic silver with a work function of 4.6eV is used as the storage gate electrode 13. By matching the work function of the storage gate electrode 13 with the energy band of the storage window 6, the hole concentration in the storage window 6 can be adjusted, and efficient regulation can be achieved under low bias voltage, reducing the programming voltage, and enhancing the hole binding ability, reducing hole leakage and extending the retention time.
[0104] In order to highlight the advantages of this embodiment, the following embodiments are used to illustrate:
[0105] The device of this embodiment is compared with the existing L-type tunneling field effect transistor (L-TFET) and U-type tunneling field effect transistor (U-TFET): in the on state (V gs =1.0V, V ds =0.5V, V gs Expressed as gate-source voltage, V ds When the drain-source voltage is expressed as , the on-state current of this embodiment is 4.11×10 -5 A / μm, which is lower than L-TFET (1.19×10 -6 A / μm) and U-TFET (4.45×10 -6 A / μm) are 34 times and 9 times higher in on-state current respectively. gs =0V, V ds =0.5V, V gs Expressed as gate-source voltage, V dsWhen the drain-source voltage is expressed as , the off-state current of this embodiment is 5.58×10 -18 A / μm, compared to the off-state current of L-TFET and U-TFET (about 10 -16 A / μm), which is reduced by about 2 orders of magnitude. At the same time, this embodiment has the steepest subthreshold swing SS avg and the highest high on-off ratio I on / I off , whose values are 20.18mV / dec and 7.45×10 12 Compared with L-TFET (SS avg 24.26mV / dec, I on / I off is 10 10 ) and U-TFET(SS avg 29.56mV / dec, I on / I off is 10 10 ), the SS of the dynamic random access memory Z-EHBTFET based on the tunneling field effect transistor of this embodiment avg The I on / I off Both increased by 2 orders of magnitude.
[0106] In summary, this embodiment can achieve higher I on , lower off-state current I off , the steepest SS avg and the largest I on / I off , which helps to significantly improve its storage performance (SM can be improved by an order of magnitude, I R1 / I R0 can be improved by 1 to 3 orders of magnitude).
[0107] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.
Claims
1. A dynamic random access memory comprising a second dielectric electrode layer, a source electrode, a drain electrode, a source region, a channel region, a storage window, a drain region, and a first dielectric electrode layer, wherein: The source electrode, drain electrode, source region, channel region, storage window, and drain region are disposed on the upper surface of the second dielectric electrode layer; the first dielectric electrode layer covers the upper surfaces of the channel region, the storage window, and the drain region. The channel region is Z-shaped, comprising a first lateral region, a first longitudinal region, and a second lateral region connected in sequence; the upper surface of the source region contacts the lower surface of the first lateral region, one side surface of the source region contacts the source electrode, and the other side surface of the source region contacts one side surface of the first longitudinal region; one side surface of the storage window contacts one side surface of the second lateral region; one side surface of the drain region contacts the drain electrode, and the other side surface of the drain region contacts the other side surface of the storage window.
2. A dynamic random access memory according to claim 1, characterized in that: The first dielectric electrode layer includes a first dielectric layer and a first tunneling gate electrode; wherein the lower surface of the first dielectric layer contacts the upper surface of the first lateral region, the upper surface of the first longitudinal region, the upper surface of the second lateral region, the upper surface of the storage window and the upper surface of the drain region, and the upper surface of the first dielectric layer is electrically connected to the first tunneling gate electrode.
3. A dynamic random access memory according to claim 2, characterized in that: The first dielectric electrode layer further includes a ferroelectric layer; wherein the ferroelectric layer is disposed on the lower surface of the first tunneling gate electrode, and the lower surface of the ferroelectric layer contacts the upper surface of the first dielectric layer.
4. A dynamic random access memory according to claim 1, characterized in that: The second dielectric electrode layer includes a second dielectric layer, a second tunneling gate electrode and a storage gate electrode; wherein the second tunneling gate electrode and the storage gate electrode are embedded in the second dielectric layer; the upper surface of the second dielectric layer is in contact with the lower surface of the source electrode, the lower surface of the drain electrode, the lower surface of the source region, the lower surface of the channel region, the lower surface of the storage window and the lower surface of the drain region.
5. The dynamic random access memory according to claim 1, wherein: The storage window is a SiGe structure.
6. A method for preparing a dynamic random access memory, characterized in that: The following steps are involved: Determining a silicon-on-insulator wafer with a substrate; Fabricating a storage window on the insulator silicon wafer to obtain a first silicon wafer; Growing an intrinsic silicon epitaxial layer on the first silicon wafer and forming a source region to obtain a second silicon wafer; The intrinsic silicon epitaxial layer of the second silicon wafer is etched to form a Z-shaped channel region, thereby obtaining a third silicon wafer; wherein the Z-shaped channel region includes a first lateral region, a first longitudinal region, and a second lateral region connected in sequence; a lower surface of the first lateral region contacts an upper surface of the source region; a side surface of the first longitudinal region contacts a side surface of the source region; and a side surface of the second lateral region contacts a side surface of the storage window; preparing a drain region on the third silicon wafer so that the drain region contacts the storage window, thereby obtaining a fourth silicon wafer; forming a first dielectric electrode layer, a source electrode, and a drain electrode on the fourth silicon wafer, such that the source electrode contacts one side of the source region, and the drain electrode contacts one side of the drain region, to obtain a fifth silicon wafer; A substrate is etched from the fifth silicon wafer, and a second dielectric electrode layer is prepared to obtain a dynamic random access memory.
7. The method for preparing a dynamic random access memory according to claim 6, wherein: The method of manufacturing a storage window on the insulator silicon wafer to obtain a first silicon wafer comprises: depositing a first mask layer on the silicon-on-insulator wafer; Defining a storage window area on the insulator silicon wafer and a first etching area on the first mask layer, removing the first etching area and growing SiGe in the storage window area to obtain a storage window and a second mask layer; The second mask layer is removed to obtain a first silicon wafer.
8. The method for preparing a dynamic random access memory according to claim 6, wherein: The step of growing an intrinsic silicon epitaxial layer on the first silicon wafer and forming a source region to obtain a second silicon wafer comprises: growing a first intrinsic silicon epitaxial layer on the first silicon wafer to obtain a first silicon wafer to be operated; depositing a third mask layer on the first silicon wafer to be operated; Delimiting a second etching region on the first silicon wafer to be operated, and delimiting a third etching region on the third mask layer, removing the second etching region and the third etching region to obtain a second silicon wafer to be operated and a fourth mask layer; Demarcating a source region on the second silicon wafer to be operated, and performing doping in the source region to obtain a source region; wherein the lower surface of the source region is in contact with the substrate; A second intrinsic silicon epitaxial layer is grown on the source region and the fourth mask layer is removed to obtain a second silicon wafer.
9. The method for preparing a dynamic random access memory according to claim 6, wherein: The step of preparing a first dielectric electrode layer, a source electrode, and a drain electrode on the fourth silicon wafer so that the source electrode contacts one side of the source region and the drain electrode contacts one side of the drain region to obtain a fifth silicon wafer comprises: Depositing a first dielectric layer, a ferroelectric layer, and a first tunneling gate electrode in sequence on the fourth silicon wafer to prepare a first dielectric electrode layer; wherein the lower surface of the first dielectric layer contacts the upper surface of the first lateral region, the upper surface of the first longitudinal region, the upper surface of the second lateral region, the upper surface of the storage window, and the upper surface of the drain region; the lower surface of the ferroelectric layer contacts the upper surface of the first dielectric layer; and the upper surface of the ferroelectric layer contacts the lower surface of the first tunneling gate electrode; A source electrode and a drain electrode are deposited on the fourth silicon wafer so that the source electrode contacts one side of the source region and the drain electrode contacts one side of the drain region, thereby obtaining a fifth silicon wafer.
10. The method for preparing a dynamic random access memory according to claim 6, wherein: The method of etching a substrate from the fifth silicon wafer and preparing a second dielectric electrode layer to obtain a dynamic random access memory comprises: etching a substrate from the fifth silicon wafer; A second dielectric electrode layer is prepared in the original substrate area of the fifth silicon wafer to obtain a dynamic random access memory, specifically: depositing an initial dielectric layer on the fifth silicon wafer; Defining a fourth etched region and a fifth etched region in the initial dielectric layer, and removing the fourth etched region and the fifth etched region to obtain a second dielectric layer; wherein the upper surface of the second dielectric layer is in contact with the lower surface of the source electrode, the lower surface of the drain electrode, the lower surface of the source region, the lower surface of the channel region, the lower surface of the storage window, and the lower surface of the drain region; Depositing metal in the fourth etched region to form a second tunneling gate electrode; wherein the second tunneling gate electrode is embedded in the second dielectric layer; Depositing metal in the fifth etched region to form a storage gate electrode; wherein the storage gate electrode is embedded in the second dielectric layer; The second tunneling gate electrode, the storage gate electrode and the second dielectric layer form a second dielectric electrode layer.