Semiconductor device and preparation method thereof, and electronic equipment

Abstract

The invention provides a semiconductor device, a preparation method thereof and electronic equipment. The semiconductor device comprises a heterojunction structure and a gate structure, the gate structure is arranged on the heterojunction structure, the gate structure comprises a first semiconductor layer and a gate which are stacked, and the first semiconductor layer is arranged on the heterojunction structure; the conduction type of the first semiconductor layer is P type, and the first semiconductor layer is made of polycrystalline gallium nitride with a first doping element. The hole concentration of the first semiconductor layer can be improved, and normal work of the semiconductor device can be ensured.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same, and an electronic device. Background Art

[0002] Gallium nitride (GaN) high electron mobility transistors (HEMTs) have demonstrated significant advantages in high voltage, high frequency, and high power applications due to their high electron mobility, wide bandgap characteristics, and high breakdown electric field.

[0003] In related technologies, a transistor typically includes a substrate, a heterojunction structure, a semiconductor layer, and a gate. The heterojunction structure is disposed on the substrate and forms a two-dimensional electron gas (2DEG). The semiconductor layer is disposed on the heterojunction structure and located between the gate and the heterojunction structure. A hole accumulation region is formed by the semiconductor layer, and the positive polarization charge of the heterojunction structure is neutralized through a polarization effect, thereby depleting the 2DEG and turning off the transistor.

[0004] However, it is currently difficult to dope the semiconductor layer with a high concentration, and it is impossible to ensure that the semiconductor layer has a sufficiently high hole concentration, resulting in a low threshold voltage of the transistor, and ultimately causing the transistor to fail to work properly. Summary of the Invention

[0005] In view of the above problems, the embodiments of the present application provide a semiconductor device and a preparation method thereof, and an electronic device, which can increase the hole concentration of the first semiconductor layer and ensure that the semiconductor device can operate normally.

[0006] In order to achieve the above objectives, the embodiments of the present application provide the following technical solutions:

[0007] In a first aspect, an embodiment of the present application provides a semiconductor device, comprising:

[0008] Heterojunction structure;

[0009] A gate structure, wherein the gate structure is arranged on the heterojunction structure, wherein the gate structure includes a first semiconductor layer and a gate arranged in a stacked manner, the first semiconductor layer is arranged on the heterojunction structure; the conductivity type of the first semiconductor layer is P-type, and the material of the first semiconductor layer is polycrystalline gallium nitride with a first doping element.

[0010] In a possible implementation, the doping concentration of the first doping element in the first semiconductor layer is greater than or equal to 5×10 19 cm -3 .

[0011] In a possible implementation, the gate structure further includes a second semiconductor layer, which is disposed between the first semiconductor layer and the heterojunction structure, and is made of single-crystal gallium nitride.

[0012] In a possible implementation, the second semiconductor layer has a second doping element, and the doping concentration of the second doping element in the second semiconductor layer is less than or equal to 1×10 19 cm -3 .

[0013] In a possible implementation, the thickness of the second semiconductor layer is greater than or equal to 5 nm.

[0014] In a possible implementation, the semiconductor device further includes a substrate, and the heterojunction structure is provided on the substrate;

[0015] The heterojunction structure includes a stacked channel layer, a dielectric layer and a barrier layer, and the first semiconductor layer is arranged on the barrier layer; wherein the material of the channel layer is gallium nitride, the material of the dielectric layer is aluminum nitride, the material of the barrier layer is aluminum gallium nitride, and the dielectric layer and the barrier layer constitute a gate dielectric layer.

[0016] In a second aspect, an embodiment of the present application provides a method for manufacturing a semiconductor device, comprising:

[0017] providing a substrate;

[0018] forming a heterojunction structure on the substrate;

[0019] performing a first deposition process to form a first semiconductor layer on the heterojunction structure, wherein the first semiconductor layer covers a portion of the heterojunction structure; the first semiconductor layer has a P-type conductivity and is made of polycrystalline gallium nitride having a first doping element;

[0020] A gate is formed on the first semiconductor layer, wherein the gate covers a portion of the first semiconductor layer, and the gate and the first semiconductor layer constitute a gate structure.

[0021] In a possible implementation, after the step of forming a heterojunction structure on the substrate and before the step of forming the first semiconductor layer, the preparation method includes:

[0022] A second deposition process is performed to form a second semiconductor layer on the heterojunction structure, wherein the second semiconductor layer is made of single crystal gallium nitride.

[0023] In a possible implementation, the deposition temperature of the first deposition process is less than or equal to 700°C.

[0024] In a third aspect, an embodiment of the present application provides an electronic device comprising the semiconductor device described in the first aspect.

[0025] In the semiconductor device and its preparation method, and electronic device provided in the embodiments of the present application, by improving the material of the first semiconductor layer, for example, the material of the first semiconductor layer is polycrystalline gallium nitride with a first doping element, which generally allows a higher dopant flow rate or more extreme growth conditions. At the same time, a large number of interstitial positions and dangling bonds exist at the grain boundaries of polycrystalline gallium nitride, which can provide additional doping sites for the first doping element, suppressing the self-compensation effect of the first doping element, and easily increasing the doping concentration of the first doping element. For example, the doping concentration of the first doping element in the first semiconductor layer is greater than or equal to 5×10 19 cm -3 , providing stronger hole injection capability for the depletion of two-dimensional electron gas (2DEG), thereby increasing the threshold voltage of the semiconductor device, so that the semiconductor device can stably maintain the off state under zero gate voltage, ensuring the normal operation of the semiconductor device.

[0026] In addition to the technical problems solved by the embodiments of the present application, the technical features that constitute the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the semiconductor devices and their preparation methods, and electronic devices provided by the embodiments of the present application, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further described in detail in the specific implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0028] Figure 1 A schematic structural diagram of a semiconductor device provided in an embodiment of the present application;

[0029] Figure 2 A diagram showing the relationship between the gate voltage and the drain current of the semiconductor device provided in an embodiment of the present application in the on state;

[0030] Figure 3 An energy band diagram of hole accumulation in the on-state of a semiconductor device provided by an embodiment of the present application;

[0031] Figure 4 A process flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application.

[0032] Description of reference numerals:

[0033] 100: heterojunction structure; 110: channel layer; 120: dielectric layer; 130: barrier layer;

[0034] 200: gate structure; 210: first semiconductor layer; 220: gate; 230: second semiconductor layer;

[0035] 300: substrate;

[0036] 400: source;

[0037] 500: drain;

[0038] 600: Insulation layer. DETAILED DESCRIPTION

[0039] In related technologies, the heterojunction structure includes aluminum gallium nitride and gallium nitride. A two-dimensional electron gas (2DEG) is formed between aluminum gallium nitride and gallium nitride. The holes formed by the semiconductor layer doped with magnesium in the gate structure and the positive polarization charge of the AlGaN layer are neutralized through the polarization effect, thereby depleting the 2DEG and making the transistor in the off state at zero gate voltage.

[0040] It can be seen that the transistor can be turned off normally at zero gate voltage, which depends only on the concentration of holes formed in the semiconductor layer, and the concentration of holes is limited by the doping concentration of magnesium. However, magnesium has high ionization energy and self-compensation effect. Among them, when Mg replaces Ga as an acceptor impurity, its ionization energy is about 150-200meV. At room temperature (~25°C), only about 1% of Mg atoms are ionized (the hole concentration is much lower than the doping concentration), resulting in an extremely low effective hole concentration. At the same time, the self-compensation effect of GaN is obvious, and common intrinsic defects (such as nitrogen vacancies VN and gallium interstitials Gai) will act as donors, release electrons, and form a self-compensation effect with Mg acceptors, reducing the effective hole concentration.

[0041] Therefore, it is difficult to ensure that the semiconductor layer in the related art has a sufficiently high hole concentration, resulting in a low threshold voltage of the transistor, and ultimately causing the transistor to fail to work properly.

[0042] In response to the above technical problems, the embodiments of the present application provide a semiconductor device, a method for manufacturing the same, and an electronic device. By improving the material of the first semiconductor layer, for example, the material of the first semiconductor layer is polycrystalline gallium nitride with a first doping element. This generally allows for a higher dopant flow rate or more extreme growth conditions. At the same time, a large number of interstitial positions and dangling bonds exist at the grain boundaries of polycrystalline gallium nitride, which can provide additional doping sites for the first doping element, suppressing the self-compensation effect of the first doping element, and easily increasing the doping concentration of the first doping element. For example, the doping concentration of the first doping element in the first semiconductor layer is greater than or equal to 5×10 19 cm -3 , providing stronger hole injection capability for the depletion of two-dimensional electron gas (2DEG), thereby increasing the threshold voltage of the semiconductor device, so that the semiconductor device can stably maintain the off state under zero gate voltage, ensuring the normal operation of the semiconductor device.

[0043] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0044] Please refer to Figure 1 The present invention provides a semiconductor device 1 including a heterojunction structure 100. The heterojunction structure 100 is the main structure of the semiconductor device. The heterojunction structure 100 forms a two-dimensional electron gas (2DEG) due to a polarization effect.

[0045] It should be noted that the heterojunction structure 100 can be supported by a substrate 300. For example, the semiconductor device further includes a substrate 300, on which the heterojunction structure 100 is disposed. The substrate 300 can be made of a semiconductor material. For example, the substrate 300 can be a silicon substrate, a germanium substrate, a silicon carbide (SiC) substrate, a silicon germanium (SiGe) substrate, or a silicon-on-insulator (SOI) substrate.

[0046] The semiconductor device further includes a gate structure 200 , which is disposed on the heterojunction structure 100 . In other words, the gate structure 200 is disposed on a surface of the heterojunction structure 100 facing away from the substrate 300 .

[0047] The gate structure 200 includes a first semiconductor layer 210 and a gate 220 that are stacked. The first semiconductor layer 210 is disposed on the heterojunction structure 100, and the gate 220 is disposed on the first semiconductor layer 210. It should be understood that the gate 220 can be a metal gate. For example, the material of the gate 220 includes but is not limited to tungsten (W) and copper (Cu).

[0048] The first semiconductor layer 210 has a P-type conductivity and is made of polycrystalline gallium nitride with a first doping element. The first semiconductor layer 210 can form a hole accumulation region below the gate structure 200 and neutralize the positive polarization charge in the heterojunction structure 100 through a polarization effect, thereby depleting the 2DEG and placing the semiconductor device in an off state at zero gate voltage. It should be noted that the first doping element can be magnesium (Mg) or beryllium (Be).

[0049] In this embodiment, during the preparation of the first semiconductor layer 210, a higher dopant flow rate or more extreme growth conditions can generally be allowed. At the same time, there are a large number of interstitial positions and dangling bonds at the grain boundaries of polycrystalline gallium nitride, which can provide additional doping sites for the first doping element, suppressing the self-compensation effect of the first doping element, and easily increasing the doping concentration of the first doping element. For example, the doping concentration of the first doping element in the first semiconductor layer 210 is greater than or equal to 5×10 19 cm -3 , providing stronger hole injection capability for the depletion of two-dimensional electron gas (2DEG), thereby increasing the threshold voltage of the semiconductor device, so that the semiconductor device can stably maintain the off state under zero gate voltage, ensuring the normal operation of the semiconductor device.

[0050] Furthermore, by modifying the material of the first semiconductor layer 210 to polycrystalline gallium nitride (Mg-doped polycrystalline GaN) with a first dopant element, the present embodiment significantly reduces the ionization energy of the magnesium acceptor by utilizing the grain boundary effect and strain field regulation in the polycrystalline structure. At room temperature, the higher defect density and carrier scattering mechanism in the polycrystalline structure promote thermally activated ionization of the Mg element, significantly increasing the hole ionization ratio, thereby effectively increasing the hole concentration and providing stronger hole injection capability for depletion of the two-dimensional electron gas (2DEG).

[0051] In one possible implementation, the gate structure 200 further includes a second semiconductor layer 230, which is disposed between the first semiconductor layer 210 and the heterojunction structure 100. The second semiconductor layer 230 is made of single-crystal gallium nitride. It should be noted that the following embodiments are described in detail using magnesium as the first doping element.

[0052] Given that highly doped magnesium has a high diffusion effect, during the preparation of the first semiconductor layer 210, magnesium is very easy to diffuse into the heterojunction structure and diffuse to the 2DEG interface, introducing edge dislocations. The diffused impurities or defects form local potential barriers in the channel layer, enhancing carrier scattering and directly reducing mobility.

[0053] Based on this, in this embodiment, a second semiconductor layer 230 is set between the first semiconductor layer 210 and the heterojunction structure 100, and its high crystal quality and low defect density are used as a diffusion barrier layer, which greatly reduces the diffusion distance of magnesium elements and prevents magnesium elements (Mg) from reaching the 2DEG interface, thereby maintaining channel mobility and significantly improving the high-frequency performance of semiconductor devices.

[0054] In addition, the second semiconductor layer 230 will greatly reduce the interface state density by physically blocking the diffusion of magnesium elements, thereby significantly reducing the gate leakage current density, meeting the application requirements of higher reliability performance.

[0055] It should be noted that the second semiconductor layer 230 may be undoped or slightly doped. In some embodiments, the second semiconductor layer 230 is not doped, so that the undoped single crystal gallium nitride (GaN) layer can be used to have a very low defect density (dislocation density <10 6 cm -2 ) and an atomically flat interface, which can form a physical barrier and effectively prevent magnesium (Mg) atoms from diffusing to the heterojunction interface.

[0056] In some other embodiments, the second semiconductor layer 230 has a second doping element, and the doping concentration of the second doping element in the second semiconductor layer 230 is less than or equal to 1×10 19 cm -3 The second doping element may be magnesium (Mg) or beryllium (Be). It should be noted that the following embodiments are described using magnesium (Mg) as the second doping element.

[0057] In this way, trace Mg doping can regulate the Fermi level of the second semiconductor layer 230, causing it to form an energy band offset with the first semiconductor layer 210 (highly doped with Mg), further enhancing the electrostatic blocking effect of the second semiconductor layer 230 on Mg diffusion, while avoiding lattice damage caused by high doping.

[0058] The embodiment of the present application also adjusts the thickness of the second semiconductor layer 230. For example, the thickness of the second semiconductor layer 230 is greater than or equal to 5 nm. This prevents the thickness of the second semiconductor layer 230 from being too low, preventing the first dopant element (such as magnesium) from bypassing the second semiconductor layer 230 through the tunneling effect or surface diffusion, thereby improving the blocking capability of the second semiconductor layer 230, thereby maintaining channel mobility and significantly improving the high-frequency performance of the semiconductor device.

[0059] It should be noted that when a forward gate voltage is applied to the gate structure 200 , the holes in the first semiconductor layer 210 are depleted and the 2DEG is reformed, thereby enabling the semiconductor device to be turned on.

[0060] In view of the second semiconductor layer 230 disposed between the first semiconductor layer 210 and the heterojunction structure 100 in this embodiment, in order to test whether the second semiconductor layer 230 has an impact on the performance of the semiconductor device when achieving the function of blocking the diffusion of the first doping element (magnesium element).

[0061] The embodiment of the present application also tests the performance of the semiconductor device in the on state, and the results are as follows: Figure 2 shown. Figure 2 The dotted line in FIG. 2 represents a curve showing the relationship between the total drain current and the gate voltage of the semiconductor device without the second semiconductor layer 230 . Figure 2 The solid line represents a curve showing the relationship between the total drain current and the gate voltage of the semiconductor device provided with the second semiconductor layer 230 .

[0062] from Figure 2 It can be clearly seen that the trends of the dotted line and the solid line are almost the same. In particular, when the gate voltage exceeds a certain threshold, the drain current rises rapidly and shows obvious switching characteristics. Therefore, the second semiconductor layer 230 on the surface, while achieving the function of blocking the diffusion of the first doping element (magnesium element), will not reduce the control ability of the gate structure 200 on the two-dimensional electron gas (or, channel layer), thereby ensuring the shutdown and opening of the semiconductor device.

[0063] The embodiment of the present application also tests the performance of a semiconductor device having both a first semiconductor layer 210 and a second semiconductor layer 230 , wherein the material of the first semiconductor layer 210 is magnesium-doped polycrystalline gallium nitride, to obtain an energy band diagram of the semiconductor device.

[0064] Please refer to Figure 3 , Figure 3 The dotted line represents the Fermi level, the figure above the dotted line is the conduction band, and the figure below the dotted line is the valence band. The band difference between the conduction band or valence band and the Fermi level determines the electron or hole concentration.

[0065] Figure 3The energy level diagram when the gate is turned on is shown. In the Fermi level diagram, the valence band of undoped GaN contacts the Fermi level, indicating that a hole accumulation layer is formed at the interface. Due to the shielding effect of the hole accumulation layer and the two-dimensional electron gas, the effective gate dielectric thickness is determined by the distance between the hole accumulation layer and the two-dimensional electron gas, and is no longer affected by the second semiconductor layer 230. Therefore, the transconductance of the first semiconductor layer 210 of the embodiment of the present application can still be maintained at a good level. In one possible implementation, the heterojunction structure 100 includes a channel layer 110, a dielectric layer 120 and a barrier layer 130. Among them, the channel layer 110 is arranged on the substrate 300, the dielectric layer 120 is arranged on the channel layer 110, and the barrier layer 130 is arranged on the dielectric layer 120.

[0066] The channel layer 110 is made of gallium nitride, the dielectric layer 120 is made of aluminum nitride, and the barrier layer 130 is made of aluminum gallium nitride. The dielectric layer 120 and the barrier layer 130 constitute a gate dielectric layer.

[0067] It should be noted that the semiconductor device provided in the embodiment of the present application further includes a source 400 and a drain 500. The source 400 and the drain 500 are disposed on the dielectric layer 120 and are respectively located on both sides of the gate structure 200. An insulating layer 600 is disposed between the gate structure 200 and the source 400, and between the gate structure 200 and the drain 500, to achieve insulation between the source 400, the drain 500, and the gate structure 200.

[0068] The present invention also provides a method for manufacturing a semiconductor device, comprising the following steps:

[0069] Step S210: providing a substrate.

[0070] Step S220: forming a heterojunction structure on the substrate.

[0071] The heterojunction structure 100 may be formed on the substrate 300 through a deposition process, wherein the heterojunction structure 100 includes a channel layer 110 , a dielectric layer 120 , and a barrier layer 130 that are stacked.

[0072] Step S230: performing a first deposition process to form a first semiconductor layer on the heterojunction structure, wherein the first semiconductor layer covers a portion of the heterojunction structure; the first semiconductor layer is of P-type conductivity and is made of polycrystalline gallium nitride having a first doping element.

[0073] The first deposition process includes but is not limited to metal organic chemical vapor deposition (MOCVD), pulsed laser deposition (PLD), or plasma enhanced atomic layer deposition (PE-ALD). The first doping element may be magnesium (Mg) or beryllium (Be).

[0074] In view of the fact that the material of the first semiconductor layer is polycrystalline gallium nitride in this embodiment, high concentration doping can be performed during the first deposition process so that the doping concentration of the first doping element in the first semiconductor layer 210 is greater than or equal to 5×10 19 cm -3 .

[0075] Step S240 : forming a gate on the first semiconductor layer, wherein the gate covers a portion of the first semiconductor layer, and the gate and the first semiconductor layer constitute a gate structure.

[0076] It should be understood that, since the gate 220 is made of metal, the gate 220 can be formed by a deposition process, or by an electroplating or magnetron sputtering process.

[0077] Thus, considering that the doping concentration of the first doping element in the first semiconductor layer 210 is greater than or equal to 5×10 19 cm -3 , providing stronger hole injection capability for the depletion of two-dimensional electron gas (2DEG), thereby increasing the threshold voltage of the semiconductor device, so that the semiconductor device can stably maintain the off state under zero gate voltage, ensuring the normal operation of the semiconductor device.

[0078] In the embodiment of the present application, the deposition temperature of the first deposition process is less than or equal to 700° C. In this way, the first semiconductor layer 210 of a certain thickness can be formed at a lower temperature, the diffusion effect of the first doping element (magnesium) can be better controlled, and the probability of the first doping element (such as magnesium) reaching the 2DEG interface can be reduced, thereby maintaining the channel mobility and significantly improving the high-frequency performance of the semiconductor device.

[0079] In one possible implementation, after the step of forming the heterojunction structure on the substrate and before the step of forming the first semiconductor layer, the method for preparing the semiconductor device further includes:

[0080] A second deposition process is performed to form a second semiconductor layer on the heterojunction structure, where the second semiconductor layer is made of single crystal gallium nitride.

[0081] The second deposition process may include, but is not limited to, metal organic chemical vapor deposition (MOCVD), pulsed laser deposition (PLD), or plasma enhanced atomic layer deposition (PE-ALD).

[0082] In this way, the high crystal quality and low defect density of the second semiconductor layer 230 can be used as a diffusion barrier layer, which greatly reduces the diffusion distance of the first doping element (such as magnesium) and prevents the first doping element (such as magnesium (Mg)) from reaching the 2DEG interface, thereby maintaining the channel mobility and significantly improving the performance of the semiconductor device.

[0083] An embodiment of the present application further provides an electronic device, comprising the semiconductor device described in any of the above embodiments.

[0084] The electronic device may be a device in the fields of communications, electronics, automobiles, or aerospace. For example, the electronic device may include, but is not limited to, a GaN charging chip, a communication module, or a radar system.

[0085] Since the electronic device provided in the embodiment of the present application includes the semiconductor device described in any of the above embodiments, and thus has all the structures and beneficial effects of the semiconductor device, this embodiment will not be described in detail here.

[0086] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0087] It should be noted that references in this specification to "one embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," and the like indicate that the described embodiment may include a particular feature, structure, or characteristic, but not necessarily every embodiment includes that particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is within the knowledge of those skilled in the art to implement such feature, structure, or characteristic in conjunction with other embodiments, whether explicitly described or not.

[0088] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor device, characterized in that: include: Heterojunction structure (100); A gate structure (200) is provided on the heterojunction structure (100), wherein the gate structure (200) comprises a first semiconductor layer (210) and a gate (220) which are stacked, and the first semiconductor layer (210) is provided on the heterojunction structure (100); the conductivity type of the first semiconductor layer (210) is P-type, and the material of the first semiconductor layer (210) is polycrystalline gallium nitride having a first doping element.

2. The semiconductor device according to claim 1, wherein The doping concentration of the first doping element in the first semiconductor layer (210) is greater than or equal to 5×10 19 cm -3 .

3. The semiconductor device according to claim 1, wherein The gate structure (200) further includes a second semiconductor layer (230), the second semiconductor layer (230) being arranged between the first semiconductor layer (210) and the heterojunction structure (100), and the material of the second semiconductor layer (230) is single crystal gallium nitride.

4. The semiconductor device according to claim 3, wherein The second semiconductor layer (230) contains a second doping element, and the doping concentration of the second doping element in the second semiconductor layer (230) is less than or equal to 1×10 19 cm -3 .

5. The semiconductor device according to claim 3 or 4, characterized in that The thickness of the second semiconductor layer (230) is greater than or equal to 5 nm.

6. The semiconductor device according to any one of claims 1 to 4, characterized in that The semiconductor device further comprises a substrate (300), and the heterojunction structure (100) is arranged on the substrate (300); The heterojunction structure (100) comprises a stacked channel layer (110), a dielectric layer (120) and a barrier layer (130), wherein the first semiconductor layer (210) is arranged on the barrier layer (130); wherein the channel layer (110) is made of gallium nitride, the dielectric layer (120) is made of aluminum nitride, the barrier layer (130) is made of aluminum gallium nitride, and the dielectric layer (120) and the barrier layer (130) constitute a gate dielectric layer.

7. A method for preparing a semiconductor device, comprising: providing a substrate; forming a heterojunction structure on the substrate; performing a first deposition process to form a first semiconductor layer on the heterojunction structure, wherein the first semiconductor layer covers a portion of the heterojunction structure; the first semiconductor layer has a P-type conductivity and is made of polycrystalline gallium nitride having a first doping element; A gate is formed on the first semiconductor layer, wherein the gate covers a portion of the first semiconductor layer, and the gate and the first semiconductor layer constitute a gate structure.

8. The method for preparing a semiconductor device according to claim 7, wherein: After the step of forming a heterojunction structure on the substrate and before the step of forming the first semiconductor layer, the preparation method includes: A second deposition process is performed to form a second semiconductor layer on the heterojunction structure, wherein the second semiconductor layer is made of single crystal gallium nitride.

9. The method for preparing a semiconductor device according to claim 8, wherein: The deposition temperature of the first deposition process is less than or equal to 700°C.

10. An electronic device, characterized in that: A semiconductor device comprising any one of claims 1 to 6.

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