Ultra-short-channel MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure capable of resisting short-channel effect and manufacturing process thereof

Abstract

The invention discloses an ultra-short channel MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure capable of resisting a short channel effect and a manufacturing process thereof, and belongs to the field of semiconductors. Comprising a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of each MOS cell; the core design is that a side symmetric P layer forms a strong depletion region, and drain induced barrier lowering (DIBL) and threshold voltage drift are directly inhibited; the top P-layer, the combined P-layer, the rectangular P-layer, the long-strip P-layer and the like form an auxiliary depletion region to further compress channel edge electric field distortion and cooperatively strengthen suppression on a short channel effect, so that the problem of performance degradation caused by shortening of the channel length in an ultra-short channel structure is solved, and the device can still keep stable electrical characteristics under the condition of small size.

Description

Technical Field

[0001] The present invention relates to a semiconductor, and in particular to an ultra-short channel MOSFET structure resistant to short channel effects and a manufacturing process thereof. Background Art

[0002] As semiconductor technology advances into the deep submicron and even nanometer scales, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) continues to shrink to meet the demands of high-integration and high-speed integrated circuits. However, when the channel length shrinks to the ultra-short range below 100nm, the short channel effect (SCE) becomes a core bottleneck restricting device performance. The drain electric field easily penetrates the channel region, leading to drain-induced barrier lowering (DIBL), threshold voltage drift, and deterioration of subthreshold swing, seriously affecting the switching characteristics and stability of the device. Patent number (CN106298878B) currently available for review describes a dual-gate MOSFET structure and its fabrication method. The disclosed dual-gate MOSFET structure utilizes III-V semiconductors as channel and source / drain materials, employing first and second gate metal layers to form a dual-gate structure. Integrated onto a silicon substrate, it enables monolithic integration with silicon-based CMOS devices. 12 This dual-gate structure enhances gate control capability and minimizes short-channel effects. Through-hole technology is employed to reduce parasitic capacitance and optimize RF characteristics. 1 Fabrication requires multiple steps, including deposition of isolation layers, bonding metal layers to form a bond pad, and bonding and etching to form the various layers. This involves various deposition methods. 34 However, the structure contains more than ten layers, diverse materials, and complex processes, potentially reducing yield. The lattice mismatch between the III-V materials and the silicon substrate may affect stability, and the high cost and complex process hinder mass production.

[0003] Therefore, developing a new MOSFET structure that can synergistically suppress the short channel effect, optimize carrier transport, and balance efficiency and stability has become a key issue in the development of ultra-short channel devices. Summary of the Invention

[0004] Purpose of the invention: The purpose of the present invention is to improve the working reliability of the device in high-frequency and high-voltage scenarios; another purpose of the present invention is to shorten the current path to reduce energy loss when conducting, accelerate carrier extraction and enhance blocking capability when shutting down, so as to meet the stringent requirements of high-density integration and high-efficiency conversion electronic systems for device switching speed and long-term stability.

[0005] Technical solution: An ultra-short channel MOSFET structure that is resistant to short channel effects, comprising a plurality of mutually parallel MOS cells, wherein a single MOS cell comprises a drain, a semiconductor epitaxial layer, a source, and a gate; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P+ layer, an N well layer, and a P well layer; a lightly doped N layer is provided in the middle of the N drift layer of a single MOS cell; A laterally symmetrical P-layer is provided inside a single MOS cell and on the left and right sides of the N drift layer. The laterally symmetrical P-layer has a trapezoidal profile, and the bottom end of the laterally symmetrical P-layer contacts the N substrate layer.

[0006] Furthermore, lateral symmetric N+ layers are formed on both sides of the lightly doped N layer by ion implantation. The lateral symmetric N+ layers are arc-shaped, and the bottom ends of the lateral symmetric N+ layers are in contact with the N substrate layer.

[0007] Furthermore, a top P-layer is formed on both sides of the lightly doped N layer by ion implantation, and a top of the top P-layer is in contact with the gate.

[0008] Furthermore, a bottom N+ layer is formed on both sides of the middle of the lightly doped N layer by ion implantation, and the bottom N+ layer is in contact with the N substrate layer.

[0009] Furthermore, a combined N+ layer is formed in the middle region of the lightly doped N layer by ion implantation, and a top of the combined N+ layer is in contact with the gate.

[0010] Furthermore, a combined P- layer is symmetrically formed on both sides of the combined N+ layer by ion implantation, and the top of the combined P- layer is in contact with the gate.

[0011] Furthermore, a vertical N+ layer is formed in the middle region of the lightly doped N layer by ion implantation, and a spherical P- layer is formed on the top of the vertical N+ layer by ion implantation.

[0012] Furthermore, a rectangular P-layer is formed in the middle area of ​​the lightly doped N layer by ion implantation, and semi-arc-shaped N+ layers are formed on both sides of the rectangular P-layer by ion implantation, the top of the rectangular P-layer contacts the gate, and the top of the semi-arc-shaped N+ layer contacts the gate.

[0013] Furthermore, a long P- layer is formed in the middle area of ​​the lightly doped N layer by ion implantation, and strip N+ layers are formed on both sides of the long P- layer by ion implantation, the top of the long P- layer contacts the gate, the top of the strip N+ layer contacts the gate, and the ends of the two strip N+ layers away from the gate are respectively in contact with both sides of the long P- layer.

[0014] According to another aspect of the present invention, an ultra-short channel MOSFET structure resistant to short channel effects and a manufacturing process thereof are provided, comprising the following steps: S1: Prepare the N substrate layer as the base substrate of the entire MOSFET structure, perform surface cleaning and pretreatment to remove impurities and natural oxide layer. S2: Prepare an N drift layer on the N substrate layer using epitaxial growth technology, control the temperature, pressure and doping concentration of the epitaxial growth, and ensure that the thickness and electrical properties of the N drift layer meet the design requirements. S3: The formation area of ​​the laterally symmetric P-layer is defined by a photolithography process. Then, ion implantation technology is used to implant P-type impurities into the left and right sides of the N drift layer to form a laterally symmetric P-layer with a trapezoidal profile, and its bottom end is in contact with the N substrate layer. Annealing is then performed to activate the implanted impurities and repair lattice damage.

[0015] S4: In the middle of the N drift layer, a lightly doped N layer region is determined by photolithography, and a low concentration of N-type impurities is injected using ion implantation technology to form a lightly doped N layer, which is then annealed.

[0016] S5: If a laterally symmetric N+ layer needs to be formed, its position is defined by photolithography, and high-concentration N-type impurities are injected into both sides of the lightly doped N layer using ion implantation technology to form an arc-shaped laterally symmetric N+ layer, ensuring that its bottom end is in contact with the N substrate layer, and then annealing is performed. S6: When the top P-layer needs to be made, the area is determined by photolithography, and P-type impurities are ion-implanted on both sides of the lightly doped N layer so that the top of the top P-layer contacts the gate formed subsequently. Annealing is performed after completion. S7: For the bottom N+ layer, the position is defined by photolithography, and high-concentration N-type impurities are ion-implanted on both sides of the middle of the lightly doped N layer to make it contact with the N substrate layer, followed by annealing. S8: To form a combined N+ layer, determine the area through photolithography, ion-implant high-concentration N-type impurities into the middle area of ​​the lightly doped N layer, ensure that its top is in contact with the gate, and then perform annealing. S9: On both sides of the combined N+ layer, the position of the combined P- layer is defined by photolithography, and P-type impurities are ion-implanted so that the top of the combined P- layer contacts the gate. After completion, annealing is performed. S10: When a vertical N+ layer and a spherical P- layer need to be produced, the area of ​​the vertical N+ layer is first defined by photolithography, and high-concentration N-type impurities are ion-implanted to form the vertical N+ layer. Then, a spherical P- layer is formed on top of the vertical N+ layer by photolithography and ion implantation, and annealing is performed separately. S11: For the rectangular P-layer and the semi-arc N+ layer, first photolithography is used to define the area of ​​the rectangular P-layer, and ion-implant P-type impurities are implanted to make its top contact with the gate; then photolithography is used to define the area of ​​the semi-arc N+ layer on both sides, and ion-implant high-concentration N-type impurities are implanted to ensure that its top contact with the gate, and then annealing is performed separately. S12: When making the long P- layer and the strip N+ layer, first photolithography is performed to define the area of ​​the long P- layer, and ion-implant P-type impurities are implanted to make its top contact with the gate; then photolithography is performed to define the area of ​​the strip N+ layer on both sides, and ion-implant high-concentration N-type impurities are implanted to make the top of the strip N+ layer contact with the gate, and the ends of the two strip N+ layers away from the gate are respectively in contact with the two sides of the long P- layer, and annealing is performed separately after completion. S13: preparing a P+ layer, an N-well layer, and a P-well layer at corresponding positions on the N-drift layer, defining regions of each layer by photolithography, and performing ion implantation and annealing treatments respectively. S14: Use photolithography and etching processes to make the gate to ensure good contact with related layers, combined N+ layer, etc. The material can be polysilicon or metal. S15: Prepare drain and source electrodes at both ends of the structure, define the area through photolithography, perform high-concentration impurity injection and metallization process to form a good ohmic contact. S16: Perform the final annealing treatment to optimize the electrical properties of the entire structure, and then perform surface passivation and post-processing processes to complete the production of an ultra-short channel MOSFET structure that is resistant to short channel effects.

[0017] Beneficial effects: It can significantly suppress the short channel effect and improve device stability. The core design is a laterally symmetrical P⁻ layer that forms a strong depletion region, which directly suppresses drain-induced barrier lowering (DIBL) and threshold voltage drift; the top P-layer, combined P-layer, rectangular P-layer, and long P-layer form auxiliary depletion regions to further compress the electric field distortion at the channel edge, synergistically enhance the suppression of the short channel effect, and solve the performance degradation problem caused by the shortening of the channel length in the ultra-short channel structure, so that the device can still maintain stable electrical characteristics at a small size.

[0018] It can optimize the conduction performance and reduce energy loss. The core design is a lightly doped N layer with a smooth longitudinal electric field distribution, which reduces carrier scattering to improve mobility; high-doping structures such as the laterally symmetrical N+ layer (arc-shaped), bottom N+ layer, vertical N+ layer, semi-arc-shaped N+ layer, and strip-shaped N+ layer shorten the current transmission path (horizontal / vertical), widen the transmission channel, and reduce the interface potential barrier. The effect is to significantly reduce the on-resistance, improve the carrier migration efficiency and current density, reduce the energy loss during the conduction process, and improve the device working efficiency.

[0019] It can accelerate the shutdown response and shorten the shutdown time. The core design is that the side-symmetrical N+ layer, bottom N+ layer, semi-arc N+ layer, strip N+ layer, etc. are connected to the N substrate layer or the gate, which can quickly extract the remaining carriers from the channel; the top P- layer, combined P- layer, rectangular P- layer, etc. quickly deplete the surrounding lightly doped N-layer area when turned off, accelerate the channel cutoff, and the effect is to shorten the shutdown delay, improve the device switching speed, and meet the needs of high-frequency application scenarios for fast state switching.

[0020] It can enhance the reverse voltage resistance and ensure the stability of the off state. The core design is that the P⁺ layer, N-well layer and P-well layer form a high-resistance blocking area; the laterally symmetrical P⁻ layer, combined P- layer, rectangular P- layer, and long P- layer construct a three-dimensional blocking network through depletion effect, and synergistically maintain the longitudinal blocking electric field. The effect is to ensure that the device can withstand high reverse voltage when turned off, avoid the risk of breakdown, and improve the working stability under extreme working conditions.

[0021] It can optimize the electric field distribution and reduce the risk of device damage. The core design uses lightly doped N-layers, spherical P-layers and other structures to smooth the longitudinal / lateral electric field distribution; various P-layers (laterally symmetrical P⁻ layer, top P-layer, etc.) suppress electric field concentration and avoid channel edge field distortion. The effect is to reduce the hot electron injection effect and carrier collision damage caused by electric field concentration, extend the service life of the device, and improve long-term working reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a structural diagram of embodiment 1 of the present invention; Figure 2 It is a structural diagram of embodiment 1 of the present invention; Figure 3 is a structural diagram of embodiment 2 of the present invention; Figure 4 is a structural diagram of embodiment 2 of the present invention; Figure 5 is a structural diagram of embodiment 3 of the present invention; Figure 6 is a structural diagram of a fourth embodiment of the present invention; Figure 7 is a structural diagram of a fourth embodiment of the present invention; Figure 8 is a structural diagram of a fifth embodiment of the present invention; Figure 9 It is a structural diagram of embodiment 5 of the present invention.

[0023] In the figure: 1. drain; 2. N substrate layer; 3. N drift layer; 4. source; 5. gate; 6. lightly doped N layer; 7. laterally symmetric P-layer; 8. P+ layer; 9. N well layer; 10. P well layer; 11. laterally symmetric N+ layer; 12. top P-layer; 13. bottom N+ layer; 14. combined N+ layer; 15. combined P-layer; 16. vertical N+ layer; 17. spherical P-layer; 18. rectangular P-layer; 19. semi-arc N+ layer; 20. long P-layer; 21. strip N+ layer. DETAILED DESCRIPTION

[0024] In order to make the technical solution of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0025] Example 1 like Figure 1 As shown, an ultra-short channel MOSFET structure resistant to short channel effects is provided, comprising a plurality of mutually parallel MOS cells, wherein a single MOS cell comprises a drain 1, a semiconductor epitaxial layer, a source 4, and a gate 5; the semiconductor epitaxial layer comprises an N substrate layer 2, an N drift layer 3, a P+ layer 8, an N well layer 9, and a P well layer 10; a lightly doped N layer 6 is provided in the middle of the N drift layer 3 of the single MOS cell; and a laterally symmetrical P- layer 7 is provided inside the single MOS cell and on the left and right sides of the N drift layer 3. The laterally symmetrical P- layer 7 has a trapezoidal profile, and the bottom end of the laterally symmetrical P- layer 7 contacts the N substrate layer 2; The laterally symmetric P⁻ layer 7 is trapezoidal and its bottom end contacts the N substrate layer 2, forming strong depletion regions on both sides of the channel, effectively suppressing drain-induced barrier lowering (DIBL) and threshold voltage drift, and significantly weakening the short channel effect. The lightly doped N layer 6 is located in the middle of the N drift layer 3, which can smooth the longitudinal electric field distribution, reduce carrier scattering, improve mobility, and at the same time reduce the hot electron injection effect, thereby enhancing device stability. The P⁺ layer 8 works synergistically with the N well layer 9 and the P well layer 10 to strengthen the control ability of the gate 5 over the channel and improve switching speed. When turned on, a forward voltage is applied to the gate 5, forming a conductive channel under the gate, and carriers are transferred from the source 4 through the channel to the drain 1. Because the laterally symmetric P⁻ layer 7 is in contact with the N substrate layer 2, it quickly depletes the surrounding N drift layer 3 under the high voltage of the drain 1, suppressing channel edge field distortion. The lightly doped N layer 6 makes the electric field of the current path more uniform, reducing energy loss. When turned off, the gate voltage is lower than the threshold and the channel is cut off; the P⁺ layer 8, the N-well layer 9, and the P-well layer 10 form a high-resistance blocking region, combined with the depletion effect of the P⁻ layer 7, to maintain a high reverse withstand voltage and achieve stable shutdown.

[0026] Example 2 like Figure 2-3As shown, an ultra-short channel MOSFET structure with resistance to short channel effect is provided. Laterally symmetrical N+ layers 11 are formed on both sides of the lightly doped N layer 6 by ion implantation. The laterally symmetrical N+ layers 11 are arc-shaped. The bottom ends of the laterally symmetrical N+ layers 11 are in contact with the N substrate layer 2. Top P- layers 12 are formed on both sides of the lightly doped N layer 6 by ion implantation. The top end of the top P- layer 12 is in contact with the gate 5. During on-state, a forward voltage is applied to gate 5, forming a conductive channel. The lateral symmetrical N+ layer 11, due to its curved design, contacts N substrate layer 2, rapidly collecting carriers, shortening the lateral current transmission path and reducing on-resistance. Its high doping properties enhance contact with the lightly doped N layer 6, reducing interface barriers and improving carrier migration efficiency. The top P- layer 12, in contact with gate 5, forms an auxiliary depletion region under the action of the gate voltage, further compressing the electric field distortion at the channel edge. This, in conjunction with the lateral symmetrical P⁻ layer 7, strengthens the suppression of short channel effects. During off-state, the top P- layer 12 rapidly depletes the upper region of the lightly doped N layer 6 as the gate voltage decreases, forming a longitudinal blocking electric field with P⁺ layer 8. Due to its connection to N substrate layer 2, the lateral symmetrical N+ layer 11 accelerates the extraction of residual carriers from the drain 1 side, shortening the turn-off time. It also collaborates with the N-well layer 9 and P-well layer 10 to maintain the reverse withstand voltage stability of the device.

[0027] Example 3 like Figure 4-5 As shown, an ultra-short channel MOSFET structure with resistance to short channel effect is provided. A bottom N+ layer 13 is formed on both sides of the middle of the lightly doped N layer 6 by ion implantation. The bottom N+ layer 13 is in contact with the N substrate layer 2. A combined N+ layer 14 is formed in the middle region of the lightly doped N layer 6 by ion implantation. The top of the combined N+ layer 14 is in contact with the gate 5. Combined P- layers 15 are formed symmetrically on both sides of the combined N+ layer 14 by ion implantation. The top of the combined P- layer 15 is in contact with the gate 5. When on, the combined N+ layer 14 contacts the gate 5, forming the core of the main current channel and enhancing the gate's control over the channel. The bottom N+ layer 13 contacts the N substrate layer 2, creating a vertical carrier transport shortcut and reducing the resistive loss of the lightly doped N layer 6. The combined P- layer 15 forms an auxiliary depletion region as the gate voltage turns on. This, in conjunction with the top P- layer 12, compresses the channel edge electric field, further suppressing the short channel effect. When off, the combined N+ layer 14 quickly extracts residual carriers from the channel, while the bottom N+ layer 13 accelerates the introduction of carriers into the N substrate layer 2, shortening the turn-off delay. The combined P- layer 15 and the P⁺ layer 8 form a vertical blocking enhancement region, which, in conjunction with the laterally symmetrical P⁻ layer 7, improves reverse withstand voltage stability and ensures the device's insulation performance in the off state.

[0028] Example 4 like Figure 6-7As shown, an ultra-short channel MOSFET structure with resistance to short channel effect is provided. A vertical N+ layer 16 is formed in the middle region of the lightly doped N layer 6 by ion implantation. A spherical P- layer 17 is formed on the top of the vertical N+ layer 16 by ion implantation. A rectangular P- layer 18 is formed in the middle region of the lightly doped N layer 6 by ion implantation. Semi-arc-shaped N+ layers 19 are formed on both sides of the rectangular P- layer 18 by ion implantation. The top of the rectangular P- layer 18 contacts the gate 5, and the top of the semi-arc-shaped N+ layer 19 contacts the gate 5. During on-state, the vertical N+ layer 16 provides a high-speed longitudinal channel for carriers, working in conjunction with the bottom N+ layer 13 to enhance current transfer efficiency. The semi-arc-shaped N+ layer 19 contacts the gate 5, widening the lateral current path and reducing on-resistance. Under the action of the gate voltage, the spherical P-layer 17 forms a local depletion region, which, in conjunction with the rectangular P-layer 18, suppresses electric field concentration in the middle of the channel, enhancing the gate 5's control over the core region. During off-state, the rectangular P-layer 18 rapidly depletes the surrounding lightly doped N-layer 6, forming a three-dimensional blocking network with the combined P-layer 15. The semi-arc-shaped N+ layer 19 accelerates carriers toward the gate 5, while the vertical N+ layer 16 directs the remaining carriers into the N substrate layer 2, significantly shortening the turn-off time. The spherical P-layer 17 enhances the uniformity of the longitudinal electric field distribution and, in conjunction with the laterally symmetrical P⁻ layer 7, further improves reverse withstand voltage stability.

[0029] Example 5 like Figure 8-9 As shown, an ultra-short channel MOSFET structure with resistance to short channel effect is provided. A long P- layer 20 is formed in the middle region of the lightly doped N layer 6 by ion implantation. Strip-shaped N+ layers 21 are formed on both sides of the long P- layer 20 by ion implantation. The top of the long P- layer 20 contacts the gate 5. The top of the strip-shaped N+ layer 21 contacts the gate 5. The ends of the two strip-shaped N+ layers 21 away from the gate 5 contact the two sides of the long P- layer 20 respectively. When on, the strip N+ layer 21 contacts the gate 5. With its top end connected to the gate and its bottom end in contact with the long P- layer 20, a stepped current channel is formed. This, in conjunction with the semi-arc-shaped N+ layer 19, widens the carrier transport path and reduces on-resistance. Its high doping properties accelerate carrier migration, synergizing with the vertical N+ layer 16 to increase current density. Under the action of the gate voltage, the long P- layer 20 forms a longitudinal depletion region, forming a multi-layer electric field control network with the spherical P- layer 17 and rectangular P- layer 18 to suppress field distortion in the middle of the channel. When off, the long P- layer 20 rapidly depletes the surrounding lightly doped N- layer 6, forming a three-dimensional blocking structure with the combined P- layer 15. The strip N+ layer 21 acts as a carrier extraction channel, directing excess charge to the gate 5 and the long P- layer 20. This, in conjunction with the vertical N+ layer 16, shortens the turn-off time and collaborates with the laterally symmetric P⁻ layer 7 to enhance reverse withstand voltage stability.

[0030] According to another aspect of the present invention, an ultra-short channel MOSFET structure resistant to short channel effects and a manufacturing process thereof are provided, comprising the following steps: S1: Prepare N substrate layer 2. Select high-purity single crystal silicon material as N substrate layer 2, and its crystal orientation is <100> , the resistivity is controlled within the range of 1-10Ω·cm, and the surface is cleaned: first, ultrasonic cleaning is performed with acetone solution for 10-15 minutes to remove surface organic pollutants; then ultrasonic cleaning is performed with anhydrous ethanol for 5-8 minutes to remove residual acetone; then the RCA cleaning method is adopted, first using SC1 solution NH4OH:H2O2:H2O=1:1:5 to clean at 75-80℃ for 10 minutes to remove particulate impurities and some metal ions, and then using SC2 solution HCl:H2O2:H2O=1:1:6 to clean at 75-80℃ for 10 minutes to further remove metal ions; finally, rinse with deionized water several times until the surface resistivity reaches above 10^16Ω, and blow dry with nitrogen.

[0031] S2: Preparation of N drift layer 3 The N drift layer 3 is grown on the N substrate layer 2 using chemical vapor epitaxy (CVD). Silane (SiH4) and phosphine (PH3) are used as the reactant gases. The SiH4 flow rate is controlled at 50-100 sccm, and the PH3 flow rate is adjusted according to the desired doping concentration, achieving a doping concentration of 10^15-10^16 cm^-3 in the N drift layer 3. The growth temperature is set at 1050-1150°C, the growth pressure is controlled at 100-300 mbar, and the growth time is calculated based on the desired thickness, typically 2-5 μm. During the growth process, the thickness and uniformity of the epitaxial layer are monitored in real time to ensure a thickness deviation of no more than ±5% and a surface roughness Ra ≤ 0.5 nm.

[0032] S3: Forming a laterally symmetric P-layer 7 Photolithography process: Coat photoresist on the surface of the N drift layer 3, use ultraviolet exposure wavelength 365nm, exposure time 10-20 seconds, define the formation area of ​​the laterally symmetric P-layer 7 through the mask, and then use developer to develop and remove the unexposed photoresist to obtain the required pattern. Ion implantation: Boron ions B+ are selected as implanted ions, the implantation energy is set to 50-100keV, and the implantation dose is 10^13-10^14cm^-2, ensuring the formation of a laterally symmetric P-layer 7 with a trapezoidal profile, and the bottom end is in contact with the N substrate layer 2. Annealing treatment: Rapid thermal annealing RTA is performed in a nitrogen protective atmosphere, the temperature is set to 900-950℃, and the temperature is kept for 10-20 seconds to activate the implanted boron ions, with an activation rate of more than 90%, while repairing lattice damage.

[0033] S4: forming a lightly doped N layer 6 Photolithography process: re-coat photoresist on the surface of the N drift layer 3, and define the area of ​​the lightly doped N layer 6 through the mask. The exposure and development parameters are the same as S3. Ion implantation: select phosphorus ions P+ as the implanted ions, the implantation energy is 30-60keV, and the implantation dose is 10^12-10^13cm^-2 to form the lightly doped N layer 6. Annealing treatment: furnace annealing is used, the temperature is set to 800-850℃, and the temperature is kept for 30-60 minutes. It is carried out in a nitrogen atmosphere to allow the impurities to fully diffuse and form a uniform lightly doped N layer 6.

[0034] S5: Forming a laterally symmetrical N+ layer 11 if necessary Photolithography process: Coat photoresist on the surface of the lightly doped N layer 6, and define the position of the laterally symmetric N+ layer 11 through a mask. The exposure and development parameters are the same as S3. Ion implantation: Arsenic ions As+ are selected as implanted ions with an implantation energy of 80-120 keV and an implantation dose of 10^15-10^16 cm^-2 to form an arc-shaped laterally symmetric N+ layer 11, ensuring that its bottom end is in contact with the N substrate layer 2. Annealing treatment: Perform RTA treatment with a temperature set at 1000-1050°C for 5-10 seconds to activate the implanted arsenic ions and increase the carrier concentration.

[0035] S6: Make top P-layer 12 when needed Photolithography process: Coat photoresist on the surface of the lightly doped N layer 6 to define the area of ​​the top P-layer 12. The exposure and development parameters are the same as S3. Ion implantation: Inject boron ions B+ with an injection energy of 20-40keV and an injection dose of 5×10^12-5×10^13cm^-2 to make the top of the top P-layer 12 contact with the subsequently formed gate 5. Annealing treatment: Use furnace tube annealing at a temperature of 750-800℃ for 20-30 minutes in a nitrogen atmosphere to activate impurities.

[0036] S7: Forming the bottom N+ layer 13, photolithography process: coating photoresist on the surface of the lightly doped N layer 6 to define the position of the bottom N+ layer 13, the exposure and development parameters are the same as S3, ion implantation: implanting arsenic ions As+, the implantation energy is 100-150keV, the implantation dose is 10^15-10^16cm^-2, so that it contacts the N substrate layer 2, annealing treatment: RTA treatment, temperature 1000-1050℃, keeping warm for 5-10 seconds to activate impurities.

[0037] S8: Forming the combined N+ layer 14 Photolithography process: Coat photoresist on the surface of the lightly doped N layer 6 to define the area of ​​the combined N+ layer 14. The exposure and development parameters are the same as S3. Ion implantation: Inject phosphorus ions P+ with an injection energy of 50-80keV and an injection dose of 10^15-10^16cm^-2 to ensure that the top is in contact with the gate 5. Annealing treatment: RTA treatment at a temperature of 950-1000℃ for 8-15 seconds to activate impurities.

[0038] S9: Forming a combined P-layer 15, photolithography process: coating photoresist on both sides of the combined N+ layer 14 to define the position of the combined P-layer 15, the exposure and development parameters are the same as S3, ion implantation: implanting boron ions B+, the implantation energy is 30-50keV, the implantation dose is 5×10^12-5×10^13cm^-2, so that the top of the combined P-layer 15 contacts the gate 5, annealing treatment: furnace annealing, temperature 800-850℃, keeping warm for 20-30 minutes, nitrogen atmosphere.

[0039] S10: Make vertical N+ layer 16 and spherical P- layer 17. When needed, form vertical N+ layer 16: After photolithography defines the area, implant arsenic ions As+, with an injection energy of 120-180keV and an injection dose of 10^15-10^16cm^-2, and RTA treatment at 1000-1050℃ for 5-10 seconds to form spherical P- layer 17: Photolithography defines the area on the top of the vertical N+ layer 16, and implant boron ions B+, with an injection energy of 10-30keV and an injection dose of 5×10^12-5×10^13cm^-2, and furnace annealing at 750-800℃ for 20-30 minutes.

[0040] S11: Make a rectangular P-layer 18 and a semi-arc N+ layer 19 to form a rectangular P-layer 18: After the photolithography definition area, inject boron ions B+, the injection energy is 30-50keV, the injection dose is 5×10^12-5×10^13cm^-2, so that its top is in contact with the gate 5, and furnace tube annealing is 800-850℃ for 20-30 minutes to form a semi-arc N+ layer 19: Photolithography definition areas on both sides of the rectangular P-layer 18, inject arsenic ions As+, the injection energy is 80-120keV, the injection dose is 10^15-10^16cm^-2, ensure that its top is in contact with the gate 5, RTA treatment is 1000-1050℃ for 5-10 seconds.

[0041] S12: Make a long P- layer 20 and a strip N+ layer 21 to form a long P- layer 20: After photolithography defines the area, implant boron ions B+ with an injection energy of 30-50keV and an injection dose of 5×10^12-5×10^13cm^-2, so that the top is in contact with the gate 5, and furnace tube annealing is performed at 800-850℃ for 20-30 minutes to form a strip N+ layer 21: Photolithography defines the area on both sides of the long P- layer 20, and implants phosphorus ions P+ with an injection energy of 50-80keV and an injection dose of 10^15-10^16cm^-2, so that the top of the strip N+ layer 21 is in contact with the gate 5, and the end away from the gate 5 is in contact with both sides of the long P- layer 20, and RTA treatment is performed at 950-1000℃ for 8-15 seconds.

[0042] S13: Prepare P+ layer 8, N well layer 9 and P well layer 10, photolithography process: define the areas of P+ layer 8, N well layer 9 and P well layer 10 respectively, with the exposure and development parameters being the same as S3, ion implantation: inject boron ions B+ into P+ layer 8, with energy of 50-100keV and dose of 10^15-10^16cm^-2; inject phosphorus ions P+ into N well layer 9, with energy of 80-120keV and dose of 10^14-10^15cm^-2; inject boron ions B+ into P well layer 10, with energy of 50-80keV and dose of 10^14-10^15cm^-2, annealing treatment: perform RTA or furnace annealing respectively, and adjust the parameters according to the requirements of each layer to ensure impurity activation and lattice repair.

[0043] S14: Fabricate gate 5. Photolithography and etching: Deposit a layer of gate material, polysilicon or metal, on the substrate surface. Polysilicon is deposited using CVD technology to a thickness of 200-500nm; aluminum or copper is deposited using sputtering technology to a thickness of 300-600nm. Then, apply photoresist to define the gate pattern. After exposure and development, dry etching, such as reactive ion etching, is used to remove excess material, forming gate 5. Contact processing: Ensure good contact between gate 5 and related layers, such as the top P- layer 12 and the combined N+ layer 14, with a contact resistance of ≤10^-6Ω・cm^2.

[0044] S15: Prepare drain 1 and source 4. Photolithography definition: Coat photoresist at both ends of the structure to define the drain 1 and source 4 regions. The exposure and development parameters are the same as S3. High-concentration impurity injection: Arsenic ions As+ are injected into both drain 1 and source 4 with an energy of 100-150keV and a dose of 10^15-10^16cm^-2 to form heavily doped regions. Metallization process: Use sputtering or evaporation technology to deposit metal aluminum or copper with a thickness of 500-1000nm, followed by photolithography and etching to form metal electrodes for the drain and source, ensuring good ohmic contact with a contact resistance of ≤10^-6Ω・cm^2.

[0045] S16: The final processing technology, annealing treatment: high temperature annealing is carried out in a nitrogen and hydrogen mixed atmosphere with a volume ratio of 9:1, the temperature is 400-500℃, and the heat preservation is carried out for 30-60 minutes to optimize the electrical properties of the entire structure, reduce the contact resistance and series resistance, surface passivation: plasma enhanced chemical vapor deposition PECVD technology is used to deposit a layer of silicon dioxide SiO2 or silicon nitride Si3N4 as a passivation layer with a thickness of 500-1000nm to protect the device surface and prevent contamination and oxidation. Post-processing: scribing, testing and other processes are carried out to complete the production of ultra-short channel MOSFET structure that is resistant to short channel effect.

[0046] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. An ultra-short channel MOSFET structure resistant to short channel effects, comprising a plurality of mutually parallel MOS cells, wherein a single MOS cell comprises a drain (1), a semiconductor epitaxial layer, a source (4) and a gate (5); the semiconductor epitaxial layer comprises an N substrate layer (2), an N drift layer (3), a P+ layer (8), an N well layer (9) and a P well layer (10), characterized in that: A lightly doped N layer (6) is provided in the middle of the N drift layer (3) of a single MOS cell; A laterally symmetrical P-layer (7) is provided inside a single MOS cell and on the left and right sides of the N drift layer (3); the laterally symmetrical P-layer (7) has a trapezoidal profile, and the bottom end of the laterally symmetrical P-layer (7) is in contact with the N substrate layer (2).

2. The ultra-short channel MOSFET structure resistant to short channel effects according to claim 1, wherein: Laterally symmetrical N+ layers (11) are formed on both sides of the interior of the lightly doped N layer (6) by ion implantation. The laterally symmetrical N+ layers (11) are arc-shaped, and the bottom end of the laterally symmetrical N+ layers (11) is in contact with the N substrate layer (2).

3. The ultra-short channel MOSFET structure resistant to short channel effects according to claim 2, wherein: A top P-layer (12) is formed on both sides of the interior of the lightly doped N layer (6) by ion implantation, and the top of the top P-layer (12) is in contact with the gate (5).

4. The ultra-short channel MOSFET structure resistant to short channel effects according to claim 1, wherein: A bottom N+ layer (13) is formed on both sides of the middle of the lightly doped N layer (6) by ion implantation, and the bottom N+ layer (13) is in contact with the N substrate layer (2).

5. The ultra-short channel MOSFET structure resistant to short channel effects according to claim 4, characterized in that: A combined N+ layer (14) is formed in the middle region of the lightly doped N layer (6) by ion implantation, and the top of the combined N+ layer (14) is in contact with the gate (5).

6. An ultra-short channel MOSFET structure resistant to short channel effects according to claim 5, characterized in that: A combined P- layer (15) is symmetrically formed on both sides of the combined N+ layer (14) by ion implantation, and the top of the combined P- layer (15) is in contact with the gate (5).

7. The ultra-short channel MOSFET structure with short channel effect resistance according to claim 1, characterized in that: A vertical N+ layer (16) is formed in the middle region of the lightly doped N layer (6) by ion implantation, and a spherical P- layer (17) is formed at the top of the vertical N+ layer (16) by ion implantation.

8. The ultra-short channel MOSFET structure resistant to short channel effects according to claim 1, characterized in that: A rectangular P-layer (18) is formed in the middle area of ​​the lightly doped N layer (6) by ion implantation, and semi-arc-shaped N+ layers (19) are formed on both sides of the rectangular P-layer (18) by ion implantation, the top of the rectangular P-layer (18) is in contact with the gate (5), and the top of the semi-arc-shaped N+ layer (19) is in contact with the gate (5).

9. The ultra-short channel MOSFET structure with resistance to short channel effect according to claim 1, characterized in that: A long P-layer (20) is formed in the middle area of ​​the lightly doped N layer (6) by ion implantation, and strip-shaped N+ layers (21) are formed on both sides of the long P-layer (20) by ion implantation. The top of the long P-layer (20) contacts the gate (5), and the top of the strip-shaped N+ layer (21) contacts the gate (5). The ends of the two strip-shaped N+ layers (21) away from the gate (5) are respectively in contact with both sides of the long P-layer (20).

10. A method for constructing an ultra-short channel MOSFET resistant to short channel effects, a method for constructing an ultra-short channel MOSFET resistant to short channel effects and a method for preparing the same, comprising the method and the method for preparing the ultra-short channel MOSFET resistant to short channel effects according to any one of claims 1 to 9, characterized in that: The following steps are involved: S1: Prepare the N substrate layer (2) as the base substrate of the entire MOSFET structure, perform surface cleaning and pretreatment to remove impurities and natural oxide layer. S2: An N drift layer (3) is prepared on the N substrate layer (2) using an epitaxial growth technique, and the temperature, pressure and doping concentration of the epitaxial growth are controlled to ensure that the thickness and electrical properties of the N drift layer (3) meet design requirements. S3: The formation area of ​​the side-symmetrical P-layer (7) is defined by a photolithography process, and then P-type impurities are injected into the left and right sides of the N drift layer (3) by ion implantation technology to form a side-symmetrical P-layer (7) with a trapezoidal profile, and its bottom end is in contact with the N substrate layer (2), and then annealing is performed to activate the injected impurities and repair lattice damage. S4: In the middle of the N drift layer (3), a region of a lightly doped N layer (6) is determined by photolithography, and a low concentration of N-type impurities is injected using ion implantation technology to form a lightly doped N layer (6), followed by annealing. S5: If a laterally symmetrical N+ layer (11) is to be formed, its position is defined by photolithography, and high-concentration N-type impurities are injected into both sides of the interior of the lightly doped N layer (6) using ion implantation technology to form an arc-shaped laterally symmetrical N+ layer (11), ensuring that its bottom end is in contact with the N substrate layer (2), and then annealing is performed. S6: When it is necessary to form the top P-layer (12), the area is determined by photolithography, and P-type impurities are ion-implanted on both sides of the interior of the lightly doped N layer (6) so that the top of the top P-layer (12) contacts the gate (5) to be formed subsequently, and annealing is performed after completion. S7: For the bottom N+ layer (13), the position is defined by photolithography, and high-concentration N-type impurities are ion-implanted on both sides of the middle of the lightly doped N layer (6) so that it contacts the N substrate layer (2), and then annealing is performed. S8: If a combined N+ layer (14) is to be formed, the region is determined by photolithography, and high-concentration N-type impurities are ion-implanted into the middle region of the lightly doped N layer (6), ensuring that its top is in contact with the gate (5), and then annealing is performed. S9: On both sides of the combined N+ layer (14), the position of the combined P- layer (15) is defined by photolithography, and P-type impurities are ion-implanted so that the top of the combined P- layer (15) contacts the gate (5), and annealing is performed after completion. S10: When it is necessary to produce a vertical N+ layer (16) and a spherical P- layer (17), first define the area of ​​the vertical N+ layer (16) by photolithography, ion-implant high-concentration N-type impurities to form the vertical N+ layer (16), and then form a spherical P- layer (17) on top of the vertical N+ layer by photolithography and ion implantation, and perform annealing treatment respectively. S11: For the rectangular P-layer (18) and the semi-arc N+ layer (19), first, photolithography is performed to define the area of ​​the rectangular P-layer (18), and ion-implantation of P-type impurities is performed to ensure that the top of the rectangular P-layer (18) contacts the gate (5); then, photolithography is performed to define the area of ​​the semi-arc N+ layer (19) on both sides thereof, and ion-implantation of high-concentration N-type impurities is performed to ensure that the top of the semi-arc N+ layer (19) contacts the gate (5), and then annealing is performed separately. S12: When making the long P- layer (20) and the strip N+ layer (21), first, photolithography is performed to define the area of ​​the long P- layer (20), and ion-implantation of P-type impurities is performed so that the top of the long P- layer (20) contacts the gate (5); then, photolithography is performed to define the area of ​​the strip N+ layer (21) on both sides thereof, and ion-implantation of high-concentration N-type impurities is performed so that the top of the strip N+ layer (21) contacts the gate (5), and the ends of the two strip N+ layers (21) away from the gate (5) are respectively in contact with the two sides of the long P- layer (20), and annealing is performed after completion. S13: preparing a P+ layer (8), an N well layer (9) and a P well layer (10) at corresponding positions on the N drift layer (3), defining the regions of each layer by photolithography, and performing ion implantation and annealing treatment respectively. S14: A gate electrode (5) is manufactured by photolithography and etching processes to ensure that the gate electrode (5) is in good contact with related layers (such as the top P- layer (12), the combined N+ layer (14), etc.). The material can be polysilicon or metal. S15: Prepare a drain (1) and a source (4) at both ends of the structure, define the area through photolithography, perform high-concentration impurity injection and metallization process to form a good ohmic contact. S16: Perform the final annealing treatment to optimize the electrical properties of the entire structure, and then perform surface passivation and post-processing processes to complete the production of an ultra-short channel MOSFET structure that is resistant to short channel effects.

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