SiC MOSFET device and manufacturing method thereof

Abstract

The invention relates to a SiC MOSFET device and a manufacturing method thereof, a cell of the SiC MOSFET device comprises an N + SiC substrate, an N-drift region, an N + source region, a P body region, a P + region, a gate dielectric layer, a gate, a field passivation layer, a source electrode, a drain electrode, a P bottom region and a hole absorption region, and the highly doped P bottom region inhibits a parasitic transistor from being opened. The hole absorption regions are arranged in a three-section structure, potential distribution near the gate dielectric layer can be optimized on the premise that the resistance of the JFET region is not greatly improved, local hole accumulation is further reduced through interconnection between the hole absorption regions, an additional path is provided for rapid export of accumulated holes, the single event effect is further relieved, and the performance of the JFET is improved. And the occurrence probability of single-particle gate penetration is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and more particularly to a SiC MOSFET device and a manufacturing method thereof. Background Art

[0002] MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is a semiconductor device widely used for switching purposes and amplification of electronic signals in electronic devices.

[0003] Early semiconductor devices primarily used silicon substrates, but inherent properties of silicon, such as its narrow bandgap, significantly limited their high-temperature, high-voltage, and radiation-resistant performance. The rise and commercialization of wide-bandgap materials, such as silicon carbide (SiC) and gallium nitride (GaN), have successfully overcome the performance bottlenecks of silicon-based devices and significantly expanded their applications.

[0004] An existing SiC MOSFET structure is as follows Figure 1 As shown, the device comprises an N+SiC substrate 101, an N-drift region 102, a P-body region 103, a P+ region 104, an N+ source region 105, a gate dielectric layer 106, a gate 107, a field passivation layer 108, a source electrode 109, and a drain electrode 110. The N+SiC substrate 101 is heavily N-type doped; the N-drift region 102 is located within the epitaxial layer of the N+SiC substrate 101 and is lightly N-type doped. The P-body region 103, the P+ region 104, and the N+ source region 105 are symmetrically distributed within the epitaxial layer of the N+SiC substrate 101 below the gate 107. The N+ source region 105 is surrounded by the P-body region 103. The portion of the N-drift region 102 between the two symmetrically arranged N+ source regions 105 serves as the JFET region of the SiC MOSFET device. Its width is equal to the distance between the two P-body regions 103, and its depth is equal to the doping depth of the P-body region 103. The gate dielectric layer 106 is a silicon dioxide layer disposed on the surface of the epitaxial layer of the N+SiC substrate 101 , and the gate 107 is generally polysilicon.

[0005] When high-energy particles bombard the device during space applications, existing SiC MOSFET devices experience a directional drift of carriers under the reverse bias electric field, generating a transient peak current. Holes migrate and accumulate in the JFET region, while electrons accumulate at the bottom of the N-drift region, distorting the depletion region boundary and reshaping the internal electric field distribution. This process causes a doubling of the local electric field strength (typically >3 MV / cm), particularly within the gate dielectric layer above the JFET region of the SiC MOSFET. This further induces single-event gate rupture (SEGR), forming a conductive path in the gate dielectric layer and ultimately destroying the SiC MOSFET device. Therefore, optimizing the electric field distribution in the JFET region through radiation-resistant design is urgently needed to mitigate the risk of gate dielectric failure. Summary of the Invention

[0006] Based on this, it is necessary to provide a SiC MOSFET device and a manufacturing method thereof to address the above problems, and to reduce the probability of single-particle gate punchthrough by optimizing the electric field distribution in the JFET region.

[0007] In order to achieve the above object, the technical solution adopted by the present invention is as follows:

[0008] A SiC MOSFET device, wherein a cell of the SiC MOSFET device includes: an N+SiC substrate, an N-drift region, an N+ source region, a P body region, a P+ region, a gate dielectric layer, a gate, a field passivation layer, a source electrode, and a drain electrode, and further includes:

[0009] A P bottom region, the P bottom region is located below the P body region and is P-type doped, the doping concentration of the P bottom region is greater than the doping concentration of the P body region and less than the doping concentration of the P+ region;

[0010] A hole absorption region, wherein the hole absorption region is P-type doped and has a columnar shape, is located in the JFET region of the SiC MOSFET device and extends to the N-drift region below the JFET region, the width of the hole absorption region is smaller than the width of the JFET region, the top of the hole absorption region is located below the gate, the bottom depth of the hole absorption region is greater than the depth of the P bottom region and less than the depth of the P+ region, wherein the hole absorption region includes a first absorption region, a second absorption region and a third absorption region, the first absorption region corresponds to the N-drift region below the JFET region, the second absorption region corresponds to the P bottom region, and the third absorption region corresponds to the P body region, and the doping concentration of the first absorption region is greater than the doping concentration of the third absorption region, and the doping concentration of the third absorption region is greater than the doping concentration of the second absorption region.

[0011] The SiC MOSFET device disclosed in the present invention adds a P bottom region, which can increase the potential of the lower part of the P body region, form a "potential buffer layer" near it, reduce the potential difference near the gate dielectric layer, alleviate the problem of hole accumulation caused by high-energy particle bombardment in space, and reduce the probability of single-particle gate penetration. At the same time, the SiC MOSFET device adds a hole absorption region. The setting of the hole absorption region can further optimize the potential distribution near the gate dielectric layer, reduce the electric field strength near the gate dielectric layer, and provide an additional path for the accumulated holes to be extracted. The three-segment hole absorption region is set to correspond to the P body region, the P bottom region, and the N-drift region below the JFET region, respectively. Combined with the setting of different doping concentrations in different parts of the hole absorption region, that is, the doping concentration of the first absorption region is greater than the doping concentration of the third absorption region, and the doping concentration of the third absorption region is greater than the doping concentration of the second absorption region. In this way, lateral diffusion can be reduced, thereby reducing the resistance of the JFET region. Ultimately, without excessively increasing the resistance of the JFET region, the potential distribution near the gate dielectric layer can be optimized, the accumulation of local holes can be reduced, and additional extraction paths can be provided for the accumulated holes, further alleviating the single-particle effect and reducing the probability of single-particle gate penetration.

[0012] In one embodiment, the JFET region depth is H, the first absorption region doping depth is H1, the second absorption region doping depth is H2, and the third absorption region doping depth is H3, wherein H1>H2>H>H3.

[0013] In one embodiment, the doping concentration of the P bottom region is in the range of 1×10 18 cm -3 above.

[0014] In one embodiment, the doping depth of the P bottom region is less than the doping depth of the P+ region.

[0015] In one embodiment, a longitudinal section of the gate dielectric layer corresponding to the JFET region along the third direction is a cap-top trapezoid, wherein the width of the JFET region is L; the bottom width of the cap-top trapezoid of the gate dielectric layer is JL1, and JL1=0.6L~0.8L; the top width of the cap-top trapezoid of the gate dielectric layer is JL2, and JL2=0.2L~0.6L; the maximum thickness of the gate dielectric layer at the cap-top trapezoid is T1, the thickness of the gate dielectric layer at the non-cap-top trapezoid is T2, and T1≥3T2.

[0016] The JFET region corresponds to a thicker gate dielectric layer, which can reduce the potential distribution in the JFET region, further alleviating the single-event effect from the perspective of the gate dielectric layer and reducing the probability of single-event gate punchthrough. Moreover, the longitudinal cross-section of the gate dielectric layer corresponding to the JFET region along the third direction is a top-hat trapezoidal shape, which can further optimize the potential distribution in the JFET region and make it more gentle.

[0017] In one embodiment, the SiC MOSFET device further includes:

[0018] A transition region, wherein the transition region is P-type doped and surrounds a plurality of cells of the SiC MOSFET device;

[0019] The hole connection region is P-type doped and is located in the N-drift region. The hole connection region is used to connect the hole absorption regions of different cells and connect the hole absorption region with the transition region.

[0020] In one embodiment, the hole absorption regions of the plurality of cells extend along a first direction and are interconnected or independent of each other, and the hole absorption regions of the plurality of cells are interconnected in a second direction through the hole connection region.

[0021] The interconnection of multiple cellular hole absorption regions can further increase the extraction paths for accumulated holes, especially enabling multiple cells to share the accumulated holes of a single or local cell, thereby improving the overall stability of the SiC MOSFET device against radiation. When the multiple cellular hole absorption regions along the first direction are independent of each other, the disconnected region has no P-type hole absorption region. The region without hole absorption regions can protect the top gate dielectric layer through the depletion of the hole absorption regions on both sides, thereby reducing its electric field. This method can reduce the proportion of the P region in the JFET region, optimizing and reducing the on-resistance of the device without reducing the radiation performance of the device.

[0022] Another embodiment discloses a method for manufacturing a SiC MOSFET device, wherein a cell of the SiC MOSFET device is the cell of the SiC MOSFET device described in any one of the above embodiments, and the P bottom region and the hole absorption are formed by an ion implantation process.

[0023] In one embodiment, the process of manufacturing the gate dielectric layer includes:

[0024] Depositing a SiO2 layer on the surface of the N+SiC substrate;

[0025] Use dry etching process to remove part of SiO2 material on both sides of the JFET area;

[0026] The remaining SiO2 material is etched using a wet etching process to form a gate dielectric layer with a cap-top trapezoidal longitudinal section in the central region. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A schematic diagram of the structure of a conventional SiC MOSFET device;

[0028] Figure 2 A schematic diagram of the structure of a SiC MOSFET device provided in Example 1 of the present invention;

[0029] Figure 3 A schematic diagram of the structure of a SiC MOSFET device provided in the second embodiment of the present invention;

[0030] Figure 4 A schematic diagram of another SiC MOSFET device structure provided in the second embodiment of the present invention;

[0031] Figure 5 A schematic diagram of the structure of a SiC MOSFET device provided in the third embodiment of the present invention (a cross-sectional view taken along the third direction at point BB');

[0032] Figure 6 A cross-sectional view of a SiC MOSFET device provided in the fourth embodiment of the present invention taken along the third direction at line AA';

[0033] Figure 7 A top view of a SiC MOSFET device provided in embodiment 4 of the present invention;

[0034] Figure 8 A three-dimensional diagram of a SiC MOSFET device provided in accordance with a fourth embodiment of the present invention;

[0035] Figure 9 A top view of a SiC MOSFET device in the first manner provided in the fifth embodiment of the present invention;

[0036] Figure 10 A three-dimensional diagram of a SiC MOSFET device in the first embodiment of the present invention;

[0037] Figure 11 A top view of a SiC MOSFET device in the second manner provided in the fifth embodiment of the present invention;

[0038] Figure 12 A three-dimensional diagram of a SiC MOSFET device in the second manner provided in the fifth embodiment of the present invention;

[0039] Figure 13A cross-sectional view of a SiC MOSFET device taken along a third direction at CC' in the second manner provided in the fifth embodiment of the present invention;

[0040] Figure 14 A top view of another SiC MOSFET device in the second manner provided in the fifth embodiment of the present invention;

[0041] Figure 15 A top view of another SiC MOSFET device in the second manner provided in the fifth embodiment of the present invention;

[0042] Figure 16 A top view of a SiC MOSFET device in the third embodiment of the present invention;

[0043] Figure 17 A top view of a SiC MOSFET device according to a fourth embodiment of the present invention is provided;

[0044] Figure 18 A schematic diagram of the steps for manufacturing a SiC MOSFET device provided in Example 7 of the present invention.

[0045] In the figure: 101, N+SiC substrate; 102, N-drift region; 103, P body region; 104, P+ region; 105, N+ source region; 106, gate dielectric layer; 107, gate; 108, field passivation layer; 109, source electrode; 110, drain electrode; 111, P bottom region; 112, hole absorption region; 113, gradient buffer layer; 114, transition region; 115, hole connection region; 1121, first absorption region; 1122, second absorption region; 1123, third absorption region. DETAILED DESCRIPTION

[0046] To facilitate understanding of the present invention, the present invention will be described in more detail below. However, it should be understood that the present invention can be implemented in many different forms and is not limited to the embodiments or examples described herein. On the contrary, the purpose of providing these embodiments or examples is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the technical field of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments or embodiments and are not intended to limit the present invention. The optional scope of the term "and / or" used herein includes any one of two or more related listed items, and also includes any and all combinations of the related listed items, including any combination of any two related listed items, any more related listed items, or all related listed items.

[0048] Example 1

[0049] Example 1 discloses a SiC MOSFET device, such as Figure 2 As shown, the cell of the SiC MOSFET device includes: N+ SiC substrate 101, N- drift region 102, N+ source region 105, P body region 103, P+ region 104, gate dielectric layer 106, gate 107, field passivation layer 108, source electrode 109 and drain electrode 110. It also includes: P bottom region 111 and hole absorption region 112.

[0050] The N+SiC substrate 101 is heavily N-type doped and includes an epitaxial layer. In addition to SiC, it is also applicable to silicon-based substrates, GaAs substrates, GaN substrates, silicon-on-insulator (SOI) substrates, and other emerging substrates (such as Al2O3, graphene, MoS2, etc.).

[0051] The N-drift region 102 is located in the epitaxial layer of the N+SiC substrate 101 and is lightly N-doped.

[0052] The N-drift region 102 is provided with an N+ source region 105, a P body region 103, and a P+ region 104. The N+ source region 105 is heavily N-doped and acts on the device's turn-on, conduction, and shutdown processes. The P body region 103 is P-medium doped and is located between the N+ source region 105 and the N+SiC substrate 101. It is the key region connecting the N+ source region 105, the JFET region, and the N+SiC substrate 101. The P+ region 104 is heavily P-doped with a doping concentration of 1×10 19 cm -3 ~1×10 21 cm -3 , located on both sides of the N+ source region 105, serving as contact regions or isolation regions of the device.

[0053] The surface of the epitaxial layer (N-drift region 102) of the N+SiC substrate 101 is provided with a gate dielectric layer 106 and a gate 107. The gate dielectric layer 106 is an insulating film located between the gate 107 and the JFET region. Through electrical isolation and electric field modulation, it controls whether carriers can enter the JFET region, thereby determining the conduction state of the device. The gate 107 is the control electrode of the device. By applying a voltage (V G ) induces an electric field below the gate dielectric layer 106, modulating the carrier concentration in the JFET region, thereby determining whether the device is turned on or not, and is the "master switch" for the device's operation.

[0054] The field passivation layer 108 is an insulating film (such as SiO2, SiN x ), its core function is to protect the device from the erosion of the external environment (such as water vapor and ions), while optimizing the surface electric field distribution and suppressing leakage current and reliability failure.

[0055] The source electrode 109 is located at the outermost layer of the SiC MOSFET device and is electrically connected to the N+ source region 105 . The drain electrode 110 is located on the back side of the N+SiC substrate 101 .

[0056] The P bottom region 111 is located below the P body region 103 and is P-type doped. The doping concentration of the P bottom region 111 is greater than that of the P body region 103 and less than that of the P+ region 104. The higher doping concentration of the P bottom region 111 increases the potential below the P body region 103, forming a "potential buffer layer" nearby. This suppresses the potential difference caused by hole accumulation, reduces the probability of parasitic transistors turning on, alleviates the problem of hole accumulation caused by high-energy particle bombardment in space, and reduces the probability of single-particle gate penetration.

[0057] The hole absorption region 112 is P-type doped and columnar, located within the JFET region and extending into the N-drift region 102 below the JFET region. The width of the hole absorption region 112 is smaller than that of the JFET region. The top of the hole absorption region 112 is located below the gate 107. The bottom of the hole absorption region 112 has a depth greater than that of the P bottom region 111 and less than that of the P+ region 104. The hole absorption region 112 includes a first absorption region 1121, a second absorption region 1122, and a third absorption region 1123. The first absorption region 1121 corresponds to the N-drift region 102 below the JFET region, the second absorption region 1122 corresponds to the P bottom region 111, and the third absorption region 1123 corresponds to the P body region 103. The doping concentration of the first absorption region 1121 is greater than that of the third absorption region 1123, and the doping concentration of the third absorption region 1123 is greater than that of the second absorption region 1122.

[0058] The doping depth is the vertical distance between the bottom of the doping region and the surface of the epitaxial layer of the N+SiC substrate 101. Preferably, the JFET region is specifically the region between the symmetrically distributed P body region 103 and the P bottom region 111. Figure 2 As shown, the depth of the JFET region is H, the doping depth of the first absorption region 1121 is H1, the doping depth of the second absorption region 1122 is H2, and the doping depth of the third absorption region 1123 is H3, wherein H1>H2>H>H3.

[0059] Furthermore, the doping depth H1 of the first absorption region 1121 of the SiC MOSFET device is 0.7 μm~1.4 μm; the doping depth H2 of the second absorption region 1122 is 0.5 μm~0.8 μm; the doping depth H3 of the third absorption region 1123 is 0.2 μm~0.6 μm, and the depth H of the JFET region is between H2 and H3. Furthermore, the doping depth H1 of the first absorption region 1121 of the SiC MOSFET device is 0.7μm, 0.8μm, 0.9μm, 1.0μm, 1.1μm, 1.2μm, 1.3μm or 1.4μm, etc.; the doping depth H2 of the second absorption region 1122 is 0.5μm, 0.6μm, 0.7μm or 0.8μm, etc.; the doping depth H3 of the third absorption region 1123 is 0.2μm, 0.3μm, 0.4μm, 0.5μm or 0.6μm, etc.

[0060] The doping concentration of the first absorption region 1121 of the SiC MOSFET device is 1×10 17 cm -3 ~1×10 18 cm-3 The doping concentration of the second absorption region 1122 is 5×10 16 cm -3 ~1×10 17 cm -3 The doping concentration of the third absorption region 1123 is 7×10 16 cm -3 ~5×10 17 cm -3 Preferably, the doping concentration of the first absorption region 1121 of the SiC MOSFET device is 1×10 17 cm -3 , 3×10 17 cm -3 , 5×10 17 cm -3 , 7×10 17 cm -3 , 9×10 17 cm -3 or 1×10 18 cm -3 etc.; the doping concentration of the second absorption region 1122 is 5×10 16 cm -3 , 6×10 16 cm -3 , 7×10 16 cm -3 , 8×10 16 cm -3 , 9×10 16 cm -3 or 1×10 17 cm -3 The doping concentration of the third absorption region 1123 is 7×10 16 cm -3 , 8×10 16 cm -3 , 9×10 16 cm -3 , 1×10 17 cm -3 , 2×10 17 cm -3 , 3×10 17 cm -3 , 4×10 17 cm -3 or 5×10 17 cm -3 wait.

[0061] The provision of the hole absorption region 112 can further optimize the potential distribution near the gate dielectric layer 106 and reduce the electric field strength near the gate dielectric layer 106. It can also provide an additional path for the discharge of accumulated holes. The three-stage hole absorption region 112 with different doping concentrations can also reduce the resistance of the JFET region. Specifically, because the doping concentration of the P bottom region 111 is greater than that of the P body region 103, and the doping concentration of the P body region 103 is greater than that of the N-drift region 102, the doping concentration of the first absorption region 1121 (corresponding to the N-drift region 102 below the JFET region) is greater than the doping concentration of the third absorption region 1123 (corresponding to the P body region 103), and the doping concentration of the third absorption region 1123 is greater than the doping concentration of the second absorption region 1122 (corresponding to the P bottom region 111). That is, a second absorption region 1122 with a lower doping concentration is set for the region with a higher doping concentration (P bottom region 111), which can reduce lateral diffusion, so as to optimize the potential distribution near the gate dielectric layer 106 without excessively increasing the resistance of the JFET region, reduce the accumulation of local holes, and provide an additional extraction path for the accumulated holes, further alleviate the single particle effect, and reduce the probability of single particle gate punchthrough.

[0062] The doping concentration of the P bottom region 111 is in the range of 1×10 18 cm -3 Above, specifically 3×10 18 cm -3 ~8×10 18 cm -3 Preferably, the doping concentration of the P bottom region 111 is in the range of 3×10 18 cm -3 , 4×10 18 cm -3 , 5×10 18 cm -3 , 6×10 18 cm -3 , 7×10 18 cm -3 , 8×10 18 cm -3 wait.

[0063] The doping depth of the P bottom region 111 is less than the doping depth of the P+ region 104, and the difference is 0.1μm to 0.4μm. Preferably, the difference between the doping depth of the P bottom region and the doping depth of the P+ region is 0.1μm, 0.2μm, 0.3μm or 0.4μm.

[0064] The setting of the P bottom region 111 can increase the electric potential of the lower part of the P body region 103, form a "potential buffer layer" nearby, reduce the potential difference near the gate dielectric layer 106, alleviate the problem of hole accumulation caused by high-energy particle bombardment in space, and reduce the probability of single particle gate penetration.

[0065] Example 2

[0066] The second embodiment discloses another SiC MOSFET device, such as Figure 3 As shown, the gate dielectric layer 106 of the SiC MOSFET device cell has a greater thickness at the center of the JFET region than at other locations. That is, the longitudinal section of the gate dielectric layer 106 along the third direction is a structure with a raised center and flat sides.

[0067] This embodiment adopts a gate dielectric layer 106 structure with a raised center and flat sides, which can reduce the potential distribution of the JFET region, further alleviate the single event effect, and reduce the probability of single event gate punch-through.

[0068] Preferably, Figure 4 As shown, a longitudinal section of the gate dielectric layer 106 corresponding to the JFET region along the third direction is a cap-shaped trapezoid. The cap-shaped trapezoid can be considered to be composed of an isosceles trapezoid plus a rectangle at its top. This structure of the gate dielectric layer 106 can be achieved using a dry-etch + wet-etch process. The cap-shaped trapezoid design can further optimize the potential distribution in the JFET region, making it more gentle.

[0069] Preferably, the width of the JFET region is L, L=2μm~4μm; the bottom width of the cap trapezoid of the gate dielectric layer 106 is JL1, and JL1=0.6L~0.8L; the top width of the cap trapezoid of the gate dielectric layer 106 is JL2, and JL2=0.2L~0.6L; the maximum thickness of the gate dielectric layer 106 at the cap trapezoid is T1, the thickness of the gate dielectric layer 106 at the non-cap trapezoid is T2, and T1≥3T2.

[0070] Specifically, the maximum thickness T1 of the gate dielectric layer 106 at the top trapezoidal portion is 100 nm to 300 nm, and the thickness T2 of the gate dielectric layer 106 at the non-top trapezoidal portion is 30 nm to 70 nm. Preferably, the maximum thickness T1 of the gate dielectric layer 106 at the top trapezoidal portion is 100 nm, 120 nm, 160 nm, 200 nm, 240 nm, 280 nm, or 300 nm, and the thickness T2 of the gate dielectric layer 106 at the non-top trapezoidal portion is 30 nm, 40 nm, 50 nm, 60 nm, or 70 nm, etc.

[0071] Example 3

[0072] Example 3 discloses another SiC MOSFET device, such as Figure 5 As shown, the SiC MOSFET device further includes a gradient buffer layer 113 , which is located between the N+SiC substrate 101 and the N-drift region 102 , and the doping concentration of the gradient buffer layer 113 changes gradually from the N-drift region 102 to the N+SiC substrate 101 .

[0073] Specifically, the SiC MOSFET device adopts a thick epitaxial and N-drift region non-penetrating structure design. The doping concentration of the gradient buffer layer gradually transitions from the N-drift region (the same doping concentration as the N-drift region) to the N+SiC substrate (the same doping concentration as the N+SiC substrate). For example, according to the 1200V device grade standard, the doping concentration of the N-drift region is 8×10 15 cm -3 , with a depth of 12 μm; the doping concentration of the gradient buffer layer is 8×10 15 cm -3 The doping concentration of the gradient buffer layer transitions to that of the N+SiC substrate, and the thickness of the gradient buffer layer is 1 μm to 3 μm.

[0074] The design of the gradient buffer layer can achieve a smooth transition of the lattice constant, inhibit impurity diffusion, optimize the interface electric field, and suppress the electric field spikes at the substrate and epitaxy under high electric fields and single-particle recombination effects, thereby reducing the probability of single-event burnout (SEB).

[0075] Example 4

[0076] The fourth embodiment discloses another SiC MOSFET device, such as Figure 6 、 Figure 7 and Figure 8 As shown, the SiC MOSFET device further includes:

[0077] The transition region 114 is P-type doped and surrounds multiple cells of the SiC MOSFET device to shield the electric field of the surrounding devices (for easy observation, Figure 8 The transition region is not shown);

[0078] The hole connection region 115 is located in the N-drift region and is used to connect the hole absorption regions 112 of different cells and connect the hole absorption region 112 with the transition region 114 .

[0079] In this embodiment, the hole connection region connects the hole absorption region with the transition region, enabling the entire SiC MOSFET device to conduct locally accumulated holes, thereby overall alleviating the problem of hole accumulation caused by high-energy particle bombardment in space and reducing the probability of single-particle gate penetration.

[0080] Specifically, the hole connection region may be the same as the first absorption region, and / or the same as the second absorption region, and / or the same as the third absorption region. That is, the hole connection region may be integrally formed with the first absorption region. Alternatively, the hole connection region may be integrally formed with the first absorption region and the second absorption region. Alternatively, the hole connection region may be integrally formed with the first absorption region, the second absorption region, and the third absorption region. In addition, the hole connection region may also be connected through the P-body region and / or the P+ region.

[0081] It should be noted that in the embodiments of the present invention, the hole absorption region structure below the gate is the hole absorption region of the SiCMOSFET device, while the structure used to connect the hole absorption region at other locations is the hole connection region. Even if the hole connection region has the same or similar structure as the hole absorption region and can also absorb and conduct holes, the function of the hole connection region is still mainly to connect the holes, and it is not located below the gate.

[0082] Preferably, Figure 6 、 Figure 7 and Figure 8 As shown, the hole connection region 115 is identical to and integrally formed with the first absorption region 1121. In this way, carriers can be conducted from both sides of the hole connection region 115, further reducing the on-resistance of the JFET region.

[0083] Example 5

[0084] Embodiment 5 discloses another SiC MOSFET device, wherein the hole absorption regions of the multiple cells extend along a first direction and are interconnected or independent of each other, and the hole absorption regions of the multiple cells are interconnected in a second direction through the hole connection region.

[0085] The first method is that the hole absorption regions of multiple cells extend along a first direction and are interconnected, and the hole absorption regions of the multiple cells are interconnected in a second direction through the hole connection region, and finally the hole absorption region and the hole connection region are distributed in a network.

[0086] Specifically, such as Figure 6 (Cross-section view), Figure 7 (Top view) and Figure 8As shown in the (stereoscopic view), the multiple cell hole absorption regions 112 under the same gate are an integrated structure and extend in a first direction in parallel to each other. In the second direction, the hole absorption regions 112 are connected by the hole connection region 115 and connected in a plurality of parallel lines through the P+ region 104. The section along the third direction at point A-A' is as follows: Figure 7 shown.

[0087] Or, as Figure 9 (Top view) and Figure 10 As shown in the (stereoscopic view), along the first direction, the multiple cell hole absorption regions 112 under the same gate are an integrated structure and form multiple parallel straight lines along the first direction; along the second direction, the hole absorption regions 112 are connected by the hole connection region 115 and connected through the N-drift region 102 between the P+ regions 104 in multiple parallel straight lines. Among them, the cross section along the third direction at BB' is as follows Figure 5 shown.

[0088] The second manner: the hole absorption regions of the plurality of cells extend along the first direction and are independent of each other, and the hole absorption regions of the plurality of cells are connected to each other in the second direction through the hole connection region.

[0089] Specifically, such as Figure 11 (Top view), Figure 12 (stereoscopic) and Figure 13 As shown in the cross-sectional view, the multiple cell hole absorption regions 112 under the same gate are grouped in pairs as an integrated structure, and each group of hole absorption regions 112 is independent of each other; the hole connection region 115 (integrated with the hole absorption region 112) is distributed in a plurality of "I" shapes along the first direction, passing through the P body region 103 and the P+ region 104, and connecting to the multiple hole absorption regions 112 in the second direction. Among them, the longitudinal section along the third direction at C-C' is as follows Figure 13 shown.

[0090] Or, as Figure 14 As shown, along the first direction, multiple cell hole absorption regions 112 under the same gate are independent of each other, and the hole connection region 115 passes through the P+ region 104 along the second direction, forming multiple parallel straight lines connecting the hole absorption regions 112 distributed in the second direction.

[0091] Or, as Figure 15 As shown, along the first direction, multiple cell hole absorption regions 112 under the same gate are independent of each other, and the hole connection region 115 passes through the N-drift region between the P+ regions 104 along the second direction, forming multiple parallel straight lines connecting the hole absorption regions 112 distributed in the second direction.

[0092] In addition, the connection modes of the hole absorption region may also include the following:

[0093] The third way: the hole absorption regions of the multiple cells are only connected to each other along the first direction.

[0094] Specifically, such as Figure 16 As shown, along the first direction, the hole absorption regions 112 below the same gate are integrated and interconnected, forming multiple parallel straight lines along the first direction along with the gate. Both ends of the hole absorption region 112 are connected to the transition region 114 (this device does not have a hole connection region structure).

[0095] The fourth way: the hole absorption regions of the plurality of cells are interconnected along the first direction and also interconnected along the direction between the second direction and the second direction, and finally the hole absorption regions and the hole connection regions are distributed in a network.

[0096] Specifically, such as Figure 17 As shown, the multiple cell hole absorption regions 112 under the same gate are an integrated structure and are multiple straight lines parallel to each other along the first direction; between the first direction and the second direction (for example: at an angle of 30°, 45°, or 60° to the second direction, etc.), multiple hole connection regions 115 are arranged that are parallel to each other and pass through the P+ region 104.

[0097] In this embodiment, when multiple cell hole absorption regions under the same gate (along the first direction) are independent of each other, the disconnected region lacks a P-type hole absorption region. Depletion of the hole absorption regions on either side of the region protects the top gate dielectric layer, reducing its electric field. This approach can reduce the proportion of the P region within the JFET region, optimizing and reducing the device's on-resistance without compromising the device's radiation performance.

[0098] It should be noted that the arrangement of the hole connection region is not limited to the second direction, the direction between the second direction and the first direction, or the mutually parallel straight lines, line segments, U-shapes, and S-shapes. It can be arranged differently according to different cell distributions. In addition, whether the hole connection region passes through the P body region and / or the P+ region is related to the structural composition and location of the hole connection region. That is, when the hole connection region is the same as the first absorption region, as Figure 6 、 Figure 7 and Figure 8 As shown, the hole connection region 115 is connected via the P+ region 104. When the hole connection region is the same as the first absorption region, the second absorption region and the third absorption region, as shown in FIG. Figure 11 、 Figure 12 and Figure 13As shown, the hole connection region 115 is connected in the second direction through the P+ region 104 and the P body region 103 along the second direction.

[0099] It should be noted that the first direction is the direction of the gate finger (pointing along the gate); the second direction is a direction parallel to the N+SiC substrate and perpendicular to the first direction; and the third direction is a direction perpendicular to the N+SiC substrate. In addition, for ease of understanding, certain structures of the SiC MOSFET device (such as the gate, N+ source region, and transition region, etc.) are not clearly marked in some embodiment drawings (especially the top view and perspective views). However, some structures well known to those skilled in the art are included in the SiC MOSFET device disclosed in the embodiments of the present invention.

[0100] Example 6

[0101] Embodiment 6 discloses a method for manufacturing a SiC MOSFET device. The cell of the SiC MOSFET device manufactured by this method is the cell of the SiC MOSFET device disclosed in any of the above embodiments. The P bottom region and hole absorption of the SiC MOSFET device are formed by an ion implantation process.

[0102] The process of manufacturing the gate dielectric layer includes:

[0103] Depositing a SiO2 layer on the surface of the N+SiC substrate;

[0104] Use dry etching process to remove part of SiO2 material on both sides of the JFET area;

[0105] The remaining SiO2 material is etched using a wet etching process to form a gate dielectric layer with a cap-top trapezoidal longitudinal section in the central region.

[0106] Example 7

[0107] Example 7 discloses a specific method for manufacturing a SiC MOSFET device, such as Figure 18 As shown, the method includes:

[0108] Step S1: Figure 18 18a, prepare an N+SiC substrate 101 with an epitaxial layer. The N+SiC substrate 101 is made of silicon carbide and the doping concentration of the epitaxial layer is 8×10 15 cm -3, with a thickness of 10μm. A graded buffer layer 113 with a thickness of 2μm is provided between the epitaxial layer and the N+SiC substrate 101. After the epitaxial layer growth is completed, RCA cleaning is performed to remove contamination and particles from the wafer surface. The epitaxial layer that is not subsequently doped becomes the N-drift region 102 of the SiC MOSFET device.

[0109] Step S2: Figure 18 18b in the figure, forming the P body region 103 and the P bottom region 111. Specifically, the first mask growth etching is performed, the oxide mask thickness is 2μm, photolithography is performed, and the P body region 103 and the P bottom region 111 are doped. The implantation type is P type, AL is implanted, and the doping concentration of the P body region 103 is 4×10 17 cm -3 , the doping concentration of the P bottom region 111 is 4×10 18 cm -3 .

[0110] Step S3: Cleaning, performing the second mask growth, the oxide mask thickness is 1μm, photolithography, N+ source region implantation, the implantation type is N type, and the doping concentration is 1×10 19 cm -3 , forming an N+ source region 105 (such as Figure 18 18c in the ).

[0111] Step S4: Cleaning, performing the third mask growth, the oxide mask thickness is 2μm, photolithography, hole absorption region injection, the injection type is P type, injection AL, using D1~D6 six high energy injections to form the hole absorption region 112 (such as Figure 18 18d in the text).

[0112] Among them, D1 (20kev~40kev) and D2 (40kev~200kev) form the third absorption region 1123, with a doping concentration range of 7×10 16 cm -3 ~5×10 17 cm -3 , with a depth of 0.2μm~0.6μm. D3 (200kev~300kev) and D4 (400kev~500kev) form the second absorption region 1122, with a doping concentration range of 5×10 16 cm -3 ~1×10 17 cm -3 , with a depth of 0.5μm~0.8μm. D5 (500kev~600kev) and D6 (600kev~900kev) form the first absorption region 1121, with a doping concentration range of 1×10 17 cm -3 ~1×10 18cm -3 The depth is 0.7 μm to 1.4 μm. In this step, the hole connection region can be integrally formed with the hole absorption region 112 .

[0113] Step S5: Cleaning, performing the fourth mask growth, the oxide mask thickness is 2μm, photolithography, P+ region implantation, the implantation type is P type, and the doping concentration is 1×10 20 cm -3 , forming a P+ region 104 (such as Figure 18 18e in FIG). The transition region and the P+ region may be formed in the same implantation step.

[0114] Step S6: performing activation annealing on all implants, with the activation annealing temperature being 1500° C. to 1850° C. and the annealing time being 30 min to 60 min.

[0115] Step S7: sacrificially oxidize and then clean the activated wafer, and form a gate dielectric layer 106 (such as Figure 18 18f in FIG). Specifically, a 200±2nm thick SiO2 layer was deposited using a low-pressure chemical vapor deposition process. Dry etching was performed to a thickness of 100±5nm, removing portions of the SiO2 material on both sides of the JFET region. A wet BOE (Buffered Oxide Etch) process was then performed using a hydrofluoric acid (HF) and ammonium fluoride (NH4F) ratio of 6:1, with a thickness of 100±5nm, to create beveled edges on both sides of the thick SiO2 layer above the JFET region. This formed a gate dielectric layer 106 with a cap-top trapezoidal shape in the central region. The gate dielectric layer 106 was then subjected to an N2O annealing process at 1200°C for 30 minutes.

[0116] Step S8: depositing polysilicon and annealing the polysilicon with POCL3 to dope P element into the polysilicon to form gate 107 (such as Figure 18 of 18g).

[0117] Step S9: Using low pressure chemical vapor deposition, a field passivation layer 108 (such as Figure 18 18h in the morning).

[0118] Step S10: Photolithography to set the gate opening.

[0119] Step S11: Use magnetron sputtering to sputter nickel, and anneal it in a rapid annealing device to form an ohmic contact of the N+ source region, and perform thick AL deposition on the front side to form a source electrode 109 (such as Figure 18 18i in ).

[0120] Step S12: Use magnetron sputtering process to sputter nickel on the back surface, perform laser annealing, and then perform thick metal TiNiAg deposition on the back surface to form the drain electrode 110 (such as Figure 18 18j in ).

[0121] The technical features of the above-described embodiments may be combined in any manner. To simplify the description, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as no contradiction exists between these combinations of technical features, they should be considered to be within the scope of this specification. The terms "first" and "second" are used for distinction only and do not limit the scope of the present invention.

[0122] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A SiC MOSFET device, wherein a cell of the SiC MOSFET device comprises: N+SiC substrate, N-drift region, N+ source region, P body region, P+ region, gate dielectric layer, gate, field passivation layer, source electrode and drain electrode, characterized in that it also includes: A P bottom region, the P bottom region is located below the P body region and is P-type doped, the doping concentration of the P bottom region is greater than the doping concentration of the P body region and less than the doping concentration of the P+ region; A hole absorption region, wherein the hole absorption region is P-type doped and has a columnar shape, is located in the JFET region of the SiC MOSFET device and extends to the N-drift region below the JFET region, the width of the hole absorption region is smaller than the width of the JFET region, the top of the hole absorption region is located below the gate, the bottom depth of the hole absorption region is greater than the depth of the P bottom region and less than the depth of the P+ region, wherein the hole absorption region includes a first absorption region, a second absorption region and a third absorption region, the first absorption region corresponds to the N-drift region below the JFET region, the second absorption region corresponds to the P bottom region, and the third absorption region corresponds to the P body region, and the doping concentration of the first absorption region is greater than the doping concentration of the third absorption region, and the doping concentration of the third absorption region is greater than the doping concentration of the second absorption region.

2. The SiC MOSFET device according to claim 1, wherein: The JFET region has a depth of H, the first absorption region has a doping depth of H1, the second absorption region has a doping depth of H2, and the third absorption region has a doping depth of H3, wherein H1>H2>H>H3.

3. The SiC MOSFET device according to claim 1, wherein: The doping concentration of the P bottom region is in the range of 1×10 18 cm -3 above.

4. The SiC MOSFET device according to claim 1, wherein: The doping depth of the P bottom region is less than the doping depth of the P+ region.

5. The SiC MOSFET device according to claim 1, wherein: The longitudinal section of the gate dielectric layer corresponding to the JFET region along the third direction is a cap-top trapezoid, wherein the width of the JFET region is L; the bottom width of the cap-top trapezoid of the gate dielectric layer is JL1, and JL1=0.6L~0.8L; the top width of the cap-top trapezoid of the gate dielectric layer is JL2, and JL2=0.2L~0.6L; the maximum thickness of the gate dielectric layer at the cap-top trapezoid is T1, the thickness of the gate dielectric layer at the non-cap-top trapezoid is T2, and T1≥3T2.

6. The SiC MOSFET device according to claim 1, wherein: Also includes: A transition region, wherein the transition region is P-type doped and surrounds a plurality of cells of the SiC MOSFET device; The hole connection region is P-type doped and is located in the N-drift region. The hole connection region is used to connect the hole absorption regions of different cells and connect the hole absorption region with the transition region.

7. The SiC MOSFET device according to claim 6, wherein: The hole absorption regions of the plurality of cells extend along a first direction and are interconnected or independent of each other, and the hole absorption regions of the plurality of cells are interconnected in a second direction through the hole connection region.

8. The SiC MOSFET device according to claim 6, wherein: The hole connecting region and the first absorption region are integrally formed.

9. A method for manufacturing a SiC MOSFET device, characterized in that: The cell of the SiC MOSFET device is the cell of the SiC MOSFET device according to any one of claims 1 to 8, and the P bottom region and the hole absorption region are formed by an ion implantation process.

10. The method for manufacturing a SiC MOSFET device according to claim 9, wherein: The process of manufacturing the gate dielectric layer includes: Depositing a SiO2 layer on the surface of the N+SiC substrate; Use dry etching process to remove part of SiO2 material on both sides of the JFET area; The remaining SiO2 material is etched using a wet etching process to form a gate dielectric layer with a cap-top trapezoidal longitudinal section in the central region.

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