Sectional type silicon carbide MOSFET structure and preparation process thereof

Abstract

The invention relates to the technical field of MOS (metal oxide semiconductor), and discloses a segmented silicon carbide MOSFET (metal oxide semiconductor field effect transistor) structure and a preparation process thereof, the segmented silicon carbide MOSFET structure comprises a plurality of parallel MOS cells, each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a grid electrode and a source electrode, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, an N well layer, a P well layer and a P + layer, a silicon carbide layer is arranged in the grid electrode, the silicon carbide layer is composed of a plurality of longitudinally arranged silicon carbide blocks, and the section height of each silicon carbide block is gradually increased from bottom to top; and a doped N-layer is formed in the N substrate layer through ion implantation. Through the design of the ladder-shaped silicon carbide layers which are longitudinally arranged in the grid electrode, the electric field intensity peak value of the grid electrode area is effectively dispersed through the structure that the section heights are increased step by step from bottom to top, the breakdown risk caused by local electric field concentration is avoided, and the voltage blocking capacity of the device is remarkably improved.

Description

Technical Field

[0001] The present invention relates to the field of MOS semiconductor technology, and in particular to a segmented silicon carbide MOSFET structure and a preparation process thereof. Background Art

[0002] Conventional silicon carbide MOSFETs face bottlenecks in high-voltage applications, including gate electric field concentration, difficulty balancing on-resistance and breakdown voltage, and insufficient high-temperature reliability. Specifically, the gate oxide is prone to breakdown due to local electric field peaks, limiting voltage withstand capability; conduction losses dominated by drift region resistance restrict high-frequency performance; and thermal stress under power cycling leads to delamination and failure at the doped region and metal interface. While existing technologies attempt to optimize electric field distribution through superjunction structures or field plate designs, these processes are complex and struggle to balance carrier migration efficiency and thermal stability.

[0003] An existing patent discloses a segmented split-gate SGT MOSFET structure (publication number CN116093146A). This patent reduces input and output capacitance through a segmented split gate, but does not address the risk of gate oxide breakdown caused by gate electric field concentration under high voltage. Summary of the Invention

[0004] The present invention provides a segmented silicon carbide MOSFET structure and a preparation process thereof to solve the existing technical problems, thereby solving the problem of gate oxide layer breakdown caused by gate electric field concentration under high voltage.

[0005] To solve the above technical problems, according to one aspect of the present invention, more specifically, a segmented silicon carbide MOSFET structure includes a plurality of mutually parallel MOS cells, wherein each MOS cell includes a drain, a semiconductor epitaxial layer, a gate, and a source, wherein the semiconductor epitaxial layer includes an N substrate layer, an N drift layer, an N well layer, a P well layer, and a P+ layer, and a silicon carbide layer is provided inside the gate, wherein the silicon carbide layer is composed of a plurality of longitudinally arranged silicon carbide blocks, and the cross-sectional height of each silicon carbide block increases stepwise from bottom to top; An N-doped layer is formed inside the N substrate layer by ion implantation. The top of the N-doped layer penetrates into the N drift layer, and the bottom of the N-doped layer is in ohmic contact with the drain.

[0006] Furthermore, a doped P-layer is formed inside the doped N-layer by ion implantation.

[0007] Furthermore, the doped P-layer is composed of a plurality of transversely arranged vertical P-shaped blocks, and the bottom end of the vertical P-shaped block is in ohmic contact with the drain.

[0008] Furthermore, the doped P-layer also includes a wide doped layer, which is composed of a coarse P-block in the middle and fine P-blocks on both sides, and the bottoms of the coarse P-block and the fine P-block are in ohmic contact with the drain.

[0009] Furthermore, silicon carbide particles are provided at the bottom ends of the longitudinal P-shaped blocks, fine P-blocks and coarse P-blocks, wherein the number of silicon carbide particles at the bottom of the coarse P-block is not less than three.

[0010] Furthermore, the doped P-layer also includes a transverse doped layer, which is composed of a plurality of transverse P-shaped blocks arranged longitudinally, and the sizes and shapes of the plurality of transverse P-shaped blocks are the same.

[0011] Furthermore, the doped P-layer also includes a contact doping layer, which is composed of a number of longitudinally arranged horizontally arranged P-shaped blocks, and the cross-sectional height of each of the horizontally arranged P-shaped blocks decreases step by step from bottom to top; wherein only the bottommost horizontally arranged P-shaped block is in ohmic contact with the drain.

[0012] A process for preparing a segmented silicon carbide MOSFET structure comprises the following steps: S. epitaxially growing an N drift layer, an N well layer, a P well layer and a P+ layer in sequence on the surface of the N substrate layer to form a semiconductor epitaxial layer stack structure; S. Through a high-energy ion implantation process, a doped N- layer is formed inside the N substrate layer and penetrates to the bottom of the N drift layer, ensuring that its bottom end achieves ohmic contact with the drain electrode formed subsequently; S. Etching a trench in a predetermined area of ​​the gate and depositing silicon carbide material of different thicknesses in the trench in sections to form a silicon carbide layer consisting of a plurality of silicon carbide blocks arranged vertically and with gradually increasing cross-sectional heights from bottom to top; S. According to the design requirements, the doped N-layer is locally implanted with P-type ions through mask technology to form a doped P-layer structure; S. growing a gate dielectric layer on the surface of the silicon carbide layer, and depositing a gate electrode material to form a gate main structure, while completing the insulation isolation around the gate; S. Etch a contact hole on the top of the semiconductor epitaxial layer and deposit metal to form a source connected to the P+ layer and the P well layer; prepare a drain on the back of the N substrate layer that is in ohmic contact with the doped N- layer.

[0013] Furthermore, in step S, a strip mask is used for lateral selective implantation when forming the vertical P-shaped blocks, ensuring that the bottom of each vertical P-shaped block extends to the bottom of the doped N-layer and forms an ohmic contact with the drain.

[0014] The present invention provides a segmented silicon carbide MOSFET structure and its preparation process. Compared with the existing technology, this method achieves the following effects: 1. The present invention adopts a design of stepped silicon carbide layers arranged longitudinally inside the gate. The structure with gradually increasing cross-sectional height from bottom to top effectively disperses the peak electric field intensity in the gate area, avoids the breakdown risk caused by local electric field concentration, and significantly improves the blocking voltage capability of the device.

[0015] 2. The present invention forms an doped N- layer inside the N substrate layer that penetrates the N drift layer and realizes ohmic contact with the drain, thereby providing a low-resistance path for carriers, greatly reducing the resistance of the drift region, thereby reducing the overall conduction loss of the device and improving high-frequency switching performance.

[0016] 3. The present invention constructs a P-type doping structure such as horizontally arranged vertical P-shaped blocks or regularly distributed horizontal P-shaped blocks in the doped N-layer, utilizes the charge compensation effect to neutralize the electric field in the drift region, and realizes uniform distribution of the electric field strength in the horizontal and vertical directions, thereby improving the breakdown voltage and suppressing the leakage current.

[0017] 4. The present invention introduces silicon carbide particles at the bottom of the P-type doped region to enhance the mechanical bonding strength of the interface between the doped layer and the drain metal, effectively alleviate the thermal stress deformation during the power cycle, and improve the contact reliability under high-temperature operation.

[0018] 5. The present invention adopts mask technology to selectively inject P-type regions of different forms (such as a combination of coarse / fine P-blocks with wide doping layers or equal-sized horizontal P-shaped blocks), while achieving electric field gradient regulation and maintaining the controllability of process steps, ensuring high uniformity of device parameters in mass production.

[0019] 6. The contact doping layer of the present invention adopts a horizontally arranged P-shaped block design with gradually decreasing height from bottom to top, and realizes a smooth transition of the off-state electric field through a gradient structure, reducing the carrier tailing effect during the shutdown process, thereby reducing switching losses and improving dynamic response speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 Schematic diagram of Example 1 of the present invention; Figure 2 This is a schematic diagram of Example 2 of the present invention; Figure 3 This is a schematic diagram of Example 3 of the present invention; Figure 4 This is a schematic diagram of Example 4 of the present invention; Figure 5 This is a schematic diagram of Example 5 of the present invention; Figure 6 This is a schematic diagram of Example 6 of the present invention.

[0021] In the figure: 1. Drain; 2. Gate; 3. Source; 4. N substrate layer; 5. N drift layer; 6. N well layer; 7. P well layer; 8. P+ layer; 9. Silicon carbide layer; 10. Doped N- layer; 11. Doped P- layer; 12. Silicon carbide particles; 1101. Wide doped layer; 1102. Lateral doped layer; 1103. Contact doped layer. DETAILED DESCRIPTION

[0022] In order to make the technical solution of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0023] like Figure 3 As shown, a process for preparing a segmented silicon carbide MOSFET structure includes the following steps: Step 1: Epitaxially grow an N drift layer 5, an N well layer 6, a P well layer 7, and a P+ layer 8 on the surface of the N substrate layer 4 to form a semiconductor epitaxial layer stacking structure. By precisely controlling the epitaxial growth sequence and thickness parameters, a stacking structure of an N drift layer, an N well layer, a P well layer, and a P+ layer is constructed on the surface of the N substrate layer to ensure that the interfaces of each layer are steep and the impurity distribution is uniform, thereby providing a high-integrity semiconductor foundation for subsequent ion implantation and gate integration, and optimizing the longitudinal carrier transport path.

[0024] Step 2: Through a high-energy ion implantation process, a doped N-layer 10 is formed inside the N substrate layer 4 and penetrates to the bottom of the N drift layer 5, ensuring that its bottom end achieves ohmic contact with the drain 1 formed subsequently; high-energy ion implantation technology is used to achieve depth control of the doped N-layer from the N substrate to the bottom of the N drift layer. Its through-type design directly establishes a low-resistance ohmic contact channel between the drain and the drift region, significantly reducing the on-resistance, avoiding the resistance bottleneck of the traditional epitaxial layer, and enhancing the large current conduction capability.

[0025] Step 3: Etch a groove in a predetermined area of ​​the gate 2, and deposit silicon carbide material of different thicknesses in the groove in sections to form a silicon carbide layer 9 consisting of a plurality of silicon carbide blocks arranged vertically and with a cross-sectional height increasing step by step from bottom to top; by depositing silicon carbide blocks of different thicknesses in the gate groove in sections, a longitudinal step structure with a cross-sectional height increasing step by step from bottom to top is formed, which effectively modulates the electric field distribution near the gate and disperses the peak value of the electric field strength, thereby increasing the breakdown voltage of the device and suppressing the risk of gate oxide failure.

[0026] Step 4: Based on design requirements, masking technology is used to locally implant P-type ions into the doped N-layer 10 to form the doped P-layer 11. In this step, a strip mask is used to selectively implant lateral P-shaped blocks to ensure that the bottom of each vertical P-shaped block extends to the bottom of the doped N-layer 10 and forms an ohmic contact with the drain 1. Masking technology is used to precisely control the position and shape of the P-type ion implantation (e.g., vertical P-shaped blocks or wide doped layers), forming a charge compensation region within the doped N-layer to balance the lateral and vertical electric field strengths in the drift region. The strip mask also ensures that the bottom of the vertical P-shaped blocks is directly connected to the drain, eliminating current path bottlenecks and optimizing dynamic characteristics.

[0027] Step 5: Grow a gate dielectric layer on the surface of the silicon carbide layer 9, and deposit gate electrode material to form the main structure of the gate 2, while completing the gate peripheral insulation isolation; synchronously grow a gate dielectric layer and deposit a gate electrode on the surface of the silicon carbide layer, and the stepped silicon carbide block provides a supporting base for the gate dielectric, improving the uniformity of the dielectric layer; combined with the peripheral insulation isolation process, effectively suppress gate leakage, improve gate control efficiency and long-term reliability.

[0028] Step 6: Contact holes are etched on the top of the semiconductor epitaxial layer and metal is deposited to form a source electrode 3 connected to the P+ layer 8 and the P-well layer 7. A drain electrode 1 is formed on the back of the N substrate layer 4, making an ohmic contact with the doped N- layer 10. A faceted process is used to etch the contact hole on the top to form the source electrode (connecting the P+ / P-well layers), and the back to form the drain electrode (ohmic contact with the doped N- layer). This double-sided metallization design shortens the longitudinal carrier transmission distance and reduces contact resistance. Silicon carbide particles at the bottom of the P-type region strengthen the interface, significantly improving electrode stability under high-temperature operation.

[0029] Example 1 like Figure 1 As shown, according to one aspect of the present invention, a segmented silicon carbide MOSFET structure is provided, comprising a plurality of mutually parallel MOS cells, wherein a single MOS cell comprises a drain 1, a semiconductor epitaxial layer, a gate 2 and a source 3, wherein the semiconductor epitaxial layer comprises an N substrate layer 4, an N drift layer 5, an N well layer 6, a P well layer 7 and a P+ layer 8, and is characterized in that: a silicon carbide layer 9 is provided inside the gate 2, and the silicon carbide layer 9 is composed of a plurality of longitudinally arranged silicon carbide blocks, and the cross-sectional height of each silicon carbide block increases step by step from bottom to top; a doped N- layer 10 is formed inside the N substrate layer 4 by ion implantation, the top of the doped N- layer 10 penetrates into the interior of the N drift layer 5, and the bottom of the doped N- layer 10 is in ohmic contact with the drain 1.

[0030] A stepwise deposition process constructs a vertically arranged silicon carbide block layer 9 within the gate 2, gradually increasing its cross-sectional height from bottom to top. Simultaneously, a doped N-layer 10 is formed within the N substrate layer 4, penetrating to the N drift layer 5 and establishing ohmic contact with the drain 1. The stepped silicon carbide layer optimizes the gate electric field distribution and enhances withstand voltage. The through-doped N-layer significantly reduces on-resistance and enhances current conduction efficiency.

[0031] Example 2 like Figure 2 As shown, a doped P-layer 11 is formed inside the doped N-layer 10 by ion implantation. The doped P-layer 11 is composed of a plurality of laterally arranged vertical P-shaped blocks, and the bottom end of the vertical P-shaped block is in ohmic contact with the drain 1.

[0032] P-type ions are laterally implanted through a strip mask within doped N-layer 10, forming a vertical P-shaped block structure 11 that runs vertically through the structure, ensuring its bottom end is directly connected to the drain 1. This vertical P-type region provides charge compensation, balancing the electric field strength in the drift region and increasing the device's breakdown voltage. The through-hole design eliminates current path bottlenecks.

[0033] Example 3 like Figure 3 As shown, a doped P-layer 11 is formed inside the doped N-layer 10 by ion implantation. The doped P-layer 11 is composed of a plurality of laterally arranged vertical P-shaped blocks, the bottom ends of which make ohmic contact with the drain 1. A silicon carbide particle 12 is provided at the bottom end of the vertical P-shaped block.

[0034] Silicon carbide particles 12 are pre-deposited at the bottom of the vertical P-shaped block and combined with P-type ion implantation to form a mechanically strengthened interface. The silicon carbide particles enhance the interfacial bonding between the P-type region and the drain, suppressing contact failure caused by thermal cycling and optimizing the carrier migration path.

[0035] Example 4 like Figure 4 As shown, doped P-layer 11 further includes a wide doped layer 1101. Wide doped layer 1101 is composed of a coarse P-block in the middle and fine P-blocks on either side. The bottoms of both the coarse and fine P-blocks make ohmic contact with the drain electrode. A silicon carbide particle 12 is located at the bottom of the fine P-block, and three silicon carbide particles 12 are located at the bottom of the coarse P-block.

[0036] A gradient mask is used to simultaneously implant coarse and fine P-blocks to form a wide doped layer 1101. Silicon carbide particles 12 are then deposited at the bottom (coarse P-blocks are distributed in three locations, while fine P-blocks are distributed in a single location). The differentiated P-type region achieves an optimized electric field distribution with high conductivity at the center and low concentration at the edges. The three-point arrangement of the particles enhances mechanical stability and prevents deformation during power cycling.

[0037] Example 5 like Figure 5 As shown, the doped P-layer 11 further includes a transverse doped layer 1102 , which is composed of a plurality of transverse P-shaped blocks arranged longitudinally, and the sizes and shapes of the plurality of transverse P-shaped blocks are the same.

[0038] Uniformly sized horizontal P-type blocks are implanted through an evenly spaced vertical mask to construct the horizontal doping layer 1102. The regularly arranged P-type blocks form a lateral electric field barrier, suppressing vertical breakdown; the uniform sizing design improves process consistency and yield.

[0039] Example 6 like Figure 6 As shown, the doped P-layer 11 also includes a contact doping layer 1103, which is composed of a number of longitudinally arranged horizontally arranged P-shaped blocks, and the cross-sectional height of each horizontally arranged P-shaped block decreases step by step from bottom to top; only the bottommost horizontally arranged P-shaped block is in 1 ohm contact with the drain.

[0040] Using a stepped mask, a horizontal array of P-shaped blocks 1103 with gradually decreasing heights is implanted. Only the lowest depth is implanted to form the drain contact. The gradually varying height structure achieves a gradient transition in the electric field, reducing off-state leakage current. The single-point contact design avoids current competition and improves switch reliability.

[0041] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A segmented silicon carbide MOSFET structure, comprising a plurality of mutually parallel MOS cells, wherein each MOS cell comprises a drain (1), a semiconductor epitaxial layer, a gate (2) and a source (3), wherein the semiconductor epitaxial layer comprises an N substrate layer (4), an N drift layer (5), an N well layer (6), a P well layer (7) and a P+ layer (8), characterized in that: A silicon carbide layer (9) is provided inside the gate (2), and the silicon carbide layer (9) is composed of a plurality of silicon carbide blocks arranged longitudinally, and the cross-sectional height of each silicon carbide block increases step by step from bottom to top; A doped N-layer (10) is formed inside the N substrate layer (4) by ion implantation, the top of the doped N-layer (10) penetrates into the inside of the N drift layer (5), and the bottom of the doped N-layer (10) is in ohmic contact with the drain (1).

2. The segmented silicon carbide MOSFET structure according to claim 1, wherein: A doped P-layer (11) is formed inside the doped N-layer (10) by ion implantation.

3. The segmented silicon carbide MOSFET structure according to claim 2, wherein: The doped P-layer (11) is composed of a plurality of transversely arranged longitudinal P-shaped blocks, and the bottom end of the longitudinal P-shaped block is in ohmic contact with the drain (1).

4. The segmented silicon carbide MOSFET structure according to claim 2, wherein: The doped P-layer (11) further comprises a wide doped layer (1101), the wide doped layer (1101) consisting of a coarse P-block located in the middle and fine P-blocks located on both sides, the bottom ends of the coarse P-block and the fine P-block both being in ohmic contact with the drain (1).

5. The segmented silicon carbide MOSFET structure according to claim 3 or 4, characterized in that: The bottom ends of the longitudinal P-shaped blocks, the fine P-blocks, and the coarse P-blocks are all provided with silicon carbide particles (12), wherein the number of silicon carbide particles (12) at the bottom of the coarse P-block is not less than three.

6. The segmented silicon carbide MOSFET structure according to claim 2, wherein: The doped P-layer (11) further comprises a transverse doped layer (1102), wherein the transverse doped layer (1102) is composed of a plurality of longitudinally arranged transverse P-shaped blocks, and the plurality of transverse P-shaped blocks are all of the same size and shape.

7. The segmented silicon carbide MOSFET structure according to claim 2, wherein: The doped P-layer (11) further includes a contact doping layer (1103), which is composed of a plurality of longitudinally arranged transversely arranged P-shaped blocks, and the cross-sectional height of each transversely arranged P-shaped block decreases step by step from bottom to top; wherein only the bottommost transversely arranged P-shaped block is in ohmic contact with the drain (1).

8. A process for preparing a segmented silicon carbide MOSFET structure, characterized in that: Applied to the segmented silicon carbide MOSFET structure according to claim 3, the preparation process of the segmented silicon carbide MOSFET structure comprises the following steps: S1, epitaxially growing an N drift layer (5), an N well layer (6), a P well layer (7) and a P+ layer (8) on the surface of an N substrate layer (4) in sequence to form a semiconductor epitaxial layer stacking structure; S2. By means of a high-energy ion implantation process, a doped N-layer (10) is formed inside the N substrate layer (4) and extends to the bottom of the N drift layer (5), ensuring that the bottom end thereof is in ohmic contact with the drain (1) formed subsequently; S3, etching a groove in a predetermined area of ​​the gate (2), and depositing silicon carbide material of different thicknesses in the groove in sections to form a silicon carbide layer (9) consisting of a plurality of silicon carbide blocks arranged longitudinally and having a gradually increasing cross-sectional height from bottom to top; S4. According to the design requirements, locally implanting P-type ions into the doped N-layer (10) by mask technology to form a doped P-layer (11) structure; S5, growing a gate dielectric layer on the surface of the silicon carbide layer (9), and depositing a gate electrode material to form a main structure of the gate (2), while completing insulation isolation around the gate; S6. Etching a contact hole on the top of the semiconductor epitaxial layer and depositing metal to form a source electrode (3) connected to the P+ layer (8) and the P well layer (7); preparing a drain electrode (1) on the back side of the N substrate layer (4) in ohmic contact with the doped N- layer (10).

9. The process for preparing a segmented silicon carbide MOSFET structure according to claim 8, wherein: In step S4, a strip mask is used to perform lateral selective implantation when forming the vertical P-shaped blocks, ensuring that the bottom end of each vertical P-shaped block extends to the bottom of the doped N-layer (10) and forms an ohmic contact with the drain (1).

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