Zero diffusion interruption for improved transistor density

Abstract

Isolated interruptions between logic cells in an integrated circuit (IC) device are disclosed. A source-drain trench between adjacent channel regions includes a pair of source or drain semiconductor bodies, a first one of the source or drain bodies in the source-drain trench being connected to a first one of the channel regions, and a second one of the source or drain bodies in the source-drain trench being connected to a second one of the channel regions. A second one of the source or drain bodies in the source-drain trench is connected to a second one of the channel regions, and a dielectric isolation is in the source-drain trench and between the pair of source or drain bodies. The dielectric isolation may include voids between layers or sidewalls of a dielectric. The pair of source or drain bodies may include a highly conductive metallization layer in contact with the dielectric isolation.

Description

Background Art

[0001] While significant resources are expended to scale transistor feature sizes and thereby increase device density, a significant portion of the layout area is consumed by diffusion breaks used to separate logic cells, i.e., between devices at cell boundaries. For example, adjacent single-transistor cells employing the early double diffusion break (DDB) design would occupy three contacted polysilicon pitches (CPPs), with one CPP (or dummy gate) used for each diffusion break on either side of each individual active gate, resulting in two dummy gates between the closest active gates. Even single-transistor cells employing the conventional single diffusion break (SDB) design still occupy two CPPs each, with a dummy gate between the active gates. While single-transistor cells are an extreme example of exaggerating the area cost of diffusion breaks, very small cells are frequently used and account for a significant proportion of the layout area of ​​nearly all integrated circuit (IC) logic chips. NAND (Not AND) logic cells are only two transistors wide, and therefore diffusion breaks at cell boundaries impose a relatively significant area cost. These small cells are estimated to occupy more than half of a typical chip's area. One accepted model for transistor density uses a 60% weighting factor for NAND cells and only a 40% weighting factor for the larger scan flip-flop cells. Especially given the prevalence of small cells, the area expenditure for diffusion breaks severely limits density growth.

[0002] New techniques, structures, and materials are needed to improve layout area utilization and improve IC device density. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The materials described herein are shown in the accompanying drawings by way of example and not by way of limitation. For simplicity and clarity of illustration, the elements shown in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. In addition, where appropriate, reference numerals have been repeated between the figures to indicate corresponding or similar elements, for example, having the same or similar functions. The present disclosure will be described in more detail and detail through the use of the accompanying drawings:

[0004] Figure 1A 、 Figure 1B and Figure 1C illustrates a cross-sectional profile of an integrated circuit (IC) device having different transistor structures and bodies of source or drain material in a shared trench but separated by trench isolation portions, according to some embodiments;

[0005] Figure 2A and Figure 2B shows a plan view of logic cells separated by zero-diffusion interrupted trench isolations in accordance with some embodiments;

[0006] Figure 3 shows a cross-sectional profile of a source and drain body bisected on both ends of a channel region and having a first interface layer and a second interface layer, according to some embodiments;

[0007] Figure 4 is a flow chart of a method for forming a dielectric isolation portion between and through a bisected source or drain body, according to some embodiments;

[0008] Figure 5A 、 Figure 5B 、 Figure 5C 、 Figure 5D 、 Figure 5E 、 Figure 5F and Figure 5G illustrates cross-sectional views of an IC device having dielectric isolation between source or drain bodies and through trenches at various stages of fabrication, according to some embodiments;

[0009] Figure 6A 、 Figure 6B 、 Figure 6C and Figure 6D illustrates cross-sectional views of an IC device having self-aligned trench isolations between source or drain bodies in the same trench at various stages of fabrication, according to some embodiments;

[0010] Figure 7A 、 Figure 7B 、 Figure 7C and Figure 7D illustrates cross-sectional views of an IC device having a highly conductive interface layer on a semiconductor body and contacting trench isolations at various stages of fabrication, according to some embodiments;

[0011] Figure 8 A schematic diagram illustrating an example data server machine employing an IC device having trench isolations between retained portions of bisected bodies of source and drain material in accordance with some embodiments; and

[0012] Figure 9 is a block diagram of an example computing device in accordance with some embodiments. DETAILED DESCRIPTION

[0013] In the following detailed description, reference is made to the accompanying drawings which show, by way of illustration, specific embodiments in which the claimed subject matter may be practiced. These embodiments are described in sufficient detail to enable one skilled in the art to practice the subject matter. The various embodiments, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein with respect to one embodiment may be implemented in other embodiments without departing from the spirit and scope of the claimed subject matter.

[0014] Reference within this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment contained within the description. Thus, use of the phrase "one embodiment" or "in an embodiment" does not necessarily refer to the same embodiment. Furthermore, the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the claimed subject matter. The following detailed description, therefore, is not to be construed in a limiting sense, and the scope of the subject matter is limited solely by the appended claims, appropriately interpreted, along with the full scope of equivalents to which such claims are entitled.

[0015] As used herein, the terms "on," "to," "between," and "over" may refer to the relative position of one layer with respect to other layers. A layer that is "on" or "on" another layer or joined "to" another layer may be in direct contact with the other layer or may have one or more intervening layers. A layer that is "between" layers may be in direct contact with the layers or may have one or more intervening layers.

[0016] The terms "coupled" and "connected," as well as their derivatives, may be used herein to describe structural relationships between components. These terms are not intended to be synonymous with each other. On the contrary, in particular embodiments, "connected" may be used to indicate two or more elements that are in direct physical or electrical contact with each other. "Coupled" may be used to indicate two or more elements that are in direct or indirect physical or electrical contact with each other (with other intervening elements between them), and / or that two or more elements cooperate or interact with each other (e.g., as in a causal relationship, an electrical relationship, a functional relationship, etc.).

[0017] The term "circuit" or "module" may refer to one or more passive and / or active components arranged to cooperate with each other to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal. The meanings of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on."

[0018] The vertical orientation is in the z direction, and the expressions "top," "bottom," "above," and "below" refer to relative positions in the z dimension and have their usual meanings. However, the embodiments are not necessarily limited to the orientations or configurations shown in the figures.

[0019] The terms "substantially," "close," "roughly," "near," and "approximately" generally refer to within ±10% of a target value (unless otherwise specified). Unless otherwise specified in the specific context of use, the term "predominantly" means more than 50%, or more than half. For example, a composition that is predominantly the first component means that more than half of the composition is the first component. The term "primarily" means the largest or largest portion. For example, a composition that is predominantly the first component means that the composition has more of the first component than any other component. A composition that is predominantly the first and second components means that the composition has more of the first and second components than any other component.

[0020] Unless otherwise stated, the use of ordinal adjectives "first," "second," and "third," etc., to describe common objects merely indicates different instances of the similar objects being referenced and is not intended to imply that the objects so described are necessarily in a given order temporally, spatially, sequentially, or in any other manner.

[0021] For the purposes of this disclosure, the phrases "A and / or B" and "A or B" mean (A), (B), or (A and B). For the purposes of this disclosure, the phrases "A, B and / or C" mean (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0022] The views labeled "section," "profile," and "planar" correspond to orthogonal planes within a Cartesian coordinate system. Thus, section and profile views are taken in the xz and yz planes, and plan views are taken in the xy plane. Typically, a profile view in the xz plane is a cross-sectional view. Where appropriate, the figures are labeled with axes to indicate the orientation of the figure.

[0023] Materials, structures, and techniques are disclosed for increasing integrated circuit (IC) device density. Zero diffusion break (ZDB) isolation allows for closer placement of transistors (e.g., field effect transistors, FETs) and logic cells by isolating adjacent devices with a dielectric between reduced-width source and drain bodies in a shared trench between channel regions, saving valuable layout area between transistors at cell boundaries.

[0024] Instead of wasting the entire contacted polysilicon pitch (CPP) between adjacent source-drain trenches at each cell boundary, trench isolation can be used within a single trench while still using trenches for the drain-source epitaxial bodies for both adjacent channels and transistors. After growth, the source-drain epitaxy can be bisected and isolated by a dielectric layer or plug between the separated epitaxial portions, which can then have a width (e.g., in the direction of the channel length) that is less than half the conventional source-drain epitaxial width, e.g., about one-third the conventional source-drain epitaxial width. The improved source-drain epitaxial width can similarly be less than half the channel length, e.g., about one-third the channel length. Other source-drain epitaxies within the cell, such as those away from the cell edge or boundary, can be retained, not split, (e.g., to maintain consistent spacing between the channel and the gate).

[0025] The source-drain epitaxy can be bisected, for example, by etching a vertical opening through the epitaxy, leaving separate epitaxy portions on either side of the opening. The opening can be used to metallize exposed surfaces, such as sidewalls, of the bisected epitaxy portion, which can reduce the resistance between the transistor channel region and the source-drain contacts on the source-drain epitaxy. The separated epitaxy portions can be contacted on opposite front and back sides to increase the spacing between the contacts and the vias, which minimizes associated parasitic capacitance.

[0026] Figure 1A 、 Figure 1B and Figure 1C A cross-sectional view of an IC device 100 is shown having source or drain material bodies 110A, 110B in different transistor structures 101 and a shared trench 115 but separated by trench isolations 140 , in accordance with some embodiments. Figure 1A include Figure 1A of a portion of view 102, and Figure 1B View 102 is shown at a greater magnification. Lateral area is saved by isolating adjacent transistor structures 101 with isolation 140 within a single trench 115 between structures 101, rather than spending the entire gate pitch (eg, channel length L plus distance D1) on isolation.

[0027] Figure 1AA stack of transistor channel regions 120 in a transistor 101 is shown separated by a distance D1 from a stack of adjacent transistor channel regions 120 in an adjacent transistor structure 101. A source or drain material body 110A, 110B is in a first trench 115, and each body 110 is coupled to a corresponding source or gate material body 110 in an adjacent second trench 115 through one or more transistor channel regions 120. The corresponding source or drain material body 110 in the adjacent trenches 115 can span the distance D1 between the stack of transistor channel regions 120, coupled to both sides of the body 110 through the stack of transistor channel regions 120. The bodies 110A, 110B and the trench isolation portion 140 together span the distance D1 across the first trench 115 between the stack of transistor channel regions 120. The region 120 can be in any suitable structure. For example, the transistor structure 101 can be a FinFET, and the channel region 120 can be in a fin of semiconductor material. In Figure 1A In the example of FIG, transistor channel region 120 is a stack of nanoribbons in each transistor structure 101. Region 120 has a channel length L between source or drain material bodies 110. The length L of region 120 is substantially equal to the distance D1 between regions 120.

[0028] The grooves 115 may extend longitudinally in the y-direction and have a width equal to the distance D1 between adjacent stacks of regions 120. The grooves 115 may extend through and between other stacks of regions 120, for example (not shown), at Figure 1A in front and behind the xz viewing plane of the trench 115. The sidewalls of the trench 115 include substantially planar sidewall surfaces 116 of the source or drain material body 110. For example, in cross section, the sidewall surfaces 116 are substantially linear and vertical along the ends of the channel regions 120. The sidewalls of the trench 115 contact the ends of the channel regions 120 on the surfaces 116 and the spacers 124 between the channel regions 120. The sidewalls of the trench 115 may also extend upward to contact the spacers 123 on the surfaces 116 and extend above the channel regions 120. The trench 115 may have a curved (e.g., U-shaped) bottom in the substrate 199 below the channel regions 120. The trench 115 may be formed into the substrate 199 by cutting or etching, the trench 115 dividing the stack of longer channel regions 120 into Figure 1A The shorter stack of channel regions 120 in FIG. 1 is shown, although the trenches 115 may be formed by other methods.

[0029] Each source or drain body 110A, 110B is coupled to a corresponding stack of channel regions 120. Bodies 110A, 110B are within a notch or trench 115, within the same or single distance D1 between the stack of transistor channel regions 120. Trench isolations 140 are also located between a pair of source or drain material bodies 110A, 110B, within the same or single distance D1 between the stack of transistor channel regions 120. Trench isolations 140 contact and separate source or drain material bodies 110A, 110B. Trench isolations 140 contact faces 117 of bodies 110A, 110B. Trench isolations 140 and bodies of source or drain material 110A, 110B separate adjacent stacks of transistor channel regions 120, and the adjacent stacks of transistor channel regions 120, isolations 140, and bodies 110A, 110B are continuous. The trench isolations 140 separating adjacent bodies 110A, 110B also separate adjacent transistor structures 101. The dielectric material of isolations 140 extends between a first body and a second body in a pair of bodies 110A, 110B to a height H1 of at least a pair of bodies of source or drain material 110A, 110B. The height H1 of bodies 110A, 110B extends upward to (or above) the top-contacted channel region 120 and downward to (or below) the bottom-contacted channel region 120. The bodies 110A, 110B may include an interface layer 113 at the top of the bodies 110A, 110B. The bodies 110A, 110B may extend into the substrate 199 well below the region 120.

[0030] The trench isolation portion 140 includes a dielectric material within a distance D1 and between a pair of source or drain material bodies 110A, 110B. The isolation portion 140 can provide insulation, e.g., electrical insulation, between adjacent bodies 110A, 110B and between adjacent transistor structures 101. The trench isolation portion 140 advantageously includes a low dielectric constant ("low-K") dielectric material. In many embodiments, the isolation portion 140 includes oxygen, e.g., in silicon oxide. The dielectric material of the isolation portion 140 can be any suitable material. Including nitrogen and / or carbon in the isolation portion 140 can help provide etch selectivity relative to other adjacent dielectric materials (e.g., dielectric materials including oxygen). In many embodiments, the isolation portion 140 includes nitrogen, e.g., in silicon nitride. In some embodiments, the isolation portion 140 includes nitrogen and oxygen, e.g., in silicon oxynitride. In some embodiments, the isolation portion 140 includes carbon, e.g., in carbon-doped silicon nitride or silicon oxynitride. The trench isolation portion 140 need not include silicon, but compounds of silicon may provide convenience in fabrication processes involving silicon structures.

[0031] Isolation 140 can be composed essentially of a dielectric material, but can also include, for example, voids 144, which can improve insulation between adjacent bodies 110A, 110B and between adjacent structures 101. Voids 144 can include a gas (e.g., nitrogen, oxygen, etc.), for example, a representative sample of the contents of a processing chamber during formation of trench isolation 140. Voids 144 can have a relative permittivity at or near the permittivity of a vacuum. Isolation 140 having a low relative permittivity and / or the dielectric material of isolation 140 including voids 144 can provide improved electrical insulation by reducing parasitic coupling between adjacent bodies 110A, 110B and between adjacent structures 101.

[0032] Trench isolation 140 can be a dielectric layer or plug formed in an opening formed between source or drain material bodies 110A, 110B, e.g., in an opening that bisects a previously single or unitary body 110 spanning distance D1 between regions 120. Bodies 110A, 110B can be symmetrical about isolation 140 bisecting trench 115, e.g., mirror images or reflections of each other. In many embodiments, bodies 110A, 110B are symmetrical about a vertical axis (e.g., centerline CL) passing through trench isolation 140. In some embodiments, both bodies 110A, 110B (e.g., in the z-dimension) have a longer face 117 on isolation 140 and a shorter face 116 on channel region 120. For example, face 117 has a height H3 greater than face 116 height H2. The bodies 110A, 110B can have curved surfaces at the bottom of the trenches 115, on the substrate 199 (or, for example, on dielectric spacers 194 on the substrate 199), and below the substantially planar or linear faces 116, 117. The dielectric spacers 194 can be on the substrate 199 at the bottom of the trenches 115. The dielectric spacers 194 can be the same dielectric material as the spacers 124 between the channel regions 120.

[0033] The source and drain material bodies 110 (e.g., bodies 110A, 110B) are electrically and physically coupled to opposite ends of the channel region 120. The source and drain material bodies 110 are impurity-doped regions, for example, semiconductor materials doped with one or more electrically active impurities. In many embodiments, the bodies 110 are primarily silicon or primarily silicon germanium, with small amounts of donor or acceptor dopants. The impurity-doped bodies 110 can have increased charge carrier availability and associated conductivity. The source and drain material bodies 110 can be doped with a type opposite to that of the channel region 120 (e.g., n-type or p-type) or a similar type. The source and drain material bodies 110 can include a dominant semiconductor material, and one or more n-dopants (e.g., phosphorus, arsenic, or antimony) or p-type impurities (e.g., boron or aluminum). Other dopant materials can also be used. Any suitable formation method can be used. The body of material 110 can be, for example, an epitaxially grown semiconductor region of a Group IV semiconductor material (e.g., Si, Ge, SiGe, or a GeSn alloy). Other semiconductor materials can be used. The body of material 110 is substantially crystalline. The source and drain body of material 110 can be polycrystalline, for example, having long-range order at at least adjacent ends of the channel region 120 and merging or joining into a single body with few grain boundaries. The source and drain body of material 110 can be substantially single crystalline.

[0034] The source and drain bodies 110 may include an interfacial layer 113, for example, having very low contact resistivity and used to contact the metallization structure 130 above the body 110. In many embodiments, the source or drain body 110 includes a highly conductive interfacial layer 113 comprising one or more metals. For example, a body 110 of silicon (including a body 110 of silicon germanium) may include a metal alloyed with silicon in the interfacial layer 113 at the top of the body 110. In some embodiments, the body 110 includes an interfacial layer 113 comprising titanium and silicon. In some embodiments, the body 110 includes an interfacial layer 113 comprising one of cobalt, nickel, ruthenium, platinum, or tungsten and silicon. Other metals may be used.

[0035] In many embodiments, at least some of the transistor structures 101 are physically symmetrical about the channel region 120, and in many contexts, the designations used for the source and drain material bodies 110 may be reversed. However, the source and drain material bodies 110 may be categorized by their electrical relationship to other components of a given circuit (e.g., and the resulting direction of current flow through the structure 101 and material body 110).

[0036] The channel region 120 can be of any suitable structure. In some embodiments, the stack of regions 120 includes more or fewer nanoribbons (e.g., each stack includes three nanoribbons). In some embodiments, the source and drain bodies are coupled through a single nanoribbon channel region 120 rather than a stack. The nanoribbon channel region 120 can have any suitable width, including a sufficiently narrow or wide width to be characterized as a nanowire or nanosheet, respectively. In some embodiments, the channel region 120 is in a substantially vertical fin coupled between the bodies 110.

[0037] The channel region 120 may comprise any suitable material(s), for example, one or more semiconductor materials. The channel region 120 may comprise silicon, germanium, silicon germanium (eg, Si 1-x Ge x ), Group III-V alloy materials (e.g., gallium arsenide or gallium nitride), or other materials. Suitable materials may include two-dimensional (2D) materials (e.g., transition metal dichalcogenides (TMDs)) or semiconductor films (e.g., certain metal oxides). The channel region semiconductor material may be doped with one or more electrically active impurities, for example, to increase channel conductivity.

[0038] The transistor structure 101 includes a gate electrode 122 and a gate dielectric 121 in a gate structure above and adjacent to a channel region 120. The gate structure includes the gate dielectric 121 above the channel region 120, for example, above and around each nanoribbon. The gate structure includes the gate electrode 122 between adjacent metallization structures 130 (e.g., above each source or drain body 110), and has the gate dielectric 121 between the gate electrode 122 and each channel region 120 (e.g., nanoribbon). The gate dielectric 121 provides electrical insulation between the channel region 120 and the gate electrode 122 and enables electrostatic control of the channel region 120 (and conduction in the region 120) via an electrical signal on the gate electrode 122. Conduction in the channel region 120 can electrically couple the adjacent source and drain bodies 110 and the corresponding metallization structures 130 coupled to the bodies 110.

[0039] The gate dielectric 121 may have more than one layer. The gate dielectric 121 may have any suitable material(s). One or more layers of the gate dielectric 121 may include silicon oxide, silicon dioxide (SiO2), silicon oxynitride, etc. Advantageously, the gate dielectric 121 includes a high dielectric constant ("high-K") dielectric (e.g., having a dielectric constant greater than 6). High-K dielectric materials may include one or more of various elements, such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. The gate dielectric 121 may include, for example, dopants for increasing the dielectric constant.

[0040] The gate electrode 122 is on the gate dielectric 121 and may include at least one of a p-type or n-type work function metal (WFM), depending on whether the transistor is a pMOS transistor or an nMOS transistor. In some embodiments, the gate electrode 122 is a stack of two or more metal layers, one or more of which is a WFM layer and at least one of which is a fill metal layer. In a pMOS transistor, for example, metals that can be used for the gate electrode 122 include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, such as ruthenium oxide. The p-type metal layer will enable the formation of a pMOS gate electrode 122 having a work function between approximately 4.9 eV and approximately 5.2 eV. These or other metals that may be deployed in the gate electrode 122 in an nMOS transistor include hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide), and the like. The n-type metal layer will enable the formation of an nMOS gate electrode 122 having a work function between approximately 3.9 eV and 4.2 eV.

[0041] The metallization structure 130 is a conductive (e.g., metal) structure that contacts the source or drain body 110. The structure 130 couples the source and drain bodies 110 (and the transistor structure 101) to an interconnect layer, for example, an interconnect network 131 above the transistor structure 101. The structure 130 contacts each of the source and drain bodies 110 at the interface layer 113. The metallization structure 130 may include any suitable material(s). In some embodiments, the structure 130 includes a stack of two or more metal layers, for example, wherein at least one of the included metal layers is a liner 136 and at least one of the metal layers is a fill metal layer. In many embodiments, the structure 130 includes one or more of copper, gold, tantalum, cobalt, tungsten, ruthenium, molybdenum, aluminum, and nickel, including in the form of alloys. In some embodiments, the structure 130 includes nitrides of metals such as tantalum and titanium. The structure 130 may include other conductive materials, including non-metals.

[0042] The interconnect network 131 can be a front-side or back-side network 131 and can include any suitable number of interconnect layers. The network 131 includes a via structure 133 that extends through a dielectric isolation portion 135 and contacts the structure 130. The dielectric isolation portion 135 can be an interlayer dielectric (ILD), for example, a low-K dielectric material that isolates the vias from other metallization structures 133.

[0043] exist Figure 1A In the cross-sectional view of FIG, the metallization structure 130 on the source or drain body 110B is coupled to the interconnect network 131 at the via structure 133 in the visible xz plane. The metallization structure 130 on the source or drain body 110A can be contacted by the via structure 133 behind or in front of the viewing plane (e.g., deeper or shallower on the y-axis than the visible xz plane).

[0044] The spacer 123 provides isolation between the metallization structure 130 and the gate electrode 122. The spacer 123 (e.g., at layer 136) contacts the structure 130 and contacts the gate electrode 122. The spacer 123 can be of any suitable insulating material. For example, the spacer 123 advantageously includes a low-K dielectric material to provide electrical isolation and reduce parasitic coupling between the adjacent structure 130 and the electrode 122.

[0045] Spacers 124 similarly provide isolation between the source and drain material bodies 110 and the gate electrode 122. Spacers 124 are in contact with the bodies 110 and the gate electrode 122. Spacers 124 are also between and in contact with the channel region 120, with spacers 124 being between the source and drain bodies 110 and the gate electrode 122. Spacers 124 can comprise any suitable insulating material, advantageously a low-K dielectric to minimize parasitic coupling between the adjacent bodies 110 and the gate electrode 122. Spacers 123, 124 can comprise the same electrically insulating material.

[0046] The insulating layer 126 comprises a dielectric material, for example, a low-K dielectric material, which provides electrical isolation between metallization structures 130, between metallization structures 130 and interconnect layers in network 131, between gate electrode 122 and network 131, and the like. Layer 126 can provide etch selectivity relative to other adjacent dielectric materials. In some embodiments, gate electrode 122 is contacted by a via structure 133 (not shown; for example, between spacers 123) extending through layer 126 (e.g., and dielectric isolation portion 135). In some embodiments, gate electrode 122 is contacted by a metallization structure 130 (not shown; for example, on electrode 122, between spacers 123) located at an unoccupied portion of layer 126.

[0047] Substrate 199 may comprise any suitable material or materials. In some examples, substrate 199 may comprise single crystal silicon (including silicon-on-insulator (SOI)), polycrystalline silicon, germanium, silicon-germanium, Group III-V alloy materials (e.g., gallium arsenide), silicon carbide (e.g., SiC), sapphire (e.g., Al2O3), or any combination thereof. Substrate 199 may specifically refer to a base material (e.g., a thick substrate or layer of semiconductor material) upon which other materials (e.g., metals and dielectrics) are built. In some contexts, substrate 199 may refer to a layer of base material and any built-up layers above the base. In many embodiments, substrate 199 comprises semiconductor material underlying body 110 and region 120, and channel region 120 comprises the same semiconductor material. In some such embodiments, trench 115 is a cut through silicon channel region 120 (e.g., a nanoribbon) and into silicon substrate 199. Substrate 199 may also comprise other semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates.

[0048] Figure 1B Shown Figure 1A 102, includes a trench isolation 140 bisecting trench 115 and separating material bodies 110A, 110B, and transistor structure 101. Source or drain material bodies 110A, 110B share first trench 115, but are in separate transistor structures 101 and coupled to separate stacks of channel regions 120. For example, source or drain material body 110A is coupled to source or drain material body 110 across adjacent second trench 115 by a distance D1 through channel region 120.

[0049] Isolation 140 includes a void 144, which can improve insulation between adjacent bodies 110A, 110B and between adjacent structures 101. Void 144 is between a first layer 141 and a second layer 141 of dielectric material of trench isolation 140. For example, first layer 141 is between void 144 and body of source or drain material 110B in first transistor structure 101, and second layer 141 is between void 144 and body of source or drain material 110A in second transistor structure 101. First layer 141 and second layer 141 can be, for example, a single, continuous layer of dielectric material of trench isolation 140 connected beneath void 144. For example, trench isolation 140 can be formed by depositing a layer of dielectric material 141 in an opening that bisects body of source or drain material 110 and trench 115 and forms bodies 110A, 110B. The dielectric material layer 141 may be deposited on the faces 117 of both bodies 110A, 110B, and below the faces 117 adjacent to the bottom of the trench 115 (eg, as shown in FIG. 1 ). Figure 1A194 ), and the layer(s) 141 may include a void 144 within the layer(s) 141 where the layer 141 below the void 144 meets the layer 141 deposited above the void 144 (e.g., as shown in FIG. Figure 1A As shown, between the dielectric isolation portion 135 below).

[0050] Collectively, the bodies 110A, 110B and the trench isolation 140 span a distance D1 across the first trench 115 between the stack of transistor channel regions 120. The source or drain material body 110B has a first width W 1B , the source or drain material body 110A has a second width W 1A , and the isolation portion 140 has a thickness W2 within the distance D1 and between the pair of source or drain material bodies 110A, 110B. The thickness W2 is proportional to the width W 1A 、W 1B The sum of the distances W and D is equal to the distance D1. The trench isolation portion 140 bisects the trench 115, and the bodies 110A and 110B have equal widths W. 1A 、W 1B In some embodiments, the bodies 110A, 110B have a width W each equal to the thickness W2. 1A 、W 1B , and the width W 1A 、W 1B and thickness W2 are each equal to one third of distance D1. Width W 1A 、W 1B These equal proportions of width W and thickness W2 can allow for sufficiently large cuts or etches through trench 115, yet still have sufficiently large bodies 110A, 110B (e.g., to ensure adequate conductivity and mechanical strength through the entire height of bodies 110A, 110B). In some embodiments, bodies 110A, 110B have widths W each equal to twice the thickness W2. 1A 、W 1B , and the width W 1A 、W 1B Each is equal to two fifths of the distance D1. Width W 1A 、W 1B These ratios greater than thickness W2 can be achieved by precise cutting or etching through trench 115 and can provide increased conductivity and mechanical strength of body 110A, 110B. In some embodiments, body 110A, 110B has a width W each equal to half of thickness W2. 1A 、W 1B , and the width W 1A 、W 1B Each is equal to one quarter of the distance D1. The thickness W2 is greater than the width W1A 、W 1B These ratios can be achieved with bodies 110A, 110B having increased conductivity and can allow for less precise cutting or etching through trench 115. In some such embodiments, bodies 110A, 110B have widths W that are each approximately equal to the thickness of dielectric layer 141. 1A 、W 1B .

[0051] Region 120 has a channel length L between the source or drain material bodies 110. The length L of region 120 is approximately equal to the distance D1 between regions 120. In some embodiments, the length L is longer than the distance D1. In some such embodiments, the bodies 110A, 110B have a width W that is each approximately equal to one-quarter of the channel length L. 1A 、W 1B .

[0052] Figure 1C A similar IC device 100 (or, for example, a similar portion of the same device 100 ) is shown having source or drain material bodies 110A, 110B in different transistor structures 101 and separated by a trench isolation 140 that bisects a shared trench 115 . Figure 1C In the example of FIG. 1 , each transistor structure 101 is coupled to one or both of a front-side and back-side interconnection network 131, 132. The interconnection network 132 includes a metallization or via structure 134 that is similar to the metallization or via structure 133, but on a side 128 opposite the side 127 of the via structure 133 and network 131. For example, the interconnection network 132 can be on the back side 128, with the opposing interconnection network 131 on the front side 127. The transistor structure 101 can be in a device layer between the front side 127 and the back side 128. A first metallization structure 130 contacts the source or drain material body 110 (coupled to the body 110A through the channel region 120). A second metallization structure 134 contacts the source or drain material body 110A. A third metallization structure 130 contacts the source or drain material body 110B. The first and third metallization structures 130 , 130 are on a first side 127 of the stack of the transistor channel region 120 , and the second metallization structure 134 is on a second side 128 of the stack of the transistor channel region 120 opposite the first side 127 .

[0053] Source or drain body 110 (including body 110A, 110B) includes an interface layer 113 in contact with metallization structure 130. In some embodiments, body 110A, 110B includes a similar interface layer 113 on side 128 opposite side 127, for example, in contact with via structure 134.

[0054] In some embodiments, after back grinding removes portions of substrate 199, including the bottoms of trenches 115 below structure 101 (e.g., including at least some of the curved surfaces) and the remainder of body 110, a backside interconnect network (e.g., network 132) is coupled to structure 101 and body 110. Trenches 115 may still be evident as gaps or interruptions between otherwise aligned channel regions 120, e.g., having sidewalls at face 116 of body 110. In some embodiments, trenches 115 extend in the y-direction through multiple parallel rows of channel regions 120 extending in the x-direction. Thus, trenches 115 may be evident in a plan view as gaps or interruptions between otherwise aligned channel regions 120.

[0055] Figure 2A and Figure 2B 1 shows a plan view of logic cells 201 separated by zero-diffusion interrupt trench isolations 140 in accordance with some embodiments. For example, Figure 2A An inverter logic cell 201 is shown separated from adjacent cells 201 by isolation 140 (e.g., between adjacent metallization structures 130A, 130B). The cell 201 is indicated by a dashed boundary that at least roughly depicts the transistor structure 101 of the cell 201. For example, the dashed boundary of the cell 201 runs through the trench isolation 140, the channel region 120, and the metallization structures 130A, 130B between adjacent structures 101. The dashed boundary of the cell 201 may also run through structures associated with a single cell 201 (e.g., structures 130A, 133).

[0056] The zero-diffusion interrupt trench isolation 140 results in significant layout area savings compared to conventional solutions. Figure 2A Three cells 201 having a width of two transistors are shown, i.e., occupying six CPPs. If the cells had a width of a single transistor, earlier double diffusion break (DBB) systems would only be able to fit two cells into the six CPPs. Conventional single diffusion break (SDB) layout schemes can fit two cells having a width of two transistors, but not three. Zero diffusion break trench isolations 140 achieve improved layout area efficiency, for example, by deploying parallel structures (as in the case of parallel branches in an inverter logic cell), saving chip area and / or allowing improved performance for the same area cost.

[0057] The cell 201 includes a transistor structure 101 having channel regions 120A, 120B. Figure 2AIn the example of FIG. 1 , the transistor structures 101 are a p-type structure 101 having a channel region 120A and an n-type structure 101 having a channel region 120B. For the center inverter cell 201 between adjacent cells 201, the source body of the transistor structure 101 is coupled to the power supply through a via structure 133 on the metallization structure 130, and the drain body is coupled together (e.g., through the central metallization structure 130 coupled to both the p-type structure 101 and the n-type structure 101). A positive power supply (e.g., V DD )Towards Figure 2A top (e.g., in the positive y direction), and the opposite (e.g., ground or negative) power supply (e.g., V SS )Towards Figure 2A 101 ). The input A to the center inverter 201 is coupled to the gate electrodes 122, which are coupled together (not shown; for example, by metallization lines extending above the gate electrodes 122 and in the x-direction). The output ā from the center inverter cell 201 is coupled to the drain body at a shared central structure 130 above and between the p-type structure 101 and the n-type structure 101. The center inverter cell 201 has parallel branches having: two parallel p-type transistor structures 101 with channel regions 120A electrically between a positive power supply and the central metallization structure 130 (above the shared drain body); and two parallel n-type transistor structures 101 with channel regions 120B electrically between an opposite power supply and the central metallization structure 130 (above the shared drain body). Each parallel branch (having one p-type structure 101 and one n-type structure 101 ) has one gate electrode 122 above both channel regions 120A, 120B.

[0058] Regions 120 extend in the x-direction. Trenches 115 (having sidewalls indicated by dashed lines) extend in the y-direction and divide or separate channel regions 120. Trenches 115 have a width of distance D1 between aligned (or coaxial) adjacent channel regions 120. Source or drain bodies (not shown) are in trenches 115, between regions 120, and under each structure 130. As described (e.g., Figure 1A ), the trench isolation portion 140 is between an adjacent pair of source or drain bodies (not shown) and between a corresponding pair of metallization structures 130.

[0059] For the inverter cell 201 shown between other cells 201, the dashed box indicates the organization of the included transistor structures 101, e.g., structures 101a1, 101a2, 101b1, 101b2. Each transistor structure 101 includes a gate electrode 122 coupled between source and drain bodies (not shown) below a metallization structure 130, over a channel region 120 (e.g., a stack of nanoribbon regions 120). Transistor structures 101a1, 101a2 are parallel p-type branches between a positive power supply and a shared drain body and a central metallization structure 130. Transistor structures 101b1, 101b2 are parallel n-type branches between an opposite power supply and a shared drain body and the central structure 130.

[0060] Transistor structure 101a1 and Figure 1A or Figure 1C 130A, with the source body (not shown, below structure 130A) separated from the other cell 210 and transistor structure by trench isolation 140. Figure 2A In the example shown, the source body is coupled to the interconnect network (e.g., front-side network) in the positive z-direction through via structure 133. The source body under structure 130A is one of a first pair of source or drain material bodies separated by isolation 140 and having a width less than distance D1, while the other of the first pair of source or drain material bodies is under structure 130B and in adjacent cell 201 and transistor structures. The source body under structure 130A is coupled to the drain body (not shown, coupled to both p-type structure 101 and n-type structure 101 under central structure 130) through the stack of channel region(s) 120A. The drain body under central structure 130 spans distance D1 in trench 115 and between regions 120A. Transistor structure 101a1 is a p-type structure 101, and gate electrode 122 is above channel region(s) 120A and between metallization structures 130A, 130.

[0061] Transistor structure 101a2 is similar to structure 101a1, but is a mirror image of structure 101a1 reflected along an axis extending in the y-direction. Transistor structure 101a2 is also p-type structure 101, but has a second gate electrode 122 above another stack of channel regions 120A (with a common body of drain material between the stack of channel regions 120A and the first stack of channel regions 120A). Transistor structure 101a2 is coupled to the same power source as structure 101a1, but through a separate via structure 133. The second pair of source or drain material bodies are split by second trench isolations 140 between adjacent cells 201 and between adjacent transistor structures. The first of the second pair of source or drain material bodies is a source body (not shown, under structure 130A) coupled to the same drain material body (not shown, spanning a distance D1 of trench 115 between regions 120A and under central structure 130 coupled to p-type structure 101 and n-type structure 101) through the second stack of transistor channel region 120A. The second of the second pair of source or drain material bodies is not shown, under structure 130B. The first of the second pair of source or drain material bodies is between the second trench isolation 140 and the stack of channel region(s) 120A.

[0062] Transistor structure 101b1 is similar to structure 101a1, but is a mirror image of structure 101a1 reflected along an axis extending in the x-direction. Transistor structure 101b1 is an n-type structure 101, coupled to the same gate electrode 122 as structure 101a1, but located above a separate stack of channel regions 120B. Transistor structure 101b1 is coupled to a second body of drain material beneath the same central structure 130 that couples to p-type and n-type structures 101, but spans a distance D1 across the central trench 115 between the different channel regions 120B. Transistor structure 101b1 is coupled to a power source (e.g., to a front-side network) opposite to that of structure 101a1 through a similar via structure 133. A third pair of source or drain material bodies is split by third trench isolations 140 between adjacent cells 201 and between adjacent transistor structures. The first of the third pair of source or drain material bodies is a source body coupled to the second drain material body between channel regions 120B (not shown, in another structure 130A). The first of the third pair of source or drain material bodies is between the stack of channel regions 120 and third isolation portion 140. (The second of the third pair of source or drain material bodies is separated from the first of the third pair of source or drain material bodies by isolation portion 140 in the adjacent cell 201 and transistor structure, in structure 130B.)

[0063] Another stack of transistor channel regions 120B (the final stack of transistor channel regions 120 in central inverter cell 201) is coupled to the second body of drain material and the first of a fourth pair of source or drain material bodies (not shown) in n-type transistor structure 101b2, and between the second body of drain material and the first of a fourth pair of source or drain material bodies (not shown) in n-type transistor structure 101b2. Transistor structure 101b2 is similar to structures 101a2 and 101b1, being a mirror image of structure 101a2 reflected along an axis extending in the x-direction and a mirror image of 101b1 reflected along an axis extending in the y-direction. The fourth pair of source or drain material bodies is separated by a fourth trench isolation 140, and the second of the fourth pair of source or drain material bodies (not shown) is located below structure 130B and in adjacent cell 201 and transistor structures. The first of the fourth pair of bodies of source or drain material is a source body between the fourth isolation 140 and the last stack of region 120B.

[0064] Each of the first of the first pair of source or drain material bodies, the first of the second pair of source or drain material bodies, the first of the third pair of source or drain material bodies, and the first of the fourth pair of source or drain material bodies (all source bodies, not shown, but beneath the corresponding metallization structure 130A) have substantially the same width, less than half the distance D1 (e.g., as shown in FIG. 1 ). Figure 1B The width W 1A Each of the complementary other of the first, second, third, and fourth pairs of source or drain material bodies (all not shown, but beneath the corresponding metallization structure 130B) has substantially the same width, less than half the distance D1 (e.g., as shown in FIG. Figure 1B The width W 1A or W 1B Each of the first, second, third and fourth trench isolation portions 140 has the same thickness W2 and a width W within a distance D1 of the trench 115. 1A (or width W 1A and W 1B ). Thickness W2 and width W 1A 、W 1B The sum of is equal to the distance D1.

[0065] Alternatively, adjacent cells 201 may be inverter cells 201 with parallel branches, e.g., with a single electrical connection (e.g., via metallization structure 130) from a shared source body (not shown; beneath structure 130) to each power supply. Drain bodies on channel regions 120A, 120B (not shown; beneath metallization structure 130B, on isolation 140 at the boundary of cell 201) may be coupled via structure 130B. The drain bodies and structure 130B may be coupled via a backside connection, e.g., via backside vias (not shown) and backside metallization lines (not shown, e.g., running in the x-direction, beneath and between regions 120A, 120B) in a backside interconnect network (not shown).

[0066] IC device 100 (and structure 101) can be coupled to one or more power sources on host component 299, or through host component 299, which is coupled to substrate 199. Host component 299 is a planar platform or substrate and can include dielectric and metallization structures. Host component 299 can be mechanically supported and electrically coupled to substrate 199. At least one side of host component 299 includes an interconnect interface, for example, for soldering or direct bonding to one or more IC dies or other substrates. The opposite side of host component 299 can include a similar interface or, for example, copper pads for plugging into another substrate or host component, such as a printed circuit board, or solder bumps for bonding to the other substrate or host component. Host component 299 can be any platform with an interconnect interface, such as a package substrate or interposer, another IC die, etc. Host component 299 itself can be a die or an insulating substrate. Host component 299 can be bonded to any platform, such as a package substrate or interposer, another IC die, etc. In many embodiments, substrate 199 is an IC die and host component 299 is a package substrate or interposer.

[0067] Figure 2B Shown with Figure 2AA similar logic cell 201 is separated from adjacent cells 201 by isolation 140, but has different metallization structures 233, 236 and lines 230, 231, making it a NAND (Not AND) cell 201. Gate electrodes 122 each represent separate inputs A and B, for example, where input B is attached to electrode 122 of transistor structures 101a1, 101b1 (above the stack of channel regions 120A, 120B), and input A is attached to electrode 122 of transistor structures 101a2, 101b2 (above the stack of channel regions 120A, 120B). The shared drain body of the p-type transistor structures 101a1, 101a2 (spanning a distance D1 in the central trench 115 between the channel regions 120A) is not coupled to the shared drain body of the n-type transistor structures via trench contact structure 130. The source body of n-type transistor structure 101b1 (under structure 130A) is attached to the opposite (e.g., ground or negative) power supply (through structures 130A, 133) as before, but the source body of n-type transistor structure 101b2 (under structure 130A) is attached to the opposite (e.g., ground or negative) power supply (through structures 130A, 133) as before. Figure 2B In the example shown in FIG. 1 , the drain body of structure 101 b 1 is the drain body of structure 101 b 1 (spanning the distance D1 in the central trench 115 between the different channel regions 120B). With the drain body of structure 101 b 2 (under substrate 130A) coupled to metallization line 231 (through via structure 233 above structure 130A, metallization line 230, and via structure 236 above line 230), the n-type transistor structures 101 b 1 and 101 b 2 are connected in series between the ground or negative power supply and the output node attached to the shared drain body of the p-type transistor structures 101 a 1 and 101 a 2. The shared drain body of the p-type transistor structures 101a1, 101a2 is coupled upward to the metallization line 231 through the via structure 236. The shared drain body of the p-type transistor structures 101a1, 101a2 is coupled to the positive power supply through a parallel branch passing through both p-type transistor structures 101a1, 101a2 (as well as both the stack of channel region 120A and the source bodies under the two corresponding structures 130A).

[0068] Figure 3 A cross-sectional profile of bisected source and drain bodies 110A, 110B on both ends of a channel region 120 and having first and second interface layers 113 , 314 is shown, in accordance with some embodiments. Figure 3 The transistor structure 101 is different from that in the previous embodiment (e.g., Figure 1C In some embodiments, as in Figure 3In the example of FIG. 1 , the transistor structure 101 includes a channel region 120 between and coupling a pair of bisected source and drain bodies 110A, 110B, for example, wherein both the source and drain bodies 110A, 110B have a width W that is less than half the distance D1 across the trench 115. 1A (or width W 1A and W 1B ). The transistor structure 101 is separated from the adjacent transistor structure 101 by the trench isolation portion 140 on both sides. The trench isolation portion 140 divides the two trenches 115 into two equal parts. The trench isolation portion 140 has a width W within a distance D1 of the trench 115. 1A (or width W 1A and W 1B ) between the thickness W2. Thickness W2 and width W 1A 、W 1B The sum of is equal to the distance D1. Figure 3 In the embodiment, the width W 1A Equal to width W 1B , and the distance D1 is equal to the thickness W2 and twice the width W 1A (or twice the width W 1B In some embodiments, as in Figure 3 In the example shown, one of the source and drain bodies 110A, 110B is coupled to the via structure 133 and the interconnect network 131, and the other of the source and drain bodies 110A, 110B is coupled to the via structure 134 and the interconnect network 132. In other embodiments, both the source and drain bodies 110A, 110B are coupled to a single network 131 or 132, for example, through via structures 133 or 134 at different depths along the y-axis. The gate electrode 122 can be coupled to either or both of the interconnect networks 131, 132.

[0069] The source and drain bodies 110 may include an interfacial layer 314 on the face 117 and the trench isolation 140. The layer 314 may extend along the entirety of the face 117, for example, along the entirety of the height H1 of the bodies 110A, 110B. The layer 314 may have a very low resistivity and a very high conductivity, for example, due to the metal content and alloying with the bulk material of the body 110, such as silicon. The layer 314 may provide a low resistance path from the bottom of the body 110 (e.g., from the via structure 134 or the lowermost nanoribbon region 120) to the top of the body 110 (e.g., at the via structure 133 or the uppermost nanoribbon region 120).

[0070] In some embodiments, layer 314 includes one or more metals. For example, a material body 110 of silicon (including a body 110 of silicon germanium) may have a metal alloyed with silicon in an interface layer 314 at a surface 117 of the body 110. In some embodiments, the body 110 includes an interface layer 314 having titanium and silicon. In some embodiments, the body 110 includes a layer 314 having one of cobalt, nickel, ruthenium, platinum, or tungsten and silicon. Other metals may also be deployed. Layer 314 may include the same or different metal(s) as layer 113. Deploying different metals may provide flexibility, such as having a first metal for minimizing resistivity in a thin contact layer 113 and a second metal for maximizing conductivity in a thicker layer 314 along the surface 117 and in contact with the isolation portion 140.

[0071] The source or drain body 110A, 110B includes an interfacial layer 113 in contact with the metallization structure 130. In some embodiments, the body 110A, 110B includes a similar interfacial layer 113 on a side 128 opposite the side 127, for example, in contact with the via structure 134. The layers 113 on both sides 127, 128 can be coupled by an interfacial layer 314 at the face 117 of the body 110.

[0072] Figure 4 is a flow chart of a method 400 for forming a dielectric isolation portion between and through a bisected source or drain body, in accordance with some embodiments. The method 400 includes operations 410-460. Figure 4 Some of the operations shown are optional. Additional operations may be included. Figure 4 An example order is shown, but the operations may be performed in other orders and some operations may be omitted. Some operations may also be performed multiple times before performing other operations. For example, multiple structures may be bisected before forming a dielectric layer or plug between the rest of the structure(s). Some operations may be included within other operations such that Figure 4 The number of operations shown is not a limitation of method 400 .

[0073] Figure 5A 、 Figure 5B 、 Figure 5C 、 Figure 5D 、 Figure 5E 、 Figure 5F and Figure 5G Cross-sectional views of an IC device 100 at various stages of fabrication are shown, in accordance with some embodiments, having a dielectric isolation 140 between source or drain bodies 110A, 110B and through trench 115 . Figures 5A-5G Shown in practice Figure 4 Possible examples of intermediate structures during an embodiment of method 400 .

[0074] Back to Figure 4 The method 400 begins at operation 410 of receiving a substrate. The substrate may be substantially as previously described (e.g., at least Figure 1A The substrate 199 is located at the substrate. For example, the substrate can include any suitable material or materials in any suitable structure, such as a wafer, a die, etc. The substrate can include semiconductor materials, including single crystal silicon or silicon germanium, etc., from which transistors can be formed and on which they are formed. The substrate can also include metals, dielectrics, dopants, and other materials commonly found in IC substrates.

[0075] In many embodiments, the substrate includes multiple channel regions, such as nanoribbons in adjacent stacks. The channel regions can be in other structures, such as fins. In some embodiments, the multiple channel regions are adjacent and coaxial (e.g., collinear or aligned on a common axis). For example, a stack of multiple fins or nanoribbons can be aligned on the same linear or (e.g., vertical) planar axis. In some embodiments, the channel regions can be formed on the substrate, for example, by etching fins from the substrate or etching fins into the substrate, and the substrate can include alternating layers of semiconductor material.

[0076] In some embodiments, the substrate includes a source or drain body between multiple channel regions, and a channel region between the source or drain bodies. The source or drain body can be a body or structure of semiconductor material between and coupled to the channel regions. For example, multiple channel regions can be aligned on the same axis, with a cut or etch forming a groove through the channel region and the axis, and the body or structure of semiconductor material (i.e., the source or drain body) can be in the groove, spanning the distance or gap between the aligned channel regions. The semiconductor material of the source or drain body between the channel regions can be any suitable material. In many embodiments, the semiconductor material is silicon. In many embodiments, the semiconductor material is silicon germanium. In some embodiments, the semiconductor material is silicon for some source and drain bodies (e.g., for n-type transistors) and silicon germanium for other source and drain bodies (e.g., for p-type transistors). Other semiconductor materials can be used.

[0077] Figure 5A A substrate 199 is shown with a source or drain body 110 between and coupled to channel regions 120, for example after performing a receiving operation 410, in accordance with some embodiments. The trench 115 has a width of a distance D1 between the channel regions 120, and the body 110 spans the distance D1. Figure 5AIn the example of FIG. 1 , the gate electrode 122 is over the channel region 120 , and the insulating layer 126 is over the electrode 122 . The dielectric filler 530 is within the dielectric liner 536 , together forming a sacrificial dielectric structure over the body 110 .

[0078] Back to Figure 4 , method 400 proceeds to depositing a mask layer at operation 420. The mask layer can be deposited or patterned over the received substrate and provide, for example, openings over each semiconductor structure for subsequent etching of the semiconductor structure. The mask can have any suitable material(s) and can be deposited by any suitable method. In many embodiments, the mask layer can include nitrogen and / or carbon, for example, to provide etch selectivity between the mask and a dielectric (e.g., oxide) present over the source and drain semiconductor structures. In some embodiments, the mask layer is deposited and patterned using a photolithographic process.

[0079] Figure 5B A mask layer 550 is shown over substrate 199 and an opening 555 in and through layer 550 and over source or drain body 110, for example, after performing deposition operation 420, in accordance with some embodiments. Layer 550 covers most features of substrate 199. Opening 555 is centered over source or drain body 110, with dielectric fill 530 and layer 536 between mask layer 550 and body 110 of semiconductor material.

[0080] Back to Figure 4 , method 400 proceeds to the bisecting semiconductor structure at operation 430. The semiconductor structure can be bisected by any suitable method. In many embodiments, the semiconductor structure is bisected by etching through an opening in a deposited mask layer (e.g., between a first sidewall and a second sidewall of the deposited mask layer). The bisecting can remove a fragment of semiconductor material between the two retained portions of the split semiconductor structure. The bisecting (e.g., etching) can form an opening between the two retained portions in place of the removed fragment. The opening can stop on or enter the dielectric material below the bisected source and drain semiconductor structures, or the opening can enter the crystalline (e.g., semiconductor) material of the substrate below the bisected source and drain semiconductor structures. Each retained portion of the semiconductor structure can be coupled to one or more channel regions on both sides of the opening. In some embodiments, the two retained portions are each coupled to a stack of nanoribbon channel regions.

[0081] Figure 5CAn opening 555 is shown between the bisected portions of bodies 110A, 110B coupled to channel region 120, e.g., after performing bisecting operation 430, in accordance with some embodiments. Opening 555 passes through trench 115 (including dielectric fill 530 and dielectric layer 536 above bodies 110A, 110B and dielectric spacer 194 at the bottom of trench 115) and into the semiconductor material of substrate 199.

[0082] Back to Figure 4 Method 400 then proceeds to forming a dielectric layer or plug at operation 440. The dielectric layer or plug may be adjacent to and between a pair of retained portions of the semiconductor structure. The dielectric layer or plug may be formed by any suitable method and may comprise any suitable material(s). In many embodiments, the dielectric layer or plug is formed by depositing a layer of dielectric material adjacent to and between a first and a second retained portion of the semiconductor structure. For example, the dielectric layer may be deposited in an opening between, on, and above the pair of retained semiconductor portions. In many embodiments, a first dielectric layer is deposited on the first retained portion, and a second dielectric layer is deposited on the second retained portion. In some such embodiments, the first and second dielectric layers are a single, continuous layer formed on the sidewalls of the opening and connected at the bottom of the opening. In some such embodiments, the dielectric layer or plug includes or comprises a gap or opening between the first and second dielectric layers.

[0083] A dielectric material may be deposited in and over the opening. In some embodiments, the dielectric material is conformally deposited, for example, on the sidewalls of the opening, for example, by chemical vapor deposition (CVD), such as atomic layer deposition (ALD). The deposited dielectric material is advantageously a low-K dielectric, which (e.g., including voids) can improve electrical isolation between the remaining semiconductor bodies (e.g., and reduce parasitic coupling). The deposited dielectric material advantageously has an etch selectivity relative to adjacent dielectrics, for example, to enable subsequent selective processing. In some embodiments, excess deposited dielectric material is removed, for example, by chemical mechanical planarization or polishing (CMP).

[0084] Figure 5D Isolation 140 is shown through trench 115 and between semiconductor bodies 110A, 110B, for example after performing forming operation 440, in accordance with some embodiments. Trench isolation 140 includes a gap 144 between bodies 110A, 110B. Dielectric material 540, having filled the opening of isolation 140, is above substrate 199 and mask layer 550.

[0085] Figure 5E Isolation 140 is shown between semiconductor bodies 110A, 110B, for example after a CMP operation, and with exposed and planarized top layer 126. The dielectric material of the isolation is absent from top layer 126.

[0086] Back to Figure 4 Method 400 proceeds to forming or metalizing an interfacial layer at operation 450. The interfacial layer can serve as a highly conductive layer for low-resistance contact to one or more source or drain semiconductor bodies. The layer can form an interface between the semiconductor material and a (e.g., metallic) contact structure subsequently formed on the one or more source or drain semiconductor bodies. For example, after selectively removing any dielectric and / or sacrificial material on the one or more source or drain semiconductor bodies, the interfacial layer can be formed by any suitable method and can have any suitable (one or more) materials. The interfacial layer can include a semiconductor material and one or more metals. In many embodiments, a thin layer of one or more metals is deposited on the semiconductor body, and the (one or more) metals and semiconductor react (e.g., due to annealing) to form an alloy or compound of the semiconductor and the (one or more) metals. In some such embodiments, the semiconductor is etched or otherwise exposed before depositing the (one or more) metals. In many embodiments, the interfacial layer includes silicon (e.g., from the semiconductor body) and one or more of titanium, cobalt, nickel, ruthenium, platinum, or tungsten. An interfacial layer having both semiconductor and metal (e.g.,) can be characterized as being part of the semiconductor body.

[0087] Method 400 optionally continues with forming a metallization structure over one or more semiconductor structures at operation 460. In many embodiments, a metallization structure is formed over one or more of the remaining semiconductor portions. The metallization structure may be formed by any suitable method and with any suitable material, for example, Figure 1AThe methods and materials described for the metallization structure 130 at operation 450 are those described for the metallization structure 130 at operation 450. In many embodiments, the metallization structure includes one or more metal layers deposited over the retained semiconductor portion. In some such embodiments, at least one liner (e.g., conformal) layer is first deposited over the semiconductor body, and a fill layer is deposited over the liner(s). In many embodiments, the metallization structure is coupled to the semiconductor body (e.g., the retained semiconductor portion) via an interface layer (formed or metallized at operation 450). The deposited liner layer can be alloyed or otherwise bonded to or interface with an upper surface of the semiconductor body, such as a highly conductive contact or interface layer of the semiconductor body, a highly conductive contact or interface layer on the semiconductor body, or a highly conductive contact or interface layer over the semiconductor body. A dielectric layer can be formed over the metallization structure, and a via structure can be formed over the metallization structure through the dielectric layer, and the via structure contacts the metallization structure.

[0088] In some embodiments, one or more metallization structures are optionally formed on one or more semiconductor structures, but on opposite sides of the metallization structures formed at operation 460. In some such embodiments, the substrate is ground and / or polished on its backside, a dielectric layer is formed over the backside, and via structures are formed through the dielectric layer on the backside of the one or more semiconductor structures, and the via structures contact the backside of the one or more semiconductor structures. In this manner, metallization structures can be formed on both sides (above and below) of the channel region and semiconductor body in the device layer between the formed metallization structures (and the transistor structures can be coupled to the interconnect network).

[0089] Figure 5F The metallization structure 130 coupled through the interface layer 113 on the semiconductor body 100 is shown, for example, after performing metallization or forming operation 450 and forming operation 460, in accordance with some embodiments. The metallization structure 130 includes a metal liner 136 on the interface layer 113. The semiconductor body 110 includes the interface layer 113. The dielectric filler 530 and the dielectric layer 536 are not present on the bodies 110A, 110B.

[0090] Figure 5G Metallization structures 130 , 134 are shown coupled to front and backside networks 131 , 132 at via structures 133 , 134 on the front and backside of the semiconductor body 110 , eg, after performing the forming operation 460 , in accordance with some embodiments.

[0091] Figure 6A 、 Figure 6B 、 Figure 6C and Figure 6DCross-sectional views of an IC device 100 at various stages of fabrication are shown, in accordance with some embodiments, having self-aligned trench isolations 140 between source or drain bodies 110 in the same trench 115 . Figures 6A-6D An example structure is shown after or during an optional example operation for bisecting the source or drain body 110 using a conformally deposited mask layer 662 over the semiconductor body 110. In some embodiments, as in Figures 6A-6D In the example of FIG. 1 , the isolation portion 140 may be formed before the gate electrode is formed on the channel region 120 .

[0092] exist Figure 6A In the received substrate shown (e.g., after receiving operation 410), the channel regions 120 have not yet been released, and sacrificial material 620 is between regions 120. Sacrificial dummy gate material 622 is above regions 120. Mask layer 626 is above dummy gate material 622. An etch stop layer 661 is conformally above substrate 199, including on the source or drain semiconductor bodies 110 and on the sidewalls of spacers 123. Layer 661 can be deposited by any suitable method, such as conformally depositing layer 661 by ALD or other CVD. Etch stop layer 661 can provide, for example, etch selectivity between a subsequently deposited mask layer 662 and one or both of spacers 123 and layer 626.

[0093] Figure 6B A mask layer 662 is shown conformally over the etch stop layer 661, for example, after performing deposition operation 420. To bisect the semiconductor structure body 110 into a first portion and a second portion, the mask layer 662 can be conformally deposited at operation 420 of method 400. The mask layer 662 can be conformally deposited to a desired thickness and corresponding width of the opening 555 between the sidewalls 663 of the layer 662. The layer 662 can be deposited by any suitable method, for example, by conformally depositing the layer 662 by CVD. The layer 662 is advantageously deposited by an operation such as ALD that allows for very precise control of the thickness of the layer 662 (and the width of the opening 555 between the sidewalls 663 of the layer 662).

[0094] Figure 6C An opening 555 is shown between the sidewalls 663, for example, after performing the bisection operation 430, and the remaining source or drain semiconductor bodies 110A, 110B coupled to the channel regions 120 on either side of the trench 115. As part of the bisection operation 430, the opening 555 can be etched between the sidewalls 663 of the conformally deposited mask layer 662 and through the source or drain semiconductor body 110. Excess material of the layers 661, 662 is not present, for example, above the spacers 123 and the layer 626. Excess material of the layers 661, 662 can be removed, for example, by planarization or polishing.

[0095] Figure 6D The trench isolation portion(s) 140 of the deposited dielectric material 540 is shown between the remaining source or drain semiconductor bodies 110A, 110B and between the layers 662, for example after performing the forming operation 440. Gate electrodes, etc. may be formed concurrently with other subsequent operations, as previously described (e.g., Figure 4 、 Figures 5D-5G Almost.

[0096] Figure 7A 、 Figure 7B 、 Figure 7C and Figure 7D Cross-sectional views of the IC device 100 at various stages of fabrication are shown, in accordance with some embodiments, having a highly conductive interface layer 314 on the semiconductor bodies 110A, 110B and contacting the trench isolations 140 . Figures 7A-7D An example structure is shown after or during an optional example operation for forming a conductive layer 314 on sidewalls or faces 117 of the source or drain semiconductor bodies 110A, 110B. Figure 7A An opening 555 is shown between the bisected partial bodies 110A, 110B coupled to the channel region 120, for example after performing the bisecting operation 430, in accordance with some embodiments, similar to FIG. Figure 5C . Opening 555 extends substantially through trench 115 (including sacrificial fill 530 and layer 536 above bodies 110A, 110B) above the semiconductor material of substrate 199, and to or into dielectric spacer 194 at the bottom of trench 115. No trench isolation 140 separates bodies 110A, 110B, and sidewalls or faces 117 of bodies 110A, 110B are exposed.

[0097] Figure 7B Conductive layer 314 is shown on sidewalls or faces 117 of source or drain semiconductor bodies 110A, 110B, for example, after performing metallization or forming operation 450 (but prior to forming trench isolations, for example, at operation 440), in accordance with some embodiments. Masking layer 550 is not present over substrate 199. Dielectric filler 530 and dielectric layer 536 are present over body 110 (including bodies 110A, 110B). Once trench isolations are formed, layer 314 will be over or between semiconductor bodies 110A, 110B and the trench isolations. Trench isolations may be formed over layer 314.

[0098] The semiconductor bodies 110A, 110B include an interfacial layer 314. After bisecting the semiconductor structure or body 110 (spanning the distance D1 between the channel regions 120) into the remaining bodies 110A, 110B, for example, by etching an opening 555 between the bodies 110A, 110B, the layer 314 may be formed by performing a metallization or forming operation 450. Etching the opening 555 between the bodies 110A, 110B may expose the semiconductor material of the bodies 110A, 110B. The (e.g., metallization) layer 314 may be formed by depositing one or more metals in the opening 555 on the sidewalls or faces 117 of the semiconductor bodies 110A, 110B. The deposited metal(s) may be one or more of titanium, cobalt, nickel, ruthenium, platinum, tungsten, or any other suitable metal. The metal(s) and the semiconductor material of the bodies 110A, 110B may react (e.g., due to annealing) to form an alloy or compound of the semiconductor and the metal(s). In many embodiments, layer 314 includes silicon (eg, in a semiconductor body 110 of silicon or silicon germanium).Interface layer 314 can be characterized as being part of semiconductor body 110A or 110B, for example, both semiconductor and metal.

[0099] Layer 314 can have very high electrical conductivity. Layer 314 can provide a low resistance path from the bottom of body 110A or 110B (e.g., from the lowermost nanoribbon region 120 or a subsequently formed metallization structure) to the top of body 110 (e.g., at the uppermost nanoribbon region 120 or a subsequently formed metallization structure).

[0100] Figure 7C The isolation portion 140 is shown passing through the trench 115 and between the semiconductor bodies 110A, 110B, for example after performing the forming operation 440, according to some embodiments. The trench isolation portion 140 includes a gap 144 between the bodies 110A, 110B. The dielectric material 540 of the isolation portion 140, which has filled the opening, is above the substrate 199. As shown at operation 450 and Figure 7B , there is no mask layer 550. Trench isolations 140 may be formed at operation 440 by depositing one or more layers of dielectric material 540 for isolation 140 on layer 314, adjacent to and between the bodies 110A, 110B. Layer 314 is on or between the respective bodies 110A, 110B and trench isolations 140.

[0101] Figure 7DMetallization structure 130 is shown on semiconductor body 110 (including bodies 110A, 110B) coupled via interface layer 113, for example, after performing metallization or forming operation 450 and forming operation 460, in accordance with some embodiments. Metallization structure 130 includes metal liner 136 on interface layer 113. Semiconductor body 110 includes interface layer 113. Layer 113 can include the semiconductor material of the body and the same or different metal(s) of layer 314. Dielectric filler 530 and dielectric layer 536 are not present on body 110. Subsequent operations such as forming other metallization structures (including via structures), back grinding, etc. can be performed.

[0102] Figure 8 A schematic diagram of an example data server 806 employing IC devices having trench isolations between retained portions of a bisected body of source and drain material is shown in accordance with some embodiments. Server 806 can be any commercial server, including, for example, any number of high-performance computing platforms housed in a rack and networked together for electronic data processing, and in an exemplary embodiment includes one or more devices 850 having trench isolations between retained portions of a bisected body of source and drain material.

[0103] Also as shown, server 806 includes a battery and / or power supply 815 to provide power to device 850 and, in some embodiments, provide power delivery functionality such as power conditioning. Device 850 can be deployed as part of a package-level integrated system 810. Integrated system 810 is further shown in expanded diagram 820. In an exemplary embodiment, device 850 (labeled "Memory / Processor") includes at least one memory chip (e.g., random access memory (RAM)) and / or at least one processor chip (e.g., a microprocessor, a multi-core microprocessor, or a graphics processor, etc.) having the features discussed herein. In an embodiment, device 850 is a microprocessor that includes static RAM (SRAM) cache memory. As shown, device 850 can be an IC device as discussed herein having a trench isolation portion between retained portions of a bisected source and drain material body. The device 850 may also be coupled (e.g., communicatively coupled) to a board, interposer, or substrate (e.g., host component 299) along with one or more of a power management IC (PMIC) 830, an RF (wireless) IC (RFIC) 825 including a broadband RF (wireless) transmitter and / or receiver (TX / RX) (e.g., including a digital baseband and analog front-end module, and also including a power amplifier on the transmit path and a low-noise amplifier on the receive path), and their controller 835. In some embodiments, the RFIC 825, the PMIC 830, the controller 835, and the device 850 include trench isolations between retained portions of the bisected source and drain material bodies.

[0104] Figure 9 is a block diagram of an example computing device 900 according to some embodiments. For example, one or more components of computing device 900 may include any of the devices or structures discussed herein. Figure 9 Many components are shown as included in computing device 900, but any one or more of these components may be omitted or duplicated as appropriate for the application. In some embodiments, some or all of the components included in computing device 900 may be attached to one or more printed circuit boards (e.g., motherboards). In some embodiments, individual components of these components may be fabricated onto a single system-on-chip (SoC) die. Additionally, in various embodiments, computing device 900 may not include a processor. Figure 9900 , but may include interface circuitry for coupling to one or more of the components shown in FIG. 901 . For example, computing device 900 may not include display device 903, but may include display device interface circuitry (e.g., connector and driver circuitry) to which display device 903 may be coupled. In another set of examples, computing device 900 may not include audio output device 904, other output device 905, global positioning system (GPS) device 909, audio input device 910, or other input device 911, but may include audio output device interface circuitry, other output device interface circuitry, GPS device interface circuitry, audio input device interface circuitry, or other input device interface circuitry to which audio output device 904, other output device 905, GPS device 909, audio input device 910, or other input device 911 may be coupled.

[0105] The computing device 900 may include a processing device 901 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" refers to a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that can be stored in registers and / or memory. The processing device 901 may include a memory 921, a communication device 922, a cooling device 923, a battery / power conditioning device 924, a logic unit 925, an interconnect 926 (i.e., optionally including a redistribution layer (RDL) or a metal-insulator-metal (MIM) device), a thermal conditioning device 927, and a hardware security device 928.

[0106] The processing device 901 may include one or more digital signal processors (DSPs), application-specific ICs (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (dedicated processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing devices.

[0107] Computing device 900 may include memory 902, which may itself include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard disk. In some embodiments, memory 902 includes memory that shares a die with processing device 901. Such memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0108] Computing device 900 may include thermal conditioning / refrigeration device 906. Thermal conditioning / refrigeration device 906 may maintain processing device 901 (and / or other components of computing device 900) at a predetermined low temperature during operation.

[0109] In some embodiments, computing device 900 may include a communication chip 907 (e.g., one or more communication chips). For example, communication chip 907 may be configured to manage wireless communications for data transmitted to and from computing device 900. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, and the like that can communicate data over a non-solid medium using modulated electromagnetic radiation. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not.

[0110] The communication chip 907 can implement any of several wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 revision), Long Term Evolution (LTE) project together with any revisions, updates and / or adaptations thereof (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). IEEE 802.16-compliant broadband wireless access (BWA) networks are generally referred to as WiMAX networks. WiMAX is an acronym for Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed compliance and interoperability testing of the IEEE 802.16 standard. The communication chip 907 can operate according to Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA) or LTE networks. The communication chip 907 can operate according to Enhanced Data Rates for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 907 can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), their derivatives, and any other wireless protocols designated as 3G, 4G, 5G and higher. In other embodiments, the communication chip 907 can operate according to other wireless protocols. The computing device 900 may include an antenna 913 to facilitate wireless communications and / or receive other wireless communications (such as AM or FM radio transmissions).

[0111] In some embodiments, the communication chip 907 can manage wired communications, such as electrical, optical, or any other appropriate communication protocol (e.g., Ethernet). As described above, the communication chip 907 can include multiple communication chips. For example, the first communication chip 907 can be dedicated to shorter-range wireless communications, such as Wi-Fi or Bluetooth, and the second communication chip 907 can be dedicated to longer-range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, the first communication chip 907 can be dedicated to wireless communications, and the second communication chip 907 can be dedicated to wired communications.

[0112] Computing device 900 may include battery / power circuitry 908. Battery / power circuitry 908 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of computing device 900 to an energy source separate from computing device 900 (e.g., AC line power).

[0113] Computing device 900 may include a display device 903 (or corresponding interface circuitry, as discussed above). Display device 903 may include any visual indicator, such as a heads-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat-panel display.

[0114] Computing device 900 may include an audio output device 904 (or corresponding interface circuitry, as discussed above). Audio output device 904 may include any device that generates an audible indication, such as a speaker, headphones, or earbuds.

[0115] The computing device 900 may include an audio input device 910 (or corresponding interface circuitry, as discussed above). The audio input device 910 may include any device that generates a signal representing sound, such as a microphone, a microphone array, or a digital instrument (e.g., an instrument with a Musical Instrument Digital Interface (MIDI) output).

[0116] Computing device 900 may include a GPS device 909 (or corresponding interface circuitry, as discussed above). GPS device 909 may communicate with a satellite-based system and may receive the location of computing device 900, as is known in the art.

[0117] Computing device 900 may include other output devices 905 (or corresponding interface circuitry, as discussed above). Examples of other output devices 905 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or additional storage.

[0118] The computing device 900 may include other input devices 911 (or corresponding interface circuitry, as discussed above). Examples of other input devices 911 may include an accelerometer, a gyroscope, a compass, an image acquisition device, a keyboard, a cursor control device such as a mouse, a stylus, or a trackpad, a barcode reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0119] Computing device 900 may include a security interface device 912. Security interface device 912 may include any device that provides security measures for computing device 900, such as intrusion detection, biometric authentication, security encoding or decoding, access list management, malware detection, or spyware detection.

[0120] The computing device 900, or a subset of its components, may have any suitable form factor, such as a portable or mobile computing device (e.g., a cellular phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a netbook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device.

[0121] The subject matter of the present description is not necessarily limited to the specific applications shown in Figures 1 - 9. As will be appreciated by those skilled in the art, the subject matter may be applied to other deposition applications, as well as any suitable manufacturing application.

[0122] The following examples pertain to other embodiments, and details in the examples may be used anywhere in one or more embodiments.

[0123] In one or more first embodiments, a device includes: a first stack of transistor channel regions, separated by a first distance from a second stack of transistor channel regions and a third stack of adjacent transistor channel regions; a first source or drain material body, spanning the first distance between the first stack of transistor channel regions and the second stack, wherein the first source or drain material body is coupled to both the first stack of transistor channel regions and the second stack; a pair of second source or drain material bodies within the first distance between the first stack of transistor channel regions and the third stack, wherein a first of the pair of second source or drain material bodies is coupled to the first stack of transistor channel regions and a second of the pair of second source or drain material bodies is coupled to the third stack of transistor channel regions; and a dielectric material within the first distance and between the pair of second source or drain material bodies.

[0124] In one or more second embodiments, further with respect to the first embodiment, it also includes a first metallization structure in contact with the first source or drain material body, a second metallization structure in contact with the first of a pair of second source or drain material bodies, and a third metallization structure in contact with the second of a pair of second source or drain material bodies, wherein the first metallization structure and the third metallization structure are on a first side of the stack body of the transistor channel region, and the second metallization structure is on a second side of the stack body of the transistor channel region opposite to the first side.

[0125] In one or more third embodiments, further to the first or second embodiment, a second of a pair of second source or drain material bodies includes a first interfacial layer in contact with the third metallization structure and including silicon and the first metal, and a second interfacial layer in contact with the dielectric material and including silicon and the first metal or the second metal.

[0126] In one or more fourth embodiments, further with respect to the first to third embodiments, the first stack and the third stack of the transistor channel region, the dielectric material and the first and second of a pair of second source or drain material bodies are continuous, the dielectric material contacts the first and second of the pair of second source or drain material bodies and separates the first and second of the pair of second source or drain material bodies, and the dielectric material extends between the first and second of the pair of second source or drain material bodies by at least the height of the pair of second source or drain material bodies.

[0127] In one or more fifth embodiments, further with respect to the first to fourth embodiments, the void is between the first layer and the second layer of dielectric material, the first layer is between the void and the first of a pair of second source or drain material bodies, and the second layer is between the void and the second of a pair of second source or drain material bodies.

[0128] In one or more sixth embodiments, further with respect to the first to fifth embodiments, a first of a pair of second source or drain material bodies includes a first width, a second of a pair of second source or drain material bodies includes a second width, the dielectric material includes a thickness within the first distance and between the pair of second source or drain material bodies, and a sum of the thickness and the first width and the second width is approximately equal to the first distance.

[0129] In one or more seventh embodiments, further with respect to the first to sixth embodiments, the first dielectric plug includes the dielectric material and the thickness, a pair of second source or drain material bodies is a first pair of second source or drain material bodies, and further includes: a second pair of second source or drain material bodies, wherein a first of the second pair of second source or drain material bodies is coupled to the first source or drain material body through a second stack in the transistor channel region, and the first of the second pair of second source or drain material bodies is between the second stack in the transistor channel region and the second dielectric plug; a fourth stack in the transistor channel region, a third source or drain material body, and a third pair of second source or drain material bodies, wherein the fourth stack in the transistor channel region is coupled to the third source or drain material body and the third pair of second source or drain material bodies a first of a third source or drain material body and between a third source or drain material body and a first of a third pair of second source or drain material bodies, the first of the third pair of second source or drain material bodies being between a fourth stack in the transistor channel region and a third dielectric plug, and the third source or drain material body being coupled to the first source or drain material body; and a fifth stack in the transistor channel region and a fourth pair of second source or drain material bodies, wherein the fifth stack in the transistor channel region is coupled to the third source or drain material body and the first of a fourth pair of second source or drain material bodies, and between the third source or drain material body and the first of a fourth pair of second source or drain material bodies, the first of the fourth pair of second source or drain material bodies being between the fifth stack in the transistor channel region and the fourth dielectric plug.

[0130] In one or more eighth embodiments, further with respect to the first to seventh embodiments, the first of the second pair of second source or drain material bodies, the first of the third pair of second source or drain material bodies, and the first of the fourth pair of second source or drain material bodies include a first width, the second dielectric plug, the third dielectric plug, and the fourth dielectric plug include the thickness, and the third source or drain material body spans a first distance between the fourth stack and the fifth stack in the transistor channel region.

[0131] In one or more ninth embodiments, further with respect to the first to eighth embodiments, the dielectric plug includes a dielectric material within a first distance and between a pair of second source or drain material bodies, a first of the pair of second source or drain material bodies is symmetrical with a second of the pair of second source or drain material bodies, and the first and second of the pair of second source or drain material bodies are symmetrical about a vertical centerline of the dielectric plug.

[0132] In one or more tenth embodiments, further with respect to the first to ninth embodiments, a first and a second of a pair of second source or drain material bodies include a first side on the dielectric plug, a first and a second of a pair of second source or drain material bodies include a second side opposite the dielectric plug, a pair of second source or drain material bodies are between the second sides, and the second sides have a first height that is higher than a second height of the first sides.

[0133] In one or more eleventh embodiments, further with respect to the first to tenth embodiments, a first source or drain material body is in a first trench, the first trench comprises a first width equal to the first distance, a pair of second source or drain material bodies are in the second trench, and a dielectric material is between the pair of second source or drain material bodies, the second trench comprises a second width equal to the first distance, and a first stack of transistor channel regions contacts the first source or drain material body and a first of the pair of second source or drain material bodies.

[0134] In one or more twelfth embodiments, a device includes: a trench between adjacent first and second transistor channel regions, wherein the trench includes a first width and the first transistor channel region is separated from the second transistor channel region by the first width; a first source or drain material body in the trench, wherein the first source or drain material body is coupled to the first transistor channel region and the first source or drain material body includes a second width; a second source or drain material body in the trench, wherein the second source or drain material body is coupled to the second transistor channel region and the second source or drain material body includes a second width; and a dielectric isolation portion in the trench and between the first source or drain material body and the second source or drain material body, wherein the dielectric isolation portion includes a third width and the first width is approximately equal to the sum of the third width and twice the second width.

[0135] In one or more thirteenth embodiments, further directed to the twelfth embodiment, the first source or drain material body includes a layer in contact with the dielectric isolation, the layer including silicon and metal.

[0136] In one or more fourteenth embodiments, further with respect to the twelfth or thirteenth embodiments, the dielectric isolation portion includes a first layer and a second layer of dielectric material, the dielectric isolation portion includes a gap between the first layer and the second layer of dielectric material, the first layer is between the gap and the first source or drain material body, and the second layer is between the gap and the second source or drain material body.

[0137] In one or more fifteenth embodiments, further with respect to the twelfth to fourteenth embodiments, the trench is a first trench, the first source or drain material body is coupled to the third source or drain material body through the first transistor channel region, the first source or drain material body and the third source or drain material body are in contact with the first transistor channel region, the third source or drain material body is in a second trench between the first transistor channel region and the third transistor channel region, and the third source or drain material body includes a first width.

[0138] In one or more sixteenth embodiments, a method includes: dividing a semiconductor structure into a first portion and a second portion, wherein the first portion is coupled to a first channel region and the second portion is coupled to a second channel region; and forming a dielectric layer adjacent to the first portion and the second portion and between the first portion and the second portion.

[0139] In one or more seventeenth embodiments, further directed to the sixteenth embodiment, further comprising conformally depositing a mask layer over the semiconductor structure, wherein bisecting the semiconductor structure into the first portion and the second portion comprises etching between a first sidewall and a second sidewall of the conformally deposited mask layer.

[0140] In one or more eighteenth embodiments, further directed to the sixteenth or seventeenth embodiments, further comprising metallizing an interface layer on or between the first portion and the dielectric layer, wherein dividing the semiconductor structure into the first portion and the second portion comprises etching an opening between the first portion and the second portion, metallizing the interface layer on or between the first portion and the dielectric layer comprises depositing metal in the opening, the interface layer comprises silicon and metal, and forming the dielectric layer adjacent to the first portion and the second portion and between the first portion and the second portion comprises depositing a dielectric material on the interface layer.

[0141] In one or more nineteenth embodiments, further with respect to the sixteenth to eighteenth embodiments, it also includes: forming a first metallization structure in contact with a first portion of the semiconductor structure, the first metallization structure being on a first side of the first channel region and the second channel region; and forming a second metallization structure in contact with a second portion of the semiconductor structure, the second metallization structure being on a second side of the first channel region and the second channel region opposite to the first side.

[0142] In one or more twentieth embodiments, further with respect to the sixteenth to nineteenth embodiments, forming a dielectric layer adjacent to and between the first and second parts includes: depositing a dielectric material on the first part and between the first and second parts; depositing a dielectric material on the second part and between the first and second parts, and the dielectric material is between the gap and the first part and between the gap and the second part.

[0143] The present disclosure may be practiced through modification and variation, and the scope of the appended claims is not limited to the embodiments described herein. For example, the embodiments described above may include a specific combination of features. However, the embodiments described above are not limited in this regard, and in various implementations, the embodiments described above may include only a subset of such features, a different order of such features, a different combination of such features, and / or additional features other than those explicitly listed. Therefore, the scope of the patent right should be determined by reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

1. A device comprising: a first stack of transistor channel regions, the first stack of transistor channel regions being separated from an adjacent second stack of transistor channel regions and an adjacent third stack of transistor channel regions by a first distance; a first body of source or drain material spanning the first distance between the first stack of the transistor channel region and the second stack of the transistor channel region, wherein the first body of source or drain material is coupled to both the first stack of the transistor channel region and the second stack of the transistor channel region; a pair of second bodies of source or drain material within the first distance between the first stack of the transistor channel region and the third stack of the transistor channel region, wherein a first of the pair of second bodies of source or drain material is coupled to the first stack of the transistor channel region and a second of the pair of second bodies of source or drain material is coupled to the third stack of the transistor channel region; and A dielectric material is within the first distance and between the pair of second source or drain material bodies.

2. The apparatus according to claim 1, further comprising: a first metallization structure, the first metallization structure being in contact with the first source or drain material body; a second metallization structure in contact with the first of the pair of second source or drain material bodies; as well as a third metallization structure, wherein the third metallization structure contacts the second of the pair of second source or drain material bodies, wherein the first metallization structure and the third metallization structure are on a first side of the first stack of the transistor channel region, the second stack of the transistor channel region, and the third stack of the transistor channel region, and the second metallization structure is on a second side of the first stack of the transistor channel region, the second stack of the transistor channel region, and the third stack of the transistor channel region opposite to the first side.

3. The apparatus according to claim 1, further comprising: a first metallization structure, the first metallization structure being in contact with the first source or drain material body; a second metallization structure in contact with the first of the pair of second source or drain material bodies; as well as a third metallization structure in contact with the second of the pair of second source or drain material bodies, wherein the second of the pair of second source or drain material bodies comprises: a first interface layer contacting the third metallization structure and comprising silicon and a first metal; and A second interface layer contacts the dielectric material and includes silicon and the first metal or the second metal.

4. The apparatus according to claim 1, wherein: The first stack of transistor channel regions and the third stack of transistor channel regions, the dielectric material, and the first and second of the pair of second source or drain electrode material bodies are continuous; the dielectric material being in contact with and separating the first and second members of the pair of second source or drain material bodies; and The dielectric material extends between the first and second of the pair of second source or drain material bodies to at least a height of the pair of second source or drain material bodies.

5. The apparatus according to any one of claims 1 to 4, wherein: a void between the first and second layers of dielectric material; the first layer being between the gap and the first of the pair of second source or drain material bodies; and The second layer is between the gap and the second one of the pair of second source or drain material bodies.

6. The apparatus according to any one of claims 1 to 4, wherein: the first of the pair of second source or drain material bodies comprising a first width; the second of the pair of second source or drain material bodies comprising a second width; the dielectric material includes a thickness within the first distance and between the pair of second source or drain material bodies; and The thickness, the first width, and the second width together are substantially equal to the first distance.

7. The apparatus according to claim 6, wherein The first dielectric plug comprises the dielectric material and the thickness, the pair of second source or drain material bodies are a first pair of second source or drain material bodies, and the apparatus further comprises: a second pair of bodies of second source or drain material, wherein a first one of the second pair of bodies of second source or drain material is coupled to the first body of source or drain material through a second stack in the transistor channel region, and the first one of the second pair of bodies of second source or drain material is between the second stack in the transistor channel region and a second dielectric plug; a fourth stack in a transistor channel region, a third body of source or drain material, and a third pair of bodies of second source or drain material, wherein the fourth stack in the transistor channel region is coupled to the third body of source or drain material and a first one of the third pair of bodies of second source or drain material, and between the third body of source or drain material and the first one of the third pair of bodies of second source or drain material, the first one of the third pair of bodies of second source or drain material is between the fourth stack in the transistor channel region and a third dielectric plug, and the third body of source or drain material is coupled to the first body of source or drain material; and a fifth stack of a transistor channel region and a fourth pair of second source or drain material bodies, wherein the fifth stack of the transistor channel region is coupled to the third source or drain material body and the first of the fourth pair of second source or drain material bodies, and between the third source or drain material body and the first of the fourth pair of second source or drain material bodies, and between the fifth stack of the transistor channel region and a fourth dielectric plug.

8. The apparatus according to claim 7, wherein: the first of the second pair of bodies of second source or drain material, the first of the third pair of bodies of second source or drain material, and the first of the fourth pair of bodies of second source or drain material comprise the first width; the second dielectric plug, the third dielectric plug, and the fourth dielectric plug comprise the thickness; and The third body of source or drain material spans the first distance between a fourth stack of the transistor channel region and a fifth stack of the transistor channel region.

9. The apparatus according to any one of claims 1 to 4, wherein: a dielectric plug comprising said dielectric material within said first distance and between said pair of second source or drain material bodies; The first of the pair of second source or drain material bodies is symmetrical to the second of the pair of second source or drain material bodies; and The first and second of the pair of second source or drain material bodies are symmetrical about a vertical centerline of the dielectric plug.

10. The apparatus according to claim 9, wherein: The first and second of the pair of second source or drain material bodies include a first face on the dielectric plug; the first and second of the pair of second source or drain material bodies include a second face opposite the dielectric plug, the pair of second source or drain material bodies being between the second faces; and The second face has a first height greater than a second height of the first face.

11. The apparatus according to any one of claims 1 to 4, wherein: the first source or drain material body being in a first trench, the first trench comprising a first width equal to the first distance; The pair of second source or drain material bodies are in a second trench with the dielectric material between the pair of second source or drain material bodies, the second trench comprising a second width equal to the first distance; and The first stack of the transistor channel region is in contact with the first body of source or drain material and the first of the pair of second bodies of source or drain material.

12. A device comprising: a trench between adjacent first and second transistor channel regions, wherein the trench comprises a first width and the first and second transistor channel regions are separated by the first width; a first body of source or drain material in the trench, wherein the first body of source or drain material is coupled to the first transistor channel region and comprises a second width; a second body of source or drain material in the trench, wherein the second body of source or drain material is coupled to the second transistor channel region and comprises the second width; and A dielectric isolation portion, the dielectric isolation portion being in the trench and between the first source or drain material body and the second source or drain material body, wherein the dielectric isolation portion includes a third width, and the first width is approximately equal to the sum of the third width and twice the second width.

13. The apparatus according to claim 12, wherein The first body of source or drain material includes a layer in contact with the dielectric isolation, the layer including silicon and metal.

14. The apparatus according to claim 12 or 13, wherein: The dielectric isolation portion includes a first layer and a second layer of dielectric material; the dielectric isolation portion comprising a gap between the first layer and the second layer of the dielectric material; The first layer is between the gap and the first source or drain material body; and The second layer is between the gap and the second source or drain material body.

15. The apparatus according to claim 12 or 13, wherein: The groove is a first groove; the first body of source or drain material being coupled to a third body of source or drain material through the first transistor channel region; The first source or drain material body and the third source or drain material body are in contact with the first transistor channel region; The third source or drain material body is in the second trench between the first transistor channel region and the third transistor channel region; and The third body of source or drain material includes the first width.

16. A method comprising: bisecting the semiconductor structure into a first portion and a second portion, wherein the first portion is coupled to the first channel region and the second portion is coupled to the second channel region; and A dielectric layer is formed adjacent to and between the first portion and the second portion.

17. The method of claim 16, further comprising conformally depositing a mask layer over the semiconductor structure, wherein Bisecting the semiconductor structure into the first portion and the second portion includes etching between first and second sidewalls of the conformally deposited mask layer.

18. The method according to claim 16 or 17, further comprising: metallizing an interface layer on or between the first portion and the dielectric layer, wherein: bisecting the semiconductor structure into the first portion and the second portion includes etching an opening between the first portion and the second portion; Metallizing the interface layer on or between the first portion and the dielectric layer includes depositing metal in the opening; The interface layer includes silicon and the metal; and Forming the dielectric layer adjacent to and between the first portion and the second portion includes depositing a dielectric material on the interface layer.

19. The method according to claim 16 or 17, further comprising: forming a first metallization structure in contact with the first portion of the semiconductor structure, the first metallization structure being on a first side of the first channel region and the second channel region; as well as A second metallization structure is formed in contact with the second portion of the semiconductor structure, the second metallization structure being on a second side of the first and second channel regions opposite the first side.

20. The method according to claim 16 or 17, wherein Forming the dielectric layer adjacent to and between the first portion and the second portion includes: depositing a dielectric material on the first portion and between the first portion and the second portion; depositing the dielectric material on the second portion between the first portion and the second portion; and The dielectric material is between the void and the first portion and between the void and the second portion.

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