Semiconductor structure and method of manufacturing the same, image sensor

Abstract

The application provides a semiconductor structure and a preparation method thereof and an image sensor. The semiconductor structure comprises: a substrate; a well region formed in the substrate; a shallow trench isolation structure used for defining a pixel unit in the well region; wherein an N-type doped layer, a first P-type doped layer and a second P-type doped layer are further arranged between the shallow trench isolation structure and the well region to form a surrounding for the sidewall and the bottom of the shallow trench isolation structure; the N-type doped layer is located between the shallow trench isolation structure and the first P-type doped layer, the first P-type doped layer is located between the N-type doped layer and the second P-type doped layer, and the second P-type doped layer is located between the first P-type doped layer and the well region; wherein the doping concentration of the second P-type doped layer is greater than the doping concentration of the first P-type doped layer and greater than the doping concentration of the well region. In this way, the dark current can be reduced while the influence on the main function of the pixel unit is reduced.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of image sensor, and particularly relate to a semiconductor structure, a preparation method thereof and an image sensor. BACKGROUND

[0002] At present, CMOS image sensors have the advantages of low power consumption, small size, high integration, etc., and are widely used in mobile phone cameras, automotive imaging, industrial video monitoring, etc.

[0003] In the CMOS image sensor, in order to reduce the crosstalk between different pixel units, a shallow trench isolation (STI) structure is usually added between adjacent pixel units.

[0004] However, the STI process introduces a large area of SiO2 / Si interface, and the mismatch between the SiO2 lattice and the Si lattice at the SiO2 / Si interface will generate lattice defects and dangling bonds, resulting in a significant increase in the generation and recombination level of electrons and holes at the SiO2 / Si interface. When the image sensor is working, movable electrons are easily generated and collected by the pixel unit to form dark current, resulting in imaging problems such as white spots and noise. SUMMARY

[0005] Therefore, the embodiments of the present application aim to provide a semiconductor structure, a preparation method thereof and an image sensor, which can improve the dark current problem caused by SiO2 / Si interface defects to a certain extent.

[0006] One embodiment of the present application provides a semiconductor structure, comprising: a substrate; a well region formed in the substrate; a shallow trench isolation structure for defining a pixel unit in the well region; wherein an N-type doped layer, a first P-type doped layer and a second P-type doped layer are further arranged between the shallow trench isolation structure and the well region to form a surrounding for the sidewall and the bottom of the shallow trench isolation structure; the N-type doped layer is located between the shallow trench isolation structure and the first P-type doped layer, the first P-type doped layer is located between the N-type doped layer and the second P-type doped layer, and the second P-type doped layer is located between the first P-type doped layer and the well region; wherein the doping concentration of the second P-type doped layer is greater than the doping concentration of the first P-type doped layer, and greater than the doping concentration of the well region.

[0007] Optionally, the doping concentration of the N-type doped layer is greater than the doping concentration of the first P-type doped layer.

[0008] Optionally, in the same direction, the width of the second P-type doped layer is smaller than the width of the first P-type doped layer and the N-type doped layer.

[0009] Optionally, the N-type doped layer, the first P-type doped layer, and the second P-type doped layer have a width ratio in the same direction of 2:2:1.

[0010] Optionally, the N-type doped layer is connected to a higher potential than the first P-type doped layer to form a reverse-biased PN junction between the N-type doped layer and the first P-type doped layer; the breakdown voltage of the reverse-biased PN junction is greater than half of the supply voltage of the pixel unit; and the potential to which the N-type doped layer is connected is lower than the breakdown voltage.

[0011] Optionally, the second P-type doped layer is configured to reduce the width of a depletion region of the reverse-biased PN junction near the pixel unit, so that the depletion region of the reverse-biased PN junction is away from a depletion region of a photodiode in the pixel unit.

[0012] Another embodiment of the present application provides a method for manufacturing a semiconductor structure, the method comprising: providing a substrate; forming a shallow trench on a surface of the substrate; performing ion implantation twice using P-type ions to form a first P-type doped layer and a second P-type doped layer surrounding a sidewall and a bottom of the shallow trench; the second P-type doped layer has a higher doping concentration than the first P-type doped layer; the first P-type doped layer has a portion of the substrate between the first P-type doped layer and the sidewall and the bottom of the shallow trench that is not implanted with ions; performing N-type ion implantation on the portion of the substrate to form an N-type doped layer; filling an isolation material in the shallow trench to form a shallow trench isolation structure; forming a well region in the substrate; the well region has a lower doping concentration than the second P-type doped layer; the shallow trench isolation structure defines a pixel region in the well region; and manufacturing a pixel unit in the pixel region.

[0013] Optionally, the method further comprises: performing a thermal oxidation process on the sidewall and the bottom of the shallow trench to form a silicon dioxide layer as a shielding oxide layer for ion implantation.

[0014] Optionally, the step of implanting N-type ions in the portion of the substrate to form the N-type doped layer comprises: removing the shielding oxide layer; performing ion implantation using germanium ions to form an amorphous layer on the sidewall and the bottom of the shallow trench; performing N-type ion implantation and activating the implanted N-type ions by thermal annealing to convert the amorphous layer into a crystal structure to form the N-type doped layer.

[0015] Yet another embodiment of the present application provides an image sensor comprising the semiconductor structure as described above.

[0016] The various embodiments provided in this application have an unexpected effect: by sequentially surrounding the shallow trench isolation structure and the well region with an N-type doped layer, a first P-type doped layer, and a second P-type doped layer, a reverse-biased PN junction can be formed using the N-type doped layer and the surrounding first P-type doped layer. This creates an additional electric field around the STI, attracting mobile electrons generated by SiO2 / Si interface defects, reducing their diffusion, and thus improving dark current. Furthermore, by adding a heavily doped second P-type doped layer between the first P-type doped layer and the well region, the depletion region corresponding to the aforementioned reverse-biased PN junction can be kept away from the depletion region of the photodiode in the pixel unit, preventing the main function of the pixel unit from being affected due to contact between the two. Attached Figure Description

[0017] Figure 1 This is a top view schematic diagram of the unit structure of a CMOS image sensor in related technologies.

[0018] Figure 2 This is a cross-sectional schematic diagram of the unit structure of a CMOS image sensor in related technologies.

[0019] Figure 3 This is a top view of a semiconductor structure provided for one embodiment of this application.

[0020] Figure 4 This is a cross-sectional schematic diagram of a semiconductor structure provided for one embodiment of this application.

[0021] Figure 5 This is a top view of a semiconductor structure provided for another embodiment of this application.

[0022] Figure 6 This is a cross-sectional schematic diagram of a semiconductor structure provided for another embodiment of this application.

[0023] Figure 7 for Figure 6 A magnified view of the area corresponding to the dashed box in the middle.

[0024] Figure 8 This is a schematic diagram of a method for fabricating a semiconductor structure according to another embodiment of this application.

[0025] Figure 9 and Figure 10 This is a schematic diagram of a substrate provided in yet another embodiment of this application.

[0026] Figure 11 This is a schematic diagram of the formation of a shielding oxide layer in another embodiment of this application.

[0027] Figure 12 This is a schematic diagram of the formation of a first P-type doped layer and a second P-type doped layer in another embodiment of this application.

[0028] Figure 13 A schematic diagram of forming an amorphous layer in another embodiment of the present application.

[0029] Figure 14 A schematic diagram of forming an N-type doped layer in another embodiment of the present application.

[0030] Figure 15 and Figure 16 A schematic diagram of forming a shallow trench isolation structure in another embodiment of the present application.

[0031] Figure 17 A schematic diagram of forming a well region in another embodiment of the present application.

[0032] Legend of reference signs:

[0033] 300, semiconductor structure; 301, substrate; 3011, well region; 3012, photodiode region; 3013, P-type heavily doped region; 3014, floating diffusion region; 302, shallow trench isolation structure; 303, pixel unit; 304, N-type doped layer; 305, first P-type doped layer; 306, second P-type doped layer; 307, transfer gate; 401, shallow trench; 402, partial substrate; 310, pixel region; 404, shielding oxide layer; 405, amorphous layer; 406, pad oxide layer; 407, silicon nitride layer. DETAILED DESCRIPTION

[0034] The technical solutions in the embodiments of the present application will be clearly and completely described in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all of the embodiments of the present application.

[0035] In the present application, the drawings are not necessarily drawn to scale, and local features can be enlarged or reduced to more clearly show the details of the local features.

[0036] Unless otherwise defined, all technical and scientific terms used in the present application have the same meanings as commonly understood by one of ordinary skill in the art to which this application belongs. The terms used in the present application are only for the purpose of describing specific embodiments, and are not intended to limit the scope of the present application. The term "and / or" used in the present application includes any and all combinations of one or more of the listed items. The singular forms "a", "an" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0037] In the description of the present application, it needs to be understood that the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can be explicitly or implicitly included one or more of the features. In the description of the embodiments of the present application, the meaning of "multiple" is two or more, unless otherwise explicitly and specifically limited.

[0038] In the description of the present application, the orientation or positional relationship indicated by the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "height", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" and the like are based on the orientation or positional relationship shown in the drawings, which is only for the convenience of the simplified description of the present application, and does not indicate that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, that is, cannot be understood as a limitation of the present application.

[0039] In the description of the present application, unless otherwise explicitly limited, the terms "mounting", "connecting", "connecting", "fixing", "setting" and the like should be broadly understood. For example, "connecting" can be fixed connection, or detachable connection, or integral; can be mechanical connection, or electrical connection; can be directly connected, or indirectly connected through intermediate medium, or the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0040] Please refer to Figure 1 and Figure 2 . The CMOS image sensor can include a plurality of pixel units. One pixel unit 100 can include the basic structure of a photodiode 101 (PD), a transfer gate 102 (TG), and a floating diffusion 103 (FD).

[0041] Among them, the photodiode 101 as the core component is used to capture light and convert it into an electrical signal. Specifically, the photodiode 101 works based on the photoelectric effect of the PN junction. When a photon hits the semiconductor material near the PN junction, it will be absorbed and excite electron transition, thereby generating electron-hole pairs. If these carriers are located in the depletion region or diffuse into the depletion region, the built-in electric field will separate them and produce a current flow.

[0042] The transfer gate 102 is used to control the process of charge transfer from the photodiode 101 to the floating diffusion 103. Specifically, by applying a proper voltage to it, the transfer gate 102 can be turned on or off, thereby allowing the accumulated charge in the photodiode 101 to be transferred to the floating diffusion 103.

[0043] The floating diffusion 103 is a small doped region used to receive the charge transferred from the photodiode 101 through the transfer gate 102. The voltage of the floating diffusion 103 varies with the amount of charge received and is detected by an amplifier in the sensor to be quantized as a digital signal for processing.

[0044] The photodiode 101 is usually formed by embedding an N-type doped layer in a P-type doped region. In some cases, a P-type heavily doped region 104 can also be provided on the N-type doped layer to form a pinned photodiode (PPD). The pinned photodiode is a device capable of converting light energy into electrical energy, with high quantum efficiency, low dark current characteristics, and compatibility with CMOS processes.

[0045] In a CMOS image sensor, a shallow trench isolation structure 106 embedded in the substrate 105 is also provided between adjacent pixel units to achieve electrical isolation between PPDs. The shallow trench isolation structure 106 is usually made of silicon dioxide, and the SiO2 / Si interface between the shallow trench isolation structure 106 and the substrate 105 will generate lattice defects and dangling bonds due to lattice mismatch, resulting in increased generation / recombination levels of electrons and holes at the SiO2 / Si interface, which can easily generate mobile electrons and trigger dark current.

[0046] In the related art, to improve the dark current problem, a high-quality passivation film is usually added on the SiO2 / Si interface, or high-concentration P-type ion implantation is performed around it to raise the barrier height of electron transition and inhibit the diffusion of mobile electrons to the photodiode, but the effect is limited.

[0047] Therefore, it is necessary to provide a semiconductor structure that can effectively improve the above-mentioned dark current problem.

[0048] Please refer to Figure 3 and Figure 4 . An embodiment of the present application provides a semiconductor structure 200, which can be a unit structure in a CMOS image sensor, comprising a substrate 201 and a shallow trench isolation structure 202, wherein the substrate 201 forms a well region 2011, a photodiode region 2012, a P-type heavily doped region 2013, and a floating diffusion region 2014, and the surface of the substrate 201 is provided with a transfer gate 207 covering the well region 2011, the P-type heavily doped region 2013, and the floating diffusion region 2014.

[0049] In the embodiment, the well region 2011 can be P-type doped. The photodiode region 2012 is used to set a photodiode, and the photodiode region 2012 can have N-type doping and P-type doping therein, and a PN junction can be formed between the two, to serve as a core component of the photodiode. In the embodiment, a depletion region of the photodiode can also be formed in the photodiode region 2012, and the depletion region corresponds to the PN junction.

[0050] In the embodiment, the shallow trench isolation structure 202 can be used to define the pixel unit 203 in the well region 2011. Specifically, the shallow trench isolation structure 202 can serve as a region boundary, and different pixel regions can be divided in the well region 2011, and each pixel region corresponds to a pixel unit. For example, in the embodiment, the part of the well region 2011, the photodiode region 2012, the P-type heavily doped region 2013, the floating diffusion region 2014, and the transfer gate 207 in the pixel region 210 can constitute a pixel unit 203.

[0051] In the embodiment, a doped structure can be formed between the shallow trench isolation structure 202 and the well region 2011, and the doped structure surrounds the sidewall and the bottom of the shallow trench isolation structure 202. Specifically, the doped structure can include an N-type doped layer 204 covering the shallow trench isolation structure 202, and a first P-type doped layer 205 covering the periphery of the N-type doped layer 204 and located between the N-type doped layer 204 and the well region 2011.

[0052] In the embodiment, the N-type doped layer 204 can be connected to a high potential, and an additional electric field can be formed around the SiO2 / Si interface. When the recombination of the electron-hole pair occurs at the SiO2 / Si interface, the movable electrons generated thereby can be attracted by the high potential, so as to avoid the diffusion of the movable electrons into the well region 2011 and the pixel unit 203, and to reduce the generation of dark current.

[0053] In the embodiment, a reverse-biased PN junction can be formed between the N-type doped layer 204 and the first P-type doped layer 205 surrounding the N-type doped layer 204. Under the reverse bias condition, the internal electric field of the depletion region of the reverse-biased PN junction can increase the potential barrier, and the majority carriers can be pushed away from the depletion region, so as to prevent the majority carriers from easily crossing the PN junction, and thus to further reduce the diffusion of the movable electrons.

[0054] However, the skilled person further finds that although the surrounding N-type doped layer 204 and the first P-type doped layer 205 are arranged on the sidewall and the bottom of the shallow trench isolation structure 202, the diffusion of movable electrons can be prevented and the dark current can be reduced, but due to the corresponding formed depletion region between the introduced N-type doped layer 204 and the first P-type doped layer 205, and the reverse bias condition makes the depletion region wider, at this time the depletion region located on the side close to the pixel unit 203 (the side of the P-type region) is easy to contact with the depletion region corresponding to the PN junction of the photodiode, resulting in an impact on the main function of the pixel unit 203.

[0055] Please refer to Figures 5-7 To solve the above problems, the skilled person improves the semiconductor structure 200 provided in the above embodiment. Another embodiment of the present application provides a semiconductor structure 300.

[0056] In the present embodiment, the semiconductor structure 300 is different from the semiconductor structure 200 in the above embodiment in that a second P-type doped layer 306 is additionally arranged in the doped structure surrounding the sidewall and the bottom of the shallow trench isolation structure 302, and the doping concentration of the second P-type doped layer 306 is greater than the doping concentration of the first P-type doped layer 305 and the doping concentration of the well region 3011.

[0057] In the present embodiment, the N-type doped layer 304, the first P-type doped layer 305 and the second P-type doped layer 306 arranged in the doped structure are arranged in sequence from the shallow trench isolation structure 302 to the well region 3011. Specifically, the N-type doped layer 304 is located between the shallow trench isolation structure 302 and the first P-type doped layer 305, the first P-type doped layer 305 is located between the N-type doped layer 304 and the second P-type doped layer 306, and the second P-type doped layer 306 is located between the first P-type doped layer 305 and the well region 3011.

[0058] In the present embodiment, the second P-type doped layer 306 is used to reduce the width of the depletion region corresponding to the reverse-biased PN junction on the side close to the pixel unit 303 or the pixel region 310, so as to make the depletion region corresponding to the reverse-biased PN junction away from the depletion region of the photodiode.

[0059] In the embodiment, the unexpected effect is that, by setting the N-type doped layer 304, the first P-type doped layer 305 and the second P-type doped layer 306 in sequence around the shallow trench isolation structure 302 and the well region 3011, the reverse-biased PN junction can be formed by the N-type doped layer 304 and the first P-type doped layer 305 around the N-type doped layer 304, and an additional electric field can be formed around the STI to attract the movable electrons generated by the SiO2 / Si interface defects, so as to reduce the diffusion of the movable electrons and improve the dark current. In addition, by setting the second P-type doped layer 306 between the first P-type doped layer 305 and the well region 3011, the depletion region corresponding to the reverse-biased PN junction can be far away from the depletion region of the photodiode in the pixel unit 303, so as to prevent the main function of the pixel unit 303 from being affected due to the contact between the two.

[0060] Meanwhile, the semiconductor structure 300 provided in the present application does not need to change the original pixel unit structure, only the ion doping concentration around the STI is changed, and no additional material is introduced, so the process cost is low.

[0061] In some embodiments, the doping concentration of the N-type doped layer 304 can be greater than the doping concentration of the first P-type doped layer 305.

[0062] In some cases, if the doping concentration of the N-type doped layer 304 is low, it can be difficult to completely apply the voltage connected to the N-type doped layer 304, which can affect the formation of the reverse-biased state or weaken the built-in electric field strength between the N-type doped layer 304 and the first P-type doped layer 305, so that the attraction effect on the movable electrons is reduced. Therefore, by using the N-type doped layer 304 with a higher doping concentration than the first P-type doped layer 305, the movable electrons can be more effectively attracted, and the diffusion of the movable electrons to the pixel unit 303 can be inhibited.

[0063] In some embodiments, in the same direction, the width of the second P-type doped layer 306 is less than the width of the first P-type doped layer 305 and the N-type doped layer 304.

[0064] In some embodiments, since the second P-type doped layer 306 is arranged between the first P-type doped layer 305 and the well region 3011, it will not only affect the width of the depletion region between the N-type doped layer 304 and the first P-type doped layer 305, but also affect the depletion region of the photodiode on the other side. If the width of the second P-type doped layer 306 is too wide, it can easily cause the width of the depletion region to not meet the requirements of the photodiode for the width of the depletion region. Therefore, by setting the width of the second P-type doped layer 306 to be less than the first P-type doped layer 305 and the N-type doped layer 304, the semiconductor structure 300 can meet the requirements of the photodiode for the width of the depletion region.

[0065] Specifically, in some embodiments, the N-type doped layer 304, the first P-type doped layer 305, and the second P-type doped layer 306 can satisfy the following in the same direction: the N-type doped layer 304 has the widest width, and the second P-type doped layer 306 has the smallest width. In some embodiments, the widths of the three can satisfy the condition that the sum of the widths of the first P-type doped layer 305 and the second P-type doped layer 306 is equal to the width of the N-type doped layer 304.

[0066] Optionally, the width ratio of the N-type doped layer 304, the first P-type doped layer 305, and the second P-type doped layer 306 in the same direction is 2:2:1.

[0067] In some embodiments, the N-type doped layer 304 forms a reverse-biased PN junction with the first P-type doped layer 305 by being connected to a potential higher than that of the first P-type doped layer 305; wherein the breakdown voltage of the reverse-biased PN junction is greater than half of the power supply voltage of the pixel unit 303; and the potential connected to the N-type doped layer 304 is lower than the breakdown voltage.

[0068] In some embodiments, by setting the breakdown voltage of the reverse-biased PN junction to at least half of the supply voltage, reverse breakdown of the PN junction is prevented at extremely low voltages, thus avoiding leakage and improving reliability.

[0069] In some embodiments, the first P-type doped layer 305 and the second P-type doped layer 306 can be grounded. In this case, the potential connected to the N-type doped layer 304 needs to be lower than the reverse breakdown voltage to prevent breakdown and improve reliability.

[0070] Please refer to Figures 8-17 Another embodiment of this application provides a method for fabricating a semiconductor structure, the method comprising the following steps.

[0071] S110: Provides a substrate.

[0072] In this embodiment, as Figure 9 As shown, a shallow trench precursor is formed on a P-type epitaxial layer using the STI trenching process. The P-type epitaxial layer contains a pad oxide layer 406 (Pad OX) and a silicon nitride layer 407.

[0073] Next, SPM solution is used for cleaning to remove polymer residues formed by shallow trench etching, and the morphology of the pad oxide layer 406 and silicon nitride layer 407 is repaired to form a shape as shown. Figure 10 The substrate 301 shown is provided. Shallow trenches 401 are formed on the surface of the substrate 301.

[0074] In some embodiments, such as Figure 11As shown, after forming the substrate 301, a thermal oxidation process can also be performed to form a silicon dioxide on the sidewall and bottom of the shallow trench 401. Specifically, the thickness of the silicon dioxide can range from 80A to 110A. The silicon dioxide formed not only serves as a shielding oxide layer 404 for ion implantation, but also effectively reduces defects on the sidewall and bottom of the shallow trench 401.

[0075] S120: Perform twice ion implantation with P-type ions to form a first P-type doped layer and a second P-type doped layer surrounding the sidewall and bottom of the shallow trench. The doping concentration of the second P-type doped layer is greater than that of the first P-type doped layer.

[0076] In this embodiment, as shown in Figure 12 , a photoresist window is opened at a designated position by a photoetching process, and a second P-type doped layer 306 is formed first, followed by a first P-type doped layer 305 by an ion implantation process. In the first ion implantation process, the ion species can be BF2, the implantation energy is set to 50 keV, and the target implantation dose is 1.0 x 1013ions / cm2. 13 In the second ion implantation process, the ion species can be BF2, the implantation energy is set to 30 keV, and the target implantation dose is 1.0 x 1013ions / cm2. 12

[0077] In this embodiment, as shown in Figure 12 , the first P-type doped layer 305 has a portion of the substrate 402 between the sidewall and bottom of the shallow trench 401 that is not implanted with ions. This portion of the substrate 402 can be used to make an N-type doped layer in a subsequent step.

[0078] S130: Perform N-type ion implantation on the portion of the substrate to form an N-type doped layer.

[0079] In some embodiments, as shown in Figure 13 , the silicon dioxide serving as the shielding oxide layer 404 is removed first, then a photoetching process is performed to open a photoresist window, and a germanium ion implantation is performed to form an amorphous layer 405 on the sidewall and bottom of the shallow trench 401. In the germanium ion implantation process, the implantation energy is set to 10 keV, and the target implantation dose is 1.0 x 1013ions / cm2. 12 The amorphous layer 405 formed can be used to limit the depth of the subsequent N-type ion implantation so that it is distributed as much as possible on the surface of the sidewall and bottom of the shallow trench 401 to serve as an N-type doped layer.

[0080] Next, as shown in Figure 14 ​As shown, N-type ion implantation is performed using an ion implantation process, and the implanted N-type ions are activated by thermal annealing to transform the amorphous layer 405 into a crystalline structure, forming an N-type doped layer 304. Specifically, the implanted ion type can be P, the implantation energy is set to 10 keV, and the target implantation dose is 1.0 × 10⁻⁶. 13 .

[0081] In some embodiments, adding germanium ion implantation before N-type ion implantation can effectively control the implantation and diffusion depth of N-type ions and optimize the performance of the final N-type doped layer 304.

[0082] S140: Fill the shallow trench with isolation material to form a shallow trench isolation structure.

[0083] In this embodiment, as Figure 15 and Figure 16 As shown, the natural oxide layer on the surface of the shallow trench 401 can be removed first, and then an oxide layer can be grown on the sidewall and bottom using the in-situ water vapor method. Finally, the trench can be filled using the HDP process to form a complete shallow trench isolation structure 302.

[0084] S150: A well region is formed in the substrate; the doping concentration of the well region is lower than the doping concentration of the second P-type doped layer; wherein, a shallow trench isolation structure defines a pixel region in the well region.

[0085] In this embodiment, as Figure 17 As shown, a well region 3011 is formed around the shallow trench isolation structure 302 and the N-type doped layer 304, the first P-type doped layer 305, and the second P-type doped layer 306 by continuing the ion implantation process.

[0086] S160: Pixel units are prepared in the pixel area.

[0087] In this embodiment, the pixel unit is fabricated through subsequent processes such as ion implantation and polysilicon processing, taking into account each component and its location region within the pixel unit, and forming a pixel unit as shown in the figure. Figure 6 The semiconductor structure shown.

[0088] The unexpected effect of the embodiment is that, by arranging the N-type doped layer 304, the first P-type doped layer 305 and the second P-type doped layer 306 in sequence around the shallow trench isolation structure 302 and the well region 3011, the N-type doped layer 304 and the first P-type doped layer 305 around the N-type doped layer 304 form a reverse-biased PN junction, an additional electric field is formed around the STI to attract movable electrons generated by the SiO2 / Si interface defects, thereby reducing the diffusion of the movable electrons and improving the dark current. Furthermore, by arranging the heavily doped second P-type doped layer 306 between the first P-type doped layer 305 and the well region 3011, the depletion region corresponding to the reverse-biased PN junction is far away from the depletion region of the photodiode in the pixel unit, thereby preventing the main function of the pixel unit from being affected due to the contact between the two.

[0089] Yet another embodiment of the present application provides an image sensor comprising the semiconductor structure as described in the foregoing embodiments.

[0090] It can be understood that the specific examples herein are only for better understanding of the embodiments of the present application by those skilled in the art, and are not intended to limit the scope of the present application.

[0091] It can be understood that, in various embodiments of the present application, the size of the serial number of each process does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0092] It can be understood that the various embodiments described in the present application can be implemented alone or in combination, and the embodiments of the present application do not limit this.

[0093] Unless otherwise defined, all technical and scientific terms used in the embodiments of the present application have the same meanings as those commonly understood by those skilled in the art of the present application. The terms used in the present application are only for the purpose of describing the specific embodiments and are not intended to limit the scope of the present application. The term "and / or" used in the present application includes any and all combinations of one or more of the listed items. The singular forms "a", "an" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0094] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; a well region is formed in the substrate; A shallow trench isolation structure, wherein the shallow trench isolation structure is used to define pixel units in the well region; The shallow trench isolation structure and the well region are further provided with an N-type doped layer, a first P-type doped layer, and a second P-type doped layer that surround the sidewalls and bottom of the shallow trench isolation structure; the N-type doped layer is located between the shallow trench isolation structure and the first P-type doped layer, the first P-type doped layer is located between the N-type doped layer and the second P-type doped layer, and the second P-type doped layer is located between the first P-type doped layer and the well region; wherein the doping concentration of the second P-type doped layer is greater than the doping concentration of the first P-type doped layer and greater than the doping concentration of the well region.

2. The semiconductor structure according to claim 1, characterized in that, The doping concentration of the N-type doped layer is greater than that of the first P-type doped layer.

3. The semiconductor structure according to claim 2, characterized in that, In the same direction, the width of the second P-type doped layer is smaller than the width of the first P-type doped layer and the N-type doped layer.

4. The semiconductor structure according to claim 3, characterized in that, The width ratio of the N-type doped layer, the first P-type doped layer, and the second P-type doped layer in the same direction is 2:2:

1.

5. The semiconductor structure according to claim 1, characterized in that, The N-type doped layer forms a reverse-biased PN junction with the first P-type doped layer by being connected to a potential higher than that of the first P-type doped layer; wherein the breakdown voltage of the reverse-biased PN junction is greater than half of the power supply voltage of the pixel unit; and the potential connected to the N-type doped layer is lower than the breakdown voltage.

6. The semiconductor structure according to claim 5, characterized in that, The second P-type doped layer is used to reduce the width of the depletion region corresponding to the reverse bias PN junction on the side close to the pixel unit, so that the depletion region corresponding to the reverse bias PN junction is far away from the depletion region of the photodiode in the pixel unit.

7. A method for fabricating a semiconductor structure, characterized in that, The preparation method includes: A substrate is provided; shallow trenches are formed on the surface of the substrate; Two ion implantations using P-type ions are performed to form a first P-type doped layer and a second P-type doped layer surrounding the sidewalls and bottom of the shallow trench; the doping concentration of the second P-type doped layer is greater than that of the first P-type doped layer; wherein, there is a portion of substrate without implanted ions between the first P-type doped layer and the sidewalls and bottom of the shallow trench. N-type ion implantation is performed on the aforementioned portion of the substrate to form an N-type doped layer; The shallow trench is filled with insulating material to form a shallow trench isolation structure; A well region is formed in the substrate; the doping concentration of the well region is lower than the doping concentration of the second P-type doped layer; wherein the shallow trench isolation structure defines a pixel region in the well region; Pixel units are prepared in the pixel region.

8. The preparation method according to claim 7, characterized in that, The preparation method further includes: Silicon dioxide is formed by thermal oxidation on the sidewalls and bottom of the shallow trench to serve as a shielding oxide layer for ion implantation.

9. The preparation method according to claim 8, characterized in that, The step of implanting N-type ions into the partial substrate to form an N-type doped layer includes: Remove the shielding oxide layer; Germanium ions are used for ion implantation to form an amorphous layer on the sidewalls and bottom of the shallow trench; N-type ion implantation is performed, and the implanted N-type ions are activated by thermal annealing to transform the amorphous layer into a crystalline structure, thereby forming the N-type doped layer.

10. An image sensor, characterized in that, Includes the semiconductor structure as described in any one of claims 1 to 6.

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