Method for manufacturing wave infrared focal plane array chip in type Ⅱ superlattice and infrared detector

Abstract

The application provides a type II superlattice mid-wave infrared focal plane array chip manufacturing method and an infrared detector, and belongs to the field of infrared focal plane array chips; solves the problem that the surface leakage current of the infrared focal plane array chip is large due to the deep mesa etching depth in the prior art; the method comprises the following steps: epitaxial material growth and cleaning; hard mask deposition, mesa lithography and etching: the required mesa pattern is obtained on the hard mask through the lithography technology, and then the epitaxial material is etched to form the mesa pattern, the mesa pattern comprises an upper electrode region and a lower electrode region, the upper electrode region is etched to the boundary between the barrier layer and the absorption zone, and the lower electrode region is etched to the lower ohmic contact layer; metal electrode manufacturing; the connection piece is connected with the readout circuit on the metal electrode, and the manufacturing of the infrared focal plane array chip is completed; and the application is applied to the type II superlattice mid-wave infrared detector.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of infrared focal plane array chip, in particular to a method for manufacturing a type-II superlattice mid-wave infrared focal plane array chip and an infrared detector. BACKGROUND

[0002] Due to the characteristics of penetrating smoke, strong anti-interference ability and all-weather working, the infrared detector has been widely used in many fields of national defense and national economy. Type-II superlattice infrared focal plane array chip has attracted more attention because of its wide spectral response range, high detection sensitivity, fast response speed, low noise level and good integrability.

[0003] The type-II superlattice mid-wave infrared focal plane array chip includes an array of interconnected infrared detection units and a readout circuit. The existing method for manufacturing the type-II superlattice mid-wave infrared focal plane array chip is to first prepare an array of infrared detection units, and then interconnect the array with the readout circuit by flip-chip bonding. Specifically, the method is as follows:

[0004] 1. Growth of epitaxial material;

[0005] 2. Cleaning of epitaxial material and deposition of hard mask;

[0006] 3. Mesa lithography and etching. Mesa lithography is to make a mesa pattern to be etched on the silicon oxide, etch the silicon oxide to the required mesa pattern using photoresist as a mask, and remove the residual photoresist by cleaning after removing the photoresist. Mesa etching is to etch the epitaxial material to the required mesa pattern using silicon oxide as a mask. The mesa pattern includes an upper electrode region and a lower electrode region, as shown in Figure 1 .

[0007] 4. Fabricating metal electrodes on the etched epitaxial material, as shown in Figure 2 .

[0008] 5. Fabricating indium pillars on the metal electrodes, connecting the indium pillars with the readout circuit by flip-chip bonding, and completing the fabrication of the infrared focal plane array chip, as shown in Figure 3 .

[0009] In the prior art, the etching depth reaches the boundary between the absorption layer and the lower ohmic contact layer when etching the mesa, and the mesa etching depth is relatively deep. The mesa etching adopts the method of ICP etching (Inductively Coupled Plasma Etching). After ICP etching, the etching material surface will be damaged, and some etching products will remain on the etching surface. These etching damage and etching product residues will form a leakage current channel, resulting in a large surface leakage current. The large surface leakage current will have a harmful effect on the final performance of the infrared focal plane array chip, as shown in Figure 4As shown in the figure, the dotted arrow is the surface leakage current channel of the etching surface, and the solid arrow is the current channel generated by the bias voltage loaded on the infrared focal plane array chip.

[0010] The working principle of the mid-wave infrared focal plane array chip in the type II superlattice is the photovoltaic effect, that is, the infrared signal detected by the infrared focal plane array chip generates a photoelectric current after reaching the absorption region of the epitaxial material. If the surface leakage channel is large, the surface leakage current will be generated from the surface leakage channel by the bias voltage loaded on the infrared focal plane array chip, which will result in the failure of the output of the photovoltaic current, and finally the performance of the infrared focal plane array chip will be deteriorated.

[0011] Therefore, the existing technology has a deep mesa etching depth, which will result in a large mesa surface leakage channel, and further result in a large surface leakage current of the infrared focal plane array chip, which seriously affects the performance of the infrared focal plane array chip. SUMMARY

[0012] In order to solve the above technical problems, the present application provides a type II superlattice mid-wave infrared focal plane array chip manufacturing method and an infrared detector, which can effectively reduce the surface leakage current of the type II superlattice mid-wave infrared focal plane array chip and improve the comprehensive performance of the type II superlattice mid-wave infrared focal plane array chip.

[0013] The technical scheme adopted by the present application is as follows: a type II superlattice mid-wave infrared focal plane array chip manufacturing method, comprising the following steps:

[0014] Step 1: epitaxial material growth and cleaning, wherein the epitaxial material includes a substrate, a buffer layer, a lower ohmic contact layer, an absorption region, a barrier layer and an upper ohmic contact layer from bottom to top;

[0015] Step 2: hard mask deposition, mesa lithography and etching: the required mesa pattern is obtained on the hard mask by lithography technology, and then the epitaxial material is etched to form the mesa pattern, which includes an upper electrode region and a lower electrode region. The upper electrode region is etched to the boundary between the barrier layer and the absorption region, and the lower electrode region is etched to the lower ohmic contact layer;

[0016] Step 3: manufacturing metal electrodes on the epitaxial material etched with the mesa pattern;

[0017] Step 4: manufacturing a connecting piece on the metal electrodes, connecting the metal electrodes with the readout circuit through the connecting piece, and completing the manufacturing of the infrared focal plane array chip.

[0018] Further, the hard mask deposition, mesa lithography and etching of step 2 are performed for the upper electrode and the lower electrode respectively, and specifically include the following steps:

[0019] Step 2.1: deposition of lower electrode hard mask;

[0020] Step 2.2: Lower electrode photoetching, forming photoetching pattern of lower electrode;

[0021] Step 2.3: Lower electrode hard mask etching: etching lower electrode hard mask, transferring photoetching pattern of lower electrode to lower electrode hard mask;

[0022] Step 2.4: Removing photoresist, cleaning and removing photoresist remained on lower electrode hard mask;

[0023] Step 2.5: Lower electrode epitaxial material etching: etching lower electrode region to lower ohmic contact layer;

[0024] Step 2.6: Upper electrode etching hard mask deposition;

[0025] Step 2.7: Upper electrode photoetching, forming photoetching pattern of upper electrode;

[0026] Step 2.8: Upper electrode hard mask etching: etching upper electrode hard mask, transferring photoetching pattern of upper electrode to upper electrode hard mask;

[0027] Step 2.9: Removing photoresist, cleaning and removing photoresist remained on upper electrode hard mask;

[0028] Step 2.10: Upper electrode epitaxial material etching: etching epitaxial material, etching upper electrode region to barrier layer and absorbing region boundary;

[0029] Step 2.11: Passivation film deposition;

[0030] Step 2.12: Passivation hole etching: placing epitaxial material on the bearing table of dry etching equipment, running dry etching program to perform passivation hole etching process.

[0031] Further, the compositions of lower ohmic contact layer, absorbing region and upper ohmic contact layer are all InAs / InAsSb, the composition of barrier layer is AlSb / AlAsSb, and the compositions of substrate and buffer layer are GaSb.

[0032] Further, the lower ohmic contact layer and the upper ohmic contact layer are both N-type ohmic contact layers.

[0033] Further, the lower electrode hard mask and the upper electrode hard mask both use silicon oxide.

[0034] Further, in step 2.3 and step 2.8, dry etching is used to etch lower electrode hard mask and upper electrode hard mask.

[0035] Further, in step 2.5 and step 2.10, silicon oxide is used as a mask to dry etch epitaxial material.

[0036] Further, the manufacturing of the metal electrode in step three includes the manufacturing of the upper and lower metal electrodes: the manufacturing of the upper and lower metal electrodes is completed through the process of photolithography, evaporation, and organic cleaning and stripping.

[0037] Further, the connecting piece in step four adopts indium column, and the manufacturing of the indium column is completed through the process of photolithography, evaporation, and organic cleaning and stripping.

[0038] A type-II superlattice mid-wave infrared detector, comprising an infrared focal plane array chip prepared by using the method for manufacturing a type-II superlattice mid-wave infrared focal plane array chip.

[0039] The method has the following beneficial effects relative to the prior art: when mesa etching is performed by using the method, the etching depth of the upper electrode region reaches the boundary between the barrier layer and the absorption region, and the etching depth of the lower electrode region reaches the lower ohmic contact layer, so that the surface area of the mesa sidewall etching can be reduced, the surface leakage current of the mid-wave infrared focal plane array chip can be reduced, and the performance of the chip can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0040] The application will be further described below with reference to the drawings:

[0041] Figure 1 A structure schematic diagram of mesa pattern formed by etching using the prior art;

[0042] Figure 2 A structure schematic diagram of metal electrode manufactured on the mesa using the prior art;

[0043] Figure 3 A structure schematic diagram of indium column and the interconnection of the indium column and the readout circuit using the prior art;

[0044] Figure 4 An etching surface and leakage current channel structure schematic diagram formed after mesa etching using the prior art;

[0045] Figure 5 A structure schematic diagram of mesa etched using the method proposed in the application;

[0046] Figure 6 An etching surface and leakage current channel structure schematic diagram formed after mesa etching using the method proposed in the application;

[0047] Figure 7 A structure schematic diagram of metal electrode manufactured on the mesa using the method proposed in the application;

[0048] Figure 8 A structure schematic diagram of indium column and the interconnection of the indium column and the readout circuit using the method proposed in the application. DETAILED DESCRIPTION

[0049] As shown in Figures 5 to 8 The application provides a method for manufacturing a middle wave infrared focal plane array chip in a type II superlattice. The main difference from the prior art is that, when mesa etching is performed, the etching depth of the upper electrode region reaches the boundary between the barrier layer and the absorption region, and the etching depth of the lower electrode region reaches the lower ohmic contact layer, as shown in Figure 5 This etching depth structure can reduce the surface area of the mesa sidewall etching under the premise of ensuring the performance of the middle wave infrared focal plane array chip, as shown in Figure 6 and further reduce the surface leakage current of the middle wave infrared focal plane array chip, thereby improving the performance of the chip.

[0050] After the mesa and the lower electrode region are etched, the upper and lower electrodes are manufactured by means of photolithography, electron beam evaporation plating, and metal stripping cleaning, as shown in Figure 7 After the upper and lower electrodes are manufactured, the indium pillars are manufactured by means of photolithography, electron beam evaporation plating, and metal stripping cleaning. After the indium pillars are manufactured, the infrared detection unit array and the readout circuit are interconnected by means of flip-chip interconnection, and finally all the processes for manufacturing the infrared focal plane array chip are completed, thereby obtaining the infrared focal plane array chip as shown in Figure 8 .

[0051] Based on this, the implementation steps of the method for manufacturing the middle wave infrared focal plane array chip in the type II superlattice according to the embodiments of the application are as follows:

[0052] Step one: epitaxial material growth and cleaning, wherein the epitaxial material includes a substrate, a buffer layer, a lower ohmic contact layer, an absorption region, a barrier layer, and an upper ohmic contact layer from bottom to top;

[0053] Step two: hard mask deposition, mesa photolithography, and etching: the required mesa pattern is obtained on the hard mask by means of photolithography, and then the epitaxial material is etched to form the mesa pattern, which includes an upper electrode region and a lower electrode region. The upper electrode region is etched to the boundary between the barrier layer and the absorption region, and the lower electrode region is etched to the lower ohmic contact layer;

[0054] Step three: manufacturing a metal electrode on the epitaxial material after the mesa pattern is etched;

[0055] Step four: manufacturing a connecting piece on the metal electrode, connecting the metal electrode and the readout circuit through the connecting piece, and completing the manufacturing of the infrared focal plane array chip.

[0056] Specifically, the epitaxial material in step one is grown by an MBE (Molecular Beam Epitaxy) device. The epitaxial material includes a GaSb substrate from bottom to top, a GaSb buffer layer, a lower N-type ohmic contact layer, an absorption region, a barrier layer, and an upper N-type ohmic contact layer. The upper and lower N-type ohmic contact layers and the absorption region of the epitaxial material are composed of InAs / InAsSb, and the barrier layer is composed of AlSb / AlAsSb.

[0057] After the epitaxial material is grown in step one, the surface of the epitaxial material is cleaned with organic solvents. The surface of the epitaxial material is sequentially cleaned with acetone, ethanol, and isopropyl alcohol. The cleaning is water bath heating cleaning, and the water bath temperature is 70°C.

[0058] The hard mask deposition, mesa lithography, and etching in step two are performed for the upper electrode and the lower electrode respectively. The specific steps include the following:

[0059] Step 2.1: After cleaning, the lower electrode hard mask is deposited. The lower electrode hard mask is silicon oxide, and the deposition method is PECVD (Plasma-Enhanced Chemical Vapor Deposition). The deposition thickness is 400 nm.

[0060] Step 2.2: Lower electrode lithography. AZ6130 photoresist is used, the photoresist thickness is 3 um, the exposure dose is 60 mJ, and the development time is 30 s, forming a lithography pattern of the lower electrode.

[0061] Step 2.3: Lower electrode hard mask etching. Dry etching is used to etch the lower electrode hard mask, and the lithography pattern of the lower electrode is transferred to the lower electrode hard mask. The etching gas is carbon tetrafluoride and trifluoromethane, and the etching time is 15 min.

[0062] Step 2.4: Remove the photoresist and clean it. The remaining photoresist on the lower electrode hard mask is removed. The cleaning solvent is acetone, the water bath heating temperature is 70°C, and the cleaning time is 30 min.

[0063] Step 2.5: Lower electrode epitaxial material etching. The lower electrode region is etched to the lower ohmic contact layer. Silicon oxide is used as a mask to dry etch the epitaxial material. The ICP etching device is used, the etching gas is chlorine, boron trichloride, and argon, the etching time is 15 min, and the etching depth is 4 um.

[0064] Step 2.6: Upper electrode etching hard mask deposition. The upper electrode hard mask is silicon oxide, and the deposition method is PECVD. The deposition thickness is 200 nm.

[0065] Step 2.7: upper electrode photolithography: AZ6130 photoresist is used, the photoresist thickness is 3um, the exposure dose is 60mJ, the development time is 30s, and the photoresist pattern of the upper electrode is formed.

[0066] Step 2.8: upper electrode hard mask etching: the upper electrode hard mask is etched by using dry etching method, the photoresist pattern of the upper electrode is transferred to the upper electrode hard mask, the etching gas is carbon tetrafluoride and trifluoromethane, and the etching time is 10min.

[0067] Step 2.9: photoresist removal and cleaning, the remaining photoresist on the upper electrode hard mask is cleaned and removed, the cleaning solvent is acetone, the water bath is heated to 70℃, and the cleaning time is 30min.

[0068] Step 2.10: upper electrode epitaxial material etching: the epitaxial material is dry etched with silicon oxide as a mask, the upper electrode region is etched to the boundary between the barrier layer and the absorption zone, the ICP etching device is used, the etching gas is chlorine, boron trichloride and argon, the etching time is 3min, and the etching depth is 600nm. After the upper electrode etching is completed, the structure as shown in Figure 5 is obtained.

[0069] Step 2.11: passivation film deposition: the passivation film is made of silicon oxide, the deposition method is PECVD, and the deposition thickness is 300nm.

[0070] Step 2.12: passivation hole etching: the epitaxial material is placed on the bearing table of the dry etching device, and the dry etching program is run to perform the hole etching process on the passivation film. The dry etching program is as follows: the etching gas is carbon tetrafluoride and trifluoromethane, the bearing table temperature is 20℃, the process chamber pressure is 30mTorr, and the RF power is 135W.

[0071] The fabrication of the metal electrode in step three includes the fabrication of the upper and lower metal electrodes: the upper and lower metal electrodes are fabricated by the processes of photolithography, evaporation and organic cleaning and stripping. After the fabrication of the upper and lower electrodes is completed, the structure as shown in Figure 7 is obtained.

[0072] The connecting piece in step four is made of indium column in this embodiment, and the indium column is fabricated by the processes of photolithography, evaporation and organic cleaning and stripping. Finally, the interconnection of the infrared detection unit array and the readout circuit is completed by flip welding interconnection, and the infrared focal plane array chip as shown in Figure 8 is obtained.

[0073] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for fabricating a Class II superlattice midwave infrared focal plane array chip, comprising: The method comprises the following steps: ​ Step 1: epitaxial material growth and cleaning, wherein the epitaxial material comprises a bottom-up substrate, a buffer layer, a lower ohmic contact layer, an absorption region, a barrier layer and an upper ohmic contact layer; Step 2: hard mask deposition, mesa lithography and etching: the desired mesa pattern is obtained on the hard mask by lithography technology, and then the epitaxial material is etched to form the mesa pattern, which comprises an upper electrode region and a lower electrode region, the upper electrode region is etched to the boundary between the barrier layer and the absorption region, and the lower electrode region is etched to the lower ohmic contact layer; Step 3: metal electrode fabrication on the epitaxial material after the mesa pattern is etched; Step 4: connection piece fabrication on the metal electrode, the metal electrode is connected with the readout circuit through the connection piece, and the infrared focal plane array chip is completed.

2. The method of claim 1, wherein the method is used for fabricating a Type II superlattice midwave infrared focal plane array chip. The hard mask deposition, mesa lithography and etching of step 2 are performed for the upper electrode and the lower electrode respectively, and specifically comprise the following steps: Step 2.1: lower electrode hard mask deposition; Step 2.2: lower electrode lithography, forming a lithography pattern of the lower electrode; Step 2.3: lower electrode hard mask etching: etching the lower electrode hard mask to transfer the lithography pattern of the lower electrode onto the lower electrode hard mask; Step 2.4: cleaning and removing the remaining photoresist on the lower electrode hard mask; Step 2.5: lower electrode epitaxial material etching: etching the lower electrode region to the lower ohmic contact layer; Step 2.6: upper electrode etching hard mask deposition; Step 2.7: upper electrode lithography, forming a lithography pattern of the upper electrode; Step 2.8: upper electrode hard mask etching: etching the upper electrode hard mask to transfer the lithography pattern of the upper electrode onto the upper electrode hard mask; Step 2.9: cleaning and removing the remaining photoresist on the upper electrode hard mask; Step 2.10: upper electrode epitaxial material etching: etching the epitaxial material to etch the upper electrode region to the boundary between the barrier layer and the absorption region; Step 2.11: passivation film deposition; Step 2.12: passivation hole etching: placing the epitaxial material on the bearing table of the dry etching equipment, and running the dry etching program to perform the hole etching process on the passivation film.

3. The method of claim 2, wherein the method is used to fabricate a Type II superlattice mid- wave infrared focal plane array chip. The compositions of the lower ohmic contact layer, the absorption region and the upper ohmic contact layer are all InAs / InAsSb, the composition of the barrier layer is AlSb / AlAsSb, and the compositions of the substrate and the buffer layer are GaSb.

4. The method of claim 3, wherein the method is used for fabricating a Type II superlattice mid- wave infrared focal plane array chip. The lower ohmic contact layer and the upper ohmic contact layer are both N-type ohmic contact layers.

5. The method of claim 2, wherein the method is used for fabricating a Type II superlattice mid- wave infrared focal plane array chip. The lower electrode hard mask and the upper electrode hard mask are both silicon oxide.

6. The method of claim 2, wherein the method is used for fabricating a Type II superlattice mid- wave infrared focal plane array chip. In step 2.3 and step 2.8, the lower electrode hard mask and the upper electrode hard mask are etched by dry etching.

7. The method of claim 2, wherein the method is used for fabricating a Type II superlattice mid- wave infrared focal plane array chip. In step 2.5 and step 2.10, the epitaxial material is dry etched with silicon oxide as a mask.

8. The method of claim 1, wherein the method is used for fabricating a Type II superlattice mid- wave infrared focal plane array chip. In step 3, the fabrication of the metal electrode includes the fabrication of the upper and lower metal electrodes: the fabrication of the upper and lower metal electrodes is completed by the processes of lithography, evaporation and organic cleaning and stripping.

9. The method of claim 1, wherein the method is used for fabricating a Type II superlattice mid- wave infrared focal plane array chip. In step 4, the connection piece is an indium column, and the fabrication of the indium column is completed by the processes of lithography, evaporation and organic cleaning and stripping.

10. A type II superlattice midwave infrared detector, characterized by: The infrared focal plane array chip comprises the infrared focal plane array chip prepared by the method for manufacturing a type II superlattice mid-wave infrared focal plane array chip according to any one of claims 1-9.

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