LED chip with improved heat dissipation and stress relief and manufacturing method thereof

Abstract

The application provides an LED chip for improving heat dissipation and stress release and a preparation method thereof. The LED chip comprises a bonding layer, a heat conducting layer, a barrier layer, a protection layer, a reflection layer and an epitaxial layer arranged on a substrate in sequence. The epitaxial layer comprises a p-type GaN layer, a multi-quantum well layer and an n-type GaN layer arranged in sequence away from the substrate. The barrier layer and the heat conducting layer realize electrical isolation between the protection layer and the bonding layer. The barrier layer realizes phosphoric acid corrosion blocking. The heat conducting layer realizes sidewall passivation and heat conducting effect of the multi-quantum well layer. Stress release is realized through a first stress release groove and a second stress release groove.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to an LED chip for improving heat dissipation and stress release and a preparation method thereof. BACKGROUND

[0002] The existing silicon substrate InGaN-based long-wavelength LED chip is mainly a separate line vertical structure, which has the problems of electrode blocking light on the light-emitting surface, low chip light extraction efficiency, poor current spreading performance under large current density, etc., resulting in obvious limitations of the silicon substrate InGaN long-wavelength vertical structure LED chip in high-power application scenarios. Long-wavelength LEDs have significant application needs in outdoor lighting, projection, display, automotive lighting, etc., such as outdoor street lamps, projectors, automotive headlamps, etc. High-power lighting and display devices, so it is urgent to solve the above problems.

[0003] The vertical via structure has been widely used in sapphire substrate and silicon substrate high-power blue LED chips, and has the advantages of good current spreading performance and high light extraction efficiency, etc. It is the mainstream chip structure of high-power LED devices, but there are many technical problems in the application of the vertical via structure to the silicon substrate InGaN-based long-wavelength LED chip. First, the In content in the InGaN-based long-wavelength LED is high, resulting in large internal stress in the epitaxial film. The silicon substrate LED chip needs to go through wafer bonding and silicon substrate peeling processes during preparation. The P-face structure of the vertical via structure LED chip is more complex, and after peeling off the silicon substrate, the epitaxial layer is often prone to breakage and abnormal electrical properties due to the large internal stress in the epitaxial layer. Second, in order to completely realize the electrical isolation of the n-electrode and the p-electrode and avoid chip short circuit, a relatively thick insulating layer is generally needed to prevent chip short circuit and leakage. The insulating layer is generally made of dielectric layer materials such as SiO2, etc. There is a large difference in thermal expansion coefficient between the InGaN epitaxial layer and the metal, which also causes the chip to have a large stress after peeling off the silicon substrate.

[0004] In addition, unlike the blue LED chip with high electro-optical conversion efficiency, low heat generation and low requirement for chip heat dissipation conditions, due to the "yellow-green gap" effect, the long-wavelength InGaN-based LED chip has low electro-optical conversion efficiency, resulting in large heat generation of the long-wavelength InGaN-based LED chip under a large current density working condition, and the thick insulating medium layer inside the chip further deteriorates the heat dissipation environment of the silicon substrate InGaN-based long-wavelength vertical through-hole structure LED chip, which can cause the LED chip to be more prone to reliability problems. Therefore, compared with the vertical through-hole structure of the high-power blue LED chip, the vertical through-hole structure of the silicon substrate InGaN-based long-wavelength LED chip has higher requirements for the heat dissipation inside the chip. At the same time, the silicon substrate InGaN-based long-wavelength LED chip generally needs to use hot phosphoric acid to etch the GaN epitaxial layer to realize the separation of adjacent epitaxial layers during the preparation process, which requires the material in direct contact with the GaN epitaxial layer at the groove of the adjacent chip to be able to withstand the hot phosphoric acid corrosion to prevent the hot phosphoric acid from etching into the chip, which requires the insulating medium layer of the chip to be able to resist the hot phosphoric acid corrosion. SUMMARY

[0005] Therefore, the purpose of the present application is to provide an LED chip and a preparation method thereof for improving heat dissipation and stress relief, aiming to solve the problems of large internal stress and poor heat dissipation of the silicon substrate vertical through-hole structure InGaN-based long-wavelength LED chip in the prior art.

[0006] According to one embodiment of the LED chip for improving heat dissipation and stress relief, the LED chip is a silicon-based InGaN long-wavelength LED chip, the epitaxial layer growth substrate is a silicon substrate, the main light emission wavelength range is 500-620 nm, and the LED chip comprises a substrate and a bonding layer, a heat-conducting layer, a barrier layer, a protective layer, a reflective layer and an epitaxial layer arranged in sequence on the substrate, wherein the epitaxial layer comprises a p-type GaN layer, a multi-quantum well layer and an n-type GaN layer arranged in sequence away from the substrate, and a passivation layer is arranged on the surface of the epitaxial layer and part of the barrier layer.

[0007] The heat-conducting layer, the barrier layer and the protective layer are in a stepped structure and are wrapped layer by layer, wherein the heat-conducting layer extends towards the n-type GaN layer to form a containing space embedded in the epitaxial layer, and an n-electrode is arranged in the containing space and in contact with the n-type GaN layer.

[0008] A groove formed by the passivation layer and the protective layer is arranged on the side surface of the epitaxial layer, and a p-electrode is arranged in the groove.

[0009] During the preparation process, a first stress relief groove is obtained by etching the epitaxial layer, and a second stress relief groove is formed by etching the heat-conducting layer to relieve stress.

[0010] Preferably, the barrier layer material is SiO2, and the barrier layer thickness is 50-300 nm.

[0011] Preferably, the thermal conductive layer material is one or a combination of SiN, AlN, Al2O3, MgO, and HfO2, and the thermal conductive layer thickness is 300-1500 nm.

[0012] Preferably, the reflective layer material is one or a combination of Ni, Ag, Al, Au, Ti, and Pt, and the reflective layer thickness is 50-400 nm.

[0013] Preferably, the protective layer material is one or a combination of Cr, Pt, Au, Al, Ti, Ni, and TiW, and the protective layer thickness is 200-1200 nm.

[0014] According to one of the embodiments of the present application, a method for preparing an LED chip with improved heat dissipation and stress relief is provided, and the method comprises the following steps:

[0015] In step S1, a silicon substrate is provided, and an AlN buffer layer, a first n-type GaN layer, a first multi-quantum well layer, and a first p-type GaN layer are sequentially grown on the surface of the silicon substrate.

[0016] In step S2, a reflective layer is prepared on the surface of the first p-type GaN layer, and a protective layer is prepared on the surface of the reflective layer.

[0017] In step S3, a portion of the first p-type GaN layer and the first multi-quantum well layer are etched to expose the first n-type GaN layer, thereby forming an n-electrode hole and a first stress relief groove.

[0018] In step S4, a barrier layer is prepared, a portion of the barrier layer is etched, a thermal conductive layer is prepared, a portion of the thermal conductive layer is etched to expose a second n-type GaN layer, thereby forming a second stress relief groove, and an n-electrode is prepared.

[0019] In step S5, a bonding layer is prepared, and the bonding layer is combined with a substrate, the silicon substrate is peeled off, and the AlN buffer layer is exposed.

[0020] In step S6, the AlN buffer layer and the second n-type GaN layer are etched.

[0021] In step S7, a portion of the initial hexagonal pyramid n-GaN, a third n-type GaN layer, a second multi-quantum well light-emitting layer, and a second p-type GaN layer are etched to expose the barrier layer and the protective layer, and a passivation layer is prepared.

[0022] In step S8, a portion of the passivation layer is etched to expose the protective layer, an p-electrode is prepared on the surface of the protective layer, and the preparation of the LED chip is completed.

[0023] Preferably, the step of providing a silicon substrate, growing an AlN buffer layer, a first n-type GaN layer, a first multi-quantum well layer and a first p-type GaN layer on the surface of the silicon substrate in sequence further comprises:

[0024] Preparation of a reflective layer on the surface of the p-type GaN layer;

[0025] Etching of a partial region of the first p-type GaN layer and the first multi-quantum well layer to expose the first n-type GaN layer, forming an n-electrode hole and a third stress release groove;

[0026] Preparation of an n-electrode on the exposed surface of the n-type GaN layer, and preparation of a protective layer on the reflective layer;

[0027] Preparation of a barrier layer, etching of a partial region of the barrier layer, preparation of a heat-conducting layer, etching of a partial region of the heat-conducting layer to expose the second n-type GaN layer, forming a second stress release groove;

[0028] Preparation of a bonding layer and bonding with a substrate, peeling off the silicon substrate to expose the AlN buffer layer;

[0029] Etching of the AlN buffer layer and the second n-type GaN layer;

[0030] Etching of a partial region of the initial hexagonal pyramid n-GaN, the third n-type GaN layer, the second multi-quantum well light-emitting layer and the second p-type GaN layer to expose the barrier layer and the protective layer, and preparation of a passivation layer;

[0031] Etching of a partial region of the passivation layer to expose the protective layer, preparation of a p-electrode on the surface of the protective layer, and completion of the preparation of the LED chip.

[0032] Preferably, the etching in step S3 is dry etching, and the etching depth is 400nm-1500nm.

[0033] Preferably, in step S5, the bonding method of the silicon substrate and the substrate is solid-liquid interdiffusion bonding.

[0034] Preferably, the etching method in steps S6 and S7 is wet etching.

[0035] The LED chip and the preparation method thereof provided in the embodiment of the application can improve heat dissipation and release stress. The bonding layer, the heat-conducting layer, the barrier layer, the protective layer, the reflective layer and the epitaxial layer are sequentially arranged on the substrate. The epitaxial layer comprises the p-type GaN layer, the multi-quantum well layer and the n-type GaN layer arranged in sequence away from the substrate. The barrier layer and the heat-conducting layer achieve electrical isolation between the protective layer and the bonding layer. The barrier layer blocks phosphoric acid corrosion. The heat-conducting layer achieves sidewall passivation and heat-conducting effect of the multi-quantum well layer. The first stress release groove and the second stress release groove release stress. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 Structure diagram of LED chip with improved heat dissipation and stress relief

[0037] Figure 2 Structure diagram of silicon substrate, AlN buffer layer, first n-type GaN layer, first multi-quantum well layer, and first p-type GaN layer

[0038] Figure 3 Structure diagram of first p-type GaN layer with deposited reflective layer

[0039] Figure 4 Structure diagram with protective layer

[0040] Figure 5 Structure diagram with n-electrode hole and first stress relief groove

[0041] Figure 6 Top view of n-electrode hole and first stress relief groove after etching

[0042] Figure 7 Structure diagram with barrier layer

[0043] Figure 8 Structure diagram with heat-conductive layer and second stress relief groove

[0044] Figure 9 Structure diagram with bonding layer

[0045] Figure 10 Structure diagram of silicon substrate completely peeled off

[0046] Figure 11 Structure diagram with initial hexagonal pyramid n-GaN

[0047] Figure 12 Structure diagram with passivation layer

[0048] Figure 13 Top view of single chip

[0049] Figure 14 Structure diagram with reflective layer, n-electrode hole, and third stress relief groove

[0050] Figure 15 Structure diagram of n-electrode prepared in n-electrode hole and protective layer prepared

[0051] Figure 16 Structure diagram with barrier layer, heat-conductive layer, n-electrode, and second stress relief groove

[0052] Explanation of figure component symbols:

[0053] Silicon substrate 1, AlN buffer layer 2, n-type GaN layer 33, multi-quantum well layer 42, p-type GaN layer 52, reflective layer 6, protective layer 7, n-electrode hole 8, first stress relief groove 9, barrier layer 10, heat conducting layer 11, second stress relief groove 12, n-electrode 13, substrate 14, bonding layer 15, hexagonal pyramid n-GaN 161, passivation layer 17, p-electrode 18, chip light emitting surface 19, initial hexagonal pyramid n-GaN 16, second n-type GaN layer 31, second p-type GaN layer 51, second multi-quantum well light emitting layer 41, first n-type GaN layer 3, first multi-quantum well layer 4, first p-type GaN layer 5, third n-type GaN layer 32, third stress relief groove 91. DETAILED DESCRIPTION

[0054] The present application can be embodied in many different forms and is not limited to the embodiments described herein. Rather, the embodiments are provided so that this disclosure will be thorough and complete.

[0055] It is to be understood that where an element is referred to as being "on" another element, it can be directly on the other element or intervening elements can also be present. Where an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements can also be present. As used herein the terms "vertical", "horizontal", "left", "right" and the like are merely used for the purpose of illustration and description.

[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0057] Embodiment one

[0058] Embodiment one of the present application provides an LED chip for improving heat dissipation and stress relief, please refer to Figure 1The structure diagram of the LED chip for improving heat dissipation and stress release, wherein the LED chip for improving heat dissipation and stress release comprises a substrate 14 and a bonding layer 15, a heat conduction layer 11, a barrier layer 10, a protective layer 7, a reflective layer 6 and an epitaxial layer arranged on the substrate 14 in sequence, the epitaxial layer comprises a p-type GaN layer 52, a multi-quantum well layer 42 and an n-type GaN layer 33 arranged in sequence away from the substrate 14, it is to be noted that the substrate is a 4-inch silicon substrate, the substrate 14 is a metal substrate or a metal and semiconductor composite material substrate, in the embodiment of the present application, the substrate 14 is a 4-inch silicon and metal composite material substrate.

[0059] Further, the LED chip is a silicon-based InGaN long-wavelength LED chip, and the main light-emitting wavelength range is 500nm-620nm, in the embodiment of the present application, the prepared silicon substrate InGaN-based vertical through-hole structure LED chip has a size of 1mmx1mm, and the prepared silicon substrate InGaN-based vertical through-hole structure LED chip emits light with a main wavelength of 550nm under a current injection of 350mA.

[0060] Further, the barrier layer 10 material is SiO2, the barrier layer 10 thickness is 50nm-300nm, for example, the barrier layer 10 thickness is 50nm, 100nm, 150nm, 200nm, 250nm or 300nm, but not limited to this; the thermal conductive layer 11 material is one or a combination of SiN, AlN, Al2O3, MgO, HfO2, the thermal conductive layer 11 thickness is 300nm-1500nm, for example, the thermal conductive layer 11 thickness is 300nm, 400nm, 600nm, 800nm, 1000nm, 1200nm or 1500nm, but not limited to this; the reflective layer 6 material is one or a combination of Ni, Ag, Al, Au, Ti, Pt, the reflective layer 6 thickness is 50nm-400nm, for example, the reflective layer 6 thickness is 50nm, 100nm, 150nm, 200nm, 250nm, 300nm or 400nm, but not limited to this, in the embodiment of the present application, the total thickness of NiAgNiAg prepared on the surface of the p-type GaN layer by physical vapor deposition equipment is 200nm as the reflective layer 6, and the reflective layer 6 is annealed in N2 and O2 atmosphere after preparation to obtain better p-type ohmic contact performance; the protective layer 7 material is one or a combination of Cr, Pt, Au, Al, Ti, Ni, TiW, the protective layer 7 thickness is 200nm-1200nm, for example, the protective layer 7 thickness is 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1000nm, 1100nm or 1200nm, but not limited to this, in the embodiment of the present application, the total thickness of CrPt prepared on the surface of the reflective layer 6 by physical vapor deposition equipment is 400nm as the protective layer 7.

[0061] The n-type GaN layer 33 far from the substrate side is hexagonal pyramid, that is, hexagonal pyramid n-GaN 161, the hexagonal pyramid structure is used to improve the total reflection problem of the LED chip light emitting surface, so as to improve the light extraction efficiency of the LED chip, the passivation layer 17 is arranged on the surface of the epitaxial layer and part of the barrier layer 10, it can be understood that due to etching of the epitaxial layer in the preparation process, the upper surface and side surface of the n-type GaN layer 33, the side surface of the multi-quantum well layer 42 and the side surface of the p-type GaN layer 52 are exposed, and the exposed part is covered by depositing the passivation layer 17.

[0062] The heat-conducting layer 11, the barrier layer 10 and the protective layer 7 are in a stepped structure and are wrapped layer by layer, and it can be understood that the heat-conducting layer 11 wraps the barrier layer 10, the barrier layer 10 wraps the protective layer 7, and the protective layer 7 wraps the reflective layer 6, wherein the heat-conducting layer 11 extends towards the n-type GaN layer 33, forms an accommodating space embedded in the epitaxial layer, one side of the accommodating space is the n-type GaN layer 33, and the other side is the bonding layer 15, the n electrode 13 is arranged in the accommodating space, and two ends of the n electrode 13 are in contact with the n-type GaN layer 33 and the bonding layer 15, respectively;

[0063] The side surface of the epitaxial layer is provided with a groove formed by the passivation layer 17 and the protective layer 7, and the p electrode 18 is arranged in the groove, and the bottom of the p electrode 18 is in contact with the protective layer 7.

[0064] It should be noted that the substrate 14 is electrically connected with the bonding layer 15, the n electrode 13, the n-type GaN layer 33; and the p electrode 18 is electrically connected with the protective layer 7, the reflective layer 6 and the p-type GaN layer 52.

[0065] In the preparation process, a first stress relief groove is obtained by etching the epitaxial layer, the first stress relief groove is used for releasing the stress of the epitaxial layer to avoid the problem of cracking of the epitaxial layer when wafer bonding and removing the silicon substrate, and a second stress relief groove is formed by etching the heat-conducting layer 11, the second stress relief groove is used for separating the whole heat-conducting layer into independent dielectric layer blocks of chip size to improve the problems of stress concentration and wafer warping caused by the mismatch of the thermal expansion coefficients of the dielectric layer and the metal in the LED chip. The heat-conducting layer 11 uses an insulating material with high thermal conductivity to realize the sidewall passivation effect of the n electrode hole and improve the heat dissipation of the multi-quantum well.

[0066] Embodiment two

[0067] The embodiment two of the present application provides a preparation method of an LED chip for improving heat dissipation and stress relief, which comprises steps S1 to S8, in particular:

[0068] Step S1, providing a silicon substrate, growing an AlN buffer layer, a first n-type GaN layer, a first multi-quantum well layer and a first p-type GaN layer on the surface of the silicon substrate in sequence.

[0069] Please refer to Figure 2 It is a structural schematic diagram of the silicon substrate, the AlN buffer layer, the first n-type GaN layer, the first multi-quantum well layer and the first p-type GaN layer, in particular, the AlN buffer layer 2, the first n-type GaN layer 3, the first multi-quantum well layer 4 and the first p-type GaN layer 5 are grown on the surface of the silicon substrate 1 in sequence by a metal organic chemical vapor deposition device, the well layer of the first multi-quantum well layer 4 is an InGaN layer, and the barrier layer is a GaN layer.

[0070] Step S2, a reflective layer is prepared on the surface of the first p-type GaN layer, and a protective layer is prepared on the surface of the reflective layer.

[0071] Please refer to Figure 3 A structural schematic diagram for depositing a reflective layer on the surface of the first p-type GaN layer is shown. Specifically, a total thickness of 200 nm of NiAgNiAg is prepared as the reflective layer 6 on the surface of the first p-type GaN layer 5 by a physical vapor deposition device, and after preparation, the reflective layer is annealed in an N2 and O2 atmosphere to obtain better p-type ohmic contact performance.

[0072] Further, please refer to Figure 4 A structural schematic diagram with a protective layer is shown. Specifically, a total thickness of 400 nm of CrPt is prepared as the protective layer 7 on the surface of the reflective layer 6 by a physical vapor deposition device, and the protective layer 7 is in a stepped shape.

[0073] Step S3, etching a partial region of the first p-type GaN layer and the first multi-quantum well layer to expose the first n-type GaN layer, forming an n-electrode hole and a first stress relief groove.

[0074] Please refer to Figure 5 A structural schematic diagram with an n-electrode hole and a first stress relief groove is shown. In this step, the etching is dry etching, and the etching depth is 400 nm to 1500 nm. Specifically, a partial region of the first p-type GaN layer 5 and the first multi-quantum well layer 4 are etched using an inductively coupled plasma device to expose the first n-type GaN layer 3, obtaining a second p-type GaN layer 51, a second multi-quantum well light-emitting layer 41, and a second n-type GaN layer 31, and simultaneously forming an n-electrode hole 8 and a first stress relief groove 9, with an etching depth of 700 nm. Please refer to Figure 6 A top view of the n-electrode hole and the first stress relief groove after etching is shown.

[0075] Step S4, preparing a barrier layer, etching a partial region of the barrier layer, preparing a heat-conducting layer, etching a partial region of the heat-conducting layer to expose the second n-type GaN layer, forming a second stress relief groove, and preparing an n-electrode.

[0076] Please refer to Figure 7 A structural schematic diagram with a barrier layer is shown. Specifically, a thickness of 100 nm of SiO2 is prepared as an initial barrier layer (not shown in the figure) by an atomic layer deposition device for subsequent process blocking phosphoric acid corrosion, and then a partial region of the initial barrier layer is etched by hydrofluoric acid to obtain the barrier layer 10, exposing the n-electrode hole 8.

[0077] Please refer to Figure 8For the structure with the heat conduction layer and the second stress relief groove, specifically, SiN with a thickness of 500 nm is prepared as the initial heat conduction layer (not shown in the figure) by a plasma enhanced chemical vapor deposition device, and the initial heat conduction layer is etched in part of the region by using hydrofluoric acid to obtain the heat conduction layer 11, expose the second n-type GaN layer 31, and form the second stress relief groove 12. Please refer to Figure 9 For the structure with the bonding layer, CrPtAu laminated metal with a total thickness of 1300 nm is deposited as the n-electrode 13 in the n-electrode hole 8 by a physical vapor deposition device.

[0078] Step S5, the bonding layer is prepared and combined with the substrate, the silicon substrate is peeled off, and the AlN buffer layer is exposed.

[0079] As shown in Figure 9 , metal Cu with a thickness of 1000 nm is prepared on the surface by a physical vapor deposition device, metal In with a thickness of 700 nm is prepared on the surface of the substrate 14 by a physical vapor deposition device, and the metal Cu and the metal In are combined by applying temperature and pressure by a wafer bonding device. In the bonding process, In melts into a liquid phase and fills the platform and the groove in the chip under the action of the applied pressure, and a eutectic reaction occurs between In and Cu to form a CuIn alloy as the bonding layer 15. The bonding layer 15 fills the region formed by the heat conduction layer 11 and the n-electrode 13.

[0080] Please refer to Figure 10 For the structure with the silicon substrate completely peeled off, specifically, the silicon substrate 1 is thinned by mechanical grinding, and the remaining silicon substrate 1 is thinned to a thickness of about 100 μm. Then, the remaining silicon substrate 1 is removed by a mixed solution of nitric acid, glacial acetic acid and hydrofluoric acid until the AlN buffer layer 2 is exposed, and the silicon substrate 1 is completely peeled off.

[0081] Step S6, etching the AlN buffer layer and the second n-type GaN layer.

[0082] Please refer to Figure 11 For the structure with the initial hexagonal pyramid n-GaN, the etching in this step is wet etching, and the AlN buffer layer 2 and the second n-type GaN layer 31 are etched by using a potassium hydroxide solution to form the third n-type GaN layer 32 and the initial hexagonal pyramid n-GaN 16.

[0083] Step S7, etching part of the initial hexagonal pyramid n-GaN, the third n-type GaN layer, the second multiple quantum well light emitting layer and the second p-type GaN layer to expose the barrier layer and the protection layer, and preparing the passivation layer.

[0084] Please refer to Figure 12For the structure schematic diagram with the passivation layer, specifically, the initial hexagonal pyramid n-GaN 16, the third n-type GaN layer 32, the second multi-quantum well light-emitting layer 41 and the second p-type GaN layer 51 in a partial region are etched by using a phosphoric acid solution at 140 DEG C, the adjacent chip epitaxial layers are completely separated, and the protective layer 7 and the barrier layer 10 of the chip are exposed, then the passivation layer 17 with a thickness of 100 nm and made of SiO2 is grown by using a plasma enhanced chemical vapor deposition device. It should be noted that, due to the existence of the barrier layer 10 and the protective layer 7, the epitaxial layer is not further etched by hot phosphoric acid after the etching.

[0085] In step S8, the passivation layer in a partial region is etched, the protective layer is exposed, the p-electrode is prepared on the surface of the protective layer, and the preparation of the LED chip is completed.

[0086] Please refer to Figure 1 For the structure schematic diagram of the LED chip for improving heat dissipation and stress relief, the etching in the step is wet etching, specifically, the passivation layer 17 on the surface of the protective layer 7 is etched by using hydrofluoric acid, the protective layer 7 is exposed, then the p-electrode 18 with a thickness of 1.2 microns is deposited on the surface of the protective layer 7 by using a physical vapor deposition device.

[0087] It should be noted that, the single chip obtained after the laser scribing along the chip peripheral separation region is completed, the InGaN long-wavelength LED chip preparation is completed, and the top view of the single chip is as shown in Figure 13 The p-electrode 18 is electrically connected with the protective layer 7, the reflective layer 6 and the p-type GaN layer 52, and serves as the anode of the LED chip, and the substrate 14 is electrically connected with the bonding layer 15, the n-electrode 13 and the n-type GaN layer 33, and serves as the cathode of the LED chip.

[0088] In addition, the n-electrode hole 8 can be circular, quadrilateral, hexagonal or any shape combination, the n-electrode hole 8 can be arranged in a rectangular, hexagonal or any arrangement, and the chip light-emitting surface 19 can be quadrilateral, hexagonal, circular or any shape.

[0089] Embodiment three

[0090] The embodiment three of the present application provides a preparation method of the LED chip for improving heat dissipation and stress relief, which is different from the preparation method of the LED chip for improving heat dissipation and stress relief provided in the embodiment two of the present application, in that the order of steps S2 and S3 is changed, and after the change, the n-electrode in step S4 is prepared at the same time as the protective layer in step S2.

[0091] It should be noted that, the preparation method of the LED chip for improving heat dissipation and stress relief provided in the embodiment three of the present application includes the following steps:

[0092] A reflective layer is prepared on the surface of the p-type GaN layer, and the reflective layer is NiAgNiAg;

[0093] The first p-type GaN layer and the first multiple quantum well layer in the partial region are etched to expose the first n-type GaN layer, and the n-electrode hole and the third stress relief groove are formed. For details, please refer to Figure 4 and Figure 14 , Figure 14 is a structural schematic diagram with a reflective layer, an n-electrode hole, and a third stress relief groove. After the reflective layer 6 is prepared, the first p-type GaN layer 5 and the first multiple quantum well layer 4 in the partial region are etched using an inductively coupled plasma device to expose the first n-type GaN layer 3, thereby obtaining the second p-type GaN layer 51, the second multiple quantum well light-emitting layer 41, and the second n-type GaN layer 31. At the same time, the n-electrode hole 8 and the third stress relief groove 91 are formed.

[0094] An n-electrode is prepared on the surface of the exposed n-type GaN layer, and a protective layer is prepared on the reflective layer. For details, please refer to Figure 15 is a structural schematic diagram for preparing an n-electrode in an n-electrode hole and a protective layer. The n-electrode 13 does not need to be prepared separately, but is prepared simultaneously with the protective layer 7. After the n-electrode hole 8 is formed, the protective layer 7 is prepared on the surface of the reflective layer 6 and the n-electrode 13 is prepared in the n-electrode hole 8 simultaneously by a physical vapor deposition device. The protective layer 7 and the n-electrode 13 are both CrPt with a thickness of 700 nm. It can be understood that there is a certain gap between the inner wall of the n-electrode hole 8 and the n-electrode 13 for subsequent preparation of the heat-conducting layer 11.

[0095] A barrier layer is prepared, a partial region of the barrier layer is etched, a heat-conducting layer is prepared, a partial region of the heat-conducting layer is etched, the n-electrode is exposed, and a second stress relief groove is formed. For details, please refer to Figure 16 is a structural schematic diagram with a barrier layer, a heat-conducting layer, an n-electrode, and a second stress relief groove. Specifically, after the protective layer 7 and the n-electrode 13 are prepared, the barrier layer 10 and the heat-conducting layer 11 are prepared, and a partial region of the barrier layer 10 and the heat-conducting layer 11 is etched using hydrofluoric acid to expose the n-electrode 13 and form the second stress relief groove 12.

[0096] A bonding layer is prepared and combined with a substrate, the silicon substrate is peeled off, and the AlN buffer layer is exposed.

[0097] The AlN buffer layer and the second n-type GaN layer are etched.

[0098] A partial region of the initial hexagonal pyramid n-GaN, the third n-type GaN layer, the second multiple quantum well light-emitting layer, and the second p-type GaN layer are etched to expose the barrier layer and the protective layer, and a passivation layer is prepared.

[0099] Etching part of the area passivation layer, exposing the protection layer, preparing a p electrode on the surface of the protection layer, and completing the preparation of the LED chip.

[0100] In conclusion, the improved heat dissipation and stress relief LED chip and the preparation method thereof in the embodiment of the present application, by sequentially arranging the bonding layer, the heat conduction layer, the barrier layer, the protection layer, the reflection layer and the epitaxial layer on the substrate, the epitaxial layer includes a p-type GaN layer, a multi-quantum well layer and an n-type GaN layer arranged in the direction away from the substrate, wherein the barrier layer and the heat conduction layer realize the electrical isolation between the protection layer and the bonding layer, the barrier layer realizes the phosphoric acid corrosion, and since the heat conduction layer extends to the multi-quantum well layer, the sidewall passivation and heat conduction effect of the multi-quantum well layer are realized, and the stress relief is realized by the first stress release groove and the second stress release groove.

[0101] The above-mentioned embodiments only express several embodiments of the present application, and the description is more specific and detailed, but it cannot be understood as the limitation of the patent scope of the present application. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which belong to the protection scope of the present application. Therefore, the protection scope of the present application patent should be subject to the appended claims.

Claims

1. An LED chip for improving heat dissipation and stress relief, characterized in that, The LED chip is a silicon-based InGaN long-wavelength LED chip, and the epitaxial layer growth substrate is a silicon substrate. The main light wavelength range is 500-620 nm. The LED chip comprises a substrate and a bonding layer, a heat-conducting layer, a barrier layer, a protective layer, a reflective layer and an epitaxial layer arranged in sequence on the substrate. The epitaxial layer comprises a p-type GaN layer, a multi-quantum well layer and an n-type GaN layer arranged in sequence away from the substrate. A passivation layer is arranged on the surface of the epitaxial layer and part of the barrier layer. The heat-conducting layer, the barrier layer and the protective layer are in a stepped structure and are wrapped layer by layer. The heat-conducting layer extends towards the n-type GaN layer to form a containing space embedded in the epitaxial layer. An n electrode is arranged in the containing space and is in contact with the n-type GaN layer. A groove formed by the passivation layer and the protective layer is arranged on the side surface of the epitaxial layer. An p electrode is arranged in the groove. In the preparation process, a first stress relief groove is obtained by etching the epitaxial layer, and a second stress relief groove is formed by etching the heat-conducting layer to relieve stress.

2. The LED chip for improving heat dissipation and stress relaxation according to claim 1, wherein, The barrier layer is made of SiO2, and the thickness of the barrier layer is 50-300 nm.

3. The LED chip for improving heat dissipation and stress relaxation according to claim 1, wherein, The heat-conducting layer is made of one or a combination of SiN, AlN, Al2O3, MgO and HfO2, and the thickness of the heat-conducting layer is 300-1500 nm.

4. The LED chip for improving heat dissipation and stress relaxation according to claim 1, wherein, The reflective layer is made of one or a combination of Ni, Ag, Al, Au, Ti and Pt, and the thickness of the reflective layer is 50-400 nm.

5. The LED chip for improving heat dissipation and stress relaxation according to claim 1, wherein, The protective layer is made of one or a combination of Cr, Pt, Au, Al, Ti, Ni and TiW, and the thickness of the protective layer is 200-1200 nm.

6. A method for fabricating an LED chip that improves heat dissipation and relieves stress, characterized in that, A method for preparing the LED chip for improving heat dissipation and relieving stress according to any one of claims 1-5, the method comprising: Step S1, providing a silicon substrate, and growing an AlN buffer layer, a first n-type GaN layer, a first multi-quantum well layer and a first p-type GaN layer in sequence on the surface of the silicon substrate; Step S2, preparing a reflective layer on the surface of the first p-type GaN layer, and preparing a protective layer on the surface of the reflective layer; Step S3, etching part of the first p-type GaN layer and the first multi-quantum well layer to expose the first n-type GaN layer, forming an n electrode hole and a first stress relief groove; Step S4, preparing a barrier layer, etching part of the barrier layer, preparing a heat-conducting layer, etching part of the heat-conducting layer to expose a second n-type GaN layer, forming a second stress relief groove, and preparing an n electrode; Step S5, preparing a bonding layer, combining the bonding layer with the substrate, and peeling off the silicon substrate to expose the AlN buffer layer; Step S6, etching the AlN buffer layer and the second n-type GaN layer; Step S7, etching part of an initial hexagonal pyramid n-GaN, a third n-type GaN layer, a second multi-quantum well light-emitting layer and a second p-type GaN layer to expose the barrier layer and the protective layer, and preparing a passivation layer; Step S8, etching part of the passivation layer to expose the protective layer, preparing a p electrode on the surface of the protective layer, and completing the preparation of the LED chip.

7. The method of claim 6, wherein the method further comprises forming a passivation layer on the LED chip. The step of providing a silicon substrate, growing an AlN buffer layer, a first n-type GaN layer, a first multi-quantum well layer and a first p-type GaN layer on the surface of the silicon substrate in sequence further comprises: a step of preparing a reflective layer on the surface of the p-type GaN layer; a step of etching part of the first p-type GaN layer and the first multi-quantum well layer to expose the first n-type GaN layer, forming an n-electrode hole and a third stress relief groove; a step of preparing an n-electrode on the exposed surface of the n-type GaN layer and preparing a protective layer on the reflective layer; a step of preparing a barrier layer, etching part of the barrier layer, preparing a heat-conducting layer, etching part of the heat-conducting layer to expose the second n-type GaN layer and form a second stress relief groove; a step of preparing a bonding layer and combining the bonding layer with a substrate, peeling off the silicon substrate to expose the AlN buffer layer; a step of etching the AlN buffer layer and the second n-type GaN layer; a step of etching part of the initial hexagonal pyramid n-GaN, the third n-type GaN layer, the second multi-quantum well light-emitting layer and the second p-type GaN layer to expose the barrier layer and the protective layer, and preparing a passivation layer; a step of etching part of the passivation layer to expose the protective layer, preparing a p-electrode on the surface of the protective layer and completing the preparation of the LED chip.

8. The method of claim 6, wherein the LED chip is prepared by improving heat dissipation and stress relaxation. The etching in step S3 is dry etching, and the etching depth is 400nm-1500nm.

9. The method of claim 6, wherein the LED chip is prepared by improving heat dissipation and stress relaxation. In step S5, the method of combining the silicon substrate with the substrate is solid-liquid interdiffusion bonding.

10. The method of claim 6, wherein the LED chip is prepared by improving heat dissipation and stress relaxation. The etching methods in steps S6 and S7 are both wet etching, and the etching solution in step S7 is a phosphoric acid solution.

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