Wafer-level gold etchant

Abstract

The invention relates to a wafer-level gold etchant which is characterized by being prepared from the following raw materials in percentage by weight: 8-12% of a sodium thiosulfate solution, 28-32% of a thiourea solution, 8-12% of a potassium ferricyanide solution and 48-52% of a potassium iodide solution. The wafer-level gold corrosive liquid disclosed by the invention has the advantages that the wafer-level gold corrosive liquid can be widely applied to a circuit which has a gold film layer thickness of more than 0.5 mu m and has a relatively high requirement on sidetrack control, so that the problems of overlarge sidetrack, line CD (Compact Disc) over-limit and even metal falling caused by corrosion of the original gold corrosive liquid are avoided. When the wafer-level gold etching liquid is used for etching, smaller sidetracking is achieved, a process window is wider, process compatibility is better, and process support is provided for high-speed and high-power photoelectric semiconductors and micro-system devices.

Description

Technical Field

[0001] The method belongs to the field of microsystems (MEMS) and wafer-level packaging, and relates to a wafer-level gold etching solution. Background Art

[0002] Gold is a yellow precious metal with extremely high chemical stability, excellent conductivity, easy soldering, and high-temperature resistance. In MEMS (microelectromechanical systems), gold is the preferred bonding and conductive material for high-precision and high-reliability chips due to its excellent conductivity and chemical stability. As chip critical dimensions (CDs) continue to decrease, developing higher-precision gold patterning processes has become a challenge in the MEMS field. Maintaining stable circuit performance requires that the resistor and the patterned gold conform to the designed dimensions.

[0003] A wide variety of patterning technologies are currently used in MEMS circuits, but etching processes can essentially be categorized as wet or dry. The etching process begins with a PVD coating on the wafer surface, which can be performed by evaporation, sputtering, or ion plating, depending on specific needs. A photoresist is then applied to the surface and patterned. The metal film layer is then removed from the photoresist-exposed areas, and then the photoresist is removed, resulting in the patterned metal. Etching involves both dry and wet etching. Wet etching offers the advantages of high selectivity and uniformity, but is only suitable for patterns with a CD greater than 3μm. Isotropic etching can also cause undercutting of the metal sidewalls. Dry etching, on the other hand, can meet the processing requirements of small CDs and anisotropic processes, but it can damage the substrate material. Sidewall polymer deposits and photoresist baked during etching are difficult to remove after etching.

[0004] The existing gold etching solution, whose main components are iodine / potassium iodide, has large side drilling after etching and cannot meet the process requirements of high metal line width accuracy. Due to the Lag effect, the etching rate of IBE dry etching is slower in small gaps, which will cause damage to the substrate in large opening areas and reduce the compatibility of product processes. In order to improve the high-precision line width patterning capability of gold, it is necessary to develop a new gold etching solution that can simultaneously meet the requirements of small side drilling and high selectivity for substrate materials.

[0005] In wet etching processes, iodine / potassium iodide is typically used to etch gold. However, because gold itself cannot stably adhere to semiconductor materials, a metal film layer such as Gr, Ti, or TiW is often required as an adhesion layer to provide adhesion. The electrochemical reaction between the two forms a galvanic cell in the solution, resulting in a higher corrosion rate at the interface between the gold and the adhesion layer. When the thickness of the corroded gold film is large, a significant inverted trapezoidal undercut can occur, causing metal shedding in the non-corroded area. Therefore, a new gold etching solution with less side drilling than existing gold etching solutions is needed to provide process support for high-speed, high-power optoelectronic semiconductors and microsystem devices. Summary of the Invention

[0006] The present invention aims to solve the problems of excessive side drilling, line CD exceeding the limit and even metal shedding caused by the original gold etching solution, and provides a wafer-level gold etching solution. The wafer-level gold etching solution can be widely used in circuits with a gold film thickness of more than 0.5 μm and high requirements for side drilling control.

[0007] In order to achieve the above object, the technical solution adopted by the present invention is as follows: A wafer-level gold etching solution is characterized by being made of the following raw materials in the following weight percentages: 8-12% sodium thiosulfate solution (stabilizer), 28-32% thiourea solution (inhibitor), 8-12% potassium ferrocyanide solution (etchant), and 48-52% potassium iodide solution (pH buffer).

[0008] Furthermore, the wafer-level gold etching solution is characterized by being made of the following raw materials in the following weight percentages: 9-11% sodium thiosulfate solution, 29-31% thiourea solution, 9-11% potassium ferrocyanide solution, and 49-51% potassium iodide solution.

[0009] Furthermore, the wafer-level gold etching solution is characterized by being made of the following raw materials in the following weight percentages: 10% sodium thiosulfate solution, 30% thiourea solution, 10% potassium ferrocyanide solution, and 50% potassium iodide solution.

[0010] The invention obtains a gold etching solution with stable etching rate and small side drilling by adjusting the ratio of complex ligand, stabilizer, inhibitor, wetting agent and pH buffer solution.

[0011] The beneficial effects of the present invention are as follows: The wafer-level gold etching solution described herein can be widely used in circuits with gold film thicknesses exceeding 0.5 μm and requiring high side drilling control, thereby avoiding the problems of excessive side drilling, line CD exceeding the limit, and even metal shedding caused by conventional gold etching solutions. Etching using the wafer-level gold etching solution described herein results in less side drilling, a wider process window, and improved process compatibility, providing process support for high-speed, high-power optoelectronic semiconductors and microsystem devices. DETAILED DESCRIPTION

[0012] A wafer-level gold etching method, the specific implementation steps are as follows: Example 1

[0013] (1) Take the SOI silicon wafer, perform standard RCA cleaning on the wafer, and then grow a 1000Å thermal oxide layer; (2) Using sputtering or evaporation technology, a layer of metal sputtering 500Å Ti and 10000Å Au is made on the top silicon surface; (3) Metal patterning is performed using a photolithography process, and the silicon wafer after metal patterning is placed in a mixed solution for etching; wherein the mixed solution is a mixture of the following raw materials in the following weight percentages: 8% sodium thiosulfate solution, 30% thiourea solution, 12% potassium ferrocyanide solution, and 50% potassium iodide solution. Example 2

[0014] (1) Take the SOI silicon wafer, perform standard RCA cleaning on the wafer, and then grow a 1000Å thermal oxide layer; (2) Using sputtering or evaporation technology, a layer of metal sputtering 500Å Ti and 10000Å Au is made on the top silicon surface; (3) Metal patterning is performed using a photolithography process, and the silicon wafer after metal patterning is placed in a mixed solution for etching; wherein the mixed solution is a mixture of the following raw materials in the following weight percentages: 10% sodium thiosulfate solution, 30% thiourea solution, 10% potassium ferrocyanide solution, and 50% potassium iodide solution. Example 3

[0015] (1) Take the SOI silicon wafer, perform standard RCA cleaning on the wafer, and then grow a 1000Å thermal oxide layer; (2) Using sputtering or evaporation technology, a layer of metal sputtering 500Å Ti and 10000Å Au is made on the top silicon surface; (3) Metal patterning is performed using a photolithography process, and the silicon wafer after metal patterning is placed in a mixed solution for corrosion; wherein the mixed solution is a mixture of the following raw materials in the following weight percentages: 10% sodium thiosulfate solution, 32% thiourea solution, 10% potassium ferrocyanide solution, and 48% potassium iodide solution, which is poured into a culture dish and thoroughly mixed.

[0016]

[0017] Comprehensive comparison shows that Example 2 (10% sodium thiosulfate solution, 30% thiourea solution, 10% potassium ferrocyanide solution, 50% potassium iodide solution) has a moderate liquid rate, minimal side drilling, a wider process window, and better process compatibility, providing more favorable process support for high-speed, high-power optoelectronic semiconductors and microsystem devices.

Claims

1. A wafer-level gold etching solution, characterized in that The invention is prepared from the following raw materials in the following weight percentages: 8-12% sodium thiosulfate solution, 28-32% thiourea solution, 8-12% potassium ferricyanide solution, and 48-52% potassium iodide solution.

2. A wafer-level gold etching solution according to claim 1, characterized in that The invention is prepared from the following raw materials in the following weight percentages: 9-11% sodium thiosulfate solution, 29-31% thiourea solution, 9-11% potassium ferrocyanide solution, and 49-51% potassium iodide solution.

3. A wafer-level gold etching solution according to claim 1, characterized in that The invention is prepared from the following raw materials in the following weight percentages: 10% sodium thiosulfate solution, 30% thiourea solution, 10% potassium ferrocyanide solution, and 50% potassium iodide solution.

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