An industrial control mainboard anti-interference performance evaluation system and method for a complex disturbance scene

Abstract

The present application relates to the technical field of industrial automation electronic testing, and specifically relates to an industrial control mainboard anti-interference performance evaluation system and method for a complex disturbance scene, comprising a clock disturbance scene generation module, a dynamic clock interference injection module, a clock bus degradation collection module and an anti-interference level output module; wherein: the clock disturbance scene generation module is used to generate a clock disturbance spectrum; the dynamic clock interference injection module converts the clock disturbance spectrum into a frequency-phase double modulation signal and injects it into the industrial control mainboard under test; the clock bus degradation collection module is used to collect bus error code features caused by clock disturbance in real time; and the anti-interference level output module is used to generate a four-level clock anti-interference level. Through the construction of a closed-loop system of disturbance injection-feature collection-level evaluation, the present application realizes quantitative evaluation and stability determination of the anti-interference capability of the industrial control mainboard under a complex disturbance scene.

Description

Technical Field

[0001] This invention relates to the field of industrial automation electronic testing technology, and in particular to a system and method for evaluating the anti-interference performance of industrial control motherboards in complex disturbance scenarios. Background Technology

[0002] With the increasing complexity and frequency of industrial automation systems, the stability of industrial control motherboards, as the core control carriers, is significantly challenged in harsh electromagnetic environments. In practical applications, transient disturbances caused by high-power equipment switching, motor start-up and shutdown, and switching power supply circuit oscillations are widespread in industrial sites. These disturbances often act on the motherboard clock system in the form of high-frequency phase jitter or periodic frequency drift, leading to abnormal phenomena such as unstable clock links, data bus errors, and signal edge inaccuracies, which seriously affect the operational reliability and real-time performance of the control system.

[0003] Existing industrial control motherboard anti-interference tests mostly rely on static redundancy design and electromagnetic compatibility indicators, lacking an integrated method for dynamic disturbance injection, link response analysis, and level quantification assessment. This makes it difficult to reflect the system's actual performance in real-world disturbance scenarios. Therefore, there is an urgent need for an industrial control motherboard anti-interference performance evaluation system and method for complex disturbance scenarios to address these issues. Summary of the Invention

[0004] To achieve the above objectives, the present invention provides a system and method for evaluating the anti-interference performance of industrial control motherboards in complex disturbance scenarios.

[0005] A system and method for evaluating the anti-interference performance of industrial control motherboards under complex disturbance scenarios, comprising a clock disturbance scenario generation module, a dynamic clock interference injection module, a clock bus degradation acquisition module, and an anti-interference level output module; wherein:

[0006] Clock disturbance scenario generation module: Based on the transient interference timing characteristics of the target industrial scenario, it generates a clock disturbance spectrum that includes the phase jitter amplitude and duration of the fundamental frequency and the third harmonic frequency;

[0007] Dynamic clock interference injection module: used to convert clock disturbance spectrum into frequency-phase dual modulation signal, and inject it into the clock generator output terminal and PLL feedback point of the industrial control motherboard under test through a low impedance probe;

[0008] Clock bus degradation acquisition module: used to acquire bus error characteristics caused by clock disturbances in real time, including error burst density and bit width offset, to form a dataset characterizing the degradation propagation of the clock to bus link;

[0009] Anti-interference level output module: used to generate a four-level clock anti-interference level based on the cumulative number of times the bus error characteristics exceed the preset threshold and the maximum offset amplitude.

[0010] Optionally, the clock disturbance scenario generation module includes an disturbance timing modeling unit, a frequency component analysis unit, and a disturbance spectrum construction unit; wherein:

[0011] Interference timing modeling unit: used to extract the time-domain waveform features of transient interference based on the electromagnetic interference signals collected in the target industrial scene, including the start and end times and duration of the interference, and convert the time-domain waveform features into data in a standard format;

[0012] Frequency component analysis unit: used to perform spectrum analysis on standard format data, determine the fundamental frequency component and the third harmonic component, and extract their amplitude and duration characteristics in interference;

[0013] Perturbation spectrum construction unit: used to integrate the amplitude and duration information corresponding to the fundamental frequency and the third harmonic to generate a clock perturbation spectrum for subsequent interference injection.

[0014] Optionally, the frequency component analysis unit includes:

[0015] Spectrum Transformation Subunit: Used to convert standard time-domain waveform data into frequency-domain signals to reveal the dominant frequency component and its amplitude response characteristics in the signal;

[0016] Frequency identification subunit: Used to identify the frequency corresponding to the maximum amplitude based on the local peak position of the spectrum amplitude, and determine it as the fundamental frequency; and to find the second peak frequency at three times the amplitude, as the third harmonic frequency;

[0017] Amplitude-time feature extraction subunit: used to extract the amplitude change intensity and duration of the identified frequency components in the original interference signal.

[0018] Optionally, the perturbation spectrum construction unit includes:

[0019] Frequency combination subunit: used to merge the identified fundamental frequency and third harmonic frequency components as interference frequency pairs and establish a list of interference components;

[0020] Amplitude-time structure mapping sub-unit: used to map the amplitude and duration features corresponding to each frequency component in the list in an ordered manner, and construct a frequency-amplitude-time triplet structure;

[0021] Perturbation spectrum output sub-unit: used to combine the triplets corresponding to two frequency components to form a complete perturbation spectrum structure.

[0022] Optionally, the dynamic clock interference injection module includes a dual modulation generation unit, an injection path identification unit, and a low-impedance probe unit; wherein:

[0023] Dual modulation generation unit: used to convert the frequency, amplitude and duration information in the perturbation spectrum into a dual modulation signal containing frequency offset and phase offset;

[0024] Injection path identification unit: used to determine the clock generator output and PLL feedback point of the motherboard under test as interference injection nodes;

[0025] Low-impedance probe unit: used to drive dual-modulation signals and coupled to the interference injection node through a low-impedance RF probe.

[0026] Optionally, the clock bus degradation acquisition module includes a bit error detection unit, a bit width monitoring unit, and a degradation data construction unit; wherein:

[0027] Bit error detection unit: Used to record bit error events in bus transmission in real time by comparing the actual received data with the standard data template during the motherboard's communication task, and to count the bit error burst density per unit time.

[0028] Bit width monitoring unit: used to detect the actual duration of each symbol of the bus signal, determine whether there is a bit width abnormality caused by edge drift, and extract the offset value of each bit;

[0029] Degraded data construction unit: used to align the bit error density and bit width offset by time to construct a degraded propagation dataset that reflects the changes in the state of the bus link from the clock.

[0030] Optionally, the bit error detection unit includes:

[0031] Data comparison subunit: used to synchronously compare the real-time data stream received by the bus under test with the preset standard data template bit by bit during the communication process, identify the bits with deviation, and output the error mark sequence;

[0032] Error localization subunit: used to record the start and end positions of consecutive error regions in the error marking sequence, in order to identify the time period in which the error set occurs and form a set of error burst segments;

[0033] Burst density calculation subunit: Used to count the number of error burst segments within a unit time window, in order to calculate the error burst density index for the corresponding time period. The formula is: Among them, D e For burst density of errors; N e T represents the number of error bursts detected within the time window. w This is for the duration of the statistical time window.

[0034] Optionally, the bit width monitoring unit includes:

[0035] Edge capture subunit: used to continuously sample bus signals and identify the rising and falling edges of each symbol based on the level threshold, and extract the start and end times of each bit;

[0036] Bit width calculation subunit: used to calculate the actual duration of each logic bit, i.e., the actual bit width, based on the start and end times of each logic bit;

[0037] Offset determination subunit: Used to compare the actual bit width with the preset standard bit width value and calculate the offset ΔW for each bit. i And determine whether it exceeds the set threshold, if |ΔW i |>δ th If so, it is marked as a bit width anomaly, δ th This is the preset maximum allowed offset threshold.

[0038] Optionally, the anti-interference level output module includes a threshold comparison unit and a level determination unit, wherein:

[0039] The value comparison unit is used to perform statistical analysis on the degradation propagation dataset, comparing the bus error burst density and bit width offset with preset tolerance thresholds, and recording the cumulative number N of exceedances. c and the maximum bit width offset ΔW within the detection period max ;

[0040] Level determination unit: used to determine the number of times the limit is exceeded (N). c Maximum bit width offset ΔW max The four-level anti-interference level is generated according to the following rules;

[0041] When N c =0 and ΔW max When the value is ≤0.1W0, it is classified as Level 1 interference immunity.

[0042] When 0 <N c ≤2 and 0.1W0<ΔW max When the interference level is ≤0.2W0, it is classified as Level 2 interference immunity.

[0043] When 2 <N c ≤5 or 0.2W0<ΔW max When the interference level is ≤0.4W0, it is classified as Level 3 interference immunity.

[0044] When N c >5 or ΔW max When the value is greater than 0.4W0, it is a level 4 interference immunity level; where W0 is the reference standard bit width.

[0045] A method for evaluating the anti-interference performance of industrial control motherboards in complex disturbance scenarios, implemented by the aforementioned system for evaluating the anti-interference performance of industrial control motherboards in complex disturbance scenarios, includes the following steps:

[0046] S1: Obtain the typical transient interference timing characteristics in the target industrial site, and extract the fundamental frequency and third harmonic frequency components based on the spectrum analysis method. Combine the corresponding phase disturbance amplitude and duration to generate a clock disturbance spectrum for simulation.

[0047] S2: Convert the clock disturbance spectrum into a frequency and phase dual modulation signal, and inject it into the clock generator output terminal and phase-locked loop feedback point of the industrial control motherboard under test through a low impedance probe;

[0048] S3: During the operation of the industrial control motherboard, the bus error burst density and signal bit width offset under the influence of interference are collected in real time to construct a link degradation dataset characterizing the clock disturbance propagation effect.

[0049] S4: Analyze the degraded dataset, count the cumulative number of times the burst density of bit errors exceeds the threshold and the maximum bit width offset, and generate a four-level anti-interference level according to the preset judgment rules.

[0050] The beneficial effects of this invention are:

[0051] This invention constructs a clock disturbance spectrum containing both frequency and phase modulation features and precisely injects it into the critical clock link of an industrial control motherboard. This effectively simulates the actual impact of typical transient interference in industrial settings on the motherboard's timing system, solving the problem of the single and untargeted disturbance injection methods in existing technologies.

[0052] This invention constructs a four-level immunity assessment model based on a level determination mechanism that uses the cumulative number of bit errors and the maximum bit width offset. This model can quantitatively classify the stability of industrial control motherboards under different levels of disturbance, improve the accuracy and engineering applicability of immunity testing, and provide a clear basis for subsequent hardware selection, fault tolerance optimization, and system reliability design. Attached Figure Description

[0053] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only for this invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0054] Figure 1 This is a schematic diagram of the anti-interference performance evaluation system according to an embodiment of the present invention;

[0055] Figure 2 This is a schematic diagram of the anti-interference performance evaluation method according to an embodiment of the present invention. Detailed Implementation

[0056] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. It should also be noted that, to make the embodiments more comprehensive, the following embodiments are the best and preferred embodiments, and those skilled in the art can use other alternative methods to implement some well-known technologies; moreover, the accompanying drawings are only for more specific description of the embodiments and are not intended to specifically limit the present invention.

[0057] like Figure 1 As shown, an anti-interference performance evaluation system for industrial control motherboards in complex disturbance scenarios includes a clock disturbance scenario generation module, a dynamic clock interference injection module, a clock bus degradation acquisition module, and an anti-interference level output module; wherein:

[0058] Clock disturbance scenario generation module: Based on the transient interference timing characteristics of the target industrial scenario, it generates a clock disturbance spectrum that includes the phase jitter amplitude and duration of the fundamental frequency and the third harmonic frequency;

[0059] Dynamic clock interference injection module: used to convert clock disturbance spectrum into frequency-phase dual modulation signal, and inject it into the clock generator output terminal and PLL feedback point of the industrial control motherboard under test through a low impedance probe;

[0060] Clock bus degradation acquisition module: used to acquire bus error characteristics caused by clock disturbances in real time, including error burst density and bit width offset, to form a dataset characterizing the degradation propagation of the clock to bus link;

[0061] Anti-interference level output module: used to generate a four-level clock anti-interference level based on the cumulative number of times the bus error characteristics exceed the preset threshold and the maximum offset amplitude.

[0062] The clock disturbance scenario generation module includes a disturbance timing modeling unit, a frequency component analysis unit, and a disturbance spectrum construction unit; among which:

[0063] Interference timing modeling unit: used to extract the time-domain waveform features of transient interference based on the electromagnetic interference signals collected in the target industrial scene, including the start and end times and duration of the interference, and convert the time-domain waveform features into data in a standard format;

[0064] Frequency component analysis unit: used to perform spectrum analysis on standard format data, determine the fundamental frequency component and the third harmonic component, and extract their amplitude and duration characteristics in interference;

[0065] The disturbance spectrum construction unit integrates the amplitude and duration information corresponding to the fundamental frequency and the third harmonic to generate a clock disturbance spectrum for subsequent interference injection, thereby achieving a realistic reproduction of clock interference in complex scenarios. Through the characteristic modeling of transient interference in industrial sites, the accurate extraction of major frequency components, and the structured generation of disturbance spectra, the above unit can ensure the representativeness and controllability of clock disturbance scenarios, providing efficient and realistic interference input for subsequent anti-interference performance evaluation of the system, thereby improving the scientificity and applicability of the evaluation results.

[0066] The frequency component analysis unit includes:

[0067] Spectrum Transform Subunit: Used to convert standard time-domain waveform data into frequency-domain signals to reveal the dominant frequency component and its amplitude response characteristics; this process is achieved by performing a Fast Fourier Transform, as shown in the formula: Where x(n) is the nth sampling point of the original interference signal; X(k) is the complex spectral value with frequency index k; N is the total number of sampling points; e is the base of the natural logarithm; j is the imaginary unit; and k is the frequency component index.

[0068] Frequency identification subunit: Used to identify the frequency corresponding to the maximum amplitude based on the local peak position of the spectral amplitude, and determine it as the fundamental frequency; and to find the second peak frequency at three times its value, as the third harmonic frequency; the determination condition used is: f0 = argmax f |X(f)|;f3=3·f0;where, is the frequency corresponding to the fundamental frequency component; f3 is the third harmonic frequency; X(f) is the spectral amplitude at frequency f; argmax represents the frequency position that maximizes the amplitude;

[0069] Amplitude-Time Feature Extraction Subunit: Used to extract the amplitude variation intensity and duration of the identified frequency components in the original interference signal. It calculates the maximum amplitude and corresponding duration of the component over the entire period by back-projecting the selected frequency in the frequency domain to a time domain window; the formula is: A(f) = max t |s f (t)|;T(f)=t2-t1, where A(f) is the maximum amplitude of the frequency component f; s f (t) represents the filtering result corresponding to frequency f in the original signal; T(f) represents the effective duration of the frequency f component; t1 and t2 represent the start and end time points when the amplitude exceeds the 50% peak threshold. By setting up three functional units—spectrum transformation, frequency point identification, and amplitude-time extraction—not only is the accurate positioning of key interference frequencies achieved, but also their amplitude and time characteristics are precisely obtained. This provides a comprehensive quantitative basis for constructing a clock disturbance spectrum that conforms to the real disturbance background, significantly enhancing the representativeness and systematicness of the interference simulation input.

[0070] The perturbation spectrum building blocks include:

[0071] Frequency combination subunit: used to merge the identified fundamental frequency and third harmonic frequency components as interference frequency pairs and establish a list of interference components, which constitutes the frequency framework for subsequent construction of clock perturbation spectrum.

[0072] Amplitude-time structure mapping subunit: used to map the amplitude and duration features corresponding to each frequency component in the list in an ordered manner, and construct a frequency-amplitude-time triplet structure to realize the standardized expression of disturbance information;

[0073] The perturbation spectrum output subunit is used to combine the triplets corresponding to two frequency components to form a complete perturbation spectrum structure. Its expression is: P = {M(f1), M(f2)}, where P is the completed clock perturbation spectrum set; M(f1) and M(f2) are the amplitude-time characteristic triplets corresponding to the fundamental frequency and the third harmonic, respectively, and are output for use by the subsequent injection module. This structure is used to reflect the perturbation feature set exhibited by the interference frequency components in the clock signal. By performing ternary mapping and structured combination of frequency components, amplitude information and perturbation duration, the above subunit can accurately construct the clock perturbation spectrum for simulation, effectively improving the expressive power of the interference injection signal and its adaptability to industrial scenarios, and providing a stable and reproducible input benchmark for evaluating the anti-interference performance of industrial control motherboards.

[0074] The dynamic clock interference injection module includes a dual modulation generation unit, an injection path identification unit, and a low-impedance probe unit; wherein:

[0075] Dual modulation generation unit: used to convert the frequency, amplitude and duration information in the disturbance spectrum into a dual modulation signal containing frequency offset and phase offset, so as to realize the composite disturbance control of the standard clock carrier;

[0076] Injection path identification unit: used to identify the clock generator output and PLL feedback point of the motherboard under test as interference injection nodes, and to cover the control path of the main clock link;

[0077] Low-impedance probe unit: used to drive dual-modulation signals and couple them to the interference injection node through a low-impedance RF probe. The port impedance of the low-impedance probe is set between 5 and 15 ohms to achieve efficient electromagnetic coupling to the target injection node. The above unit, by setting a modulation signal generation mechanism with dual perturbation capabilities of frequency and phase, and combining the selection of key injection positions with electrical adaptation of the low-impedance probe, can achieve high-fidelity perturbation simulation of the industrial control motherboard clock system, thereby improving the pertinence and accuracy of anti-interference assessment.

[0078] The dual modulation generation unit includes:

[0079] Frequency modulation subunit: Based on the frequency value and duration of each interference component in the disturbance spectrum, it performs frequency offset processing on the reference clock signal to construct a modulated jumping frequency signal, simulating the frequency fluctuation characteristics in the interference scenario; the specific formula is: Where f(t) is the modulated clock frequency signal; f c The center frequency of the reference clock; Δf i For the i-th perturbation frequency component relative to f c Frequency offset; u(tt) i ) is the unit step function, used to represent the starting point of the i-th disturbance; n is the number of frequency components in the disturbance spectrum;

[0080] Phase modulation subunit: Used to convert the interference amplitude into an equivalent phase offset based on the amplitude information corresponding to the disturbance spectrum, and superimpose it onto the reference clock signal to simulate the transient effects of phase jitter in an industrial environment; the formula is: Where φ(t) is the instantaneous phase after the phase perturbation; Δφ i For the corresponding frequency component f i The phase perturbation amplitude; f i Let i be the i-th frequency component in the perturbation spectrum;

[0081] Modulation fusion output subunit: Used to synchronously superimpose the control quantities output by the frequency modulation subunit and the phase modulation subunit to generate a dual-modulation signal containing frequency offset and phase drift, and output it to the subsequent injection path to form a composite disturbance waveform; the expression of the dual-modulation signal is:

[0082] Wherein, S(t) is the final generated dual-modulation clock signal; A is the amplitude of the reference clock signal; f(τ) is the instantaneous frequency function under the time variable τ; τ is the time integration variable, used to calculate the contribution of frequency change to the total phase over the time interval [0,t]; dτ is the integration sign, corresponding to the small time increment of the integration variable τ; φ(t) is the phase offset at time t; the above sub-units decompose the triplet information in the disturbance spectrum into two channels, frequency modulation and phase modulation, and process them separately, and finally synthesize them in the fusion sub-unit, which can realize fine disturbance control of the clock signal of the industrial control motherboard, which not only improves the reproduction of the interference simulation, but also ensures the controllability and repeatability of the interference injection.

[0083] The clock bus degradation acquisition module includes a bit error detection unit, a bit width monitoring unit, and a degradation data construction unit; wherein:

[0084] Bit error detection unit: Used to record bit error events in bus transmission in real time by comparing the actual received data with the standard data template during the motherboard's communication task, and to count the bit error burst density per unit time.

[0085] Bit width monitoring unit: used to detect the actual duration of each symbol of the bus signal, determine whether there is a bit width abnormality caused by edge drift, and extract the offset value of each bit;

[0086] Degraded data construction unit: used to align bit error density and bit width offset by time to construct a degradation propagation dataset that reflects the changes in the state of the clock-to-bus link; by synchronously collecting bit error density and bit width offset characteristics and forming a unified degradation dataset, it can accurately characterize the impact of clock disturbances on the stability of motherboard data link transmission, providing a high-timeliness and high-resolution input basis for subsequent anti-interference level determination.

[0087] The bit error detection unit includes:

[0088] Data comparison subunit: During communication, it synchronously compares the real-time data stream received by the bus under test with a preset standard data template bit by bit, identifies the bits with deviations, and outputs an error mark sequence; specifically, for each valid data packet received, it is aligned with the corresponding standard template and an XOR operation is performed to determine the location of the error.

[0089] Error localization subunit: used to record the start and end positions of consecutive error regions in the error marking sequence, in order to identify the time period in which the error set occurs and form a set of error burst segments; the error burst is defined as follows: if the interval between two error events is less than the set minimum interval threshold, they are considered to belong to the same error burst segment;

[0090] Burst density calculation subunit: Used to count the number of error burst segments within a unit time window, in order to calculate the error burst density index for the corresponding time period. The formula is: Among them, D e For burst density of errors; N e T represents the number of error bursts detected within the time window. w To determine the duration of the statistical time window, a three-step detection mechanism is constructed, consisting of bit-by-bit comparison, centralized error location, and time window density analysis. This mechanism can quickly and accurately identify and quantify sudden bit errors in the bus, truly reflecting the transient interference effect of clock disturbances at the digital link layer, thus providing a highly sensitive error indicator for degraded link analysis.

[0091] The bit width monitoring unit includes:

[0092] Edge capture subunit: used to continuously sample bus signals and identify the rising and falling edges of each symbol based on the level threshold, and extract the start and end times of each bit;

[0093] Bit width calculation subunit: used to calculate the actual duration of each logic bit, i.e., the actual bit width, based on the start and end times of each logic bit; the formula is: W i =t i,end -t i,start Among them, W i t represents the actual bit width of the i-th bit. i,start With t i,end These are the start and end times of that position, respectively;

[0094] Offset determination subunit: Used to compare the actual bit width with the preset standard bit width value and calculate the offset ΔW for each bit. i And determine whether it exceeds the set threshold, if |ΔW i |>δ th If it is not, it is marked as a bit width abnormality; the formula for calculating the offset is: ΔW i =W i -W0, where W0 is the standard bit width, δ th The maximum allowable offset threshold is preset; by extracting signal edges bit by bit and calculating the actual bit width offset, the symbol compression or stretching problem caused by clock disturbance can be identified with high precision, improving the ability to detect timing structure anomalies in link degradation, thereby providing a reliable time domain feature basis for bus stability assessment.

[0095] The anti-interference level output module includes a threshold comparison unit and a level determination unit, wherein:

[0096] The value comparison unit is used to perform statistical analysis on the degradation propagation dataset, comparing the bus error burst density and bit width offset with preset tolerance thresholds, and recording the cumulative number N of exceedances. c and the maximum bit width offset ΔW within the detection period max ;

[0097] Level determination unit: used to determine the number of times the limit is exceeded (N). c Maximum bit width offset ΔW max The four-level anti-interference level is generated according to the following rules;

[0098] When N c =0 and ΔW max When the value is ≤0.1W0, it is classified as Level 1 interference immunity.

[0099] When 0 <N c ≤2 and 0.1W0<ΔW max When the interference level is ≤0.2W0, it is classified as Level 2 interference immunity.

[0100] When 2 <N c ≤5 or 0.2W0<ΔW max When the interference level is ≤0.4W0, it is classified as Level 3 interference immunity.

[0101] When N c >5 or ΔW max When the value is >0.4W0, it is a level 4 immunity level; where W0 is the reference standard bit width. By using the error rate and the maximum bit width offset as joint judgment indicators, a level 4 immunity level evaluation model is constructed, which can finely quantify the stability of industrial control motherboards under interference scenarios, and provide a clear basis for hardware selection, structural optimization and immunity margin assessment.

[0102] like Figure 2 As shown, a method for evaluating the anti-interference performance of industrial control motherboards in complex disturbance scenarios is implemented by the aforementioned system for evaluating the anti-interference performance of industrial control motherboards in complex disturbance scenarios, and includes the following steps:

[0103] S1: Obtain the typical transient interference timing characteristics in the target industrial site, and extract the fundamental frequency and third harmonic frequency components based on the spectrum analysis method. Combine the corresponding phase disturbance amplitude and duration to generate a clock disturbance spectrum for simulation.

[0104] S2: Convert the clock disturbance spectrum into a frequency and phase dual modulation signal, and inject it into the clock generator output terminal and phase-locked loop feedback point of the industrial control motherboard under test through a low impedance probe;

[0105] S3: During the operation of the industrial control motherboard, the bus error burst density and signal bit width offset under the influence of interference are collected in real time to construct a link degradation dataset characterizing the clock disturbance propagation effect.

[0106] S4: Analyze the degraded dataset, count the cumulative number of times the burst density of bit errors exceeds the threshold and the maximum bit width offset, and generate a four-level anti-interference level according to the preset judgment rules to reflect the stability level of the motherboard under test in the target interference scenario.

[0107] This invention encompasses any substitutions, modifications, equivalent methods, and solutions made within the spirit and scope of this invention. To provide the public with a thorough understanding of this invention, specific details are described in detail in the following preferred embodiments; however, those skilled in the art will fully understand the invention even without these details. Furthermore, to avoid unnecessary misunderstanding of the essence of this invention, well-known methods, processes, procedures, components, and circuits are not described in detail.

[0108] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A system for evaluating the anti-interference performance of industrial control motherboards in complex disturbance scenarios, characterized in that, It includes a clock disturbance scenario generation module, a dynamic clock interference injection module, a clock bus degradation acquisition module, and an anti-interference level output module; among which: Clock disturbance scenario generation module: Based on the transient interference timing characteristics of the target industrial scenario, it generates a clock disturbance spectrum that includes the phase jitter amplitude and duration of the fundamental frequency and the third harmonic frequency; Dynamic clock interference injection module: used to convert clock disturbance spectrum into frequency-phase dual modulation signal, and inject it into the clock generator output terminal and PLL feedback point of the industrial control motherboard under test through a low impedance probe; Clock bus degradation acquisition module: used to acquire bus error characteristics caused by clock disturbances in real time, including error burst density and bit width offset, to form a dataset characterizing the degradation propagation of the clock to bus link; Anti-interference level output module: used to generate a four-level clock anti-interference level based on the cumulative number of times the bus error characteristics exceed the preset threshold and the maximum offset amplitude.

2. The anti-interference performance evaluation system for industrial control motherboards in complex disturbance scenarios according to claim 1, characterized in that, The clock disturbance scenario generation module includes a disturbance timing modeling unit, a frequency component analysis unit, and a disturbance spectrum construction unit; wherein: Interference timing modeling unit: used to extract the time-domain waveform features of transient interference based on the electromagnetic interference signals collected in the target industrial scene, including the start and end times and duration of the interference, and convert the time-domain waveform features into data in a standard format; Frequency component analysis unit: used to perform spectrum analysis on standard format data, determine the fundamental frequency component and the third harmonic component, and extract their amplitude and duration characteristics in interference; Perturbation spectrum construction unit: used to integrate the amplitude and duration information corresponding to the fundamental frequency and the third harmonic to generate a clock perturbation spectrum for subsequent interference injection.

3. The anti-interference performance evaluation system for industrial control motherboards in complex disturbance scenarios according to claim 2, characterized in that, The frequency component analysis unit includes: Spectrum Transformation Subunit: Used to convert standard time-domain waveform data into frequency-domain signals to reveal the dominant frequency component and its amplitude response characteristics in the signal; Frequency identification subunit: Used to identify the frequency corresponding to the maximum amplitude based on the local peak position of the spectrum amplitude, and determine it as the fundamental frequency; and to find the second peak frequency at three times the amplitude, as the third harmonic frequency; Amplitude-time feature extraction subunit: used to extract the amplitude change intensity and duration of the identified frequency components in the original interference signal.

4. The anti-interference performance evaluation system for industrial control motherboards in complex disturbance scenarios according to claim 3, characterized in that, The perturbation spectrum construction unit includes: Frequency combination subunit: used to merge the identified fundamental frequency and third harmonic frequency components as interference frequency pairs and establish a list of interference components; Amplitude-time structure mapping sub-unit: used to map the amplitude and duration features corresponding to each frequency component in the list in an ordered manner, and construct a frequency-amplitude-time triplet structure; Perturbation spectrum output sub-unit: used to combine the triplets corresponding to two frequency components to form a complete perturbation spectrum structure.

5. The anti-interference performance evaluation system for industrial control motherboards in complex disturbance scenarios according to claim 1, characterized in that, The dynamic clock interference injection module includes a dual modulation generation unit, an injection path identification unit, and a low-impedance probe unit; wherein: Dual modulation generation unit: used to convert the frequency, amplitude and duration information in the perturbation spectrum into a dual modulation signal containing frequency offset and phase offset; Injection path identification unit: used to determine the clock generator output and PLL feedback point of the motherboard under test as interference injection nodes; Low-impedance probe unit: used to drive dual-modulation signals and coupled to the interference injection node through a low-impedance RF probe.

6. The anti-interference performance evaluation system for industrial control motherboards in complex disturbance scenarios according to claim 1, characterized in that, The clock bus degradation acquisition module includes a bit error detection unit, a bit width monitoring unit, and a degradation data construction unit; wherein: Bit error detection unit: Used to record bit error events in bus transmission in real time by comparing the actual received data with the standard data template during the motherboard's communication task, and to count the bit error burst density per unit time. Bit width monitoring unit: used to detect the actual duration of each symbol of the bus signal, determine whether there is a bit width abnormality caused by edge drift, and extract the offset value of each bit; Degraded data construction unit: used to align the bit error density and bit width offset by time to construct a degraded propagation dataset that reflects the changes in the state of the bus link from the clock.

7. The anti-interference performance evaluation system for industrial control motherboards in complex disturbance scenarios according to claim 6, characterized in that, The bit error detection unit includes: Data comparison subunit: used to synchronously compare the real-time data stream received by the bus under test with the preset standard data template bit by bit during the communication process, identify the bits with deviation, and output the error mark sequence; Error localization subunit: used to record the start and end positions of consecutive error regions in the error marking sequence, in order to identify the time period in which the error set occurs and form a set of error burst segments; Burst density calculation subunit: Used to count the number of error burst segments within a unit time window, in order to calculate the error burst density index for the corresponding time period. The formula is: ,in, For error burst density; This represents the number of error bursts detected within the time window. This is for the duration of the statistical time window.

8. The anti-interference performance evaluation system for industrial control motherboards in complex disturbance scenarios according to claim 6, characterized in that, The bit width monitoring unit includes: Edge capture subunit: used to continuously sample bus signals and identify the rising and falling edges of each symbol based on the level threshold, and extract the start and end times of each bit; Bit width calculation subunit: used to calculate the actual duration of each logic bit, i.e., the actual bit width, based on the start and end times of each logic bit; Offset determination subunit: Used to compare the actual bit width with the preset standard bit width value and calculate the offset of each bit. And determine whether it exceeds the set threshold. If so, it is marked as a bit width abnormality. This is the preset maximum allowed offset threshold.

9. The anti-interference performance evaluation system for industrial control motherboards in complex disturbance scenarios according to claim 1, characterized in that, The anti-interference level output module includes a threshold comparison unit and a level determination unit, wherein: Threshold comparison unit: Used for statistical analysis of the degradation propagation dataset, comparing the bus error burst density and bit width offset with preset tolerance thresholds, and recording the cumulative number of times the limits are exceeded. and the maximum bit width offset within the detection period ; Level determination unit: used to determine the number of times the limit is exceeded. offset from maximum bit width The four-level anti-interference level is generated according to the following rules; when and At that time, it is classified as Level 1 anti-interference. when and At that time, it was classified as Level 2 anti-interference. when or At that time, it was classified as Level 3 anti-interference. when or At that time, it was classified as Level 4 anti-interference level; among which, This is the reference standard bit width.

10. A method for evaluating the anti-interference performance of industrial control motherboards in complex disturbance scenarios, implemented by the anti-interference performance evaluation system for industrial control motherboards in complex disturbance scenarios as described in any one of claims 1-9, characterized in that, Includes the following steps: S1: Obtain the typical transient interference timing characteristics in the target industrial site, and extract the fundamental frequency and third harmonic frequency components based on the spectrum analysis method. Combine the corresponding phase disturbance amplitude and duration to generate a clock disturbance spectrum for simulation. S2: Convert the clock disturbance spectrum into a frequency and phase dual modulation signal, and inject it into the clock generator output terminal and phase-locked loop feedback point of the industrial control motherboard under test through a low impedance probe; S3: During the operation of the industrial control motherboard, the bus error burst density and signal bit width offset under the influence of interference are collected in real time to construct a link degradation dataset characterizing the clock disturbance propagation effect. S4: Analyze the degraded dataset, count the cumulative number of times the burst density of bit errors exceeds the threshold and the maximum bit width offset, and generate a four-level anti-interference level according to the preset judgment rules.

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