A DDS signal implementation method based on CORDIC optimization algorithm

Abstract

This invention belongs to the field of wireless communication signal processing, and specifically relates to a DDS signal implementation method based on the CORDIC optimization algorithm. It includes: setting the frequency control word and phase control word of the DDS circuit to calibrate the output frequency; dividing the output frequency to form 32 frequency-divided branches, with each adjacent frequency-divided branch separated by a frequency control word; mapping the phase to the first quadrant, that is, mapping the binary radian data input to each frequency-divided branch to the first quadrant; calculating the sine and cosine waveform values ​​of the corresponding frequencies using the CORDIC optimization algorithm; and modulating the sine and cosine waveform values ​​with the input signal to obtain the DDS signal. This invention optimizes the conventional CORDIC algorithm by adding preprocessing and post-compensation, which can significantly save hardware design resources and substantially reduce hardware overhead and latency.

Description

Technical Field

[0001] This invention belongs to the field of wireless communication signal processing, and specifically relates to a DDS signal implementation method based on the CORDIC optimization algorithm. Background Technology

[0002] Direct Digital Frequency Synthesis (DDS) is a next-generation signal frequency synthesis technology with advantages such as high frequency resolution, fast conversion rate, and phase continuity. A DDS system mainly consists of a phase accumulator, a phase-to-amplitude conversion circuit, and an analog-to-digital conversion circuit. It accumulates the phase according to the step size specified by the frequency adjustment control word through the phase accumulator, then converts the instantaneous phase into a corresponding sine or cosine value sequence output by the phase-to-amplitude conversion circuit, and finally obtains the sine or cosine signal through analog-to-digital conversion and low-pass filtering.

[0003] In DDS circuits, the commonly used algorithm is the CORDIC algorithm. However, the conventional CORDIC algorithm requires multiple iterations to achieve high-precision rotation, resulting in a large hardware scale and occupying a large amount of hardware resources. At the same time, the rotation angle depends on a special angle, leading to insufficient flexibility and poor scalability. Summary of the Invention

[0004] The purpose of this invention is to provide a DDS signal implementation method based on the CORDIC optimization algorithm, which has the characteristics of small hardware size, high operating frequency and flexible parameters, ensuring a high operating frequency while greatly saving computing resources.

[0005] To address the aforementioned technical problems, this invention provides a DDS signal implementation method based on the CORDIC optimization algorithm, comprising:

[0006] The frequency control word and phase control word of the DDS circuit are set to calibrate the output frequency;

[0007] The output frequency is divided to form 32 frequency division branches, with a frequency control word between each two adjacent frequency division branches;

[0008] Phase mapping is performed on the first quadrant, which means mapping the binary radian data input from each frequency division branch to the first quadrant.

[0009] The CORDIC optimization algorithm is used to calculate the sine and cosine waveform values ​​of the corresponding frequencies. The CORDIC optimization algorithm includes: performing a lookup table on the high-order data and preprocessing the low-order data; performing butterfly algorithm operation on the middle-order data and rotation compensation on the low-order data based on the lookup table and the results of the preprocessing calculation.

[0010] The sine and cosine waveform values ​​are modulated with the input signal to obtain the DDS signal.

[0011] Preferably, the frequency control word consists of three parts: FTW, A, and B, i.e.: Frequency control word = FTW, A, and B are all values ​​of the frequency setting registers, each with a data width of 48 bits, enabling frequency generation at any ratio; phase control word DDSC_NCO_PHASE_OFFEST is the register value for setting the phase offset.

[0012] Preferably, the specific process of dividing the output frequency includes: under the premise of setting the frequency control word, accumulating and counting the frequency control word through an accumulator, and sampling the 32 frequency division branches respectively using a clock and a phase offset according to the accumulated count value.

[0013] Preferably, the binary radian data is divided into four parts based on the high 3 bits, wherein the phase data involved in the CORDIC optimization algorithm calculation is the low 14 bits.

[0014] Preferably, the CORDIC optimization algorithm selects the rotation direction based on the bit values ​​of its own binary data, wherein the bit values ​​of the binary data are represented as follows:

[0015] ;

[0016] in This represents the input binary data in radians. It is a constant. .

[0017] Preferably, the CORDIC optimization algorithm first uses... Begin coordinate rotation, then determine the rotation direction based on the bit values ​​of the binary data, and rotate by angle sequentially. angle.

[0018] Preferably, the CORDIC optimization algorithm specifically includes:

[0019] The high-order binary data is used as the address for the lookup table. The addressing depth is determined by the bit width of the high-order binary data input. That is, the bit value of the binary data corresponding to k is less than or equal to N / 3, and the lookup table is used to perform the calculation process.

[0020] The remaining binary data in the lookup table are preprocessed and calculated. The preprocessing calculation method includes: counting whether the bit value of the binary data corresponding to k is greater than N / 2 is 1, and selecting all 1s or all 0s for preprocessing calculation based on the count value.

[0021] The butterfly algorithm is used to calculate the bit values ​​of the binary data when k is in the range of N / 3 to N / 2.

[0022] Preferably, the preprocessing calculation based on the count value to select all 1s or all 0s includes: when the count value is greater than N / 4, performing an all-1 calculation on the bit values ​​of the binary data corresponding to k being greater than N / 2 in the lookup table, and compensating for the operation of bit values ​​being 0; when the count value is less than N / 4, performing an all-0 calculation on the bit values ​​of the binary data corresponding to k being greater than N / 2 in the lookup table, and compensating for the operation of bit values ​​being 1.

[0023] The present invention also provides a DDS signal implementation system based on the CORDIC optimization algorithm, which adopts a DDS signal implementation method based on the CORDIC optimization algorithm as described above.

[0024] Preferably, a DDS signal implementation system based on the CORDIC optimization algorithm includes:

[0025] An accumulator is used to accumulate and count the frequency control word.

[0026] The phase offset module is used to offset the phase.

[0027] The frequency divider module is used to divide the output frequency to form 32 frequency divider branches;

[0028] The quadrant mapping module is used to map the phase to the first quadrant;

[0029] The CORDIC optimization algorithm module includes a lookup table module, a butterfly algorithm calculation module, an angle compensation module, and a counter. The lookup table module is used to perform lookup table operations on the high-order data, the butterfly algorithm calculation module is used to perform butterfly algorithm operations on the middle-order data, the angle compensation module is used to perform operations to compensate for bit values ​​of 0 and 1, and the counter is used to count whether the bit value of the binary data is 1.

[0030] The modulation module is used to modulate the sine and cosine waveform values ​​output by the CORDIC optimization algorithm module with the input signal to obtain a DDS signal;

[0031] The selector is used to select the output of the DDS signal from the modulation module.

[0032] Compared with the prior art, the present invention has the following beneficial effects:

[0033] This invention employs a controllable frequency word generation method, which can generate waveforms of arbitrary frequencies. It differs from the conventional CORDIC algorithm by using non-special angle rotation, thus saving hardware design resources. Furthermore, it optimizes the conventional CORDIC algorithm by adding pre-processing and post-compensation, significantly reducing hardware overhead and latency. The invention also optimizes the output sequence by setting frequency and phase control words, dividing the output sequence by 32, spacing it by one frequency word, mapping the phase to the first quadrant, performing a lookup table and pre-calculation on the high-order data, and then performing butterfly algorithm operations and compensation based on the lookup table results. Attached Figure Description

[0034] Figure 1 The flowchart illustrates the DDS signal implementation method based on the CORDIC optimization algorithm provided by this invention.

[0035] Figure 2 The CORDIC butterfly calculation vector diagram provided by this invention.

[0036] Figure 3 This is a structural block diagram of the CORDIC optimization algorithm provided by the present invention.

[0037] Figure 4 A flowchart of the CORDIC optimization algorithm provided by this invention.

[0038] Figure 5 The structural block diagram of the preprocessing calculation provided by the present invention. Detailed Implementation

[0039] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0040] like Figure 1 As shown in the figure, this invention specifically discloses a DDS signal implementation method based on the CORDIC optimization algorithm, including the following steps:

[0041] The frequency control word and phase control word of the DDS circuit are set to calibrate the output frequency;

[0042] The output frequency is divided to form 32 frequency division branches, with a frequency control word between each two adjacent frequency division branches;

[0043] Phase mapping is performed on the first quadrant, which means mapping the binary radian data input from each frequency division branch to the first quadrant.

[0044] The CORDIC optimization algorithm is used to calculate the sine and cosine waveform values ​​of the corresponding frequencies. The CORDIC optimization algorithm includes: performing a lookup table on the high-order data and preprocessing the low-order data; performing butterfly algorithm operation on the middle-order data and rotation compensation on the low-order data based on the lookup table and the results of the preprocessing calculation.

[0045] The sine and cosine waveform values ​​are modulated with the input signal to obtain the DDS signal.

[0046] like Figure 2 As shown, the rotation step calculation method used in this design is the butterfly calculation method. For example, the initial vector is A0(x a ,y a After rotating by an angle θ, we obtain the vector B0(x). b ,y b The calculation process is as follows:

[0047]

[0048] like Figure 3 and Figure 4 As shown, the DDS signal implementation method based on the CORDIC optimization algorithm of this invention first requires setting the frequency control word corresponding to the target frequency. The control word consists of three parts: FTW, A, and B. FTW corresponds to the main frequency components, while A and B are used for frequency fine-tuning to achieve the purpose of synthesizing arbitrary frequencies. After the frequency control word is set, it enters the accumulator. The accumulator outputs phase information when accumulating the frequency control word. The frequency calculation formula has two modes, and the specific calculation methods are as follows:

[0049] Mode 1: Enable modulus:

[0050] Mode 2: Disable modulus:

[0051] in: It is the generation frequency of DDS; This is the reference clock frequency of the DDS; in the main channel DDS circuit, the reference clock here is the DAC clock; m is the DDS frequency to be set; n is the system reference frequency; X is the configured FTW register value; A and B are the configured register values ​​respectively; N is the bit width of the frequency control word; after the phase information is output, the phase offset needs to be configured. The phase offset calculation formula is as follows:

[0052]

[0053] After the phase offset information is increased, frequency division processing is performed, resulting in a total of 32 branches. Each pair of branches is separated by a frequency control word, thereby reducing the system's processing frequency and power consumption.

[0054] Continue reading Figure 4 The following is a flowchart of the optimized CORDIC algorithm of this invention. The specific implementation steps are as follows:

[0055] Perform binary radian data input for each branch Mapping can be achieved by removing the high-order bits, as follows:

[0056] First, remove the highest-order bit. Based on the characteristics of sine and cosine curves, the data will be evenly distributed around the X-axis. Therefore, for complete sine and cosine values, we can focus only on the upper half of the X-axis data; the lower half is the inverse of the upper half. Secondly, based on the values ​​of the second-highest and second-highest bits, we can choose different... The results of sine and cosine calculations are used to generate values ​​for the remaining quadrants, which reduces the number of subsequent calculations and the circuit area.

[0057] CORDIC calculations are performed using the mapped radian data. The angle rotation formula for the standard CORDIC algorithm is: Therefore, it should be in Small enough hour, Therefore, this part can be replaced by a lookup table to save hardware resources.

[0058] First, the high-order bits are used as the address for lookup table calculation. The addressing depth is determined by the width of the high-order bits of the input binary data; here, k ≤ N / 3. The formula for calculating the lookup table value is as follows:

[0059]

[0060]

[0061] Furthermore, the CORDIC optimization algorithm does not select... Rotation is not performed at a special angle, but rather the direction of rotation is selected based on whether its binary bit value is 0 or 1. The binary data representation is as follows:

[0062]

[0063]

[0064] in This represents the input binary data in radians. It is a constant. .

[0065] Based on the bit count of the lower N / 2 radian values, as follows: Figure 5The structure shown is preprocessed. The preprocessing calculation method includes the following: First, the binary bit values ​​of the part k > N / 2 need to be counted. The counting target is the number of bits with 1s greater than N / 2. When the count is greater than N / 4, the data bit values ​​of the part k > N / 2 are pre-calculated in the lookup table, with all bits counted as 1s. When k > N / 2, the 0s are doubled. When the count is less than N / 4, the data bit values ​​of the part k > N / 2 are pre-calculated in the lookup table, with all bits counted as 0s. When k > N / 2, the 1s are doubled. This reduces the number of operations for summing the data bit values ​​of the part k > N / 2 by more than half.

[0066] Further, based on the high-order lookup table and the results of preprocessing calculations, the middle value is calculated using a standard butterfly algorithm, as follows:

[0067]

[0068] in , This represents the vector coordinates obtained in the previous calculation. , Indicates rotation angle The obtained vector coordinates.

[0069] Further rotation compensation for low-order values: It is worth noting that in this embodiment of the invention, since the low-order data has been preprocessed and calculated beforehand, the low-order data here needs to be doubled. The compensation is based on the result of counting the low-order values. If the count is greater than N / 4, then double the 0 value needs to be compensated. If the count is less than N / 4, then double the 1 value needs to be compensated.

[0070] As a further explanation of the CORDIC optimization algorithm in this embodiment of the invention, this embodiment also specifically provides a technical solution with phase N=14, wherein the iterative calculation of angle rotation includes the following steps:

[0071] 1) Use the high 5 bits of data to design a lookup table to replace the conventional butterfly operation, and perform preprocessing calculations;

[0072] 2) Take the 10th bit and the 9th bit data and perform a regular butterfly operation;

[0073] 3) Perform angle compensation on the remaining 7 bits.

[0074] To better realize the present invention, step 1) further includes the following steps:

[0075] Based on the bit width of the initial phase data, the required lookup table bit value is calculated to be 5 bits. A lookup table with a depth of 32 is created. The content of the lookup table is the coordinate value after clockwise or counterclockwise rotation based on the corresponding bit value.

[0076] While performing a lookup table on the high 5 bits, the number of bits with a value of 1 in the low 7 bits is counted. If the number of bits with a value of 1 in the low 7 bits is greater than 3, then all bits with a value of 1 are pre-calculated in the low 7 bits during the preprocessing calculation stage. If the number of bits with a value of 1 in the low 7 bits is less than or equal to 3, then all bits with a value of 0 are pre-calculated in the preprocessing calculation stage.

[0077] To better realize the present invention, step 2) further includes the following steps:

[0078] 2-1) Based on the value of the 10th bit, if it is 0, rotate clockwise; if it is 1, rotate counterclockwise. The rotation is measured in radians. ;

[0079] 2-2) Based on the value of the 9th bit, if it is 0, rotate clockwise; if it is 1, rotate counterclockwise. The rotation is measured in radians. ;

[0080] 2-3) The formula for the butterfly algorithm is:

[0081] .

[0082] Angle compensation is performed on the remaining 7 bits of data. Since the lower 7 bits of data were pre-calculated as either all 1s or all 0s in step 1), but the actual lower 7 bits of data cannot be guaranteed to be all 1s or all 0s, compensation is still needed based on the lower 7 bits of data in addition to the pre-processing calculation. The compensation steps are as follows:

[0083] If the number of 1s in the lower 7 bits is greater than 3, all-1 preprocessing will be performed in the preprocessing stage, that is, assuming that all 7 bits in the lower 7 bits are 1. Therefore, in the compensation stage, the bits that were originally 0 need to be compensated in and doubled.

[0084] If the number of 1s in the lower 7 bits is less than 3, all-zero preprocessing will be performed in the preprocessing stage, that is, assuming that all 7 bits in the lower 7 bits are 0. Therefore, in the compensation stage, the bits that were originally 1 need to be compensated in, and double compensation will be performed.

[0085] This invention also discloses a DDS signal implementation system based on the CORDIC optimization algorithm, comprising:

[0086] An accumulator is used to accumulate and count the frequency control word.

[0087] The phase offset module is used to offset the phase.

[0088] The frequency divider module is used to divide the output frequency to form 32 frequency divider branches;

[0089] The quadrant mapping module is used to map the phase to the first quadrant;

[0090] The CORDIC optimization algorithm module includes a lookup table module, a butterfly algorithm calculation module, an angle compensation module, and a counter. The lookup table module is used to perform lookup table operations on the high-order data, the butterfly algorithm calculation module is used to perform butterfly algorithm operations on the middle-order data, the angle compensation module is used to perform operations to compensate for bit values ​​of 0 and 1, and the counter is used to count whether the bit value of the binary data is 1.

[0091] The modulation module is used to modulate the sine and cosine waveform values ​​output by the CORDIC optimization algorithm module with the input signal to obtain a DDS signal;

[0092] The selector is used to select the output of the DDS signal from the modulation module.

[0093] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for implementing DDS signals based on the CORDIC optimization algorithm, characterized in that, include: The frequency control word and phase control word of the DDS circuit are set to calibrate the output frequency; The output frequency is divided to form 32 frequency division branches, with a frequency control word between each two adjacent frequency division branches; Phase mapping is performed on the first quadrant, which means mapping the binary radian data input from each frequency division branch to the first quadrant. The sine and cosine waveform values ​​for the corresponding frequencies are calculated using the CORDIC optimization algorithm; The CORDIC optimization algorithm includes: performing a lookup table on the high-order data and preprocessing the low-order data; performing butterfly algorithm operations on the middle-order data and rotation compensation on the low-order data based on the lookup table and the results of the preprocessing calculation; The sine and cosine waveform values ​​are modulated with the input signal to obtain the DDS signal; The CORDIC optimization algorithm selects the rotation direction based on the bit values ​​of its own binary data, where the bit values ​​of the binary data are represented as follows: ； in This represents the input binary data in radians. It is a constant. ; The CORDIC optimization algorithm specifically includes: The high-order binary data is used as the address for the lookup table. The addressing depth is determined by the bit width of the high-order binary data input. That is, the bit value of the binary data corresponding to k is calculated by replacing it with a lookup table. The remaining binary data in the lookup table are preprocessed and calculated. The preprocessing calculation method includes: counting whether the bit value of the binary data corresponding to k is greater than N / 2 is 1, and selecting all 1s or all 0s for preprocessing calculation based on the count value. Perform a butterfly algorithm to calculate the bit values ​​of the binary data corresponding to k when it is in the range of N / 3 to N / 2; The preprocessing calculation based on the count value to select all 1s or all 0s includes: when the count value is greater than N / 4, performing an all-1 calculation on the bit values ​​of the binary data corresponding to k being greater than N / 2 in the lookup table, and compensating for the operation of bit values ​​being 0; when the count value is less than N / 4, performing an all-0 calculation on the bit values ​​of the binary data corresponding to k being greater than N / 2 in the lookup table, and compensating for the operation of bit values ​​being 1.

2. The DDS signal implementation method based on the CORDIC optimization algorithm as described in claim 1, characterized in that, The frequency control word consists of three parts: FTW, A, and B, i.e.: Frequency control word = FTW, A, and B are all values ​​of the frequency setting registers, each with a data width of 48 bits, enabling frequency generation at any ratio; phase control word DDSC_NCO_PHASE_OFFEST is the register value for setting the phase offset.

3. The DDS signal implementation method based on the CORDIC optimization algorithm as described in claim 1, characterized in that, The specific process of dividing the output frequency includes: under the premise of setting the frequency control word, the frequency control word is accumulated and counted by an accumulator, and the 32 frequency division branches are sampled by using a clock and a phase offset according to the accumulated count value.

4. The DDS signal implementation method based on the CORDIC optimization algorithm as described in claim 1, characterized in that, The binary radian data is divided into four parts based on the high 3 bits, of which the phase data involved in the CORDIC optimization algorithm calculation is the low 14 bits.

5. The DDS signal implementation method based on the CORDIC optimization algorithm as described in claim 1, characterized in that, The CORDIC optimization algorithm first uses... Begin coordinate rotation, then determine the rotation direction based on the bit values ​​of the binary data, and rotate by angle sequentially. angle.

6. A DDS signal implementation system based on the CORDIC optimization algorithm, characterized in that, The method for implementing DDS signals based on the CORDIC optimization algorithm as described in any one of claims 1 to 5 is adopted.

7. The DDS signal implementation system based on the CORDIC optimization algorithm as described in claim 6, characterized in that, include: An accumulator is used to accumulate and count the frequency control word. The phase offset module is used to offset the phase. The frequency divider module is used to divide the output frequency to form 32 frequency divider branches; The quadrant mapping module is used to map the phase to the first quadrant; The CORDIC optimization algorithm module includes a lookup table module, a butterfly algorithm calculation module, an angle compensation module, and a counter. The lookup table module is used to perform lookup table operations on the high-order data, the butterfly algorithm calculation module is used to perform butterfly algorithm operations on the middle-order data, the angle compensation module is used to perform operations to compensate for bit values ​​of 0 and 1, and the counter is used to count whether the bit value of the binary data is 1. The modulation module is used to modulate the sine and cosine waveform values ​​output by the CORDIC optimization algorithm module with the input signal to obtain a DDS signal; The selector is used to select the output of the DDS signal from the modulation module.

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