Data processing device, data processing method, and electronic device

Abstract

The application discloses a data processing device, a data processing method and an electronic equipment, relates to the technical field of data processing, and the data processing device comprises a physical layer memory and a data receiving module connected with the physical layer memory; the physical layer memory is configured with a primitive power table and a forward error correction storage table, the data receiving module comprises a check matrix unit and an error correction unit, after receiving a first code word, the check matrix unit determines whether a plurality of first data symbols exist errors and a first error position according to the primitive power table and a plurality of first check symbols, and after receiving the first error position, the error correction unit finds a corresponding first error correction result from the forward error correction storage table according to the first error position, and updates the first code word according to the first error correction result. In the error correction process, the error correction structure is determined by table lookup, a series of calculation processes are omitted, the error correction delay can be compressed to the nanosecond level, and the real-time demand of transmission is better met.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data processing, and in particular to a data processing device, a data processing method and an electronic device. BACKGROUND

[0002] With the increasing of the bus rate of computer system interconnection, the signal integrity problem is increasingly prominent. In order to ensure the reliability of data transmission, the bus introduces the error correction mechanism of forward error correction (FEC). The feature of forward error correction is that the sending end embeds additional redundant check information (error correction code) in the data, so that the receiving end can automatically detect and repair part of the errors generated in transmission through the error correction code without requesting retransmission from the sending end.

[0003] Although the forward error correction technology improves the reliability of the high-speed bus, the complex error correction mechanism also brings an unavoidable delay overhead, which becomes a key factor restricting the performance of the bus. Specifically, the coding and decoding in the forward error correction technology have high computational complexity. Taking Reed-Solomon (RS) code as an example, the decoding process involves matrix operations, iterative checks and other steps, and the hardware implementation still needs multiple clock cycles to complete. SUMMARY

[0004] The present application provides a data processing device, a data processing method and an electronic device to improve the problem of high delay in the error correction process of the related art.

[0005] The present application provides a data processing device, which comprises a physical layer memory and a data receiving module connected with the physical layer memory.

[0006] The physical layer memory is configured with a primitive element power table and a forward error correction storage table, and the data receiving module comprises a check matrix unit and an error correction unit, wherein the forward error correction storage table is used to represent the correspondence between a plurality of error positions and a plurality of error correction results.

[0007] The check matrix unit is used to receive at least one first code word, wherein the first code word comprises a plurality of first data symbols and a plurality of first check symbols.

[0008] The check matrix unit is further used to determine whether the plurality of first data symbols have errors and the first error position according to the primitive element power table and the plurality of first check symbols, and to send the first error position to the error correction unit when it is determined that there are errors.

[0009] The error correction unit is used to find the corresponding first error correction result from the forward error correction storage table according to the first error position, and to update the first code word according to the first error correction result.

[0010] The application further provides a data processing method, which comprises the following steps:

[0011] receiving at least one first codeword, wherein the first codeword comprises a plurality of first data symbols and a plurality of first check symbols;

[0012] determining whether the plurality of first data symbols have errors and a first error position according to the primitive power table and the plurality of first check symbols obtained from the physical layer memory;

[0013] finding a corresponding first error correction result from the forward error correction storage table stored in the physical layer memory according to the first error position;

[0014] updating the first codeword according to the first error correction result.

[0015] The application further provides an electronic device comprising the data processing apparatus provided in any of the above embodiments.

[0016] The data processing apparatus provided by the application, after the check matrix unit receives the first codeword, determines whether the plurality of first data symbols have errors and a first error position according to the primitive power table and the plurality of first check symbols, and sends the first error position to the error correction unit when it is determined that there are errors, and the error correction unit finds a corresponding first error correction result from the forward error correction storage table according to the first error position after receiving the first error position, and updates the first codeword according to the first error correction result. The application completes the error correction process by setting the check matrix unit and the error correction unit, and determines the error correction result by the table lookup method in the error correction process, which omits a series of calculation processes, can compress the FEC error correction delay to the nanosecond level, and better meets the real-time demand of transmission. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the application, the drawings needed in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0018] Figure 1 a structural schematic diagram of a data processing apparatus provided by the embodiments of the application;

[0019] Figure 2 a structural schematic diagram of a check matrix unit provided by the embodiments of the application;

[0020] Figure 3 a framework schematic diagram of an error correction training storage provided by the embodiments of the application;

[0021] Figure 4A flowchart of error correction training storage provided by the embodiment of the present application is shown in the figure;

[0022] Figure 5 A logic diagram of error correction lookup table provided by the embodiment of the present application is shown in the figure;

[0023] Figure 6 A structure diagram of another data processing device provided by the embodiment of the present application is shown in the figure;

[0024] Figure 7 A structure diagram of another data processing device provided by the embodiment of the present application is shown in the figure;

[0025] Figure 8 A structure diagram of an encoder provided by the embodiment of the present application is shown in the figure;

[0026] Figure 9 A structure diagram of a forward error correction architecture provided by the embodiment of the present application is shown in the figure;

[0027] Figure 10 A flowchart of a data processing method provided by the embodiment of the present application is shown in the figure.

[0028] Reference signs: 100, data processing device; 110, physical layer memory; 111, primitive power table; 112, forward error correction storage table; 120, data receiving module; 121, check matrix unit; 1211, first multiplier; 1212, accumulator; 122, error correction unit; 123, level demodulation unit; 124, data output unit; 130, data sending module; 131, data receiving unit; 132, encoder; 1321, data grouping unit; 1322, second multiplier; 1323, polynomial generator; 1324, check symbol adding unit; 133, level modulation unit. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0030] It should be noted that in the description of the present application, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or inherent to such a process, method, article or device. The terms "first", "second" and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0031] With the rapid development of technologies such as cloud computing, distributed storage and big data analysis, higher requirements are put forward for the bus rate of computer system interconnection. Based on this demand, semiconductor technology continues to evolve to promote the improvement of high-speed bus performance. Taking the high-speed serial computer expansion (Peripheral Component Interconnect express, PCIe) bus as an example, the transmission rate of the bus has jumped from 8 GT / s of PCIe 3.0 to 64 GT / s of PCIe 6.0, that is, the transmission rate of the bus has realized an 8-fold performance leap.

[0032] Among them, PCIe is a high-speed serial bus standard used to connect various peripherals and expansion cards inside a computer. PCIe provides a high-bandwidth, low-latency data transmission method and is widely used in desktop computers, servers, network devices and other fields.

[0033] In the process of technology evolution, the improvement of bus transmission rate makes the signal integrity problem more prominent. In order to ensure the reliability of data transmission, it is necessary to solve the problems of high-frequency signal attenuation and crosstalk in the transmission process. Therefore, the bus needs to introduce error correction mechanism, and at the same time needs to balance the delay problem introduced by error correction.

[0034] The traditional non-return-to-zero (Non Return to Zero, NRZ) level and error retransmission error correction mechanism is constrained by the Shannon limit, and gradually faces a bottleneck with the continuous improvement of bus transmission rate. For example, when the NRZ signal reaches a rate of 56 Gbps or more, its channel insertion loss is greater than 36 dB (Nyquist frequency 28 GHz), and the inter-symbol interference (Inter-Symbol Interference, ISI) causes the eye diagram to close, prompting the physical layer to switch to multi-level modulation technologies such as 4-level pulse amplitude modulation (4-Level Pulse Amplitude Modulation, PAM4).

[0035] In digital communication, binary data needs to be converted into physical level signals before transmission in the channel. The logic of NRZ encoding is to use two different fixed levels to represent binary 0 and 1 respectively, and the level remains unchanged throughout the bit period and does not return to zero level. Shannon limit is a channel capacity formula proposed by Claude Shannon, which defines the maximum error-free transmission rate that a communication channel can achieve under a given bandwidth and noise level, and is the physical upper limit of all wired / wireless communications. PAM4 encoding represents binary data through 4 different signal levels, thereby achieving higher transmission rate than traditional 2-level modulation (such as NRZ) under the same channel bandwidth.

[0036] However, PAM4 requires a higher signal-to-noise ratio, resulting in a significant deterioration of the bit error rate (BER). For example, the typical value of PCIe bus increases from 1E-12 of PCIe 5.0 NRZ level BER to 1E-6 of PCIe 6.0 PAM4 level BER. In addition, the signal integrity challenge under ultra-high speed requires that the error correction delay be compressed to the nanosecond level, and the traditional error correction scheme based on retransmission or software post-processing cannot meet the demand.

[0037] BER is the ratio of the number of bits that occur errors during transmission to the total number of transmitted bits within a sampling period. BER is used to reflect the degree of influence of interference, noise and other factors on the signal during transmission, processing or storage, and is an index for measuring the reliability and transmission quality of data transmission link. The smaller the BER value, the stronger the anti-interference ability of the communication system and the more stable the transmission quality.

[0038] In related technologies, in order to ensure error correction capability while meeting real-time requirements, a forward error correction (FEC) error correction mechanism is introduced in bus transmission. The principle of FEC is that the sending end adds redundant check information (error correction code) to the original data before transmission through a specific encoding algorithm; after the receiving end receives the data stream containing redundant information, it can automatically detect the errors caused by noise, interference, etc. during data transmission without requesting retransmission from the sending end, and correct most of the errors, thereby improving the reliability of data transmission.

[0039] However, as mentioned in the background, the decoding in FEC requires multiple iterations (such as companion calculation, key equation solving, etc.), which has high computational complexity, resulting in still large error correction delay.

[0040] Therefore, the data processing apparatus, the data processing method and the electronic device provided in the present application split the process of FEC decoding into multiple independent hardware circuits (a check matrix unit and an error correction unit) instead of software, and when it is determined that the received data has errors, the error correction result is determined by looking up a table, thereby omiting the calculation process of locating errors and determining error values, and the error correction delay can be compressed to the nanosecond level, thereby better meeting the real-time requirements of transmission.

[0041] In order to enable those skilled in the art to better understand the present application, the present application will be further described in detail below in combination with the drawings and specific embodiments.

[0042] As shown in the Figure 1 , the data processing apparatus 100 provided in the present application is arranged in the bus physical layer of the receiving end. Specifically, at least two communication devices are connected through the bus and transmit data through the bus. The sending end is a communication device that sends data outward during the data transmission process, and the receiving end is a communication device that receives data during the data transmission process. The communication device can be a computer device, a server or a computer device.

[0043] The data processing apparatus provided in the present application can be applied to a communication device connected by a PCIe 6.0 bus.

[0044] When transmitting information through the transmission channel formed by the bus at the sending end, due to the influence of factors such as interference and noise, the data received by the bus physical layer of the receiving end can have errors. The data processing apparatus 100 is used to determine whether the received data has errors after receiving the data, and correct the errors when there are errors.

[0045] The data processing apparatus 100 includes a physical layer memory 110 and a data receiving module 120, and the data receiving module 120 is connected with the physical layer memory 110. The physical layer memory 110 is configured with a primitive power table 111 and a forward error correction storage table 112, and the data receiving module 120 includes a check matrix unit 121 and an error correction unit 122.

[0046] The forward error correction storage table is used to represent the correspondence between a plurality of error positions and a plurality of error correction results. The plurality of error positions and the plurality of error correction results are one-to-one corresponding. The forward error correction storage table can include a mapping relationship between the error position and the physical address. The physical address is the address of the error correction result corresponding to the error position in the physical layer memory 110.

[0047] The primitive element is a non-zero element in the Galois field (Galois Field, GF), which is also called a finite field. The finite field contains elements, is a positive integer, non-zero elements in the element One, the original element A power of can generate all non-zero elements in a finite field. A Galois field is a type of field structure in algebra with a finite number of elements. A field is a mathematical structure that contains a set of elements and two basic operations (addition and multiplication).

[0048] Primitive power tables are used to represent the power form of primitives. The correspondence between the polynomial (or numerical) forms of elements of a finite field and their corresponding forms. , The primitive power table can associate the power of a primitive (the basis for generating all non-zero elements) with the specific representation of the element (polynomial, binary value), and is a key tool for simplifying addition and multiplication operations in finite fields.

[0049] The verification matrix unit 121 is used to receive at least one first codeword, which is the data to be transmitted after being processed by an encoder (such as an RS encoder). The first codeword is the codeword received by the verification matrix unit 121 of the receiving end from the encoder of the transmitting end.

[0050] The first codeword comprises multiple first data symbols and multiple first check symbols. A symbol can consist of several consecutive binary bits and is the basic unit of data processing. The first data symbol refers to the received symbol carrying the original information to be transmitted from the sending end. The first check symbol refers to the received redundant symbol calculated by the encoder based on the data symbols and a preset mathematical algorithm (such as polynomial operations or linear algebra operations). The first check symbol is the basis for determining whether there are errors in the first data symbols and also the basis for correcting erroneous first data symbols.

[0051] The verification matrix unit 121 is also used to determine whether there are errors in multiple first data symbols and the first error position according to the primitive power table 111 and multiple first verification symbols, and to send the first error position to the error correction unit 122 when it is determined that there are errors in the first codeword.

[0052] Specifically, the check matrix unit 121 determines multiple syndromes (checkers) based on the primitive power table 111 and multiple first check symbols, with each syndrome corresponding to a first check symbol. When all syndromes are 0, the check matrix unit 121 can determine that the multiple first data symbols corresponding to the first codeword are normal (i.e., there are no errors); when any syndrome is not 0, the check matrix unit 121 can determine that multiple first data symbols have errors, and determines the number of bits (positions) of the first check symbol corresponding to the non-zero syndrome as the first error position. The number of first error positions can be one or more.

[0053] In error correction coding, syndrome is a key tool for detecting and locating transmission errors, and its essence is a mathematical representation of the difference between received data and ideal error-free data. By calculating the syndrome, the check matrix unit 121 can determine whether the data is incorrect and further determine the location and size of the error, providing a basis for error correction.

[0054] The calculation of the syndrome relies on the power representation of the elements of the finite field. Compared with the software calculation of the power representation of the elements, the application can determine the power representation of the elements by accessing the primitive element power table 111 in the physical layer memory 110, which omits the calculation process and speeds up the process of determining the syndrome by the check matrix unit 121.

[0055] The error correction unit 122 is configured to find the first error correction result corresponding to the first error position from the forward error correction storage table 112 and update the first codeword according to the first error correction result. The first error correction result includes the position of the first data symbol of the error indicated by the first error position and the correction amount corresponding to the first data symbol of the error.

[0056] Specifically, after receiving the first error position, the error correction unit 122 accesses the forward error correction storage table 112 in the physical layer memory 110, determines the same error position as the first error position (denoted as the target error position) from the preset plurality of error positions, and determines the error correction result corresponding to the target error position in the forward error correction storage table 112 as the first error correction result. Then, according to the correction amount in the first error correction result, the first data symbol of the error is corrected to obtain the updated first codeword.

[0057] In the traditional FEC decoding process, if the syndrome is not 0, not only is it necessary to locate which data symbols in the codeword have errors by the Berlekamp-Massey algorithm or other algorithms, but also it is necessary to calculate the error value of each error data symbol by the Forney algorithm or other algorithms, and then correct the error data symbol according to the error value. However, in the present application, after determining that the syndrome is not 0, the error correction result can be directly determined by table lookup (forward error correction storage table 112), which omits a series of calculation processes and reduces the delay to 1-2 clock cycles.

[0058] The Berlekamp-Massey algorithm is an efficient algorithm for solving the shortest linear recurrence relation from a sequence, which can quickly find the shortest linear feedback shift register (LFSR) generating the sequence (such as the syndrome of error correction code) when the sequence is known, and provides a key basis for error location and correction. The Forney algorithm is used to quickly calculate the specific amplitude (error value) of the error in the error correction code under the premise of knowing the error location polynomial and the syndrome, and finally complete the error correction.

[0059] It should be noted that the above delay (1-2 clock cycles) is not a fixed value, but depends on the read / write speed of the physical layer memory 110 itself.

[0060] The data processing apparatus provided in the present application, the check matrix unit 121 determines whether the plurality of first data symbols exist errors and the first error position according to the primitive element power table 111 and the plurality of first check symbols after receiving the first codeword, and sends the first error position to the error correction unit 122 when it is determined that there is an error, and the error correction unit 122 finds the corresponding first error correction result from the forward error correction storage table 112 according to the first error position after receiving the first error position, and updates the first codeword according to the first error correction result. The present application completes the error correction process by setting the check matrix unit 121 and the error correction unit 122, and determines the error correction result by table lookup method in the error correction process, which omits a series of calculation process, can compress the FEC error correction delay to nanosecond level, and better meet the real-time demand of transmission.

[0061] For example, the check matrix unit 121 can include a first multiplier and an accumulator.

[0062] Specifically, the first multiplier is used to perform multiplication operation on the target polynomial corresponding to the target codeword and the check matrix of the check matrix to obtain a plurality of multiplication results, and send the plurality of multiplication results to the accumulator. Wherein, the target codeword is one of the at least one first codeword, the check matrix is determined based on the primitive element power table 111 and the target check symbol, and the target check symbol is one of the plurality of first check symbols in the target codeword.

[0063] The accumulator is used to accumulate the plurality of multiplication results to determine the target check sub. When the target check sub is not 0, it is determined that the first data symbol in the target codeword exists error, and the first error position is the bit number corresponding to the target check symbol. The accumulator is also used to determine that the first data symbol in the target codeword is normal when the target check sub corresponding to the plurality of first check symbols is 0.

[0064] Optionally, the expression of the target check sub can be as shown in formula (1):

[0065]

[0066] in, Indicates the target checker. , This indicates the number of first check symbols in the target codeword. This represents the target polynomial corresponding to the target codeword. Represents the fundamental element of the Galois domain. , H represents the parity check matrix. This represents the total number of first data symbols and first check symbols in the target codeword. For example, if the number of first data symbols is... ,but The parity-check matrix H is a A 3D matrix.

[0067] The target polynomial corresponding to the target codeword can be , Indicates the number of bits in the sign. It also indicates the target code word. This represents a polynomial corresponding to multiple first data symbols. This represents a polynomial corresponding to multiple first check symbols.

[0068] Specifically, the accumulator can calculate the values ​​corresponding to multiple first check symbols in the first codeword. The value of any one If the first character contains an error and needs correction, then all... If the first character is correct (i.e., there is no error in the first character), then the first character is correct.

[0069] In some implementations, such as Figure 2 As shown, the number of first multipliers 1211 and the number of accumulators 1212 are the same as the number of first check symbols. Multiple first multipliers 1211 correspond one-to-one with multiple first check symbols, and multiple accumulators 1212 correspond one-to-one with multiple first multipliers 1211.

[0070] For example, if the number of the first check symbols is The number of the first multiplier 1211 is The number of accumulators 1212 is also... At this point, the check matrix unit 121 can be determined in parallel. The value of the checksum is increased, improving computational efficiency. Moreover, since the multipliers and accumulators occupy a small area, setting multiple first multipliers 1211 and multiple accumulators 1212 will not significantly affect the area occupied by the check matrix unit.

[0071] In other embodiments, the number of the first multipliers 1211 and the number of the accumulators 1212 can also be less than the number of the first check symbols, in which case, the values of the check subscripts are calculated in batches, saving the area occupied by the check matrix unit 121.

[0072] For example, the check matrix unit 121 is also configured to receive at least one second codeword formed by random data code before receiving the first codeword, wherein the second codeword includes a plurality of second data symbols and a plurality of second check symbols. The check matrix unit 121 is also configured to determine whether the plurality of second data symbols has errors and the second error positions according to the primitive power table 111 and the plurality of second check symbols, and to send the second error positions to the error correction unit 122 when it is determined that there are errors.

[0073] The error correction unit 122 is also configured to determine a second error correction result according to the second error positions, and to create a mapping relationship between the second error positions and the second error correction result to generate the forward error correction storage table 112, and to configure the forward error correction storage table 112 in the physical layer memory 110.

[0074] Specifically, the second codeword is similar to the first codeword, except that the second codeword is a codeword formed by the encoder based on random data code in a test scenario, and the first codeword is a codeword formed by the encoder based on data obtained from the data link layer in an application scenario. The calculation process of the encoder forming a codeword based on random data code is the same as the calculation process of the encoder forming a codeword based on data obtained from the data link layer.

[0075] The random data code is a Pseudo-Random Binary Sequence (PRBS), which is a binary digital sequence that appears random but has a deterministic generation rule. Using the reproducible pseudo-randomness of PRBS, real random data can be simulated, and PRBS can be generated through a Linear Feedback Shift Register (LFSR).

[0076] After receiving the second codeword, the check matrix unit 121 processes the second codeword in a similar manner to the first codeword. Specifically, the check matrix unit 121 first determines a plurality of check subscripts (H1, H2, …, Hn) according to the primitive power table 111 and the plurality of first check symbols, and the plurality of check subscripts and the plurality of second check symbols correspond one-to-one. At all times, the check matrix unit 121 can determine that the plurality of second data symbols corresponding to the second codeword are normal; when , the check matrix unit 121 can determine that the plurality of second data symbols have errors, and send the second error positions to the error correction unit 122. , the check matrix unit 121 can determine that the plurality of second data symbols have errors, and send the second error positions to the error correction unit 122.​​ determining the second error position.

[0077] After receiving the second error position, the error correction unit 122 can determine the second error correction result in a manner commonly used in the art, for example, after determining the second error position, the second error correction result corresponding to the second error position can be determined by the Berlekamp-Massey algorithm and the Forney algorithm.

[0078] The number of times of transmitting the random data code in the bus is multiple, so as to obtain a plurality of second error positions and a second error correction result of each second error position, and a mapping relationship between the plurality of created second error positions and the plurality of second error correction results is determined as the forward error correction storage table.

[0079] That is to say, after the data processing apparatus 100 is arranged at the physical layer of the bus, the random data code is first transmitted in the bus to perform bus data transmission training, and after the plurality of second error positions and the corresponding second error correction results are counted to form the forward error correction storage table 112, the real data is then transmitted in the bus, and the delay overhead of the forward error correction process on the bus is reduced by the lookup table method.

[0080] Specifically, the inventors have found through research that the errors in the transmission path of the bus (i.e., the errors of the data received by the receiving end) are mainly caused by the physical properties of the link, such as the semiconductor characteristics of the sending end and the receiving end, the physical medium properties in the transmission link, the code interference, or the power supply noise, etc. Therefore, after the interconnection channel between the receiving end and the sending end is established, the errors in data transmission are relatively fixed. The transmission link can refer to the transmission channel formed by the bus, and the physical medium of the transmission channel includes copper cable conductor, optical fiber or other medium.

[0081] Before transmitting the real data in the bus, the present application uses the random data code to perform data transmission training in the bus to obtain the forward error correction storage table. Since the errors in data transmission are relatively fixed, the determined forward error correction storage table is a customized storage table, which can more accurately reflect the possible errors of the bus of a specific data processing apparatus when transmitting real data, thereby improving the accuracy of the data processing apparatus in correcting errors.

[0082] Further, after determining the second error position, the check matrix unit 121 is further configured to store the number of times of errors of the second code word at the second error position, and configured to send the second error position to the error correction unit 122 when the number of times is greater than or equal to a preset number of times.

[0083] The preset number of attempts is the threshold for triggering entry into the forward error correction store. This preset number can be configured by the designer based on factors such as the depth of the forward error correction store and the probability of errors occurring. For example, the preset number of attempts could be 5 or 6.

[0084] The depth of the forward error correction memory table refers to the total number of rows of storage cells in the table. The depth of the forward error correction memory table reflects its storage capacity. The hardware area of ​​the physical layer memory is positively correlated with its storage capacity; the greater the depth, the greater the storage capacity, and the larger the hardware area of ​​the physical layer memory. The physical layer memory can be Static Random Access Memory (SRAM), a high-speed, volatile random access memory implemented using semiconductor circuits.

[0085] In this embodiment, the process of generating the forward error correction storage table in the physical layer memory can be as follows: Figure 3 and Figure 4 As shown, in the bus data transmission training, the transmitting end first sends PRBS training data that has undergone encoding and modulation processing, so that the parity check matrix unit 121 at the receiving end can receive at least one second codeword. Then, the parity check matrix unit 121 determines whether there is an error in the second codeword (i.e., determines the corresponding second parity symbols). (Whether it is 0). At that time, the second codeword is determined to be at the second error position by a counter. Number of errors and store To record the probability of the same error occurring; when all If the second codeword is found to be normal, then the next second codeword is re-evaluated for errors.

[0086] when When the number of times is greater than or equal to the preset number, The reflected second error location is sent to the error correction unit 122, which determines it. The corresponding second error correction result generates the second error location ( The forward error correction physical address mapping is performed, and a forward error correction memory table is generated and stored in the physical layer memory; when If the number of attempts is less than the preset number, continue to determine the corresponding second check symbols. The next one Is it 0? Where, in the determined... Under the value, generate Errors and targeting The error correction is fixed.

[0087] This embodiment is in After greater than or equal to a preset number of times, error correction calculation and storage are performed, which is equivalent to a lightweight processing of the forward error correction storage table, reduces the storage capacity of the forward error correction storage table, thereby reducing the occupied area of the forward error correction storage table, and reducing the design difficulty of the bus physical layer.

[0088] In the embodiment, the error correction process of the first codeword can be as shown in Figure 5 Specifically, after the check matrix unit 121 receives the first codeword that may contain errors, it is determined whether the first codeword is 0, and when , the first codeword is output to the error correction unit 122. The error correction unit 122 determines the address mapping logic (corresponding to the physical address) based on , and accesses the forward error correction storage table, finds the error correction logic (error correction result) from the forward error correction storage table based on the address mapping logic, and then updates the first codeword based on the error correction logic, and outputs the updated first codeword (i.e. corrected data). Specifically, the error correction processing through the lightweight forward error correction table can realize fast query of the error correction code while taking into account the storage capacity of the forward error correction lookup table, i.e. taking into account the reduction of the area occupied by the forward error correction storage table. i As shown in

[0089] , the data receiving module 120 further includes a level demodulation unit 123 connected with the bus. The level demodulation unit 123 is configured to receive the first physical signal transmitted by the bus, and convert the first physical signal into at least one first codeword, and send the at least one first codeword to the check matrix unit 121.

[0090] As shown in Figure 6 , the data receiving module 120 further includes a level demodulation unit 123 connected with the bus. The level demodulation unit 123 is configured to receive the first physical signal transmitted by the bus, and convert the first physical signal into at least one first codeword, and send the at least one first codeword to the check matrix unit 121.

[0091] Specifically, the sending end needs to convert the encoded data into a physical signal (such as an electrical signal) that can be transmitted in a physical medium before transmitting the encoded data to the bus. Correspondingly, the receiving end needs to perform level demodulation processing on the received physical signal to obtain the encoded data.

[0092] For example, the bus is a PCIe bus. When the bus is a PCIe bus, the demodulation processing of the level demodulation unit 123 is to map the received differential level signal into a first codeword.

[0093] In some embodiments, as shown in Figure 6 , the data receiving module 120 further includes a data output unit 124.

[0094] ​Specifically, the error correction unit 122 is also used to send the updated first codeword to the data output unit 124 after updating the first codeword. The data output unit 124 is used to extract multiple first data symbols from the updated first codeword and send the multiple first data symbols to the data link layer.

[0095] Meanwhile, the check matrix unit 121 is also used to send the first codeword to the data output unit 124 when it is determined that the first codeword is normal. The data output unit 124 is also used to extract multiple first data symbols from the first codeword and send the multiple first data symbols to the data link layer.

[0096] The data link layer is a key transition layer between the physical layer and the network layer in the layered architecture of computer networks. It is used to manage physical links and enable reliable data interaction between adjacent devices.

[0097] like Figure 7 As shown, the data processing device also includes a data transmission module 130 connected to the physical layer memory. The data transmission module 130 includes a data receiving unit 131, an encoder 132, and a level modulation unit 133.

[0098] The data receiving unit 131 receives raw data from the data link layer and sends the raw data to the encoder 132. The encoder 132 processes the raw data according to the primitive power table to form at least one third codeword, and sends the at least one third codeword to the level modulation unit 133. The level modulation unit 133 converts the at least one third codeword into a third physical signal and sends the third physical signal to the target device via a bus.

[0099] Specifically, the raw data can be the raw binary data bitstream of the input data receiving unit 131. The encoder can be an RS encoder, used to encode the raw binary data bitstream, converting it into codewords. For ease of distinction, the codewords obtained by the encoder 132 are denoted as the third codeword, which includes multiple third data symbols and multiple third check symbols. After obtaining the third codeword, it is converted into a third physical signal by the level modulation unit 133 and transmitted to the target device via a transmission channel formed by the bus. The target device is another communication device connected to the communication device where the data processing unit 100 is located. At this time, the communication device where the data processing unit 100 is located is the transmitting end, and the target device is the receiving end.

[0100] The process by which the level modulation unit 133 converts the third codeword into a third physical signal is determined by the physical level specified by the bus transmission protocol. For example, when the bus is a PCIe bus, since PCIe uses differential signal transmission, the level modulation unit 133 maps the third codeword into a differential level signal.

[0101] The bus physical layer of the embodiment is a full duplex resource including a data receiving module 120 (also referred to as a receiver) and a data sending module 130 (also referred to as a generator), the receiver and the generator can share a unified primitive power table, saving storage space, and also can make the layout of the data receiving module 120 and the data sending module 130 more reasonable, reducing the error probability.

[0102] As shown in the figure, the encoder 132 can include a data grouping unit 1321, a second multiplier 1322, a polynomial generator 1323 and a check symbol adding unit 1324. Figure 8

[0103] The data grouping unit 1321 is configured to divide the original data into at least one data group according to the number of third data symbols, and to send the at least one data group to the second multiplier 1322. The data group includes a plurality of third data symbols. For example, if the number of third data symbols is , the original data is divided into data groups of symbols each, and each symbol can include bits.

[0104] The second multiplier 1322 is configured to generate a check polynomial according to the bit number of the third data symbol, the number of third check symbols and the primitive power table, and to send the check polynomial and the data group to the polynomial generator 1323.

[0105] Specifically, the expression of the check polynomial can be as shown in formula (2):

[0106]

[0107] wherein, represents the check polynomial, represents the bit number of the symbol, represents the primitive element of the Galois field , and represents the number of third check symbols.

[0108] The expansion form of the check polynomial can be as shown in formula (3):

[0109]

[0110] wherein, represents the coefficient of the th term, represents the coefficient of the 1st term, is a constant.

[0111] ​The polynomial generator 1323 is configured to convert the data group into an information polynomial, generate an extended data polynomial according to the information polynomial and the number of third check symbols, and send the check polynomial and the extended data polynomial to the check symbol appending unit 1324.

[0112] Specifically, the expression of the information polynomial can be shown in formula (4), and the expression of the extended data polynomial can be shown in formula (5):

[0113]

[0114] wherein, represents the information polynomial, represents the coefficient of the i-th term, represents the number of third data symbols, is a constant, represents the extended data polynomial, and the check symbol bit is reserved.

[0115] The check symbol appending unit 1324 is configured to determine the third check symbol according to the extended data polynomial and the check polynomial, generate a third code word according to the third check symbol and the extended data polynomial, and send the third code word to the level modulation unit 133.

[0116] Specifically, the check symbol appending unit 1324 includes a linear feedback shift register (LFSR) which divides the extended data polynomial by the check polynomial to obtain a remainder polynomial, and the remainder polynomial is the third check symbol. At this time, represents the quotient polynomial.

[0117] wherein, the tap coefficient of the LFSR is determined by the coefficient of the check polynomial, and the register state is updated every time a symbol is input. The state flow of the LFSR is used to implicitly complete the division operation of the extended data polynomial and the check polynomial, and the efficiency is higher than that of the explicit polynomial division.

[0118] After the third check symbol is determined, the remainder polynomial is appended to the data group, and a complete code word with a length of can be obtained, and the polynomial form of the third code word can be

[0119] The data stream transmission process under the forward error correction architecture of the present application will be described in detail below with reference to the accompanying drawings.​​​​​​​​​​​

[0120] As shown in Figure 9 , first, the data receiving unit of the sending end bus physical layer receives the original binary data bit stream from the data link layer, and transmits the original binary data bit stream to the encoder. The encoder divides the input original binary data bit stream into data blocks of a fixed length (each block of symbols), and generates check symbols through finite field operation, appends the check symbols to the data blocks to form a code word of length , and then the encoder sends the code word of symbols to the level modulation unit. Among them, the code word can resist up to symbol errors.

[0121] The code word of symbols is converted into a physical signal by the level modulation unit and output to the transmission channel. The physical signal converted by the code word of symbols is transmitted to the data processing device of the receiving end bus physical layer through the transmission channel.

[0122] The level demodulation unit in the data processing device demodulates the received physical signal to obtain the code word, and transmits the code word to the check matrix unit. The check matrix unit performs error checking to determine the transmission error and locate (i.e., determine the error position), and then sends the error position to the error correction unit. The error correction unit accesses the forward error correction storage table, finds the error correction result corresponding to the received error position from the forward error correction storage table, and corrects the received code word according to the error correction result. Among them, when the number of errors is less than or equal to , the error can be corrected.

[0123] After correcting the code word, the error correction unit sends the corrected code word to the data output unit. The data output unit extracts data symbols from the code word of symbols, and sends the data symbols to the data link layer of the receiving end.

[0124] The embodiment of the application also provides a data processing method, which can be executed by the data processing device provided by any of the above embodiments. The data processing method provided by the application is described in detail in combination with the execution flow of the data processing method as shown in Figure 10 .

[0125] As shown in Figure 10 , the data processing method provided by the application at least includes the following steps:

[0126] Step S1001, receiving at least one first code word.

[0127] The first code word includes a plurality of first data symbols and a plurality of first check symbols.

[0128] Specifically, the first data symbol refers to a received symbol carrying original to-be-transmitted information of a sending end, and the first check symbol refers to a received redundant symbol calculated by an encoder based on the data symbol and a preset mathematical algorithm (such as polynomial operation or linear algebra operation).

[0129] In step S1002, whether the plurality of first data symbols has an error and a first error position are determined according to the primitive power table obtained from the physical layer memory and the plurality of first check symbols.

[0130] The primitive power table is used to represent a power form of a primitive element and a corresponding relationship between a polynomial form (or a numerical form) of a finite field element.

[0131] Specifically, the data processing apparatus can determine a plurality of syndrome subscripts according to the primitive power table and the plurality of first check symbols, and the plurality of syndrome subscripts and the plurality of first check symbols correspond to each other in a one-to-one manner. When all the plurality of syndrome subscripts are 0, it can be determined that the plurality of first data symbols corresponding to the first code word are normal. When any one of the plurality of syndrome subscripts is not 0, it can be determined that the plurality of first data symbols has an error, and a bit number (position) of the first check symbol corresponding to the accompanying formula of the non-0 syndrome subscript is determined as the first error position.

[0132] In step S1003, a first error correction result corresponding to the first error position is searched from a forward error correction storage table stored in the physical layer memory.

[0133] The forward error correction storage table is used to represent a corresponding relationship between a plurality of preset error positions and a plurality of error correction results, and the plurality of error positions and the plurality of error correction results correspond to each other in a one-to-one manner.

[0134] Specifically, after determining the first error position, the data processing apparatus accesses the forward error correction storage table in the physical layer memory, determines an error position (denoted as a target error position) same as the first error position from the plurality of preset error positions, and determines an error correction result corresponding to the target error position in the forward error correction storage table as the first error correction result.

[0135] In step S1004, the first code word is updated according to the first error correction result.

[0136] The data processing method provided in the application can search a first error correction result corresponding to the first error position from a forward error correction storage table stored in the physical layer memory after determining the first error position, and then correct the first code word according to the first error correction result, thereby omitting the calculation process of locating errors and determining error values, realizing fast query of error correction codes, and better meeting the real-time requirement of data transmission.

[0137] For example, the step S1002 can include steps a1 to a3 as follows:

[0138] In step a1, the target polynomial corresponding to the target codeword is multiplied by the check matrix to obtain a polynomial multiplication result.

[0139] The target codeword is one of the at least one first codeword, and the check matrix is determined based on the primitive element power table and a target check symbol, which is one of the plurality of first check symbols in the target codeword.

[0140] In step a2, the polynomial multiplication result is accumulated to determine a target syndrome.

[0141] In step a3, when the target syndrome is not 0, it is determined that the first data symbol in the target codeword has an error, and the first error position is the bit number corresponding to the target check symbol.

[0142] Specifically, when all target syndromes corresponding to the first check symbols are 0, it can be determined that the target codeword has no error.

[0143] In some embodiments, before the step S1001, the data processing method further includes steps b1 to b4 as follows:

[0144] In step b1, before receiving the first codeword, at least one second codeword formed by random data is received.

[0145] The second codeword includes a plurality of second data symbols and a plurality of second check symbols.

[0146] In step b2, whether the plurality of second data symbols has an error and a second error position are determined according to the primitive element power table and the plurality of second check symbols.

[0147] In step b3, when the second error position is determined, the number of times of errors of the second codeword at the second error position is stored.

[0148] In step b4, when the number of times is greater than a preset number of times, a second error correction result is determined according to the second error position, and a mapping relationship between the second error position and the second error correction result is created to generate a forward error correction storage table.

[0149] The preset number of times is a threshold for triggering the forward error correction storage table, and the preset number of times can be configured by a designer based on factors such as the depth of the forward error correction storage table and the probability of easy error. For example, the preset number of times can be 5 or 6, etc.

[0150] In this embodiment, before the step S1001, The error correction calculation and storage are performed after the preset number of times, which is equivalent to a lightweight processing of the forward error correction storage table, reduces the storage capacity of the forward error correction storage table, thereby reducing the occupied area of the forward error correction storage table, and reducing the design difficulty of the bus physical layer.

[0151] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be realized by means of software and necessary general hardware platform, of course, it can also be realized by hardware, but in many cases, the former is a better embodiment.

[0152] Embodiments of the present application also provide an electronic device, which comprises the data processing apparatus provided by any of the above embodiments. Illustratively, the electronic device further comprises a memory and a processor, the memory stores a computer program, and the processor is configured to run the computer program to enable the data processing apparatus to perform the steps in any of the above data processing method embodiments.

[0153] Embodiments of the present application also provide a computer readable storage medium, which stores a computer program, wherein the computer program is configured to perform the steps in any of the above data processing method embodiments when running.

[0154] In an exemplary embodiment, the above computer readable storage medium can include, but is not limited to, a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.

[0155] Embodiments of the present application also provide a computer program product, which comprises a computer program, and the computer program is executed by a processor to implement the steps in any of the above data processing method embodiments.

[0156] Embodiments of the present application also provide another computer program product, which comprises a non-volatile computer readable storage medium, and the non-volatile computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the steps in any of the above data processing method embodiments.

[0157] Those skilled in the art will further realize that the mere conception of the examples described herein is sufficient to enable practitioners to practice the examples as further described below. Therefore, many modifications and adaptations will be apparent to those skilled in the art (e.g., variations in sizes, dimensions, structures, materials, and / or use of the example's components, changes in the arrangement of components, methods, and / or functions, etc.). For example, the dimensions and / or types of the components can be varied, and the size of the components can be either increased to accommodate larger wireless devices or decreased to accommodate smaller wireless devices. Therefore, the examples are not limited to the specific examples described herein, but instead have numerous applications, modifications and adaptations from the various, and / or obvious, combinations where indicated, of the components described herein, and / or variations of the methods described herein. Therefore, the scope of the application should be determined not with reference to the above description, but should instead be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. The disclosures of each patent, patent application, and publication cited above are hereby incorporated herein by reference.

[0158] The above provides a data processing device, a data processing method and an electronic device. The principles and implementation manners of the present application are described by using specific examples. The above description of the examples is only applicable to help understand the method and the core idea of the present application. It should be pointed out that, for those skilled in the art, without departing from the principles of the present application, some improvements and modifications can be made to the present application. These improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A data processing apparatus, characterized by, The data processing apparatus comprises a physical layer memory and a data receiving module connected with the physical layer memory; The physical layer memory is configured with a primitive power table and a forward error correction storage table, and the data receiving module comprises a check matrix unit and an error correction unit, wherein the forward error correction storage table is used to represent the correspondence between a plurality of error positions and a plurality of error correction results; The check matrix unit is configured to receive at least one first codeword, wherein the first codeword comprises a plurality of first data symbols and a plurality of first check symbols; The check matrix unit is further configured to determine whether a plurality of first data symbols exist errors and a first error position according to the primitive power table and a plurality of first check symbols, and to send the first error position to the error correction unit when it is determined that there is an error; The error correction unit is configured to find a corresponding first error correction result from the forward error correction storage table according to the first error position, and to update the first codeword according to the first error correction result.

2. The data processing apparatus according to claim 1, characterized in that, The check matrix unit comprises a first multiplier and an accumulator; The first multiplier is configured to perform multiplication operation on a target polynomial corresponding to a target codeword and a check matrix to obtain a plurality of multiplication results, and send the plurality of multiplication results to the accumulator, wherein the target codeword is one of the at least one first codeword, and the check matrix is determined based on the primitive power table and a target check symbol, and the target check symbol is one of a plurality of first check symbols in the target codeword; The accumulator is configured to accumulate the plurality of multiplication results to determine a target syndrome, and determine that a first data symbol in the target codeword exists an error when the target syndrome is not 0, and the first error position is a bit number corresponding to the target check symbol.

3. The data processing apparatus according to claim 2, characterized in that, The number of the first multipliers and the number of the accumulators are the same as the number of the first check symbols, a plurality of the first multipliers correspond to a plurality of the first check symbols one by one, and a plurality of the accumulators correspond to a plurality of the first multipliers one by one.

4. The data processing apparatus according to claim 2, characterized by The expression of the target syndrome is as follows: wherein, denotes a target syndrome, , denotes a number of first check symbols in the target codeword, denotes a target polynomial corresponding to the target codeword, denotes a primitive element of a Galois field, , denotes a total number of first data symbols and first check symbols in the target codeword.

5. The data processing apparatus according to claim 2, wherein The accumulator is further configured to determine that a first data symbol in the target codeword is normal when a plurality of target syndromes corresponding to a plurality of first check symbols are all 0.

6. The data processing apparatus according to any one of claims 2 to 5, wherein The check matrix unit is further configured to receive at least one second codeword formed by random data before receiving the first codeword, wherein the second codeword comprises a plurality of second data symbols and a plurality of second check symbols; The check matrix unit is further configured to determine whether a plurality of second data symbols exist errors and a second error position according to the primitive power table and a plurality of second check symbols, and to send the second error position to the error correction unit when it is determined that there is an error; The error correction unit is further configured to determine a second error correction result according to the second error position, create a mapping relationship between the second error position and the second error correction result, and generate the forward error correction storage table, and configured to configure the forward error correction storage table in the physical layer memory.

7. The data processing apparatus of claim 6, wherein, The check matrix unit is further configured to store a number of times of errors of the second codeword at the second error position after determining the second error position, and configured to send the second error position to the error correction unit when the number of times is greater than or equal to a preset number of times.

8. The data processing apparatus according to any one of claims 1 to 5, characterized by, The data receiving module further comprises a level demodulation unit connected with the bus; The level demodulation unit is configured to receive the first physical signal transmitted by the bus, convert the first physical signal into at least one first codeword, and send the at least one first codeword to the check matrix unit.

9. The data processing apparatus according to claim 8, characterized in that, The bus is a PCIe bus.

10. The data processing apparatus according to any one of claims 1 to 5, characterized by, The data receiving module further comprises a data output unit; The error correction unit is further configured to send the updated first codeword to the data output unit after updating the first codeword; The data output unit is configured to extract a plurality of first data symbols from the updated first codeword, and send the plurality of first data symbols to the data link layer.

11. The data processing apparatus of claim 10, wherein, The check matrix unit is further configured to send the first codeword to the data output unit when determining that the first codeword is normal; The data output unit is further configured to extract a plurality of the first data symbols from the first codeword, and send the plurality of the first data symbols to the data link layer.

12. The data processing apparatus according to any one of claims 1 to 5, characterized by, The data processing apparatus further comprises a data sending module connected with the physical layer memory, the data sending module comprising a data receiving unit, an encoder, and a level modulation unit; The data receiving unit is configured to receive original data from the data link layer, and send the original data to the encoder; The encoder is configured to process the original data according to the primitive element power order table, form at least one third codeword, and send the at least one third codeword to the level modulation unit; The level modulation unit is configured to convert the at least one third codeword into a third physical signal, and send the third physical signal to a target device through a bus.

13. The data processing apparatus according to claim 12, characterized in that, The third codeword comprises a plurality of third data symbols and a plurality of third check symbols, and the encoder comprises a data grouping unit, a second multiplier, a polynomial generator, and a check symbol appending unit; The data grouping unit is configured to divide the original data into at least one data group according to a number of the third data symbols, and send the at least one data group to the second multiplier, wherein the data group comprises a plurality of the third data symbols; The second multiplier is configured to generate a check polynomial according to the bit number of the third data symbol, the number of the third check symbol and the primitive element power table, and to send the check polynomial and the data group to the polynomial generator; The polynomial generator is configured to convert the data group into an information polynomial, to generate an extended data polynomial according to the information polynomial and the number of the third check symbol, and to send the check polynomial and the extended data polynomial to the check symbol appending unit; The check symbol appending unit is configured to determine the third check symbol according to the extended data polynomial and the check polynomial, to generate the third code word according to the third check symbol and the extended data polynomial, and to send the third code word to the level modulation unit.

14. The data processing apparatus according to claim 13, characterized by The check symbol appending unit is configured to determine the third check symbol as a remainder polynomial obtained by dividing the extended data polynomial by the check polynomial.

15. The data processing apparatus according to claim 13, wherein, The check polynomial is expressed as follows: wherein, denotes the check polynomial, denotes the number of bits of a symbol, denotes a primitive element of the Galois field, denotes the number of third check symbols.

16. The data processing apparatus according to claim 15, wherein, The extended data polynomial is expressed as follows: wherein denotes the extension data polynomial, denotes the information polynomial, denotes the number of third information symbols.

17. A data processing method, characterized by, The data processing method comprises: receiving at least one first code word, wherein the first code word comprises a plurality of first data symbols and a plurality of first check symbols; determining whether the plurality of first data symbols has an error and a first error position according to a primitive element power table obtained from a physical layer memory and the plurality of first check symbols; finding a corresponding first error correction result from a forward error correction storage table stored in the physical layer memory according to the first error position; updating the first code word according to the first error correction result.

18. The data processing method according to claim 17, characterized in that, The determining whether the plurality of first data symbols has an error and a first error position according to a primitive element power table obtained from a physical layer memory and the plurality of first check symbols comprises: performing multiplication operation on a target polynomial corresponding to a target code word and a check matrix to obtain a plurality of multiplication results, wherein the target code word is one of the at least one first code word, and the check matrix is determined based on the primitive element power table and a target check symbol, and the target check symbol is one of the plurality of first check symbols in the target code word; accumulating the plurality of multiplication results to determine a target check syndrome; when the target check syndrome is not 0, determining that a first data symbol in the target code word has an error, and the first error position is a bit number corresponding to the target check symbol.

19. The data processing method of claim 17, wherein, The data processing method further comprises: receiving at least one second code word formed by random data before receiving the first code word, wherein the second code word comprises a plurality of second data symbols and a plurality of second check symbols; determining whether the plurality of second data symbols has an error and a second error position according to the primitive element power table and the plurality of second check symbols; when the second error position is determined, storing a number of times that the second code word has an error at the second error position. When the number of times is greater than the preset number of times, a second error correction result is determined according to the second error position, and a mapping relationship between the second error position and the second error correction result is created to generate the forward error correction storage table.

20. An electronic device, comprising: The electronic device includes the data processing apparatus of any one of claims 1 to 16.

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