A processor fault recovery method

Abstract

The application discloses a processor fault recovery method and relates to the technical field of computer system structure. The method sets multiple levels of hardware checkpoints on a processor superscalar pipeline. There is a preset interval between adjacent hardware checkpoints. When a to-be-processed instruction reaches any hardware checkpoint of the processor superscalar pipeline, the instruction state content output by the previous stage of the stage where the hardware checkpoint is located is backed up, and fault detection is performed on the processor superscalar pipeline. In the case that the processor superscalar pipeline has a fault, the backup instruction state content is moved to the processor superscalar pipeline, so that the fault of the processor superscalar pipeline is recovered. The method solves the problem that the fault recovery cost of the processor superscalar pipeline is high due to the large depth.

Description

Technical Field

[0001] This invention relates to the field of computer system architecture technology, and in particular to a processor fault recovery method. Background Technology

[0002] Checkpoints are an important technique for protecting computer systems from hardware failures. This technique typically involves creating a backup of the hardware state at system startup, recording it as the system runs, so that in the event of a failure, the system can be restored to its most recent stable and correct state. In virtualized and real-time systems, hardware checkpointing mechanisms are a key component in ensuring system availability and fault tolerance. By regularly creating hardware checkpoints, system administrators can restore the system state in the event of hardware failures, errors, or other anomalies, minimizing service interruption time.

[0003] In traditional checkpointing mechanisms, hardware checkpoints are typically placed at the end of the pipeline. For superscalar processors, considering the worst-case scenario where a soft error occurs at the instruction fetch stage at the beginning of the pipeline, the checkpoint is checked and recovery begins at the commit stage. This results in the greatest recovery latency, as instructions entering the pipeline during this period must be cleared and then re-executed, representing a significant waste of performance. Given the deep pipeline of superscalar processors, this situation leads to substantial recovery overhead.

[0004] Therefore, there is an urgent need for a processor fault recovery method to solve the problem of high fault recovery overhead caused by the large depth of superscalar processor pipelines. Summary of the Invention

[0005] Therefore, it is necessary to provide a processor fault recovery method to address the aforementioned technical problems. This method can solve the problem of high fault recovery overhead caused by the large depth of superscalar processor pipelines.

[0006] The present invention adopts the following technical solution:

[0007] This invention provides a processor fault recovery method, comprising:

[0008] Multiple hardware checkpoints are set up in the processor superscalar pipeline; there is a preset interval between adjacent hardware checkpoints;

[0009] When an instruction to be processed reaches any hardware checkpoint in the processor's superscalar pipeline, the instruction status content output by the previous stage of the stage where the hardware checkpoint is located is backed up, and the processor's superscalar pipeline is fault-detected.

[0010] In the event of a fault in the processor's superscalar pipeline, the fault can be recovered by moving the backed-up instruction state content to the processor's superscalar pipeline.

[0011] Preferably, the multi-stage hardware checkpoint comprises a first-stage hardware checkpoint and a second-stage hardware checkpoint; the multi-stage hardware checkpoint is arranged on the processor superscalar pipeline, and specifically comprises:

[0012] The first-stage hardware checkpoint is arranged at a dispatch stage of the processor superscalar pipeline, and the second-stage hardware checkpoint is arranged at a write-back stage of the processor superscalar pipeline; an interval between the first-stage hardware checkpoint and the second-stage hardware checkpoint is half of a whole cycle of the processor superscalar pipeline.

[0013] Preferably, the hardware checkpoint is the first-stage hardware checkpoint; the backup of the instruction state content output by a previous stage of the stage where the hardware checkpoint is located comprises:

[0014] The register renaming mapping table output by a previous stage of the dispatch stage is acquired; the register renaming mapping table comprises information required for an instruction to access a general register;

[0015] The register renaming mapping table is stored into a first backup circuit; a structure of the first backup circuit is consistent with a structure of the register renaming mapping table.

[0016] Preferably, the hardware checkpoint is the second-stage hardware checkpoint; the backup of the instruction state content output by a previous stage of the stage where the hardware checkpoint is located comprises:

[0017] The calculation result output by a previous stage of the write-back stage is acquired; the calculation result is data required to be backed up into a general register and a control state register;

[0018] The calculation result is stored into a second backup circuit; a structure of the second backup circuit is a register file structure.

[0019] Preferably, the backup of the instruction state content output by a previous stage of the stage where each hardware checkpoint is located is performed in parallel with the processor superscalar pipeline.

[0020] The application provides a processor fault recovery device, comprising:

[0021] A setting module is configured to arrange a multi-stage hardware checkpoint on a processor superscalar pipeline; a preset interval exists between adjacent hardware checkpoints;

[0022] A backup and detection module is configured to, when a to-be-processed instruction reaches any hardware checkpoint of the processor superscalar pipeline, backup instruction state content output by a previous stage of the stage where the hardware checkpoint is located, and detect a fault of the processor superscalar pipeline;

[0023] The recovery module is configured to, in the case that the processor superscalar pipeline has a fault, move the backed-up instruction state content to the processor superscalar pipeline to recover the fault of the processor superscalar pipeline.

[0024] The application provides a processor fault recovery medium, and a storage medium stores a computer program.

[0025] The application provides a computer device, which comprises a memory, a processor, and a computer program stored in the memory and capable of running on the processor.

[0026] The application achieves the following beneficial effects by adopting the above at least one technical scheme:

[0027] The application sets multiple levels of hardware checkpoints on the processor superscalar pipeline, and a preset interval exists between adjacent hardware checkpoints; when a to-be-processed instruction reaches any hardware checkpoint of the processor superscalar pipeline, the instruction state content output by the last stage of the stage where the hardware checkpoint is located is backed up, and the processor superscalar pipeline is detected for faults; in the case that the processor superscalar pipeline has a fault, the backed-up instruction state content is moved to the processor superscalar pipeline to recover the fault of the processor superscalar pipeline. The application backs up the output content of the last stage at each level of hardware checkpoint, detects the processor superscalar pipeline for faults, and moves the backed-up content to the processor superscalar pipeline to recover the fault if the fault exists, so that the timing of the processor superscalar pipeline is not affected, the time for system interruption recovery is minimized, the availability and fault tolerance of the system are improved, and compared with a single hardware checkpoint, the application reduces the redundant periods between the error detection and recovery periods and the waste of processor performance caused by instruction clearing in the superscalar pipeline with too many pipeline levels, so that the overhead of fault recovery is smaller than that of a single hardware checkpoint, and the problem that the fault recovery overhead is large due to the large depth of the processor superscalar pipeline is solved. BRIEF DESCRIPTION OF DRAWINGS

[0028] The accompanying drawings, which are included to provide a further understanding of the application and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:

[0029] Figure 1 A processor fault recovery method flowchart provided by the application;

[0030] Figure 2The first-level hardware checkpoint position schematic diagram of the processor superscalar pipeline provided by the present application is shown in the figure.

[0031] Figure 3 The second-level hardware checkpoint position schematic diagram of the processor superscalar pipeline provided by the present application is shown in the figure.

[0032] Figure 4 The three-pipeline lockstep schematic diagram provided by the present application is shown in the figure.

[0033] Figure 5 The first-level hardware checkpoint backup mechanism timing diagram provided by the present application is shown in the figure.

[0034] Figure 6 The second-level hardware checkpoint backup mechanism timing diagram provided by the present application is shown in the figure.

[0035] Figure 7 The two-level hardware checkpoint backup flowchart provided by the present application is shown in the figure.

[0036] Figure 8 The performance impact evaluation diagram of the two-level hardware checkpoint mechanism provided by the present application is shown in the figure.

[0037] Figure 9 The processor fault recovery device schematic diagram provided by the present application is shown in the figure.

[0038] Figure 10 The computer device schematic diagram for implementing the processor fault recovery method provided by the present application is shown in the figure. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical scheme and advantages of the present application clearer, the technical scheme of the present application will be described clearly and completely below by combining the specific embodiments of the present application with the corresponding drawings. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0040] The technical scheme provided by each embodiment of the present application will be described in detail below by combining the drawings.

[0041] Figure 1 The processor fault recovery method flowchart provided by the present application is shown in the figure, which specifically includes the following steps:

[0042] S101: setting multiple levels of hardware checkpoints on the processor superscalar pipeline; there is a preset interval between adjacent hardware checkpoints.

[0043] In an exemplary embodiment, the multi-level hardware checkpoint comprises a first-level hardware checkpoint and a second-level hardware checkpoint; the multi-level hardware checkpoint is arranged on the processor superscalar pipeline, specifically comprising: arranging the first-level hardware checkpoint at a dispatch stage of the processor superscalar pipeline, and arranging the second-level hardware checkpoint at a write-back stage of the processor superscalar pipeline; the interval between the first-level hardware checkpoint and the second-level hardware checkpoint is half of the entire cycle of the processor superscalar pipeline.

[0044] Specifically, as shown in Figure 2 , the first-level hardware checkpoint is arranged at the dispatch stage of the processor superscalar pipeline, the dispatch stage being a critical point from sequential execution to out-of-order execution, and the related information of the instructions after register renaming is written into corresponding reservation stations, reorder buffers and the like, and the main function is to dispatch the instructions to the operation unit after decoding; as shown in Figure 3 , the second-level hardware checkpoint is arranged at the write-back stage of the processor superscalar pipeline, after the reservation stations of the instructions in the pipeline are emitted out-of-order, the physical register stack is read, and the out-of-order write-back is executed, finally the Reorder Buffer (ROB) is used to ensure that the instructions are submitted in program order, and the write-back stage is responsible for writing the calculation results obtained in the instruction execution stage back to the general-purpose register and the Control Status Register (CSR). For some counting registers in the CSR used for system performance monitoring, and the hardware acceleration or partial function registers defined by the designer, the correctness of the data itself will not affect the working state of the system. Therefore, the processor system will not list these registers as the backup content of the hardware checkpoint, and even if the fault occurs in these registers, the system will not detect and recover.

[0045] S102: When the to-be-processed instruction reaches any hardware checkpoint of the processor superscalar pipeline, the instruction state content output by the last stage of the stage where the hardware checkpoint is located is backed up, and the processor superscalar pipeline is fault detected.

[0046] In an exemplary embodiment, the hardware checkpoint is a first-level hardware checkpoint; the instruction state content output by the last stage of the stage where the hardware checkpoint is located is backed up, specifically comprising: obtaining the Static Register Allocation Table (SRAT) output by the last stage of the dispatch stage; the register renaming mapping table comprises the information required by the instructions to access the general-purpose register; storing the register renaming mapping table into the first backup circuit; the structure of the first backup circuit is consistent with the structure of the register renaming mapping table.

[0047] In an exemplary embodiment, the hardware checkpoint is a second-level hardware checkpoint; the instruction state content output by the previous stage of the stage where the hardware checkpoint is located is backed up, specifically including: obtaining the calculation result output by the previous stage of the write-back stage; the calculation result is data that needs to be backed up into the general register and the control state register; storing the calculation result into the second backup circuit; the structure of the second backup circuit is a register stack structure.

[0048] The instruction state content that needs to be backed up by the hardware checkpoint is the output state content after the previous stage of the hardware checkpoint executes instructions.

[0049] Specifically, the instruction state content that needs to be backed up by the first-level hardware checkpoint is the register renaming mapping table based on speculative execution, which contains information of instructions accessing the general register; the instruction state content that needs to be backed up by the second-level hardware checkpoint is the data in the general register and part of the control state register; in order to reduce the overhead, the control state register whose data correctness does not affect the working state of the system will not be backed up; in addition, the fault detection result can be returned to the commit stage of the pipeline for instruction retirement judgment.

[0050] Specifically, it is assumed that the system is currently running under a triple pipeline lock step (TPLS) mechanism.

[0051] TPLS synchronously executes instructions by three pipelines, which is equivalent to a single-core superscalar processor in performance, such as Figure 4 As shown, the TPLS management unit is responsible for the clock synchronization of the three pipelines, fault detection, majority voting, and fault synchronization recovery control tasks. The three pipelines synchronously execute the same instructions under the triple pipeline lock step mechanism, and the data of the internal modules should be consistent under normal circumstances. Each pipeline backs up the specified content at the designed hardware checkpoint and sends the signals that need to be detected to the TPLS management unit for fault detection. If no error occurs, the pipeline can continue to execute and complete the interaction with the outside through the AXI (Advanced eXtensible Interface, AXI) bus. If the pause and resume signals from the synchronization control unit are received, the pipeline that produces errors will complete the fault recovery operation under the scheduling of the TPLS management unit, and the other two pipelines need to pause the execution of the current instructions and wait for the start signal after the fault recovery is completed to continue the lock step execution.

[0052] The fault detection unit is located inside the TPLS management unit, responsible for receiving three groups of interfaces required for detection of the three pipelines, including register related information, memory access address and data, and detecting in real time through combinational logic. According to different system running states, different error detection methods will be taken, including comparators of double-pipeline lockstep mechanism and triple-pipeline lockstep mechanism. In addition, the error detection of the pipeline can be carried out at different stages of the pipeline, for example, two-stage fault detection can be used to carry out fault detection at the distribution stage and the write-back stage of the pipeline respectively, and the error signal error_f at the detection position is generated by combinational logic to provide excitation for pipeline recovery.

[0053] Specifically, as shown in Figure 5 , in the first-level hardware checkpoint backup mechanism timing diagram, the first pipeline pipeline1 generates a soft error at the renm2 clock period, and the error signal error is generated by the combinational logic circuit, but because of the beat of the synchronization control unit, the system can only obtain the fault detection result signal error_f at the renm3 clock period, and due to the one clock period delay of the system backup, when the first pipeline pipeline1 needs fault recovery at the renm3 stage, the system state state_ds_p0 of the zeroth pipeline at the distribution stage and the system state state_ds_p2 of the second pipeline at the distribution stage start to backup s1, so the backup starts from the register renaming stage output interface, which is in parallel with the distribution stage logic, as shown in Figure 4 , the system state state_renm_p0 of the zeroth pipeline at the renaming stage and the system state state_renm_p2 of the second pipeline at the renaming stage have completed s1 backup, and can start to recover pipeline1 at the next clock period.

[0054] When the clock period of the first pipeline backup is the same as the clock period of the distribution stage, the backup content is the register renaming mapping table output by the previous stage, and the register renaming mapping table includes the information required for instruction access to general registers, otherwise an extra backup circuit and storage body will be needed, and under the triple-pipeline mechanism, three extra backup overheads will be needed, which will bring one-time hardware cost compared with one clock period delay. In addition, when the first-level hardware checkpoint performs backup, the backup content also needs to be delayed by one beat, mainly to wait for the completion of the state backup of the previous stage to ensure that the instruction gets the correct backup content in the case of fault recovery.

[0055] Specifically, as shown in Figure 6As shown in the second level hardware checkpoint backup mechanism timing diagram, similarly, the first pipeline pipeline 1 produces a soft error at the exe2 clock cycle, the error signal error is generated by the combinational logic circuit, but because of the beat of the synchronous control unit, the system can obtain the fault detection result signal error_f at the exe3 clock cycle, and due to the one clock cycle delay of the system backup, when the first pipeline pipeline 1 needs fault recovery at the exe3 stage, the zeroth pipeline system state state_rf_p0 at the write-back stage and the second pipeline system state state_rf_p2 at the write-back stage start to backup s1, so the backup starts from the execution stage, which is parallel to the write-back stage logic, that is, as shown in the figure Figure 6 The zeroth pipeline system state state_exe_p0 at the execution stage and the second pipeline system state state_exe_p2 at the execution stage have completed s1 backup, and can start to recover pipeline 1 at the next clock cycle.

[0056] When the clock cycle of the backup of the first pipeline is the same as the clock cycle of the write-back stage, the backup content is the data in the general register and part of the control state register before the current instruction is written back, otherwise an extra backup circuit and storage will be needed, and three pipeline mechanisms will need three extra backup overheads, which will bring a one-time hardware cost compared with one clock cycle delay. In addition, when the second level hardware checkpoint is backed up, the backup content needs to be delayed by one beat, mainly to wait for the backup of the content output in the last stage to be completed, so as to ensure that the instruction gets the correct backup content in the case of fault recovery.

[0057] Specifically, the first level hardware checkpoint needs to backup the content based on the register renaming mapping table of speculative execution, so the backup circuit designed for it has the same structure as the register renaming mapping table, and can complete the fast recovery of the register mapping table in one cycle after the fault recovery enable is obtained. In addition, after the fault occurs, the fault pipeline also needs to be refreshed and recovered according to the correct pipeline content; the backup circuit structure of the second level checkpoint is consistent with the register stack structure, which also ensures that the fast recovery of the processor state is completed in one cycle when fault recovery.

[0058] In an exemplary embodiment, the backup of the instruction state content output by the last stage of each level hardware checkpoint is performed in parallel with the processor superscalar pipeline.

[0059] Specifically, the data source of the two-level hardware checkpoint backup is the output of the previous stage, and the output of the stage where the two-level hardware checkpoint is located is irrelevant to the backup mechanism. The logic of the two is parallel processing, which will not affect the original timing of the pipeline, and will not normally occupy the additional performance overhead of the processor.

[0060] Specifically, the backup of the instruction state content of the previous stage output of the stage where the hardware checkpoint is located is performed in real time, and the instruction state content of the previous stage output of the stage where the hardware checkpoint is located is backed up every clock cycle.

[0061] S103: In the case of a fault in the processor superscalar pipeline, the backup instruction state content is moved to the processor superscalar pipeline to recover the fault in the processor superscalar pipeline.

[0062] The first level hardware checkpoint detects the occurrence of a fault, and needs to use the same backup circuit as the register renaming mapping table structure to combine the content of the first level hardware checkpoint in S102 to flush and recover the fault pipeline, during which the remaining pipeline waits; the second level hardware checkpoint detects the occurrence of a fault, and needs to use the same backup circuit as the register stack structure to combine the content of the second level hardware checkpoint in S102 to flush and recover the fault pipeline, during which the remaining pipeline waits.

[0063] In one specific embodiment, as shown in Figure 7 , a recovery process of two-level hardware checkpoints is provided, Figure 7 The first checkpoint is the first level hardware checkpoint in the present application, and the second checkpoint is the second level hardware checkpoint in the present application. When the program executes to the first level checkpoint, the SRAT output of the previous stage of the first level checkpoint is backed up, the SRAT includes the information required for the instruction to access the general register, and the processor superscalar pipeline is subjected to first level fault detection. If there is a fault, the processor superscalar pipeline is recovered using the first backup circuit combined with the content of the first level hardware checkpoint backup. If there is no fault, the program continues to execute, and when the program executes to the second level checkpoint, the content of the general register and part of the control state register is backed up, and the processor superscalar pipeline is subjected to second level fault detection. If there is a fault, the processor superscalar pipeline is recovered using the second backup circuit combined with the content of the second level checkpoint backup, and if there is no fault, the program continues to execute.

[0064] As shown in Figure 8As shown, the same processor superscalar pipeline, using the same test program for instruction input, ensures that both use consistent fault simulation excitation, strictly controls other irrelevant variables, and the two-level hardware checkpoint mechanism is compared with the one-level hardware checkpoint mechanism.

[0065] Compared with a single hardware checkpoint, in a superscalar pipeline with too many pipeline stages, the number of redundant cycles during error detection and recovery and the waste of processor performance caused by instruction clearing are reduced. The backup logic of the two-level pipeline backup mechanism proposed in the application is independent of and parallel to the pipeline logic, does not affect the pipeline timing, and helps to minimize the time of system interruption recovery, improve the availability and fault tolerance of the system. The two-level hardware checkpoint mechanism reduces the program running time by 9.54% compared with the one-level hardware fault checkpoint mechanism under the same target test program and the same amount of consistent fault conditions, which is equivalent to the performance improvement.

[0066] The server mentioned in the application can be a server arranged in a service platform or a device such as a desktop computer, a notebook computer, etc. capable of executing the scheme of the application. For the convenience of description, only the server is taken as the execution subject for description below.

[0067] When the processor fault recovery method provided by the application is applied, the execution of each step can not be performed according to the order shown in the figure, and the execution order of each step can be determined as required, which is not limited by the application. Figure 1 The execution order of each step can be determined as required, which is not limited by the application.

[0068] The above is a processor fault recovery method provided by one or more embodiments of the application. Based on the same idea, the application also provides a corresponding processor fault recovery device, as shown in the figure. Figure 9

[0069] Figure 9 The processor fault recovery device provided by the application is a schematic diagram, which comprises:

[0070] The setting module 901 is configured to set a plurality of hardware checkpoints on the processor superscalar pipeline, and a preset interval exists between adjacent hardware checkpoints.

[0071] The backup and detection module 902 is configured to backup the instruction state content output by the previous stage of the stage where the hardware checkpoint is located when the to-be-processed instruction reaches any hardware checkpoint of the processor superscalar pipeline, and perform fault detection on the processor superscalar pipeline.

[0072] ​The recovery module 903 is configured to, in the case that the processor superscalar pipeline has a fault, recover the fault of the processor superscalar pipeline by moving the backup instruction state content to the processor superscalar pipeline.

[0073] The specific limitation of the processor fault recovery apparatus can refer to the limitation of the processor fault recovery method, which is not repeated here. Each module of the processor fault recovery apparatus can be realized by software, hardware, and a combination thereof, in whole or in part. Each module can be embedded in or independent of the processor in the computer device in hardware form, or stored in the memory in the computer device in software form, so that the processor can call and execute the operation corresponding to each module.

[0074] The application further provides a computer readable storage medium, which stores a computer program, and the computer program can be used to execute the processor fault recovery method. Figure 1 The application provides a processor fault recovery method.

[0075] The application further provides a computer readable storage medium, which stores a computer program, and the computer program can be used to execute the processor fault recovery method. Figure 10 The application provides a computer device, as shown in the structure diagram. Figure 10 As shown in the hardware level, the computer device includes a processor, an internal bus, a network interface, a memory, and a non-volatile memory, and can further include other hardware required by a business. The processor reads the corresponding computer program from the non-volatile memory into the memory and then runs to implement the processor fault recovery method. Figure 1 The application provides a processor fault recovery method.

[0076] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer readable storage medium, and when executed, can include the processes of the above-mentioned embodiment methods. In the embodiments of the application, any reference to the memory, storage, database, or other medium can include at least one of the non-volatile and volatile memories. The non-volatile memory can include a read-only memory (ROM), a tape, a floppy disk, a flash memory, or an optical memory. The volatile memory can include a random access memory (RAM) or an external cache memory. As an illustration but not limitation, the RAM can be in various forms, such as a static random access memory (SRAM) or a dynamic random access memory (DRAM).

[0077] The technical features of the above embodiments can be combined in any manner. For the sake of brevity, not all possible combinations of the technical features described in the above embodiments are described, however, as long as the combinations of the technical features do not contradict each other, they should be considered to be within the scope of the present application.

Claims

1. A processor fault recovery method, characterized by, The method comprises: a plurality of levels of hardware checkpoints are set on a processor superscalar pipeline; there is a preset interval between adjacent hardware checkpoints; when an instruction to be processed reaches any hardware checkpoint of the processor superscalar pipeline, the instruction state content output by the previous stage of the stage where the hardware checkpoint is located is backed up, and fault detection is performed on the processor superscalar pipeline; in the case where the processor superscalar pipeline has a fault, the fault of the processor superscalar pipeline is recovered by moving the backed-up instruction state content to the processor superscalar pipeline. The plurality of levels of hardware checkpoints comprise a first level of hardware checkpoint and a second level of hardware checkpoint; the setting of the plurality of levels of hardware checkpoints on the processor superscalar pipeline specifically comprises: setting the first level of hardware checkpoint at a dispatch stage of the processor superscalar pipeline, and setting the second level of hardware checkpoint at a write-back stage of the processor superscalar pipeline; the interval between the first level of hardware checkpoint and the second level of hardware checkpoint is half of the entire cycle of the processor superscalar pipeline.

2. The method of claim 1, wherein, The hardware checkpoint is the first level of hardware checkpoint; the backup of the instruction state content output by the previous stage of the stage where the hardware checkpoint is located specifically comprises: a register renaming mapping table output by the previous stage of the dispatch stage is acquired; the register renaming mapping table comprises information required for an instruction to access a general-purpose register; the register renaming mapping table is stored into a first backup circuit; the structure of the first backup circuit is consistent with the structure of the register renaming mapping table.

3. The method of claim 1, wherein, The hardware checkpoint is the second level of hardware checkpoint; the backup of the instruction state content output by the previous stage of the stage where the hardware checkpoint is located specifically comprises: a calculation result output by the previous stage of the write-back stage is acquired; the calculation result is data that needs to be backed up into a general-purpose register and a control state register; the calculation result is stored into a second backup circuit; the structure of the second backup circuit is a register file structure.

4. The method of claim 1, wherein, The backup of the instruction state content output by the previous stage of the stage where each level of hardware checkpoint is located is performed in parallel with the processor superscalar pipeline.

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