Mixed catalog setting method, storage medium, and electronic device

Abstract

The application discloses a mixed directory setting method, a storage medium and an electronic device, relates to the technical field of data processing, and the method comprises the steps of determining the number of processor cores of a data copy with a shared resource; if the number of processor cores does not exceed a preset number threshold, using a limited pointer directory as a target directory, and the pointers of the limited pointer directory are associated with the processor cores with the data copy of the shared resource; otherwise, using a two-level sparse directory as the target directory, dividing the processor cores into multiple subsets, and using a first-level table item and a second-level table item in the two-level sparse directory to associate the processor cores with the data copy in the target subset; if there is a processor core performing a consistency change operation on the shared resource, adjusting the data copy of the processor core with the data copy through the target directory, so that each processor core synchronizes the consistency change operation, and the availability of the directory is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data processing, and in particular, to a hybrid directory setting method, a storage medium and an electronic device. BACKGROUND

[0002] In computer architecture, cache coherence refers to ensuring the consistency of shared resource data in multiple local caches. This is particularly important in a multi-core processor environment, because multiple clients (such as processor cores) in the system can cache shared memory resources, leading to inconsistent data. With the popularity of multi-core processors, the main problem of cache coherence is how to maintain the consistency of the same data in multiple caches and memories.

[0003] In a single-core processor system, since there is only one CPU core and its cache in the system, there is no cache coherence problem across multiple cores. However, in a multi-processor or multi-core system, in order to improve system performance, each processor or core is usually equipped with its private cache. These caches play a key role in computer architecture by providing convenient access to frequently accessed data quickly. However, maintaining the consistency of data in these private caches is a challenging task that often leads to cache coherence problems.

[0004] The main function of the cache coherence directory system is to solve the data consistency problem. This system relies on a centralized directory to maintain the cache coherence state. In this system, the coherence state generally includes Modified (M), Exclusive (E), Shared (S), and Invalid (I) states. When a processor initiates a memory access request, the directory is queried to verify the current state of the data block, so as to determine the subsequent memory operation. In addition, when the state of the data block in the cache of a processor changes, the latest state must also be updated in the directory in a timely manner to maintain cache coherence in a multi-processor system.

[0005] In related technologies, the state and location of the cache block are directly reflected by copying all the tag and state information in the private cache. This method is convenient to manage and can find the corresponding location of each processor's data block in the replicated directory, thereby providing optimal performance. However, this scheme has low space utilization and poor scalability, especially when the number of processor cores increases, the required storage space increases significantly, making it difficult to support the expansion of the system. Therefore, although the replicated directory has advantages in some aspects, its limitations in handling large-scale problems affect its universal availability. SUMMARY

[0006] The present application aims to at least partially solve one of the technical problems in the related art. To this end, one object of the present application is to provide a hybrid directory setting method, a storage medium and an electronic device to improve the availability of a directory.

[0007] According to a first aspect of an embodiment of the present application, a hybrid directory setting method is provided, the method comprising:

[0008] determining the number of processor cores having a data copy of a shared resource;

[0009] if the number of processor cores does not exceed a preset number threshold, using a limited pointer directory as a target directory, the pointers of the limited pointer directory being associated with processor cores having a data copy of a shared resource;

[0010] otherwise, using a two-level sparse directory as a target directory, dividing the processor cores into multiple subsets, using a primary table entry in the two-level sparse directory to identify a target subset in which the processor cores having the data copy are located, and recording the consistency state of the data copy in the primary table entry, and using a secondary table entry in the sparse directory to associate the processor cores having the data copy in the target subset;

[0011] if there is a processor core performing a consistency change operation on a shared resource, adjusting the data copy of the processor core having the data copy through the target directory, so that each processor core synchronizes the consistency change operation.

[0012] Optionally, in the case where the pointers of the limited pointer directory are associated with C processor cores, each pointer has a field of bits.

[0013] Optionally, the primary table entry includes a tag field, a state bit and a first bit vector, wherein the tag field identifies the address of the shared resource, the state bit records the consistency state, and the first bit vector identifies the subset having the data copy of the shared resource.

[0014] Optionally, the secondary table entry includes a subset number and a second bit vector, and the second bit vector identifies the processor cores having the data copy in the subset identified by the subset number.

[0015] Optionally, the first index of the primary table entry is obtained according to the address information of the data block in which the data copy is located; the second index of the secondary table entry is included in the second bit vector, and the second index is obtained based on a hash operation of the first index and the subset number.

[0016] Optionally, the limited pointer directory and the two-level sparse directory share a directory storage space.

[0017] If there is a target entry to be allocated and there is a free entry in the directory storage space, the free entry is allocated to the target entry.

[0018] Optionally, if there is no free entry in the directory storage space, a non-free entry in the directory storage space is replaced by the target entry, and a data copy corresponding to the replaced non-free entry is invalidated.

[0019] Optionally, the primary entry and the secondary entry are stored in the same data block and are distinguished by the highest bit of the entry.

[0020] According to a second aspect of the embodiment of the present application, a computer readable storage medium is provided, and the computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the mixed directory setting method.

[0021] According to a third aspect of the embodiment of the present application, an electronic device is provided, and the electronic device comprises a memory and a processor, and the memory stores a computer program, and the computer program is executed by the processor to implement the mixed directory setting method.

[0022] In the scheme provided by the embodiment of the present application, when the number of processor cores with data copies is small, the limited pointer directory is used to record the processor cores, and the pointer in the limited pointer directory can directly retrieve the specific core containing the data copy, the directory searching process is simple, the overall processing efficiency of the system and the management efficiency of the data sharing information can be significantly improved; when the number of processor cores of the shared resource exceeds the preset threshold, the two-level sparse directory is automatically switched to in the case that the number of processor cores of the shared resource is large, so as to maintain the efficiency and continuity of data access, and the sharing information of all processor cores is managed according to subsets, when the directory is searched, all processor cores in the system no longer need to be traversed, and only the subsets related to the data copy need to be concerned, more processor cores can be accommodated, the storage cost is reduced, the system can maintain high efficiency while being expanded in scale, the directory switching mechanism ensures that the management strategy is dynamically adjusted according to different use scenarios, avoids the shortcomings of a single directory structure, and brings significant performance improvement and stronger adaptability to a large-scale multiprocessor system. Therefore, the present application increases the expansibility, efficiency and flexibility of data sharing management, improves the system processing capability, effectively reduces network traffic and performance bottlenecks, and improves the availability of the directory.

[0023] Additional aspects and advantages of the present application will be given in part in the following description, become apparent from the following description, or be learned by practice of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 is a flowchart of a mixed catalog setting method provided by an embodiment of the present application;

[0025] Figure 2 is a structure diagram of a mixed catalog provided by an embodiment of the present application;

[0026] Figure 3 is a structure diagram of a sparse catalog provided by an embodiment of the present application;

[0027] Figure 4 is a structure diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0028] Embodiments of the present application are described in detail below with reference to examples shown in the attached drawings, wherein the same or similar notations represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by reference to the attached drawings are exemplary and are intended to explain the present application, and cannot be understood as limiting the present application.

[0029] A mixed catalog setting method, a storage medium and an electronic device according to embodiments of the present application are described below with reference to the attached drawings.

[0030] In one embodiment of the present application, referring to Figure 1 , a mixed catalog setting method is provided, which comprises the following steps S101-S104.

[0031] S101: determining the number of processor cores that store data copies of a shared resource;

[0032] S102: if the number of processor cores does not exceed a preset number threshold, using a limited pointer catalog as a target catalog, and the pointers of the limited pointer catalog are associated with the processor cores that store data copies of the shared resource;

[0033] S103: otherwise, using a two-level sparse catalog as a target catalog, dividing the processor cores into multiple subsets, using a primary entry in the two-level sparse catalog to identify the subset in which the processor core that stores a data copy is located, recording the consistency state of the data copy in the primary entry, and using a secondary entry in the sparse catalog to associate the processor core that stores the data copy in the target subset;

[0034] S104: if there is a processor core that performs a consistency change operation on the shared resource, adjusting the data copy of the processor core that stores the data copy through the target catalog, so that each processor core synchronizes the consistency change operation.

[0035] In step S101, each processor core can set a cache to store a data copy of a shared resource.

[0036] When the number of processor cores is less than the preset number threshold, the number of processor cores can be considered to be small, so that the limited pointer directory can directly point to the processor core through the pointer, facilitating the searching and management.

[0037] As shown in Figure 2 , the limited pointer directory includes table entries of SetM to SetN, wherein the pointer 1, the pointer 2, …, and the pointer i in each table entry are the pointers of the limited pointer directory, and different pointers can point to different data block addresses of the processor core storing the data copy, thereby realizing the association.

[0038] Figure 2 As described in , when the number of sharers is less than or equal to n, the limited pointer directory is used, and n is the preset number threshold.

[0039] Other association methods include recording the unique number identifier of each processor core, and the embodiments of the present application do not limit this.

[0040] In an embodiment of the present application, the primary table entry includes a tag field, a state bit, and a first bit vector, wherein the tag field identifies the address of the shared resource, the state bit records the consistency state, and the first bit vector identifies the subset of the processor core having the data copy of the shared resource.

[0041] Similarly, as shown in

[0042] , the secondary table entry can also have the Tag field. Figure 2 Figure 2 and Figure 3 In the embodiment, the consistency state of the primary table entry and the limited pointer directory is the state bit.

[0043] Figure 2 In , the number of sharers is greater than n, that is, the number of processor cores exceeds the preset number threshold, and then the two-level coefficient directory is used as the target directory. Assuming that C processor cores of the multi-core system are coded from 1 to C, and every N cores form a subset, there are C / N subsets. The bit vector of the primary table entry is C / N bits, and assuming that the i-th bit is 1, it indicates that there is a processor core having a data copy in the i-th subset, for example, the bit vector is 01001, which indicates that there is a processor core having a data copy in the 2nd and 5th subsets, which are the target subsets. The consistency state recorded in the primary table entry includes modification, exclusive, shared, invalid, etc., and different states can be represented by different bit sequences, thereby being distinguished.

[0044] If the number of processor cores having data copies is increased, the length of the bit vector can be correspondingly increased to record.

[0045] Figure 2 In the embodiment, the subset number in the secondary table entry is used to select a subset, and if there is a processor core with a data copy in the 2nd subset and the 5th subset, the subset number is 2, and the current secondary table entry selects the 2nd subset.

[0046] The secondary table entry includes a subset number and a second bit vector, and the second bit vector identifies the processor core with a data copy in the subset identified by the subset number.

[0047] The second bit vector is Figure 2 In the embodiment, the bit vector in the secondary table entry.

[0048] The C cores of the multi-core system are coded from 1 to C, and every N cores form a subset, and there are C / N subsets, and the bit vector of the primary table entry of the directory is C / N bits, and if the i-th bit is 1, it indicates that there is a processor core with a data copy in the i-th subset, and if the j-th bit of the fine-grained bit vector is 1, it indicates that the number of the processor core with a data copy is .

[0049] In this way, when a consistency change operation occurs, the data copy state of all the processor cores with data copies can be found and updated through the two-level sparse directory.

[0050] The primary table entry and the secondary table entry are stored in the same data block and are distinguished by the highest bit of the table entry. The specific primary table entry and the secondary table entry can be distinguished by Figure 2 In the embodiment, the highest bit is 0 or 1, and in the figure, the highest bit is displayed at the leftmost side of each table entry. 0 indicates a primary table entry, and 1 indicates a secondary table entry.

[0051] By dividing the processor cores into subsets and using a two-level sparse directory, the application can accurately record the information of the data sharer and improve the data management efficiency. The first level identifies the subset containing the data copy through the bit vector, and the second level further locates the specific processor core in the subset, thereby optimizing the overall processing performance of the system.

[0052] The consistency change operation can include modifying the content of the shared resource in a processor core or deleting the shared resource, so that the consistency state of the data copy changes. Taking modification as an example, other processor cores holding data copies of the uniform shared resource need to modify the content synchronously, and then the target directory needs to be used to find the processor cores holding the data copies, so as to synchronize the data of the processor cores to achieve adjustment.

[0053] According to the scheme provided by the embodiment of the application, when the number of processor cores with data copies is small, the limited pointer directory is used to record the processor cores, and the pointer in the limited pointer directory can directly retrieve the specific core containing the data copy, the directory lookup process is simple, and the overall processing efficiency of the system and the management efficiency of the data sharing information can be significantly improved; when the number of processor cores of the shared resource exceeds the preset number threshold, the two-level sparse directory is automatically switched to in the case that the number of processor cores of the shared resource is large, the shared information of all processor cores is managed according to subsets, when the directory is queried, all processor cores in the system no longer need to be traversed, and only the subsets related to the data copy need to be focused on, more processor cores can be accommodated, the storage overhead is reduced, the system can maintain high efficiency while being expanded in scale, the directory switching mechanism ensures that the management strategy is dynamically adjusted according to different use scenarios, the shortcomings of a single directory structure are avoided, and significant performance improvement and stronger adaptability are brought to the large-scale multiprocessor system. Therefore, the expansibility, efficiency and flexibility of the data sharing management are increased, the network traffic and performance bottleneck are effectively reduced while the system processing capability is improved, and the availability of the directory is improved.

[0054] In an embodiment of the application, each pointer of the limited pointer directory is associated with C processor cores, and each pointer has a field of bits.

[0055] Each pointer has a field of bits, which is used to identify a specific processor core number.

[0056] In the related art, the bit vector needs to allocate a bit for each potential sharer, which leads to a large storage overhead in the case that the number of processor cores is large. In order to improve the efficiency, the pointer is used to record the shared resource. Specifically, in a chip with C processor cores, each core occupies 1 bit in the bit vector, and if the i-th bit in the bit vector corresponding to the i-th processor core is set to 1 and the other bits are set to 0, a complete C processor core sharing requires a C-bit bit vector.

[0057] As an improvement, each processor core uses a bit pointer, and after the improvement, a total of bits are required to record i processor cores. Research shows that many cache blocks actually have no sharer, and the sharer is a processor core holding a data copy or only one sharer, so in most cases The limited pointer directory has higher storage efficiency. The difference in efficiency is more obvious in large-scale systems involving more cores. In the hybrid directory architecture, whenever a new data block is accessed, the system will preferentially attempt to allocate a table entry in the limited pointer directory. This table entry is linked to the data copy through a pointer, enabling fast positioning and access, thereby providing significant operational efficiency in scenarios with fewer sharers.

[0058] When synchronizing data copies using a directory, in addition to sequentially retrieving the directory to find all processor cores holding the same data copy and adjusting the data copy according to the consistency change operation, an index can also be used. The first index of the first-level table entry is obtained based on the address information of the data block where the data copy is located; the second index of the second-level table entry is contained in the second bit vector, and the second index is obtained based on the hash operation of the first index and the subset number.

[0059] This associates the two-level index, and after finding the first index, the second index can be quickly obtained based on the hash operation of the first index.

[0060] Specifically, the first index uses the low M bits of the address excluding the offset within the data block as the set index. As shown in , the first-level table entry and the second-level table entry of the two-level sparse directory are stored in the same data block. Each row in the block stores a table entry, and M is the total number of rows in the block. Figure 3

[0061] Figure 3 and Figure 2 , , , …, Figure 3 are processor cores sharing n resources. Figure 2 The structure of the two-level sparse directory of is the same as the structure of the two-level sparse directory in

[0062] .

[0063] In another embodiment, the limited pointer directory and the two-level sparse directory share the directory storage space.

[0064] As shown in Figure 2 , the hybrid directory includes a limited pointer directory and a two-level sparse directory, which are stored in Set0-SetN

[0065] ​In the prior art, each data corresponds to a plurality of table entries, in order to improve the directory query speed, each way adopts a block of SRAM (Static Random-Access Memory) to support parallel access. SetM-SetN is divided into one path, and Set0-SetM-1 is divided into one path, forming a 2-way set associative.

[0066] The target table entry is any table entry to be added in the limited pointer directory, and can be a first-level or second-level table entry in the two-level sparse directory. If there is a null table entry, each field of the target table entry is directly filled with shared information.

[0067] The Set index of the two-level sparse directory, that is, the first index and the second index described above, is set to log2M bits, and the Set index of the limited pointer directory is set to log2(N-M) bits; for the limited pointer directory, the value of log2(N-M) bits of the address excluding the block offset is added to the number of Sets M of the sparse directory as the Set index.

[0068] According to the different degrees of data sharing in the system, M and N can be implemented as configurable parameters, and the most suitable M and N for the system are determined through experiments. By adjusting the ratio of the bit vector to the pointer record, the architecture can balance between the sparse directory and the limited pointer directory, while reducing the additional investment of hardware.

[0069] In an embodiment of the present application, if there is no null table entry in the directory storage space, the target table entry is used to replace the non-null table entry in the directory storage space, and the data copy corresponding to the replaced non-null table entry is invalidated.

[0070] When block conflict occurs due to insufficient directory capacity, a pseudo-LRU (Least Recently Used) replacement strategy can be used for replacement. In other embodiments, other directory replacement strategies can also be used, such as a first-in-first-out algorithm, an optimal replacement algorithm, etc., and the embodiments of the present application do not limit this.

[0071] If the replaced table entry is a second-level table entry, the Valid of the table entry is set to 0, all processor cores having data copies in the subset need to be invalidated, and the bit corresponding to the subset number in the bit vector of the first-level table entry is reset. According to the foregoing embodiment, the 1 representing the subset position is reset to 0. If the replaced table entry is a first-level table entry, all processor cores having data copies of the data need to be invalidated, that is, the data copies in these processor cores are deleted, and the Valid of all second-level table entries corresponding to the first-level table entry is set to an invalid position, and the Valid of the first-level table entry is set to an invalid position. Figure 2The V field in the first and second level entries of the finite pointer directory and the two-level sparse directory indicates whether the entry is valid. Specifically, the Valid field can be set to 0 to indicate invalidity and 1 to indicate validity. After allocation, setting the Valid field of the valid pointer entry to 0 is used. Compared to the traditional sparse directory replacement which requires invalidating all sharers, this scheme only requires invalidating all processor cores containing data copies when the first level directory is replaced, and only invalidates a subset of processor cores containing data copies in the second level directory, thus reducing the amount of data processing during the invalidation process.

[0072] In one embodiment of the present invention, a computer-readable storage medium is also provided, on which a computer program is stored, wherein when the computer program is executed by a processor, the hybrid directory setting method described in any of the above embodiments is implemented.

[0073] In one embodiment of the present invention, an electronic device is also provided, including: a memory and a processor; the memory stores a computer program, and when the computer program is executed by the processor, it implements the hybrid directory setting method described in any of the above embodiments.

[0074] Figure 4 This is a structural block diagram of an electronic device according to an embodiment of the present invention.

[0075] like Figure 4 As shown, the electronic device 400 includes a processor 401 and a memory 403. The processor 401 and the memory 403 are connected, for example, via a bus 402. Optionally, the electronic device 400 may also include a transceiver 404. It should be noted that in practical applications, the transceiver 404 is not limited to one type, and the structure of the electronic device 400 does not constitute a limitation on the embodiments of the present invention.

[0076] Processor 401 may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this invention. Processor 401 may also be a combination that implements computational functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0077] The bus 402 can include a path that transmits information between the above-described components. The bus 402 can be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The bus 402 can be divided into an address bus, a data bus, a control bus, etc. For convenience of representation, Figure 4 Only one thick line is used to represent the bus in the middle, but it does not mean that there is only one bus or one type of bus.

[0078] The memory 403 is used to store a computer program corresponding to the mixed catalog setting method of the above-described embodiments of the present application, which is controlled and executed by the processor 401. The processor 401 is used to execute the computer program stored in the memory 403 to realize the content shown in the above-described method embodiments.

[0079] Among them, the electronic device 400 includes but is not limited to: mobile terminals such as mobile phones, notebook computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Tablet PCs), PMPs (Portable Multimedia Players), vehicle terminals (such as vehicle navigation terminals), etc. and fixed terminals such as digital TVs, desktop computers, etc. Figure 4 The electronic device 400 shown is only an example, and should not bring any limitation to the function and use range of the embodiments of the present application.

[0080] It is to be appreciated that the above description and the examples that follow are intended to be illustrative only and that changes can be made to the description and examples without departing from the scope of the application. Note also that the use of particular brand names in the description is solely for illustration and should not be construed as an endorsement of such brands.

[0081] It should be understood that aspects of the application can be implemented in hardware, software, firmware or a combination thereof. In the above embodiments, various steps or methods can be implemented in software or firmware that is stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any of the following technologies, known in the art, can be used: a hybrid of the technologies mentioned above, discrete logic circuitry having logic gates for implementing logic functions upon an application of data signals, application specific integrated circuits having appropriate combinational logic gates, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0082] In the description of the present application, reference has been made to the use of terms such as "one embodiment", "some embodiments", "an example", "a specific example" or "some examples" means that a particular feature, structure, material or characteristic is included in at least one embodiment or example of the present application. The illustrative examples given are not necessarily to be construed as preferred or advantageous or with the exclusion of other equally valid examples that can be particularly adapted to a given application. Moreover, such illustrative examples are not necessarily mutually exclusive as the various aspects of the application can be combined in any suitable manner.

[0083] In the description of the application, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the application and simplifying the description, and does not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the application.

[0084] In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the application, the meaning of "a plurality of" is at least two, such as two, three, etc., unless otherwise explicitly specified and limited.

[0085] In the present application, unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting", "fixing" and the like should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or it can be integrated; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal communication of two elements or the interaction relationship between two elements, unless otherwise explicitly limited. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0086] In the present application, unless otherwise explicitly specified and limited, the first feature is "on" or "under" the second feature, which can be direct contact between the first and second features, or indirect contact between the first and second features through an intermediate medium. Moreover, the first feature "above", "above" and "above" the second feature can be directly above or obliquely above the first feature, or only indicate that the horizontal height of the first feature is higher than that of the second feature. The first feature "below", "below" and "below" the second feature can be directly below or obliquely below the first feature, or only indicate that the horizontal height of the first feature is less than that of the second feature.

[0087] Although the embodiments of the application have been shown and described above, it should be understood that the above embodiments are exemplary and cannot be understood as a limitation on the application, and those skilled in the art can make changes, modifications, replacements and variations to the above embodiments within the scope of the application.

Claims

1. A method for setting up a hybrid directory, characterized in that, The method includes: Determine the number of processor cores that have data copies of shared resources; If the number of processor cores does not exceed a preset threshold, a limited pointer directory is used as the target directory, and the pointers in the limited pointer directory are associated with processor cores that store data copies of shared resources. Otherwise, a two-level sparse directory is used as the target directory to divide the processor core into multiple subsets. The first-level table entries in the two-level sparse directory are used to identify the target subset where the processor core containing the data copy is located, and the consistency status of the data copy is recorded in the first-level table entries. The second-level table entries in the sparse directory are used to associate the processor cores containing the data copy in the target subset. If there is a processor core that performs a consistency change operation on shared resources, the data copy of the processor core containing the data copy is adjusted through the target directory so that each processor core synchronizes the consistency change operation.

2. The method according to claim 1, characterized in that, In the case where the pointers in the finite pointer directory are associated with C processor cores, each pointer has Bit fields.

3. The method according to claim 1, characterized in that, The first-level table entry includes a label field, a status bit, and a first bit vector, wherein the label field identifies the address of the shared resource, the status bit records the consistency status, and the first bit vector identifies a subset of data copies of the shared resource.

4. The method according to claim 3, characterized in that, The secondary entry includes a subset number and a second bit vector, the second bit vector identifying the processor core that has the data copy within the subset identified by the subset number.

5. The method according to claim 4, characterized in that, The first index of the first-level table entry is obtained based on the address information of the data block where the data copy is located; the second bit vector contains the second index of the second-level table entry, and the second index is obtained based on the hash operation of the first index and the subset number.

6. The method according to claim 1, characterized in that, The finite pointer directory and the two-level sparse directory share the same directory storage space; If there is a target table entry to be allocated, and there is an empty table entry in the directory storage space, then the empty table entry is allocated to the target table entry.

7. The method according to claim 6, characterized in that, If there are no empty entries in the directory storage space, the target entry is used to replace the non-empty entries in the directory storage space, and the data copy corresponding to the replaced non-empty entry is invalidated.

8. The method according to claim 1, characterized in that, The first-level entries and the second-level entries are stored in the same data block and are distinguished by the highest bit of the entry.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the hybrid directory setting method as described in any one of claims 1-8.

10. An electronic device, characterized in that, include: Memory, processor; The memory stores a computer program, which, when executed by the processor, implements the hybrid directory setting method as described in any one of claims 1-8.

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