Methods, apparatus, and media for chip placement

Abstract

Methods, devices and media for chip layout are provided according to example embodiments of the present disclosure. In the method, a plurality of elements are obtained, each element representing one chip to be placed in a target area. Then, the plurality of elements are sequentially placed in a plurality of sub-areas in the target area along a first direction by performing the following placement operations: selecting a target element from the elements of the plurality of elements that are not placed, based on sizes of the elements that are placed in the target area; and determining a placement position of the target element based on positions of the elements that are placed in a current sub-area and cutting paths of the elements that are placed in the target area, if the current sub-area is not the first sub-area in the target area. In this way, not only the automation of the layout can be achieved, but also the cutting paths can be ensured to be as straight as possible, so as to achieve a balance between higher mask utilization and lower cutting loss.

Description

Technical Field

[0001] The embodiments of this disclosure primarily relate to the field of computer-aided design, and more specifically, to methods, apparatus, and media for chip layout. Background Technology

[0002] In integrated circuit (IC) manufacturing, after the chip design is completed, the circuit patterns corresponding to multiple chips are often arranged on a mask (also called a photomask). This process is also called chip layout. Then, the circuit pattern is transferred to a wafer with the help of the mask, and the chip is obtained by cutting the wafer.

[0003] The area of ​​a mask available for chip placement is typically fixed. The goal is to place as many chips as possible within a single mask to reduce manufacturing costs and improve raw material utilization. Furthermore, the dicing process inevitably causes wafer wear, affecting chip yield. Therefore, improving mask utilization and reducing dicing losses are pressing issues that need to be addressed. Summary of the Invention

[0004] In a first aspect of this disclosure, a method for chip layout is provided. The method includes: acquiring a plurality of elements, each element representing a chip to be placed in a target region; and sequentially placing the plurality of elements in a plurality of sequentially adjacent sub-regions in the target region along a first direction by performing the following layout operations: selecting a target element from the plurality of unplaced elements based on the size of elements already placed in the target region; and if the current sub-region to be filled is not the first sub-region in the target region, determining the placement position of the target element based on the position of elements already placed in the current sub-region and the cutting edges of elements already placed in the target region.

[0005] In a second aspect of this disclosure, an electronic device is provided. The electronic device includes a processor and a memory coupled to the processor. The memory has instructions stored therein, which, when executed by the processor, cause the electronic device to perform a method for chip layout according to a first aspect of this disclosure.

[0006] In a third aspect of this disclosure, a computer-readable storage medium is provided. A computer program is stored on the computer-readable storage medium. When executed by a processor, the computer program implements a method for chip layout according to a first aspect of this disclosure.

[0007] According to the embodiments of this disclosure, the element to be placed is selected by considering the size of the already placed elements, and the placement position of the element to be placed is determined by considering the position of the already placed elements and their cutting paths. In this way, chip layout can be automated, eliminating reliance on manual experience, effectively improving layout efficiency, and making layout experience easily reusable and disseminated. Furthermore, by considering both the element size and the cutting paths of the already placed elements, the cutting path can be optimized, ensuring the cutting paths are as straight as possible while also maximizing area utilization. This approach reduces cutting complexity and time, and achieves a balance between high mask utilization and low cutting loss.

[0008] It should be understood that the content described in this summary section is not intended to limit the key or essential features of the embodiments of this disclosure, nor is it intended to restrict the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0009] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. In the drawings, the same or similar reference numerals denote the same or similar elements, wherein:

[0010] Figure 1 A schematic diagram of an example environment in which the various embodiments of this disclosure can be implemented is shown;

[0011] Figure 2 A schematic diagram illustrating chip-based generation of corresponding elements according to some embodiments of the present disclosure is shown;

[0012] Figures 3 to 13 Schematic diagrams of chip layout processes according to some embodiments of the present disclosure are shown respectively;

[0013] Figure 14 A flowchart of a method for chip layout according to some embodiments of the present disclosure is shown; and

[0014] Figure 15 A block diagram of an electronic device in which one or more embodiments of the present disclosure may be implemented is shown. Detailed Implementation

[0015] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0016] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0017] Chip layout using masks generally falls into two categories: the first is product-specific masks for mass production; the second is masks used for multi-project wafers (MPW) or technology qualification vehicles (TQV). In the first type, each chip on the mask is usually the same size, but sometimes a small number of chips with different sizes may exist. The main purpose of the second type is to reduce development costs by sharing masks for chips of different designs. In this shared mask application scenario, the size of each chip is often different.

[0018] As mentioned above, to improve mask utilization and reduce dicing losses, the chips to be manufactured need to be rationally arranged on the mask to fully utilize the mask and optimize the dicing path. One existing solution is manual arrangement. This solution relies heavily on human experience, resulting in low arrangement efficiency, difficulty in reusing and disseminating experience, and limitations in the number of times and methods that can be performed manually, leading to problems such as uneven dicing paths and low area utilization.

[0019] Therefore, embodiments of this disclosure propose a scheme for chip layout. According to various embodiments of this disclosure, elements representing chips are laid out by considering the positions of already placed elements and the cutting edges of the already placed elements. Specifically, according to the chip layout scheme of embodiments of this disclosure, multiple elements are obtained, each element representing a chip to be placed in a target area. Further, the multiple elements are sequentially placed in multiple adjacent sub-areas along a first direction in the target area by performing the following layout operations: selecting a target element from the unplaced elements among the multiple elements based on the size of the already placed elements in the target area; and if the current sub-area to be filled is not the first sub-area in the target area, determining the placement position of the target element based on the positions of the already placed elements in the current sub-area and the cutting edges of the already placed elements in the target area.

[0020] As will be more clearly understood from the following description, according to the embodiments of this disclosure, the element to be placed is selected by considering the size of the already placed elements, and the placement position of the element to be placed is determined by considering the position of the already placed elements and the cutting paths of the already placed elements. In this way, chip layout can be automated, thus eliminating reliance on manual experience, effectively improving layout efficiency, and making layout experience easily reusable and disseminated. Furthermore, by considering both the element size and the cutting paths of the already placed elements, the cutting path can be optimized, ensuring the cutting paths are as straight as possible while also maximizing area utilization. This approach reduces cutting complexity and time, and achieves a balance between high mask utilization and low cutting loss.

[0021] Example Environment

[0022] The following will describe in detail various example implementations of this scheme with reference to the accompanying drawings. First, see... Figure 1 The illustration shows a schematic diagram of an example environment 100 in which the various embodiments of the present disclosure can be implemented. Example environment 100 may generally include electronic device 120. In some embodiments, electronic device 120 may be a computing device such as a personal computer, workstation, server, etc. The scope of the present disclosure is not limited in this respect.

[0023] Electronic device 120 can acquire multiple elements 110-1, 110-2, ..., 110-N (hereinafter referred to individually or collectively as element 110), where N is a positive integer and represents the number of chips to be arranged. Each element 110 can represent the chip to be placed in a target area (e.g., ...). Figure 3 One of several chips within the target area 320. Figure 1In the diagram, element 110 is shown as having a rectangular shape. It should be understood that element 110 can also have any other suitable shape, such as a triangle, parallelogram, trapezoid, pentagon, etc.

[0024] In some embodiments, element 110 may be input by a user into electronic device 120. In other embodiments, element 110 may have been pre-stored in electronic device 120. In still other embodiments, element 110 may be generated by electronic device 120. In yet another embodiment, electronic device 120 may also be communicatively coupled to other devices to obtain element 110 from those other devices. The scope of this disclosure is not limited in this respect.

[0025] Electronic device 120 can select element 110 to be placed based on the size of elements already placed in the target area, and further determine the placement position of element 110 by considering the position of elements already placed in the current sub-region and the cutting edges of the placed elements. This will be discussed in detail below. Figures 3 to 13 Further detailed description. It should be understood that the structure and function of environment 100 are described for illustrative purposes only and do not imply any limitation on the scope of this disclosure.

[0026] Example chip layout process

[0027] See below for reference Figures 2 to 13 This section outlines a chip layout process according to exemplary embodiments of the present disclosure. As briefly mentioned above, electronic device 120 may acquire a plurality of elements 110. Each of these elements 110 represents one of a plurality of chips to be placed within a target area 320. In some embodiments, the shape and size of element 110 may depend on the shape and size of the chip it represents. Electronic device 120 may acquire the shape and / or size of the chip by any suitable means, for example, by parsing a file describing chip information, or by receiving shape and / or size information input by a user.

[0028] In some embodiments, element 110 has the same shape as the corresponding chip, and its dimensions are the same as the corresponding chip dimensions. In other embodiments, element 110 has the same shape as the corresponding chip, but its dimensions depend on the chip dimensions and a preset spacing between different chips. This preset spacing may be associated with a dicing channel, for example, determined based on factors such as cracks generated during dicing or the actual dimensions of the dicing channel. In the context of this disclosure, a dicing channel refers to a spacing structure between chips to facilitate dicing. A dicing channel may also be referred to as a scribe line, saw channel, or street.

[0029] Exemplarily, and not limitingly, the preset spacing can be set to be equal to the actual size of the dicing channel, for example, 80 μm, 150 μm, etc. Furthermore, the element 110 corresponding to the chip can be obtained by expanding the preset spacing outward by half based on the chip's shape and size.

[0030] refer to Figure 2 This illustrates a schematic diagram 200 of generating corresponding elements 110-K based on chip 210-K according to some embodiments of the present disclosure, where K can be any positive integer less than or equal to N. For example... Figure 2 As shown, chip 210-K has a rectangular shape with a length of L1 and a width of W1. It should be noted that... Figure 2 The shape and dimensions of the chip 210-K shown are illustrative and not limiting. The element 110-K corresponding to chip 210-K can also have a rectangular shape with a length of L2 and a width of W2. The length L1 and width W1 of chip 210-K and the length L2 and width W2 of element 110-K can, for example, satisfy the following relationship: L2 = L1 + 2 × LD, and W2 = W1 + 2 × WD. LD is the expansion distance in the length direction, for example, equal to half of the preset spacing, and WD is the expansion distance in the width direction, for example, equal to half of the preset spacing. It should be understood that the dimensional relationship between chip 210-K and element 110-K is exemplary and not limiting, and the expansion distance can also be any other suitable value, for example, equal to the preset spacing.

[0031] It is understood that when two elements 110 generated in the above manner are placed close together, the distance between the corresponding two chips can be guaranteed to meet the preset spacing requirement. Therefore, it can be ensured that the distance between each chip in the layout result 130 meets the preset spacing requirement, thereby facilitating subsequent cutting operations and minimizing the cutting of defective chips. In this way, the chip yield can be effectively improved. It should be understood that the corresponding elements 110 can also be generated based on the chips in any other suitable manner, and the scope of this disclosure is not limited in this respect.

[0032] Research has revealed that, since chips may not fill the entire exposure area of ​​a mask during actual chip layout, it is necessary to determine the size constraints of the target area required for the actual layout in order to place the chips as compactly as possible. In some embodiments, the size constraints of the target area can be determined based on the maximum exposure size of the mask for multiple chips and the total area of ​​the multiple elements. In one example embodiment, the ratio of the maximum exposure size in a first direction to the maximum exposure size in a second direction that is different from the first direction can be determined. In some embodiments, the first and / or second directions can be any suitable direction. Exemplarily, the second direction can be orthogonal to the first direction. In one embodiment, the first direction can be vertically upward and the second direction can be horizontally to the right. In another embodiment, the first direction can be horizontally to the left and the second direction can be vertically downward. For ease of illustration, the following description uses the example of the first direction being vertically upward (corresponding to the height direction) and the second direction being horizontally to the right (corresponding to the width direction). It should be understood that the second direction can also be any suitable direction other than the first direction, and the scope of this disclosure is not limited in this respect.

[0033] Furthermore, based on the determined proportions and the total area of ​​the multiple elements, dimensional constraints for the target region can be determined. As an example, rather than a constraint, the dimensional constraints for the target region can be determined based on the following formula:

[0034]

[0035] Where TS1 represents the size of the target area in the first direction, TS2 represents the size of the target area in the second direction, MS1 represents the maximum exposure size in the first direction, and MS2 represents the maximum exposure size in the second direction, and... The total area of ​​multiple elements can be represented. This method can also be referred to as a forward determination method for the actual exposure size. It should be understood that the size limit for the target area can also be determined in any other suitable manner based on the determined proportions and the total area of ​​multiple elements, and the scope of this disclosure is not limited in this respect.

[0036] In this way, the size limit of the target area can be approximately proportional to the maximum exposure size limit, allowing the chip to be distributed as evenly as possible around the exposure center. Since the closer to the exposure center, the better the exposure quality in subsequent photolithography processes, this can effectively improve the overall exposure quality of the mask, thereby increasing the chip yield.

[0037] In another embodiment, the size constraint for the target region can be determined based on the following formula:

[0038]

[0039] Among them TS1 -2 TS2 can represent the position of the boundary between the penultimate and last sub-regions in a first direction (this will be described in further detail below), MS2 can represent the size of the target region in a second direction different from the first direction, and MS2 can represent the size of the maximum exposure size in the second direction. This can represent the total area of ​​multiple elements. This method can also be called a backward-looking determination method based on the actual exposure size. In this way, the size limit of the target area can be dynamically determined according to the real-time layout status, thus making the size limit more flexible.

[0040] It should be understood that the size limit of the target area can also be determined in any other suitable manner. For example, the size can be predetermined, or it can be equal to the maximum exposure size, and the scope of this disclosure is not limited in this respect. For ease of description, the above-described backward determination method will be used as an example below. It should be understood that the use of this method is for illustrative purposes only and does not constitute a limitation on the scope of this disclosure.

[0041] Furthermore, the electronic device 120 can perform layout operations based on the size constraints of the target area, which will be referred to below. Figures 3 to 13 Let me describe it in detail. Figures 3 to 13 Schematic diagrams of chip layout processes according to some embodiments of the present disclosure are shown.

[0042] If no elements are yet placed in the target area, elements that meet predetermined conditions can be placed in predetermined positions within the target area. These predetermined conditions can be any suitable criteria, such as maximum area, maximum height, or the largest number of elements of the same size. For ease of description, the following explanation uses the maximum area as an example. (Reference) Figure 3 As shown, select element 110-1, which has the largest area among all elements 110. This method prioritizes elements that will occupy a larger area, thereby improving layout efficiency and quality.

[0043] Then, element 110-1 can be placed in the predetermined position within target area 320. Figure 3 In the example, the predetermined position is the lower left corner of the target area 320. It should be understood that the predetermined position can also be any position within the target area 320. For example, if the first direction is horizontal to the left and the second direction is vertical downwards, the predetermined position could be the upper right corner. This disclosure does not limit this.

[0044] like Figure 3 As shown, after placing element 110-1 into target region 320, the upper boundary 330-1 of the first sub-region 310-1 is obtained. As will be understood from the following description, this upper boundary 330-1 corresponds to the cutting path along the second direction for all elements in sub-region 310-1, and its position can change as other elements are subsequently placed in sub-region 310-1. Sub-region 310-1 can be determined as the current sub-region to be filled. In the context of this disclosure, a sub-region can refer to a plurality of adjacent intervals along the first direction within target region 320, in which one or more elements can be placed.

[0045] Furthermore, based on the dimensions of the elements already placed in the target area 320, the target element to be placed can be selected from the unplaced elements among a plurality of elements. If elements are already placed in the current sub-area, the first direction reference dimension can be determined based on the dimension of at least one element in the current sub-area in the first direction. For example, if only one element exists in the current sub-area, the dimension of that element in the first direction can be determined as the first direction reference dimension. Figure 3 In the example shown, the current sub-region 310-1 contains only element 110-1. Therefore, the first direction reference dimension can be determined based on the dimension of element 110-1 in the first direction (i.e., the vertical direction in this embodiment). In this example, the first direction reference dimension is the height of element 110-1.

[0046] Furthermore, a target element can be selected from the unplaced elements based on a first-direction reference dimension. For example, the selected target element could be the unplaced element whose dimension in the first direction has the smallest absolute difference from the first-direction reference dimension. Figure 3 In the example, the element whose height has the smallest absolute difference from element 110-1 can be selected (i.e., Figure 4 Element 110-2 is used as the target element. In this way, the dimensions of elements placed in the same sub-region will be as close as possible in the first direction, thereby reducing wasted area while ensuring that the cutting path can be straight along the second direction.

[0047] It should be understood that the target element can also be selected in any other way based on the first direction reference dimension among elements that have never been placed; for example, the element with the largest area can be selected from among multiple elements whose absolute difference from the first direction reference dimension is less than a threshold. The scope of this disclosure is not limited in this respect.

[0048] Next, the placement of element 110-2 needs to be determined. If elements are already placed in the target area 320 and the current sub-area is the first sub-area in the target area 320, the placement of the target element can be determined based on the positions of the elements already placed in the current sub-area. In one embodiment, a candidate placement position for the target element can be determined as a position that is adjacent to the boundary of the target area 320 in a first direction and adjacent to the previously placed element in a second direction. Further, if it is determined that placing the target element in the candidate placement position will not exceed the target area 320, the candidate placement position can be determined as the target element's placement position. If it is determined that placing the target element in the candidate placement position will exceed the target area 320, the target element is reassigned to the unplaced elements to determine its placement position in a sub-area following the current sub-area.

[0049] Reference Figure 4 Since element 110-1 has already been placed in target area 320, and the current sub-area 310-1 is the first sub-area in the target area, the position within sub-area 310-1 that is horizontally adjacent to element 110-1 and vertically adjacent to the lower boundary of target area 320 can be determined as the candidate placement position for element 110-2. Because placing element 110-2 in this candidate placement position will not exceed target area 320, this candidate placement position can be determined as the actual placement position for element 110-2. Figure 4 The placement of element 110-2. In this way, the elements placed in each sub-region can be close to each other in the second direction, thereby improving the area utilization of the mask.

[0050] It should be noted that, since the height of element 110-2 is greater than the height of element 110-1, after element 110-2 is placed, the upper boundary of sub-region 310-1 relative to its height... Figure 3 The position in the middle is moved upward. In other words, the region cutting path between subregion 310-1 and its adjacent subregions is determined based on the maximum height of the elements already placed in subregion 310-1.

[0051] Furthermore, the next target element to be placed can be selected from among the unplaced elements based on the dimensions of the elements already placed in the target area 320. For example, a first-direction reference dimension can be determined based on the dimension of at least one element in the current sub-region in the first direction. If multiple elements exist in the current sub-region, the average dimension of the multiple elements in the first direction can be determined as the first-direction reference dimension. Figure 4 As shown, elements 110-1 and 110-2 are already placed within the target area 320, therefore the average height of elements 110-1 and 110-2 can be determined as the first directional reference dimension. In some embodiments, the average value can be calculated based on an arithmetic mean. Alternatively, the average value can be calculated based on a weighted average, for example, the weights can be proportional to the element area. In still other embodiments, the average value can be calculated based on a geometric mean. The scope of this disclosure is not limited in this respect.

[0052] It should be noted that, in other embodiments, even if multiple elements already exist in the current sub-region, the first direction reference dimension can be determined by considering only the dimension of the previously placed element in the first direction. The scope of this disclosure is not limited in this respect.

[0053] Furthermore, target elements can be selected from the unplaced elements based on a first-direction reference dimension. For example, the selected target element could be the unplaced element whose dimension in the first direction has the smallest absolute difference from the first-direction reference dimension. Figure 4 In the example, the element with the smallest absolute difference from the average height of elements 110-1 and 110-2 can be selected (i.e., Figure 5 Element 110-3 is used as the target element. The process of determining the placement of element 110-3 is the same as the one mentioned above. Figure 4 The process of determining the placement of element 110-2 is similar and will not be repeated here.

[0054] After the placement of sub-region 310-1 is completed (for example) Figure 5 As shown, after element 110-3 is placed in the manner described above, subsequent elements cannot be added to sub-region 310-1, and the placement operation will continue to the next sub-region.

[0055] To select a target element from among multiple elements that are not currently placed, when no elements are currently placed in the current sub-region, a second-direction reference dimension can be determined based on the second-direction dimension of at least one element in at least one sub-region that was filled before the current sub-region. For example, if only one sub-region exists before the current sub-region, the second-direction reference dimension can be determined by the second-direction dimension of an element at a predetermined position in that sub-region. The determination method when multiple sub-regions exist before the current sub-region will be discussed below. Figure 11 Further detailed description.

[0056] refer to Figure 5 The example shown shows that, due to the second sub-region (in) Figure 5 Not shown in the image, corresponding to Figure 6 Since there was only one subregion 310-1 before subregion 310-2, the second direction reference dimension can be determined based on the dimension of element 110-1 in the second direction (i.e., the width of element 110-1).

[0057] Furthermore, a target element can be selected from the unplaced elements based on the second-direction reference dimension. For example, the selected target element could be the unplaced element whose dimension in the second direction has the smallest absolute difference from the second-direction reference dimension. Figure 5 In the example, you can choose the element whose width has the smallest absolute difference from element 110-1 (i.e., Figure 6 The elements in the first column (110-4) are used as the target elements. In this way, the widths of the elements placed in the first column will be as similar as possible, so that the cutting path is as straight as possible in the vertical direction.

[0058] It should be understood that the target element can also be selected in any other way based on the second-direction reference dimension from elements that have never been placed, such as selecting the element with the largest area from a plurality of elements whose absolute difference from the second-direction reference dimension is less than a threshold. The scope of this disclosure is not limited in this respect.

[0059] Next, the placement of element 110-4 needs to be determined. If the current sub-region to be filled is not the first sub-region in the target region 320, the placement of the target element can be determined based on the positions of elements already placed in the current sub-region and the cutting edges of elements already placed in the target region 320. For example, if no element has been placed in the current sub-region, the target element can be placed at a position that is immediately adjacent to the cutting edge between the current and previous sub-regions in a first direction and immediately adjacent to the boundary of the target region 320 in a second direction, where the cutting edge is determined based on the maximum size of elements already placed in the previous sub-region in the first direction.

[0060] Reference Figure 5 Since no elements have been placed in the second sub-region, the position of element 110-4 can be determined as being adjacent to the upper boundary 330-1 of sub-region 310-1 (i.e., the region cutting path) in the vertical direction and adjacent to the left boundary of target region 320 in the horizontal direction. In this way, on the one hand, the right boundary of the first element placed in each sub-region will be aligned as much as possible, so that the cutting path is as straight as possible in the vertical direction. On the other hand, adjacent sub-regions can be close to each other in the first direction, thereby improving the area utilization of the mask.

[0061] like Figure 6 As shown, after placing element 110-4 in the aforementioned position, the upper boundary 330-2 of the second sub-region 310-2 is obtained. Similar to the upper boundary 330-1 of sub-region 310-1 described above, the upper boundary 330-2 of this second sub-region 310-2 corresponds to the cutting path along the second direction for all elements in sub-region 310-2, and its position can change as other elements are subsequently placed in sub-region 310-2. Sub-region 310-2 can be determined as the current sub-region to be filled.

[0062] After placing element 110-4, you can select the next target element to place. This is similar to the above reference. Figure 4 The selection of element 110-2 is achieved in the same way. That is, the element with the smallest absolute difference in height from element 110-4 can be selected (i.e., Figure 9 The element 110-5 in the middle is used as the target element.

[0063] Next, the placement of element 110-5 needs to be determined. If elements are already placed in the current sub-region, the placement of the target element can be determined based on the boundary of the previously placed element and the cutting paths between elements already placed in the sub-regions filled before the current sub-region. Furthermore, from the cutting paths between elements already placed in the sub-regions filled before the current sub-region, the cutting path that is closest in the second direction to the reference boundary of the previously placed element adjacent to the portion to be filled in the current sub-region can be determined as the reference cutting path. Figure 6 In the example, the previous element placed is element 110-4 in subregion 310-2, the reference boundary is the right boundary of element 110-4, and the reference cutting path is the cutting path 340-1 between element 110-1 and element 110-2 in subregion 310-1.

[0064] Furthermore, candidate placement positions for the target element can be determined based on the relative position between the reference boundary and the reference cutting channel. For example, if the absolute value of the distance between the reference boundary and the reference cutting channel is greater than or equal to a threshold, a first position in the current sub-region can be determined as a candidate placement position, wherein the first position is adjacent to the region cutting channel in a first direction and adjacent to the reference boundary in a second direction. In some embodiments, the threshold can be determined based on a preset cutting channel width. For example, the threshold can be set as the product of a preset cutting channel width and a preset space waste coefficient (e.g., 1.1 or 1.2, etc.). It should be understood that the threshold can also be a preset fixed value or a dynamic value determined in real time in any form, and this disclosure does not limit this. As will be understood from the following description, by means of this threshold, the ratio of space waste can be controlled, thereby effectively preventing excessive waste of area to ensure straight-through cutting channels.

[0065] refer to Figure 7 Assuming the absolute value of the distance between the reference boundary (i.e., the right boundary of element 110-4) and the reference cut (i.e., cut 340-1) is greater than or equal to a threshold, the area wasted in aligning the left boundary of element 110-5 with cut 340-1 would be significant in this case. To address this, we can... Figure 7 The position 710 shown is determined as a candidate placement position for element 110-5. This position 710 is vertically adjacent to the area cutting channel (i.e., cutting channel 330-1) between sub-regions 310-1 and 310-2, and horizontally adjacent to the reference boundary (i.e., the right boundary of element 110-4).

[0066] If the absolute value of the distance between the reference boundary and the reference cut line is less than a threshold and the extension line of the reference cut line does not cross the previously placed element, then a second position in the current sub-region can be determined as a candidate placement position, which is adjacent to the region cut line in the first direction and adjacent to the extension line of the reference cut line in the second direction. Reference Figure 8 Assuming the absolute value of the distance between the reference boundary (i.e., the right boundary of element 110-4) and the reference cut line (i.e., cut line 340-1) is less than a threshold, and the extension line of the reference cut line does not pass through the previously placed element (i.e., element 110-4), the area wastage caused by aligning the left boundary of element 110-5 with cut line 340-1 is still within an acceptable range, and cutting along cut line 340-1 will not damage element 110-4. Therefore, it is possible to... Figure 8 The position 810 shown is determined as a candidate placement position for element 110-5. This position 810 is vertically adjacent to the area cutting channel (i.e., cutting channel 330-1) between sub-regions 310-1 and 310-2, and horizontally adjacent to the extension line of cutting channel 340-1.

[0067] In some embodiments, a coordinate system can be established based on the target area, and the coordinates of each placed element can be determined. This allows for comparison of coordinates to determine whether the extension line of the reference cutting path will pass through the previously placed element. For example, the reference cutting path can be calculated in the second direction (in... Figure 8 In the example, the coordinate value in the horizontal direction is subtracted from the largest coordinate value of the previously placed element in the second direction. The sign of the result is used to determine the direction. If the result is positive, the extension line of the reference cutting path will not pass through the previously placed element; otherwise, it will.

[0068] As can be seen, by considering the threshold of the area that can be wasted to ensure the straightness of the cutting path, the candidate placement position of the target element can be determined, which can effectively achieve a balance between low cutting loss and high area utilization, and can avoid cutting damage to the chip and improve the yield of the finished product.

[0069] For ease of description, the following text will use the term "foreign language". Figure 8Taking position 810 as a candidate placement position for element 110-5 as an example, the layout process continues. Similar to the description of element 110-2 above, if it is determined that placing the target element in the candidate placement position will not exceed the target area 320, then the candidate placement position is determined as the placement position of the target element. If it is determined that placing the target element in the candidate placement position will exceed the target area 320, then the target element is returned to the unplaced elements to determine the placement position of the target element in the sub-area after the current sub-area. Since placing element 110-5 in position 810 will not exceed the target area 320, position 810 can be determined as the actual placement position of element 110-5.

[0070] It should be noted that since the height of element 110-5 is less than the height of element 110-4, the upper boundary of sub-region 310-2 remains aligned with the upper boundary of element 110-4 after element 110-5 is placed.

[0071] Furthermore, the next target element to be placed can be selected from the unplaced elements among multiple elements based on the size of the elements already placed in sub-region 310-2, in the same way as the element selection 110-3 above. Figure 10 The element 110-6 in the text.

[0072] Next, we need to determine the placement of element 110-6. For this, we can refer to the above... Figure 6 The same method described is used to determine the reference boundary and reference cut line that need to be considered at this point. Figure 8 In the example, the previous element placed is element 110-5 located at position 810 in subregion 310-2, the reference boundary is the right boundary of element 110-5, and the reference cutting path is the cutting path 340-2 between element 110-2 and element 110-3 in subregion 310-1.

[0073] refer to Figure 9 Assuming that the absolute value of the distance between the reference boundary (i.e., the right boundary of element 110-5) and the reference cutting path (i.e., cutting path 340-2) is less than a threshold and the extension line of the reference cutting path passes through the previous placed element (i.e., element 110-5), the following first position in the current sub-region can be determined as a candidate placement position, which is close to the region cutting path in the first direction and close to the reference boundary in the second direction.

[0074] exist Figure 9In the example, position 910 can be identified as a candidate placement location for element 110-6. Position 910 is vertically adjacent to the area cut-out channel (cut-out channel 330-1) between sub-regions 310-1 and 310-2, and horizontally adjacent to the reference boundary (i.e., the right boundary of element 110-5). Since placing element 110-6 at position 910 will not exceed the target area 320, position 910 can be identified as the actual placement location for element 110-6. In this way, elements within the same sub-region can be placed as close as possible to each other in the second direction without damaging the chip, thereby improving area utilization.

[0075] It should be noted that, in this case, the cutting path between element 110-5 and element 110-6 at position 910 is not cutting path 340-2, but corresponds to the boundary between element 110-5 and element 110-6.

[0076] In some additional embodiments, when elements 110-6 are placed at position 910, the cutting path along the first direction can be adjusted by attempting to move elements in previously placed sub-regions. For example, for a sub-region that was filled before the current sub-region, it can be determined whether moving one or more elements in that sub-region after the reference cutting path in the second direction by the absolute value of the distance between the reference boundary and the reference cutting path would exceed the target region 320. If it is determined that it would exceed the target region 320, then no movement of one or more elements may be performed. If it is determined that it would not exceed the target region 320, then movement of one or more elements may be performed.

[0077] exist Figure 9 In the example, it can be determined that the element after cutting path 340-2 in sub-region 310-1 before the current sub-region 310-2 (i.e., element 110-3) will not exceed the target region 320 after moving it a distance D1 to the right. Therefore, element 110-3 can be moved a distance D1 to the right. (See reference) Figure 10 After moving element 110-3, elements 110-2 and 110-3, and elements 110-5 and 110-6, can share the same cutting path 340-2, thus making the cutting path in the first direction (i.e., the vertical direction) as straight as possible. It should be understood that when there are multiple sub-regions before the current sub-region, it can be determined for each sub-region in the above manner whether the cutting path can be aligned by moving elements.

[0078] In this way, the alignment of the cutting tracks can be dynamically adjusted during the layout process to select the local optimal solution, thereby making the cutting tracks as straight as possible without affecting the area utilization rate, so as to further reduce cutting losses.

[0079] It should be understood that the placement position of the target element can also be determined in any other suitable manner based on the positions of elements already placed in the current sub-region and the cutting lines of elements already placed in the target region. In some alternative embodiments, the position of the cutting line that is adjacent to the region cutting line in a first direction and adjacent to the cutting line of the previous element already placed in the same sub-region in a second direction can be directly determined as the position of the target element to be placed. In other alternative embodiments, if the extension line of the reference cutting line passes through the previous placed element or the absolute value of the distance between the reference boundary and the reference cutting line is greater than or equal to a threshold, then a first position in the current sub-region is determined as a candidate placement position, which is adjacent to the region cutting line in a first direction and adjacent to the reference boundary in a second direction. Otherwise, a second position in the current sub-region is determined as a candidate placement position, which is adjacent to the region cutting line in a first direction and adjacent to the extension line of the reference cutting line in a second direction. The scope of this disclosure is not limited in this respect.

[0080] Furthermore, elements 110-7 can be selected and placed in the manner described above to complete the filling of sub-region 310-2.

[0081] The next target element to be placed can then be selected using a process similar to that described above for selecting element 110-4. However, the difference lies in the fact that multiple sub-regions (i.e., sub-regions 310-1 and 310-2) exist prior to the current sub-region. For this purpose, the average size of the dimensions of the elements at predetermined positions in the multiple sub-regions in the second direction can be determined as the second-direction reference size. In some embodiments, the average size can be calculated based on an arithmetic mean. Alternatively, the average size can be calculated based on a weighted average, for example, the weights can be proportional to the element area. In still other embodiments, the average size can be calculated based on a geometric mean. The scope of this disclosure is not limited in this respect.

[0082] It should be noted that, in some embodiments, even if multiple sub-regions exist before the current sub-region, the second direction reference dimension can be determined by considering only the dimension of the element at a predetermined position in the previous sub-region (e.g., the first element, etc.) in the second direction. The scope of this disclosure is not limited in this respect.

[0083] Furthermore, a target element can be selected from the unplaced elements based on the second-direction reference dimension. The selected target element can be the unplaced element whose dimension in the second direction has the smallest absolute difference from the second-direction reference dimension. Figure 11 In the example, you can choose the element with the smallest absolute difference from the average width of elements 110-4 and 110-1 (i.e., Figure 12The elements 110-8 in the table are used as the target elements.

[0084] Next, we need to determine the placement of elements 110-8. (Refer to...) Figure 12 Since no element has been placed in the third sub-region, the position of element 110-8 can be determined as the position that is close to the upper boundary 330-2 of sub-region 310-2 in the vertical direction (i.e., the region cutting channel) and close to the left boundary of target region 320 in the horizontal direction.

[0085] Then, the electronic device can continue to select and place the target element from the remaining unplaced elements in a manner similar to that described above, until all elements 110 have been placed, or until the target area 320 can no longer place another element 110.

[0086] Figure 13 A schematic diagram illustrating the final result of a chip layout process according to some embodiments of the present disclosure is shown. It can be seen that there are M sub-regions sequentially adjacent along the vertical direction, namely sub-regions 310-1 to 310-M, where M is a positive integer. The boundary between the second-to-last sub-region and the last sub-region corresponds to boundary 330-(M-1), and the upper boundary of the last sub-region corresponds to boundary 330-M. It can be seen that in the layout results obtained by the chip layout schemes according to various embodiments of the present disclosure, it is possible to achieve a layout along the second direction (in... Figure 13 In the example, the horizontal direction) the cut is very straight, and along the first direction (in Figure 13 In the example (where the cutting path is vertical), the cutting path should also be as straight as possible. Straight cutting paths can increase cutting efficiency and reduce chip waste during the cutting process.

[0087] Through the above combination Figures 2 to 13 As described, in the chip layout schemes according to various embodiments of this disclosure, the elements to be placed are selected by considering the size of already placed elements, and the placement position of the elements to be placed is determined by considering the positions of already placed elements and their cutting paths. In this way, chip layout can be automated, eliminating reliance on manual experience, effectively improving layout efficiency, and making layout experience easily reusable and disseminated. Furthermore, by considering both element size and the cutting paths of already placed elements, the cutting path can be optimized, ensuring the cutting paths are as straight as possible while also maximizing area utilization. This reduces cutting complexity and time, and achieves a balance between high mask utilization and low cutting loss.

[0088] Although the embodiments of the present disclosure have been described above using the application scenario of chip layout on a mask as an example, it should be understood that the solutions of the embodiments of the present disclosure can also be applied to other application scenarios that require layout. For example, in the semiconductor industry, it is used to lay out components within a chip. Another example is in the clothing industry, where it is used to lay out patterns on fabric for making clothes. Yet another example is in manufacturing, where it is used to lay out parts to be manufactured on steel. The scope of the present disclosure is not limited in this respect.

[0089] Example Method

[0090] Figure 14 A flowchart of a method 1400 for chip layout according to some embodiments of the present disclosure is shown. In some embodiments, method 1400 can be performed as follows: Figure 1 The method is performed at the illustrated electronic device 120. It should be understood that method 1400 may also include additional boxes not shown and / or one (or some) of the boxes shown may be omitted, and the scope of this disclosure is not limited in this respect.

[0091] At box 1402, multiple elements are acquired, each representing a chip to be placed within the target area. At box 1404, the multiple elements are sequentially placed within a plurality of adjacent sub-regions along a first direction within the target area by performing the following layout operations: selecting the target element from the unplaced elements among the multiple elements based on the size of the elements already placed in the target area; and determining the placement position of the target element based on the position of the elements already placed in the current sub-region and the cutting edges of the elements already placed in the target area if the current sub-region to be filled is not the first sub-region in the target area.

[0092] In some embodiments, method 1400 further includes: if an element has been placed in the current sub-region, performing the following operations: determining a first direction reference dimension based on the dimension of at least one element in the current sub-region in a first direction; and selecting a target element from the unplaced elements based on the first direction reference dimension.

[0093] In some embodiments, determining a first direction reference dimension based on the dimension of at least one element in the current sub-region in a first direction includes: if there is only one element in the current sub-region, determining the dimension of that element in the first direction as the first direction reference dimension; or if there are multiple elements in the current sub-region, determining the average of the dimensions of the multiple elements in the first direction as the first direction reference dimension.

[0094] In some embodiments, the selected target element is the element among the unplaced elements whose absolute difference between its dimension in the first direction and the reference dimension in the first direction is the smallest.

[0095] In some embodiments, method 1400 further includes: if no element has been placed in the current sub-region, performing the following operations: determining a second direction reference dimension based on the dimension of at least one element in at least one sub-region that has been filled before the current sub-region in a second direction, wherein the second direction is different from the first direction; and selecting a target element from the unplaced elements based on the second direction reference dimension.

[0096] In some embodiments, determining a second direction reference dimension based on the dimension of at least one element in at least one sub-region preceding the current sub-region in the second direction includes: if there is only one sub-region preceding the current sub-region, determining the dimension of an element at a predetermined position in that sub-region in the second direction as the second direction reference dimension; or if there are multiple sub-regions preceding the current sub-region, determining the average of the dimensions of the elements at predetermined positions in the multiple sub-regions in the second direction as the second direction reference dimension.

[0097] In some embodiments, the selected target element is the element among the unplaced elements whose absolute difference between its dimension in the second direction and the reference dimension in the second direction is the smallest.

[0098] In some embodiments, method 1400 further includes: if no element has been placed in the current sub-region, determining a position in the current sub-region as the placement position of the target element, the position being adjacent to a region cutting channel between the current sub-region and the previous sub-region in a first direction and adjacent to the boundary of the target region in a second direction, wherein the region cutting channel is determined based on the maximum size of the element already placed in the previous sub-region in the first direction; or if an element has been placed in the current sub-region, determining the placement position of the target element based on the boundary of the previously placed element and the cutting channel between the elements already placed in the sub-regions filled before the current sub-region.

[0099] In some embodiments, determining the placement position of a target element based on the boundary of the previously placed element and the cutting paths between placed elements in the sub-regions filled before the current sub-region includes: determining, from the cutting paths between placed elements in the sub-regions filled before the current sub-region, the cutting path closest in a second direction to the reference boundary of the previously placed element adjacent to the portion to be filled in the current sub-region as a reference cutting path; determining a candidate placement position of the target element based on the relative position between the reference boundary and the reference cutting path; and determining the candidate placement position as the placement position of the target element if it is determined that placing the target element at the candidate placement position will not exceed the target region; or if it is determined that placing the target element at the candidate placement position will exceed the target region, reassigning the target element to the unplaced elements to determine the placement position of the target element in the sub-region following the current sub-region.

[0100] In some embodiments, determining a candidate placement position of a target element based on the relative position between a reference boundary and a reference cutting channel includes: if the absolute value of the distance between the reference boundary and the reference cutting channel is greater than or equal to a threshold, then a first position in the current sub-region is determined as a candidate placement position, the first position being adjacent to the region cutting channel in a first direction and adjacent to the reference boundary in a second direction; or if the absolute value of the distance between the reference boundary and the reference cutting channel is less than a threshold and the extension line of the reference cutting channel does not pass through the previously placed element, then a second position in the current sub-region is determined as a candidate placement position, the second position being adjacent to the region cutting channel in a first direction and adjacent to the extension line of the reference cutting channel in a second direction; or if the absolute value of the distance between the reference boundary and the reference cutting channel is less than a threshold and the extension line of the reference cutting channel passes through the previously placed element, then a first position in the current sub-region is determined as a candidate placement position.

[0101] In some embodiments, the layout operation further includes: if the absolute value of the distance between the reference boundary and the reference cut line is less than a threshold and the extension line of the reference cut line passes through the previously placed element, then performing the following operations: for a sub-region that was filled before the current sub-region, determining whether moving one or more elements in the sub-region after the reference cut line in the second direction by an absolute value of the distance would exceed the target region; and if it is determined that they would exceed the target region, not moving one or more elements; or if it is determined that they would not exceed the target region, moving one or more elements.

[0102] In some embodiments, the layout operation further includes: if no element has been placed in the target area, placing the element that meets the predetermined conditions among the multiple elements into a predetermined position in the target area; or if an element has been placed in the target area and the current sub-area is the first sub-area in the target area, determining the placement position of the target element based on the position of the element already placed in the current sub-area.

[0103] In some embodiments, determining the placement position of a target element based on the positions of elements already placed in the current sub-region includes: determining a position in the current sub-region as a candidate placement position for the target element, the position being adjacent to the boundary of the target region in a first direction and adjacent to the previous placed element in a second direction different from the first direction; and if it is determined that placing the target element at the candidate placement position will not exceed the target region, then determining the candidate placement position as the placement position of the target element; or if it is determined that placing the target element at the candidate placement position will exceed the target region, then reassigning the target element to the unplaced elements to determine the placement position of the target element in a sub-region following the current sub-region.

[0104] In some embodiments, the predetermined condition includes maximum area.

[0105] In some embodiments, method 1400 further includes: determining a size constraint for a target region based on the maximum exposure size of the mask for the plurality of chips and the total area of ​​the plurality of elements.

[0106] In some embodiments, determining a size limit for a target region based on the maximum exposure size of a mask for multiple chips and the total area of ​​multiple elements includes: determining a ratio of the maximum exposure size in a first direction to the maximum exposure size in a second direction that is different from the first direction; and determining a size limit for the target region based on the determined ratio and the total area of ​​multiple elements.

[0107] In some embodiments, the size limit for the target region is determined based on the following formula:

[0108]

[0109] Where TS1 represents the size of the target area in the first direction, TS2 represents the size of the target area in the second direction, MS1 represents the maximum exposure size in the first direction, and MS2 represents the maximum exposure size in the second direction. It represents the total area of ​​multiple elements.

[0110] In some embodiments, the size limit for the target region is determined based on the following formula:

[0111]

[0112] Among them TS1 -2 TS2 represents the position of the boundary between the penultimate and last sub-regions in a first direction, TS2 represents the size of the target region in a second direction different from the first direction, and MS2 represents the maximum exposure size in the second direction. It represents the total area of ​​multiple elements.

[0113] In some embodiments, obtaining multiple elements includes: determining the shape and size of multiple elements based on the shape, size, and desired spacing of multiple chips.

[0114] Example device

[0115] Embodiments of this disclosure also provide corresponding apparatus for implementing the above methods or processes. Figure 15 A block diagram is shown of an electronic device 1500 in which one or more embodiments of the present disclosure may be implemented. The electronic device 1500 may, for example, be used to implement... Figure 1 The electronic device 120 shown. It should be understood that, Figure 15 The electronic device 1500 shown is merely exemplary and should not be construed as limiting the functionality and scope of the embodiments described herein.

[0116] like Figure 15 As shown, electronic device 1500 is in the form of a general-purpose electronic device. Components of electronic device 1500 may include, but are not limited to, one or more processors or processing units 1510, memory 1520, storage device 1530, one or more communication units 1540, one or more input devices 1550, and one or more output devices 1560. Processing unit 1510 may be a physical or virtual processor and is capable of performing various processes according to programs stored in memory 1520. In a multiprocessor system, multiple processing units execute computer-executable instructions in parallel to improve the parallel processing capability of electronic device 1500.

[0117] Electronic device 1500 typically includes multiple computer storage media. Such media can be any available media accessible to electronic device 1500, including but not limited to volatile and non-volatile media, removable and non-removable media. Memory 1520 can be volatile memory (e.g., registers, cache, random access memory (RAM)), non-volatile memory (e.g., read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory), or some combination thereof. Storage device 1530 can be removable or non-removable media and can include machine-readable media, such as flash drives, disks, or any other media that can be used to store information and / or data (e.g., training data for training) and can be accessed within electronic device 1500.

[0118] Electronic device 1500 may further include additional removable / non-removable, volatile / non-volatile storage media. Although not explicitly stated... Figure 15 As shown, disk drives for reading from or writing to removable, non-volatile disks (e.g., "floppy disks") and optical disk drives for reading from or writing to removable, non-volatile optical disks can be provided. In these cases, each drive can be connected to a bus (not shown) via one or more data media interfaces. Memory 1520 may include computer program product 1525 having one or more program modules configured to perform various methods or actions of various embodiments of this disclosure.

[0119] The communication unit 1540 enables communication with other electronic devices via a communication medium. Additionally, the functionality of the components of the electronic device 1500 can be implemented using a single computing cluster or multiple computing machines capable of communicating via communication connections. Therefore, the electronic device 1500 can operate in a networked environment using logical connections to one or more other servers, network personal computers (PCs), or another network node.

[0120] Input device 1550 can be one or more input devices, such as a mouse, keyboard, trackball, etc. Output device 1560 can be one or more output devices, such as a monitor, speaker, printer, etc. Electronic device 1500 can also communicate with one or more external devices (not shown) via communication unit 1540 as needed. These external devices include storage devices, display devices, etc., and can communicate with one or more devices that enable user interaction with electronic device 1500, or with any device that enables electronic device 1500 to communicate with one or more other electronic devices (e.g., network card, modem, etc.). Such communication can be performed via input / output (I / O) interface (not shown).

[0121] According to an exemplary implementation of this disclosure, a computer-readable storage medium is provided that stores one or more computer instructions, wherein one or more computer instructions are executed by a processor to implement the methods described above.

[0122] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products implemented according to this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0123] These computer-readable program instructions can be provided to a processing unit of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processing unit of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner. Thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0124] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions that execute on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0125] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction, which contains one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0126] Various implementations of this disclosure have been described above. The foregoing description is exemplary and not exhaustive, nor is it limited to the disclosed implementations. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described implementations. The terminology used herein is chosen to best explain the principles, practical applications, or improvements to technology in the market, or to enable others skilled in the art to understand the implementations disclosed herein.

Claims

1. A method for chip layout, characterized in that, The method includes: Retrieve multiple elements, each representing a chip to be placed within the target area; and The following layout operations are performed to place the multiple elements sequentially into multiple adjacent sub-regions along the first direction within the target area: Based on the dimensions of the elements already placed in the target area, select the target element from the unplaced elements among the plurality of elements; and If the current sub-region to be filled is not the first sub-region in the target region, the placement position of the target element is determined based on the position of the element already placed in the current sub-region and the cutting edge of the element already placed in the target region. This includes: if no element has been placed in the current sub-region, the following position in the current sub-region is determined as the placement position of the target element: the position is adjacent to the area cutting edge between the current sub-region and the previous sub-region in the first direction and adjacent to the boundary of the target region in the second direction, wherein the area cutting edge is determined based on the maximum size of the element already placed in the previous sub-region in the first direction.

2. The method for chip layout according to claim 1, characterized in that, Selecting a target element from the unplaced elements among the plurality of elements based on the size of the elements already placed in the target area includes: If an element is already placed in the current sub-region, perform the following operation: A first-direction reference dimension is determined based on the dimension of at least one element in the current sub-region in the first direction; and Based on the first directional reference dimension, the target element is selected from the unplaced elements.

3. The method for chip layout according to claim 2, characterized in that, Determining the first direction reference dimension based on the dimension of at least one element in the current sub-region in the first direction includes: If only one element exists in the current sub-region, then the dimension of that element in the first direction is determined as the reference dimension in the first direction; or If there are multiple elements in the current sub-region, the average value of the dimensions of the multiple elements in the first direction is determined as the reference dimension in the first direction.

4. The method for chip layout according to claim 2, characterized in that, The selected target element is the element among the unplaced elements whose absolute difference in size in the first direction is the smallest compared to the reference size in the first direction.

5. The method for chip layout according to claim 1, characterized in that, Selecting a target element from the unplaced elements among the plurality of elements based on the size of the elements already placed in the target area includes: If no element has been placed in the current sub-region, perform the following operation: A second direction reference dimension is determined based on the dimension of at least one element in at least one sub-region that was filled prior to the current sub-region in the second direction, wherein the second direction is different from the first direction; and Based on the second direction reference dimension, the target element is selected from the unplaced elements.

6. The method for chip layout according to claim 5, characterized in that, Determining the second direction reference dimension based on the dimension of at least one element in at least one sub-region preceding the current sub-region in the second direction includes: If only one subregion exists before the current subregion, then the dimension of the element at the predetermined position in that subregion in the second direction is determined as the reference dimension in the second direction; or If multiple subregions exist before the current subregion, the average value of the dimensions of each element at a predetermined position in the multiple subregions in the second direction is determined as the reference dimension in the second direction.

7. The method for chip layout according to claim 5, characterized in that, The selected target element is the element among the unplaced elements whose absolute difference in size in the second direction is the smallest compared to the reference size in the second direction.

8. The method for chip layout according to claim 1, characterized in that, Determining the placement position of the target element based on the positions of the elements already placed in the current sub-region and the cutting edges of the elements already placed in the target region also includes: If an element has already been placed in the current sub-region, the placement position of the target element is determined based on the boundary of the previously placed element and the cutting edge between the elements placed in the sub-regions that were filled before the current sub-region.

9. The method for chip layout according to claim 8, characterized in that, Determining the placement position of the target element based on the boundary of the previously placed element and the cutting edge between the placed elements in the sub-regions filled before the current sub-region includes: From the cutting paths between placed elements in the sub-regions that were filled before the current sub-region, determine the cutting path in the second direction that is closest to the reference boundary of the previous placed element that is adjacent to the portion to be filled in the current sub-region as the reference cutting path. Based on the relative position between the reference boundary and the reference cutting path, the candidate placement position of the target element is determined; and If it is determined that placing the target element in the candidate placement position will not exceed the target area, then the candidate placement position is determined as the placement position of the target element; or if it is determined that placing the target element in the candidate placement position will exceed the target area, then the target element is returned to the unplaced elements, so as to determine the placement position of the target element in the sub-region after the current sub-region.

10. The method for chip layout according to claim 9, characterized in that, Determining the candidate placement position of the target element based on the relative position between the reference boundary and the reference cutting channel includes: If the absolute value of the distance between the reference boundary and the reference cutting channel is greater than or equal to a threshold, then the following first position in the current sub-region is determined as the candidate placement position, wherein the first position is adjacent to the region cutting channel in the first direction and adjacent to the reference boundary in the second direction; or If the absolute value of the distance between the reference boundary and the reference cut line is less than the threshold and the extension line of the reference cut line does not pass through the previously placed element, then the following second position in the current sub-region is determined as the candidate placement position, which is adjacent to the region cut line in the first direction and adjacent to the extension line of the reference cut line in the second direction; or If the absolute value of the distance between the reference boundary and the reference cutting path is less than the threshold and the extension line of the reference cutting path passes through the previously placed element, then the first position in the current sub-region is determined as the candidate placement position.

11. The method for chip layout according to claim 10, characterized in that, The typesetting operation also includes: If the absolute value of the distance between the reference boundary and the reference cut line is less than the threshold and the extension line of the reference cut line passes through the previously placed element, then perform the following operation: For a sub-region filled before the current sub-region, determine whether moving one or more elements in that sub-region after the reference cut line by the absolute value of the distance in the second direction would exceed the target region; and If it is determined that the movement would exceed the target area, then the movement of the one or more elements is not performed; or If it is determined that the movement will not exceed the target area, then the movement is performed on the one or more elements.

12. The method for chip layout according to claim 1, characterized in that, The typesetting operation also includes: If no element is placed in the target area, then the element that meets the predetermined conditions among the plurality of elements is placed in the predetermined position in the target area; or If an element has already been placed in the target area and the current sub-region is the first sub-region in the target area, then the placement position of the target element is determined based on the position of the element already placed in the current sub-region.

13. The method for chip layout according to claim 12, characterized in that, Determining the placement position of the target element based on the positions of the elements already placed in the current sub-region includes: The following position within the current sub-region is determined as a candidate placement position for the target element: this position is adjacent to the boundary of the target region in the first direction and adjacent to the previously placed element in the second direction, which is different from the first direction; and If it is determined that placing the target element in the candidate placement position will not exceed the target area, then the candidate placement position is determined as the placement position of the target element; or If it is determined that placing the target element in the candidate placement position would exceed the target area, the target element is reassigned to the unplaced elements so that the placement position of the target element can be determined in the sub-region following the current sub-region.

14. The method for chip layout according to claim 12, characterized in that, The predetermined conditions include the maximum area.

15. The method for chip layout according to claim 1, characterized in that, The method further includes: Based on the maximum exposure size of the mask and the total area of ​​the plurality of elements, a size limit for the target region is determined.

16. The method for chip layout according to claim 15, characterized in that, Determining the size constraints for the target region based on the maximum exposure size of the mask and the total area of ​​the plurality of elements includes: Determine the ratio of the maximum exposure size in the first direction to the maximum exposure size in the second direction, which is different from the first direction; and Based on the determined proportions and the total area of ​​the plurality of elements, the size limit for the target region is determined.

17. The method for chip layout according to claim 16, characterized in that, The size constraint for the target region is determined based on the following formula: Where TS1 represents the size of the target area in the first direction, TS2 represents the size of the target area in the second direction, MS1 represents the size of the maximum exposure size in the first direction, and MS2 represents the size of the maximum exposure size in the second direction, and... This represents the total area of ​​the multiple elements.

18. The method for chip layout according to claim 15, characterized in that, The size constraint for the target region is determined based on the following formula: Among them TS1 -2 TS2 represents the position of the boundary between the penultimate and last sub-regions in the first direction, MS2 represents the size of the target region in the second direction (different from the first direction), and MS2 represents the size of the maximum exposure size in the second direction. This represents the total area of ​​the multiple elements.

19. The method for chip layout according to any one of claims 1 to 18, characterized in that, Obtaining the multiple elements includes: The shape and size of the multiple elements are determined based on the shape, size, and desired spacing of the multiple chips to be laid out.

20. An electronic device, characterized in that, include: processor; as well as A memory coupled to the processor, the memory having instructions stored therein, which, when executed by the processor, cause the electronic device to perform the method for chip layout according to any one of claims 1 to 19.

21. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the computer program implements the method for chip layout according to any one of claims 1 to 19.

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