A clock tree synthesis method, computer device, readable storage medium and program product

Abstract

The application relates to a clock tree synthesis method, computer equipment, a readable storage medium and a program product in the field of chip design. The steps of the clock tree synthesis method include clustering, delay reduction, power consumption reduction and flattening. The method adopts a new detailed layout mode in the clock tree synthesis process, adjusts the detailed layout between the power consumption reduction stage and the flattening stage, makes the timing device move caused by the legalization of the placement position in the detailed layout more scientific, reduces the movement of the timing device caused by the legalization of the placement position in the detailed layout, and makes the clock tree synthesis result closer to the theoretical expectation. The search range during the calculation of the candidate position is limited by the boundary frame, the controllability of the device movement range in the detailed layout is realized through the position keeping parameter, the position change of the timing device is smaller, the result quality of the clock tree synthesis is more stable, and especially under the constraint of the lower maximum placement density, the method can reduce the deterioration of the result quality of the clock tree synthesis caused by the detailed layout.

Description

Technical Field

[0001] This invention relates to the field of chip design, and in particular to a clock tree synthesis method, computer equipment, readable storage medium, and program product. Background Technology

[0002] Clock tree synthesis is a crucial step in the design process of very large-scale integrated circuit (VLSI) chips. The purpose of clock tree synthesis is to generate a tree structure from the clock source signal to each register, minimizing the delay of the clock signal reaching the registers through this tree structure and ensuring that the arrival time deviation between different registers is not significant, thus guaranteeing that the timing devices on the chip can function properly.

[0003] During clock tree synthesis, numerous buffers or inverters are added to propagate the clock signal in order to build a complete clock tree. These buffers need to be placed in their proper positions in a timely manner. Other timing components, such as integrated clock gating devices, also require resizing and repositioning during clock tree synthesis. All of these processes require detailed placement. This step validates the positions of the placed buffers, resolving issues such as overlap and congestion. The coordinates calculated at this point are the final actual placement coordinates. However, the detailed placement in existing clock tree synthesis methods introduces many unnecessary component movements. These unnecessary movements can cause the final placement of buffers to deviate significantly from the appropriate positions calculated by the clock tree synthesis itself, ultimately leading to a deterioration in result quality. Furthermore, since the results of detailed placement are inherently affected by multi-threaded uncertainties, this also increases the volatility of the result quality, impacting subsequent processes. Summary of the Invention

[0004] To address the technical problems of poor performance and low stability of existing clock tree synthesis methods, this invention provides a clock tree synthesis method, a computer device, a readable storage medium, and a program product. The clock tree synthesis method includes the following steps: providing a laid-out chip design layout file, which includes physical and timing information of registers; performing clock tree synthesis on the chip design layout file, the clock tree synthesis steps sequentially including clustering, latency reduction, power reduction, and flattening; in the clustering stage, registers are grouped according to their physical and timing information to construct an initial clock tree structure and initially insert buffers; in the latency reduction stage, the size and position of buffers are adjusted, and new buffers are inserted; in the power reduction stage, the size of buffers is adjusted and clock gating is inserted; in the flattening stage, balancing cells are inserted and their placement is validated; a first detailed layout is performed after the power reduction stage and before the flattening stage; after completing all the steps of clock tree synthesis, a second detailed layout is performed to construct the clock network of the completed chip design layout.

[0005] Preferably, the timing requirements of the chip design are provided, and the coordinates of the reference point are calculated in conjunction with the chip design layout file; the coordinates of the candidate points for placing the buffer are calculated based on the coordinates of the reference points, and a bounding box is set at the coordinates of the reference points when calculating the candidate points, and the coordinates of the candidate points are searched within the bounding box.

[0006] Preferably, when no suitable candidate position can be found within the bounding box, a reference point is set as a candidate point, and the buffer is placed at the coordinates of the reference point.

[0007] Preferably, the bounding box is set as a rectangle centered at the reference point with a side length of 30 times the height of the standard cell.

[0008] Preferably, a position holding parameter is provided, which controls the priority placement of buffers during the detailed layout process.

[0009] Preferably, when setting position optimization parameters and calculating candidate positions, if the reference point has a bounding box, the coordinates of the candidate point are found within the bounding box; if the reference point does not have a bounding box and the position optimization range parameter is greater than zero, a bounding box is set at the reference point according to the position optimization parameters and the coordinates of the candidate point are found within the bounding box.

[0010] Preferably, when the location optimization range parameter is less than zero, candidate points are searched according to the geometric grid method, the electric drive method, or the congestion sensing method. Once a candidate point is found, its coordinates are output. If no candidate point is found, a reference point is set as a candidate point.

[0011] To solve the above-mentioned technical problems, the present invention also provides a computer device, including a storage device, a processor, and a computer program stored on the storage device, wherein the processor executes the computer program to implement the steps of the clock tree synthesis method described above.

[0012] To address the aforementioned technical problems, the present invention also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the aforementioned clock tree synthesis method.

[0013] To address the aforementioned technical problems, the present invention also provides a computer program product, including a computer program / instructions, which, when executed by a processor, implement the steps of the aforementioned clock tree synthesis method.

[0014] Compared with the prior art, the clock tree synthesis method, computer device, readable storage medium, and program product provided by the present invention have the following advantages:

[0015] 1. This invention provides a clock tree synthesis method. The clock tree synthesis steps include clustering, latency reduction, power reduction, and flattening. A first detailed layout is performed after the power reduction stage, and a second detailed layout is performed after all clock tree synthesis steps are completed. In this method, the first detailed layout is adjusted to be performed after the power reduction stage and before the flattening stage. At this time, the buffers in the chip design layout have completed the power reduction stage, and the buffers are closer to their final size. This reduces unnecessary movement of timing devices in the chip design layout due to the detailed layout, avoiding the need for detailed layout in earlier stages, such as immediately after clustering, where buffers are relatively large and detailed layout would cause many unnecessary timing device movements. This method, by adopting a new detailed layout approach, reduces the impact of placement legitimization on timing device movement during detailed layout, making the clock tree synthesis result closer to theoretical expectations. Furthermore, because the positional changes of timing devices are smaller, the quality of the clock tree synthesis result is more stable.

[0016] 2. In this invention, when calculating candidate positions for buffer placement, a bounding box is set at the coordinates of a reference point. Candidate point coordinates are searched within the bounding box, which is a rectangle centered at the reference point with a side length 30 times the height of a standard cell. If no suitable candidate position is found within the bounding box, the reference point is set as a candidate point, and the buffer is placed at the reference point coordinates. This method utilizes the bounding box to limit the search range when calculating candidate positions, improving the controllability of the timing device movement range in detailed layout, and further ensuring that the final placement position of the timing devices is close to the target position calculated during clock tree synthesis.

[0017] 3. When calculating candidate positions, this invention searches for candidate point coordinates within a bounding box if the reference point has one. If the reference point does not have a bounding box, and the position optimization range parameter is greater than zero, a bounding box is set at the reference point, and candidate point coordinates are searched within the bounding box. When the position optimization range parameter is less than zero, candidate points are searched using the geometric grid method, electric drive method, or congestion sensing method. If a candidate point is found, its coordinates are output; otherwise, the reference point is set as a candidate point. By controlling the selection of candidate point positions through the position optimization parameter, the position of the buffer changes less, and the quality of the clock tree synthesis results becomes more stable.

[0018] 4. The present invention also provides a computer device, including a storage device, a processor, and a computer program stored on the storage device. The processor executes the computer program to implement the steps of the clock tree synthesis method described above, and has the same beneficial effects as the clock tree synthesis method described above, which will not be elaborated here.

[0019] 5. The present invention also provides a computer-readable storage medium having a computer program stored thereon, which, when executed, implements the above-described clock tree synthesis method and has the same beneficial effects as the above-described clock tree synthesis method, and will not be described in detail here.

[0020] 6. The present invention also provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps of the clock tree synthesis method described above, and has the same beneficial effects as the clock tree synthesis method described above, which will not be elaborated here. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a flowchart illustrating steps S1 to S4 in a clock tree synthesis method provided in an embodiment of the present invention.

[0023] Figure 2 This is a schematic diagram of the process for calculating candidate positions in a clock tree synthesis method provided in an embodiment of the present invention.

[0024] Figure 3 This is a schematic diagram of a computer device structure provided in the second embodiment of the present invention.

[0025] Figure 4 This is a schematic diagram of a computer-readable storage medium structure provided in the third embodiment of the present invention.

[0026] Figure 5 This is a schematic diagram of a computer program product structure provided in the fourth embodiment of the present invention.

[0027] Explanation of reference numerals in the attached diagram:

[0028] 10. Computer equipment; 20. Computer-readable storage media; 30. Computer program products. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0030] In the embodiments provided by this invention, it should be understood that "B corresponding to A" means that B is associated with A, and B can be determined based on A. However, it should also be understood that determining B based on A does not mean determining B solely based on A; B can also be determined based on A and / or other information.

[0031] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of the invention. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Those skilled in the art should also recognize that the embodiments described in the specification are optional embodiments, and the actions and modules involved are not necessarily essential to the invention.

[0032] In various embodiments of the present invention, it should be understood that the sequence number of each process does not necessarily imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0033] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It is particularly important to note that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0034] Clock tree synthesis is a crucial step in the design process of very large-scale integrated circuit (VLSI) chips. The purpose of clock tree synthesis is to generate a tree structure from the clock source signal to each register, minimizing the delay of the clock signal reaching the registers through this tree structure and ensuring that the arrival time deviation between different registers is not significant, thus guaranteeing that the timing devices on the chip can function properly.

[0035] During clock tree synthesis, numerous buffers or inverters are added to propagate the clock signal in order to build a complete clock tree. These buffers need to be placed in their proper positions in a timely manner. Other timing components, such as integrated clock gating devices, also require resizing and repositioning during clock tree synthesis. All of these processes require detailed placement. This step validates the positions of the placed buffers, resolving issues such as overlap and congestion. The coordinates calculated at this point are the final actual placement coordinates. However, the detailed placement in existing clock tree synthesis methods introduces many unnecessary component movements. These unnecessary movements can cause the final placement of buffers to deviate significantly from the appropriate positions calculated by the clock tree synthesis itself, ultimately leading to a deterioration in result quality. Furthermore, since the results of detailed placement are inherently affected by multi-threaded uncertainties, this also increases the volatility of the result quality, impacting subsequent processes.

[0036] To address the technical issues of poor performance and low stability of existing clock tree synthesis methods, please refer to [link / reference needed]. Figure 1 The first embodiment of the present invention provides a clock tree synthesis method, which includes the following steps:

[0037] S1: Provides the chip design layout file after layout, which includes the physical and timing information of registers. Clustering is performed on the chip design layout file. In the clustering stage, registers are grouped according to their physical and timing information, an initial clock tree structure is constructed, and buffers are initially inserted.

[0038] S2: Delay reduction phase, adjust the size and position of the buffer, and continue to insert new buffers;

[0039] S3: Power reduction stage, adjust the size of the buffer and insert clock gating, and perform the first detailed layout after completion;

[0040] S4: Flattening stage, inserting balancing cells and performing legal placement. After completion, a second detailed layout is performed to build the clock network of the chip design layout.

[0041] It's important to note that clock tree synthesis occupies a central position in the physical implementation phase of the chip design flow, connecting placement and routing, and directly impacting timing convergence, power consumption, and signal integrity. Clock tree synthesis utilizes the physical coordinates of registers, initial timing constraints, and clock domain definitions and drive strengths obtained during the placement phase to provide a structured clock network and precise clock propagation delays for routing. In clock tree synthesis, sequential devices are the core components for building a stable clock network. These devices include buffers, inverters, gate units, delay units, and frequency dividers, where buffer size and dimensions refer to drive strength and physical footprint, respectively. Chip placement typically involves two phases: global placement and detailed placement. In the detailed placement phase, design tools optimize and refine the initial placement results obtained from the global placement. Detailed placement further optimizes circuit performance based on the global placement, including reducing signal transmission delay, lowering circuit power consumption, and optimizing routing lengths. This stage typically considers more refined constraints and limitations of chip physical implementation to achieve the final placement design goals. Through the two-stage design process of global placement and detailed placement, the design tool can effectively optimize chip design performance and ensure that the final placement meets design requirements and constraints. Step S1 provides the chip design layout after all placements are completed. Since new timing devices are inserted during clock tree synthesis and existing timing devices may also change, a detailed placement operation is performed again during clock tree synthesis for local legalization and lithography design rule repair.

[0042] This invention provides a clock tree synthesis method. The clock tree synthesis steps include clustering, latency reduction, power reduction, and flattening. A first detailed placement is performed after the power reduction stage, and a second detailed placement is performed after all clock tree synthesis steps are completed. In this method, the first detailed placement is adjusted to be performed after the power reduction stage and before the flattening stage. At this time, the buffers in the chip design layout have already completed the power reduction stage, and the buffers are closer to their final size, which can reduce unnecessary movement of buffers and other timing devices in the chip design layout due to detailed placement. This avoids performing detailed placement in earlier stages, such as immediately after clustering, when the buffers are relatively large, and detailed placement would cause many unnecessary timing device movements. This method, by adopting a new detailed placement method, reduces the movement of timing devices due to placement legitimization in the detailed placement, making the clock tree synthesis result closer to the theoretical expectation. At the same time, because the positional changes of the timing devices are smaller, the quality of the clock tree synthesis result is also more stable.

[0043] It's important to note that in the clock tree synthesis process, the calculation of buffer candidate positions spans multiple stages, and the strategy dynamically adjusts the calculated candidate positions according to the stage objectives. Calculating candidate positions refers to determining the coordinates of valid candidate points based on the input reference point coordinates. In clock tree synthesis, the reference point coordinates are often target values ​​calculated based on information such as the coordinates of other buffers. The calculated candidate points are theoretically possible placement positions near the reference point and aligned with other devices on the chip, and these positions may overlap with other devices. In this case, a detailed layout is required to validate the positions of already placed buffers, resolving issues such as overlap and congestion. The coordinates calculated at this stage are the final, actual placement coordinates.

[0044] Understandably, the timing requirements of the chip design are provided, and reference point coordinates are calculated using the chip design layout file. Based on these reference point coordinates, candidate point coordinates for buffer placement are calculated. A bounding box is set at the reference point coordinates during candidate position calculation, and candidate point coordinates are searched within the bounding box. If no suitable candidate position is found within the bounding box, the reference point is set as a candidate point, and the buffer is placed at the reference point coordinates. This method utilizes the bounding box to limit the search range when calculating candidate positions, improving the controllability of the timing device movement range in detailed placement, and further ensuring that the final placement of the timing devices is close to the target position calculated during clock tree synthesis.

[0045] Optionally, the bounding box is set to a rectangle centered at the reference point with a side length of 30 times the height of a standard cell.

[0046] As one implementation, the chip design layout file provided in step S1 includes location retention parameters. During detailed placement, these parameters control the priority placement of timing devices. Specifically, the location retention parameter is set to HxPreserveClockTreeLocation=true. In the chip physical design flow, the location retention parameter is a key control item to ensure the quality of the clock tree. It solves the problem of timing device displacement during the placement legalization process through a priority redirection mechanism, sacrificing the placement freedom of ordinary cells in exchange for the stability of the clock tree structure.

[0047] Please see Figure 2When calculating candidate positions by setting location optimization parameters, if the reference point has a bounding box, the coordinates of the candidate point are searched within the bounding box. If the reference point does not have a bounding box, and the location optimization range parameter is greater than zero, a bounding box is set for the reference point according to the location optimization parameters, and the coordinates of the candidate point are searched within the bounding box. When the location optimization range parameter is less than zero, candidate points are searched using the geometric grid method, the electric drive method, or the congestion sensing method. If a candidate point is found, its coordinates are output; if no candidate point is found, the reference point is set as the candidate point. This scheme controls the selection of candidate point positions through location optimization parameters, resulting in smaller changes in the buffer position and more stable clock tree synthesis results.

[0048] This embodiment compares the clock tree synthesis results provided by the present invention with those of existing clock tree synthesis methods (hereinafter referred to as the two methods) through several numerical examples. The main metrics of interest are: Worst Negative Slack (WNS), Total Negative Slack (TNS), skew, maximum delay, minimum delay, number of buffers, and buffer area. The first five metrics indicate the quality of the clock tree; the worst negative slack and total negative slack are negative values, and larger values ​​indicate better clock tree quality. The skew, maximum delay, and minimum delay are positive values, and smaller values ​​indicate better clock tree quality. The last two metrics indicate the power consumption of the clock tree; more buffers and a larger buffer area indicate higher power consumption.

[0049] Table 1. Results quality of the old and new methods when the maximum placement density is 70.

[0050]

[0051] Table 2 shows the quality of results from the old and new methods when the maximum placement density is 90%.

[0052]

[0053] The results in Tables 1 and 2 show that under lower maximum placement density constraints, the detailed placement process performs more movement operations on devices to meet the constraints. This results in a significant discrepancy between the actual positions of timing devices and the expected positions calculated by the original clock tree synthesis, leading to a deterioration in result quality. The new method, however, can significantly optimize the results. Under the higher maximum placement density constraints shown in Table 2, the result quality of the old and new methods is essentially equivalent.

[0054] The following compares the differences in the quality of results obtained by the new and old methods under different maximum placement density constraints. Specifically, we directly subtract the corresponding positions in Table 1 and Table 2 to form Table 3. In Table 3, we mainly focus on the absolute value of the change of each indicator, without caring about its positive or negative sign.

[0055] Table 3. Differences in the quality of results between the old and new methods when the maximum placement density is 70 and 90.

[0056]

[0057] Table 3 shows that under different maximum placement density constraints, the results of the new method exhibit significantly lower fluctuations than those of the old method. It also demonstrates better stability in complex environments.

[0058] This method employs a novel detailed placement approach in the clock tree synthesis process, positioning it between the power reduction and flattening stages. This allows for a more scientific timing of detailed placement, reducing the movement of timing devices caused by placement validation during detailed placement, and resulting in clock tree synthesis results that more closely approximate theoretical expectations. Furthermore, detailed placement can prioritize different types of devices, meeting diverse needs. Bounding boxes limit the search range when calculating candidate locations, and position-preserving parameters ensure controllability of device movement during detailed placement. Because the positional changes of timing devices are smaller, the quality of clock tree synthesis results is more stable, especially under lower maximum placement density constraints. This method reduces the degradation of clock tree synthesis results caused by detailed placement, and the quality fluctuations are smaller under different maximum placement density constraints.

[0059] To resolve the above technical issues, please refer to [link / reference]. Figure 3 The second embodiment of the present invention also provides a computer device 10, including a storage device, a processor, and a computer program stored in the storage device. The processor executes the computer program to implement the steps of the clock tree synthesis method described above, and has the same beneficial effects as the clock tree synthesis method described above, which will not be described in detail here.

[0060] To resolve the above technical issues, please refer to [link / reference]. Figure 4 The third embodiment of the present invention also provides a computer-readable storage medium 20, on which a computer program is stored. When the computer program is executed by a processor, it implements the steps of the clock tree synthesis method described above and has the same beneficial effects as the clock tree synthesis method described above, which will not be described in detail here.

[0061] To resolve the above technical issues, please refer to [link / reference]. Figure 5The fourth embodiment of the present invention also provides a computer program product 30, including a computer program / instruction. When the computer program / instruction is executed by a processor, it implements the steps of the clock tree synthesis method described above and has the same beneficial effects as the clock tree synthesis method described above, which will not be described in detail here.

[0062] The foregoing has provided a detailed description of a clock tree synthesis method, computer device, storage medium, and program product disclosed in the embodiments of the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention. Any modifications, equivalent substitutions, and improvements made within the principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A clock tree synthesis method, characterized in that: Provide the chip design layout file after layout. The chip design layout file includes the physical and timing information of the registers. Perform clock tree synthesis on the chip design layout file. The clock tree synthesis steps include clustering, latency reduction, power reduction and flattening in sequence. In the clustering phase, registers are grouped according to their physical and timing information, an initial clock tree structure is constructed, and buffers are initially inserted. In the delay reduction phase, the size and position of the buffers are adjusted, and new buffers are inserted. In the power reduction phase, the size of the buffer is adjusted and a clock gate is inserted; in the flattening phase, a balancing cell is inserted and its placement is validated; after the power reduction phase and before the flattening phase, the first detailed layout is performed; after completing all the steps of clock tree synthesis, the second detailed layout is performed to build the clock network of the chip design layout.

2. The clock tree synthesis method according to claim 1, characterized in that: Provide the timing requirements for the chip design and calculate the reference point coordinates based on the chip design layout file; calculate the candidate point coordinates for the candidate locations where the buffer can be placed based on the reference point coordinates; set a bounding box at the reference point coordinates when calculating the candidate locations, and search for the candidate point coordinates within the bounding box.

3. The clock tree synthesis method according to claim 2, characterized in that: If no suitable candidate location can be found within the bounding box, set the reference point as the candidate point and place the buffer at the coordinates of the reference point.

4. The clock tree synthesis method according to claim 3, characterized in that: The bounding box is set to a rectangle centered at the reference point with a side length of 30 times the height of a standard cell.

5. The clock tree synthesis method according to claim 1, characterized in that: Provide position holding parameters, which control the priority placement of buffers during detailed layout.

6. The clock tree synthesis method according to claim 3, characterized in that: When setting location optimization parameters and calculating candidate locations, if the reference point has a bounding box, the coordinates of the candidate point are searched within the bounding box; if the reference point does not have a bounding box and the location optimization range parameter is greater than zero, a bounding box is set on the reference point according to the location optimization parameters, and the coordinates of the candidate point are searched within the bounding box.

7. A clock tree synthesis method according to claim 6, characterized in that: When the location optimization range parameter is less than zero, candidate points are searched using the geometric grid method, electric drive method, or congestion sensing method. Once a candidate point is found, its coordinates are output. If no candidate point is found, a reference point is set as a candidate point.

8. A computer device, comprising a storage unit, a processor, and a computer program stored in the storage unit, characterized in that: The processor executes the computer program to implement the steps of a clock tree synthesis method as described in any one of claims 1 to 7.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by the processor, it implements the steps of a clock tree synthesis method as described in any one of claims 1 to 7.

10. A computer program product comprising a computer program / instructions, characterized in that: When the computer program / instruction is executed by the processor, it implements the steps of a clock tree synthesis method as described in any one of claims 1 to 7.

Images