Quantum bit partitioning method and device, circuit adjusting method and device, medium and product

Abstract

The invention discloses a quantum bit partitioning method and device, a circuit adjusting method and device, a medium and a product, and the method comprises the steps: carrying out the layering and partitioning of a physical quantum bit through employing a layering and partitioning method according to the topological structure of the physical quantum bit in a quantum chip; performing quality evaluation on all the quantum bit partitions in each layer to obtain partition evaluation results of all the quantum bit partitions in each layer; and distributing the quantum bit partitions for the quantum lines in the parallel quantum line set according to the partition evaluation result and the complexity of the quantum lines. According to a topological structure of physical quantum bits in a quantum chip, a communication relation of the physical quantum bits is determined, the physical quantum bits are layered and partitioned according to the communication relation, all possible effective partitions are reserved, and quality evaluation is performed on all quantum bit partitions in each layer. And allocating an optimal unoccupied quantum bit partition to the current quantum circuit according to a partition evaluation result and the complexity of the quantum circuit.

Description

Technical Field

[0001] The present invention relates to the field of quantum technology, and in particular to a quantum bit partitioning and circuit adjustment method, device, medium and product. Background Art

[0002] Parallel processing of multiple quantum computing tasks is a novel approach to quantum computing task processing. Compared to mainstream single-quantum computing task processing techniques, this technology can manage and optimize the concurrent execution of multiple quantum computing tasks. First, by managing and scheduling multiple quantum computing tasks, a combination of tasks for combined execution is determined. Then, quantum bit partitioning is performed to allocate the required hardware resources to the quantum circuits corresponding to each task. Finally, a scheduling algorithm is used to determine the execution time of the quantum circuits. This fully utilizes hardware resources and enables the combined execution of multiple quantum circuits, thereby improving the throughput of quantum hardware and enhancing the processing efficiency of multiple quantum computing tasks.

[0003] Currently, qubit partition mapping methods for parallel processing of multiple quantum computing tasks implement qubit partitioning by continuously merging qubit partition nodes with the largest reward function to construct a structure tree. However, each partition node can only participate in one merge, which directly misses a large number of potentially valid partitions, resulting in a single final partitioning result. This fails to provide diverse hardware resource options for quantum circuits of varying complexity, limiting the adaptability of multi-circuit parallel processing. Alternatively, qubit partitions are generated dynamically based on the quantum computing task, rather than pre-dividing them. This process requires even greater time complexity and introduces greedy behavior when generating partitions, making it impossible to achieve a globally optimal partitioning result for multiple quantum computing tasks. Therefore, existing qubit partition mapping methods suffer from insufficient partition diversity and global optimality. Summary of the Invention

[0004] The present invention provides a quantum bit partitioning and circuit adjustment method, device, medium and product, which can solve the problems of insufficient partition diversity and global optimality in the quantum bit partition mapping method of the prior art, and improve the processing efficiency of quantum computing tasks.

[0005] To achieve the above objectives, an embodiment of the present invention provides a quantum bit partitioning method, comprising: Based on the topological structure of the physical qubits in the quantum chip, the physical qubits are hierarchically partitioned using a hierarchical partitioning method; wherein the hierarchical partitioning method is a partitioning strategy that divides the physical qubits in the quantum chip into qubit partitions layer by layer according to a hierarchical progressive logic and the connectivity relationship of the qubits in the topological structure of the physical qubits; Performing quality assessment on all qubit partitions in each layer to obtain partition assessment results for all qubit partitions in each layer; The quantum bit partitions are allocated to the quantum circuits in the parallel quantum circuit set according to the partition evaluation results and the complexity of the quantum circuits.

[0006] As an improvement to the above solution, the physical qubits in the quantum chip are hierarchically partitioned using a hierarchical partitioning method according to the topological structure of the physical qubits, including: Obtaining a topological structure of physical qubits in a quantum chip, and using a hierarchical partitioning method based on the topological structure to treat each physical qubit in the quantum chip as a single qubit partition, and grouping all single qubit partitions into single-bit layers; Starting from the single-bit layer, according to the connectivity relationship of the quantum bits in the topological structure, the corresponding bit layers are constructed layer by layer in the order of increasing number of bits until all physical quantum bits are divided into one quantum bit partition, thereby completing the hierarchical partitioning of the physical quantum bits.

[0007] As an improvement to the above solution, starting from the single-bit layer, according to the connectivity relationship of the qubits in the topological structure, the corresponding bit layers are constructed layer by layer in the order of increasing number of bits until all physical qubits are divided into one qubit partition, thereby completing the hierarchical partitioning of the physical qubits, including: Combining all single-qubit partitions in the single-bit layer in pairs, taking each pair of combinations having the connectivity of the topological structure as a two-qubit partition, and classifying all the two-qubit partitions into a two-bit layer; Combining two-qubit partitions having the same qubit in the two-bit layer to obtain a three-qubit layer; If all physical quantum bits are not divided into one bit partition, the quantum bit partitions of the current bit layer are combined in order of increasing number of bits to obtain the next bit layer, until all physical quantum bits are divided into one bit partition, and the hierarchical partitioning of the physical quantum bits is completed.

[0008] As an improvement to the above solution, the quality assessment of all qubit partitions in each layer is performed to obtain partition assessment results of all qubit partitions in each layer, including: The quality of all quantum bit partitions in each layer is evaluated according to the quality evaluation formula, and the partitions are sorted from large to small according to the quality evaluation results to obtain the partition evaluation results of all quantum bit partitions in each layer.

[0009] As an improvement to the above solution, allocating the quantum bit partitions to the quantum circuits in the parallel quantum circuit set according to the partition evaluation results and the complexity of the quantum circuits includes: Sort the quantum circuits in the parallel quantum circuit set according to the complexity of the quantum circuits; The quantum bit partitions are sequentially allocated to the quantum circuit according to the partition evaluation results and the sorting results.

[0010] As an improvement to the above solution, allocating the quantum bit partitions to the quantum circuit in sequence according to the partition evaluation results and the sorting results includes: According to the partition evaluation result and the sorting result, the optimal quantum bit partition in the bit layer corresponding to the quantum circuit to be currently allocated is selected according to the number of quantum bits required by the quantum circuit to be currently allocated; If the optimal quantum bit partition is already occupied by the previous quantum circuit, then the suboptimal quantum bit partition in the corresponding bit layer is selected; If all qubit partitions in the corresponding bit layer have been occupied by the previous quantum circuit, then reselect the suboptimal qubit partition in the corresponding bit layer for the last allocated quantum circuit, and release the occupied optimal qubit partition; Then, the optimal quantum bit partition is allocated to the quantum circuit to be currently allocated until all quantum circuits in the parallel quantum circuit set are allocated to the quantum bit partition.

[0011] As an improvement to the above solution, before evaluating the partition results and the complexity of the quantum circuit, the method further includes: The quantum computing tasks in the task list are combined and evaluated to obtain a set of parallel quantum circuits for the quantum computing tasks.

[0012] As an improvement to the above solution, the quantum computing tasks in the task list are combined and evaluated to obtain a set of parallel quantum circuits for the quantum computing tasks, including: Taking the quantum computing task that is queued at the top of the task list as the benchmark task, performing a combined evaluation on the other quantum computing tasks in the task list, and sorting them from largest to smallest according to the combined evaluation results; The quantum circuit corresponding to the benchmark task is added to the parallel quantum circuit set. If the number of quantum bits in the parallel quantum circuit set is less than a preset threshold, quantum circuits corresponding to other quantum computing tasks are selected from the sorted task list and added to the parallel quantum circuit set until the number of quantum bits in the parallel quantum circuit set is no less than the preset threshold.

[0013] To achieve the above objectives, an embodiment of the present invention provides a quantum circuit adjustment method, comprising: Execute each quantum circuit in the parallel quantum circuit set independently to obtain the independent execution results of each quantum circuit; performing a combined execution on all quantum circuits in the parallel quantum circuit set according to the execution timing scheme of the parallel quantum circuit set to obtain a combined execution result of each quantum circuit; An execution mode of the quantum circuit in the parallel quantum circuit concentration is adjusted according to the independent execution results and the combined execution results.

[0014] As an improvement to the above solution, adjusting the execution mode of the parallel quantum circuit centralized quantum circuit according to the independent execution result and the combined execution result includes: Statistically calculate the probability distribution of quantum bit states in the independent execution results and combined execution results of each quantum circuit; Calculating a difference between a probability distribution of the combined execution result and a probability distribution of the independent execution results to obtain a fidelity loss of the combined execution; If the fidelity loss is greater than a preset fidelity threshold, each quantum circuit in the parallel quantum circuit set is independently executed; If the fidelity loss is not greater than the preset fidelity threshold, all quantum circuits in the parallel quantum circuit set are combined and executed.

[0015] To achieve the above objectives, an embodiment of the present invention provides a quantum bit partitioning device, including: a qubit partitioning module for partitioning the physical qubits in the quantum chip into qubit partitions based on the topological structure of the physical qubits in the quantum chip using a hierarchical partitioning method; wherein the hierarchical partitioning method is a partitioning strategy for partitioning the physical qubits in the quantum chip into qubit partitions layer by layer according to a hierarchical progressive logic and the connectivity relationship of the qubits in the topological structure of the physical qubits; A bit partition evaluation module is used to perform quality evaluation on all quantum bit partitions in each layer and obtain partition evaluation results for all quantum bit partitions in each layer; The quantum circuit allocation module is used to allocate the quantum bit partitions to the quantum circuits in the parallel quantum circuit set according to the partition evaluation results and the complexity of the quantum circuit.

[0016] To achieve the above objectives, an embodiment of the present invention provides a quantum circuit adjustment device, comprising: The circuit independent execution module is used to independently execute each quantum circuit in the parallel quantum circuit set and obtain the independent execution result of each quantum circuit; a circuit merging execution module, configured to merge and execute all quantum circuits in the parallel quantum circuit set according to the execution timing scheme of the parallel quantum circuit set, and obtain a merged execution result of each quantum circuit; A circuit execution adjustment module is used to adjust the execution mode of the quantum circuit in the parallel quantum circuit set according to the independent execution result and the combined execution result.

[0017] In order to achieve the above-mentioned objectives, an embodiment of the present invention provides a terminal device, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor. When the processor executes the computer program, the above-mentioned quantum bit partitioning method or the above-mentioned quantum circuit adjustment method is implemented.

[0018] In order to achieve the above-mentioned purpose, an embodiment of the present invention further provides a computer-readable storage medium, which includes a stored computer program, wherein when the computer program is running, the device where the computer-readable storage medium is located is controlled to execute the above-mentioned quantum bit partitioning method or the above-mentioned quantum circuit adjustment method.

[0019] To achieve the above-mentioned purpose, an embodiment of the present invention also provides a computer program product, which is stored in a storage medium and executed by at least one processor to implement the steps of the above-mentioned quantum bit partitioning method or the steps of the above-mentioned quantum circuit adjustment method.

[0020] Compared to the prior art, the embodiments of the present invention disclose a quantum bit partitioning and circuit adjustment method, device, medium, and product. This method partitions the physical quantum bits in a quantum chip using a hierarchical partitioning method based on the topological structure of the physical quantum bits. A quality assessment is performed on all quantum bit partitions in each layer to obtain a partition assessment result for all quantum bit partitions in each layer. Based on the partition assessment results and the complexity of the quantum circuit, the quantum bit partitions are assigned to quantum circuits in a set of parallel quantum circuits. The connectivity relationships of the physical quantum bits in the quantum chip are determined based on the topological structure of the physical quantum bits. The physical quantum bits are then hierarchically partitioned based on these connectivity relationships, retaining all possible valid partitions. A quality assessment is performed on all quantum bit partitions in each layer, and the optimal unoccupied quantum bit partition is assigned to the current quantum circuit based on the partition assessment results and the complexity of the quantum circuit. This method addresses the issues of insufficient partition diversity and global optimality in prior quantum bit partition mapping methods, thereby improving the processing efficiency of quantum computing tasks. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 1 is a flow chart of a quantum bit partitioning method provided by an embodiment of the present invention; Figure 2 This is a flowchart of parallel processing of quantum computing tasks provided by an embodiment of the present invention; Figure 3 This is a flow chart of a quantum circuit adjustment method provided by an embodiment of the present invention; Figure 4 This is a framework diagram of a parallel processing mechanism for quantum computing tasks provided by an embodiment of the present invention; Figure 5 1 is a schematic structural diagram of a quantum bit partitioning device provided by an embodiment of the present invention; Figure 6 1 is a schematic structural diagram of a quantum circuit adjustment device provided by an embodiment of the present invention; Figure 7 It is a structural diagram of a terminal device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0022] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0023] It should be noted that the terms "comprises" and "specifically" and any variations thereof in the present invention are intended to cover non-exclusive inclusions. For example, a process, method, system, product or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or are inherent to these processes, methods, products or apparatuses.

[0024] See also Figure 1 , Figure 1 1 is a flow chart of a quantum bit partitioning method provided by an embodiment of the present invention, the quantum bit partitioning method comprising: S11, hierarchically partitioning the physical qubits in the quantum chip using a hierarchical partitioning method according to the topological structure of the physical qubits; wherein the hierarchical partitioning method is a partitioning strategy that divides the physical qubits in the quantum chip into qubit partitions layer by layer according to a hierarchical progressive logic and the connectivity relationship of the qubits in the topological structure of the physical qubits; S12, performing quality assessment on all quantum bit partitions in each layer to obtain partition assessment results for all quantum bit partitions in each layer; S13, allocating the quantum bit partitions to the quantum circuits in the parallel quantum circuit set according to the partition evaluation results and the complexity of the quantum circuits.

[0025] For example, the underlying physical qubit topology of the quantum chip is obtained (the physical connectivity between each physical qubit is clearly defined). Each qubit is then treated as a partition, forming a single-bit layer. Based on the physical connectivity between each physical qubit, all pairs of connected qubits are then partitioned into a dual-bit layer. Similarly, all physical qubits are grouped into a partition, forming a full-bit layer, completing the hierarchical partitioning of the physical qubits. Each partition layer must meet the following requirements: uniqueness (no duplicate partitions within the same layer); connectivity (all qubits within a partition are physically connected); and completeness (all physical qubits are covered by all partitions at each layer). A quality assessment is performed on all qubit partitions in each layer based on key physical qubit parameters (the average fidelity of qubit measurements and the average fidelity of quantum gate operations between any two connected qubits). All qubit partitions within the same layer are then sorted from highest to lowest by quality assessment results. The sorted result serves as the partition assessment result for that layer, ultimately yielding a partition assessment result for all qubit partitions in each layer. The hierarchical partitioning in the embodiment of the present invention covers partitions with different bit numbers, can adapt to the resource requirements of different quantum circuits, and provides diverse selection and quantitative guidance for the partition allocation of parallel quantum circuit sets to ensure the efficiency and fidelity of quantum circuit execution.

[0026] It should be noted that the above steps S11-S12 can be regarded as preliminary preparations in the parallel processing mechanism of quantum computing tasks. They are offline operations and do not need to be repeated each time a quantum computing task is processed in parallel. Among them, the quantum bit hierarchical partitioning only needs to be repeated when the physical quantum bit topology structure in the quantum chip changes, and the hierarchical evaluation is repeated after the fidelity information is updated.

[0027] Specifically, the step S11 includes: S111, obtaining a topological structure of physical qubits in a quantum chip, and using a hierarchical partitioning method based on the topological structure to treat each physical qubit in the quantum chip as a single qubit partition, and grouping all single qubit partitions into single-bit layers; S112, starting from the single-bit layer, according to the connectivity relationship of the quantum bits in the topological structure, the corresponding bit layer is constructed layer by layer in the order of increasing number of bits until all physical quantum bits are divided into one quantum bit partition, thereby completing the hierarchical partitioning of the physical quantum bits.

[0028] like Figure 2 As shown, Figure 2 This is a flowchart of parallel processing of quantum computing tasks provided by an embodiment of the present invention. Figure 2The qubit hierarchical partitioning shown in the figure obtains the physical qubit topology of the quantum chip from the bottom layer and then groups each qubit into a single-bit layer. Within the single-bit layer, all partitions within that layer are combined in pairs. Based on the connectivity of the physical qubit topology, the combinations that show connectivity are grouped into two-bit layers. When constructing the three-bit layer, partitions with the same qubit in the two-bit layer are directly combined. When constructing the next level of partitions, simply combine them based on the previous level's partitions, until all qubits are grouped into a single partition. This completes the hierarchical partitioning of qubits, ensuring that the partitions within each layer are unique.

[0029] More specifically, step S112 includes: S1121, combining all single-qubit partitions in the single-bit layer in pairs, taking each pair of combinations having the connectivity of the topological structure as a two-qubit partition, and classifying all two-qubit partitions into a two-bit layer; S1122, combining two-qubit partitions having the same qubit in the two-bit layer to obtain a three-qubit layer; S1123, if all physical quantum bits are not divided into one bit partition, then the quantum bit partitions of the current bit layer are combined in order of increasing number of bits to obtain the next bit layer, until all physical quantum bits are divided into one bit partition, and the hierarchical partitioning of the physical quantum bits is completed.

[0030] For example, suppose there is a simple quantum chip containing 5 quantum bits, marked as 、 、 、 、 , in its topological structure and 、 connected, and 、 connected, and connected, and connected, It is not connected to any other qubits. The qubit layering partitioning process: Single-bit layer: partitioned into { }、{ }、{ }、{ }、{ }; Dual-bit layer: According to connectivity, the combinations with connectivity are { , }、{ , }、{ , }, forming these three two-bit partitions; Three-bit layer: Two-bit layer { , }and{ , } have the same quantum bits , combined to form { , , }partition;{ , }and{ , } have the same quantum bits , combined to form { , , }partition.

[0031] Four-bit layer: , , }and{ , , There are multiple identical qubits that can be combined to form { , , , }partition.

[0032] Five-qubit layer: All qubits are finally combined into { , , , , }partition.

[0033] Specifically, step S12 includes: The quality of all quantum bit partitions in each layer is evaluated according to the quality evaluation formula, and the partitions are sorted from large to small according to the quality evaluation results to obtain the partition evaluation results of all quantum bit partitions in each layer.

[0034] For example, all qubit partitions in each layer are quality evaluated and sorted from large to small according to the quality evaluation results, where the quality evaluation includes the connectivity of the qubits in the partition. , the average fidelity of quantum bit measurements And the average fidelity of quantum gate operations between any two connected qubits , since the quality evaluation is performed at the same level (i.e. the same number of qubits), The number of edges in the topology graph corresponding to the partition / The number of qubits in the corresponding partition express, The larger the value, the tighter the physical connection of the quantum bits. The fidelity can be obtained by random benchmarking. The quality evaluation formula is as follows: .

[0035] Specifically, step S13 includes: S131, sorting the quantum circuits in the parallel quantum circuit set according to the complexity of the quantum circuits; S132, allocating the quantum bit partitions to the quantum circuit in sequence according to the partition evaluation result and the sorting result.

[0036] Exemplarily, the parallel quantum circuit set is sorted according to the complexity of the quantum circuit, and the quantum bit partitions are sequentially allocated to the quantum circuit according to the partition evaluation results and the sorting results. The quantum circuit complexity is determined by the number of multi-qubit gates in the quantum circuit. / Number of qubits used in quantum circuits Characterize, the formula for quantum circuit complexity is as follows: , Where, is the complexity of the quantum circuit.

[0037] In the embodiment of the present invention, the circuits with higher complexity are preferentially assigned the optimal partitions of the corresponding layers, thereby preventing high-quality resources from being occupied by simple tasks.

[0038] More specifically, step S132 includes: S1321, based on the partition evaluation result and the sorting result, and according to the number of qubits required by the current quantum circuit to be allocated, selecting the optimal qubit partition in the bit layer corresponding to the current quantum circuit to be allocated; S1322, if the optimal quantum bit partition is already occupied by the previous quantum circuit, select a suboptimal quantum bit partition in the corresponding bit layer; S1323: If all qubit partitions in the corresponding bit layer have been occupied by the preceding quantum circuit, reselect the suboptimal qubit partition in the corresponding bit layer for the last allocated quantum circuit, and release the occupied optimal qubit partition. S1324, allocating the optimal quantum bit partition to the current quantum circuit to be allocated, until all quantum circuits in the parallel quantum circuit set are allocated to the quantum bit partition.

[0039] For example, when allocating partitions, first clarify the requirements of each quantum circuit: according to the number of qubits required for the quantum circuit, determine which partition to choose from the corresponding layer (for example, if a 2-qubit circuit is required, select a partition from the two-bit layer); then allocate them in order of circuit complexity: the circuit with the highest complexity is selected first, and the best evaluation result is obtained from the corresponding layer (i.e. The largest, unoccupied partition is assigned and marked as used. This process is repeated for each sorted quantum circuit. If a circuit cannot find an unoccupied optimal partition in the corresponding layer (e.g., the optimal partition is occupied by a more complex circuit, or the suboptimal and suboptimal partitions are also occupied), the optimal partition is reassigned to the previous circuit and reassigned to the suboptimal partition, freeing up the optimal partition for the current circuit. If this partition is still insufficient, the optimal partition is reassigned to the previous circuit until an available partition is found for the current circuit, ensuring that all circuits can be assigned to a partition.

[0040] It should be noted that the number of bits required for the quantum circuit strictly corresponds to the partition layering to ensure that the quantum circuit can operate normally within the allocated partition; the problem of insufficient partitions is solved by backtracking adjustment to ensure that all parallel quantum circuits can obtain available partitions, avoiding task stagnation due to lack of resources.

[0041] Furthermore, before evaluating the partition results and the complexity of the quantum circuit, the method further includes: S1301, performing a combined evaluation on the quantum computing tasks in the task list to obtain a parallel quantum circuit set of the quantum computing tasks.

[0042] Specifically, the combined evaluation of the quantum computing tasks in the task list to obtain the parallel quantum circuit set of the quantum computing tasks includes: Taking the quantum computing task that is queued at the top of the task list as the benchmark task, performing a combined evaluation on the other quantum computing tasks in the task list, and sorting them from largest to smallest according to the combined evaluation results; The quantum circuit corresponding to the benchmark task is added to the parallel quantum circuit set. If the number of quantum bits in the parallel quantum circuit set is less than a preset threshold, quantum circuits corresponding to other quantum computing tasks are selected from the sorted task list and added to the parallel quantum circuit set until the number of quantum bits in the parallel quantum circuit set is no less than the preset threshold.

[0043] For example, the quantum computing task that is at the top of the task list As a benchmark task, other quantum tasks in the task list Perform combination evaluation and sort from largest to smallest. The corresponding quantum circuit is added to the parallel quantum circuit set. When the parallel quantum circuit set is less than the preset threshold Under the premise of continuous selection of quantum circuits corresponding to quantum computing tasks from the sorted task list, the quantum circuits are added to the parallel quantum circuit set, where Set to , in order to reduce the crosstalk caused by the intensive use of quantum bits, is the number of physical quantum bits in the quantum chip. It is understandable that the preset threshold can be set according to other requirements.

[0044] The combination evaluation formula is as follows: , Where, For the combined evaluation results, is the number of quantum computing tasks in the task list; The sequence number of the current task in the task list; Indicates the depth of the quantum circuit corresponding to the quantum computing task.

[0045] It should be noted that from the list of quantum computing tasks to be processed, the task at the front of the queue is selected as the benchmark task to ensure the priority of task processing and first-come-first-served, which is in line with the conventional task scheduling logic; at the same time, the line depth of the benchmark task (reflecting the complexity of the task, the greater the depth, the longer the task execution time) is used as a reference to screen tasks with high compatibility with it to reduce decoherence errors during parallel processing.

[0046] Furthermore, after allocating the quantum bit partitions to the quantum circuits in the parallel quantum circuit set, the method further includes: The SABRE algorithm is used to perform quantum bit mapping on the quantum circuit to the corresponding quantum bit partition, and the quantum circuit is also performed quantum bit mapping on the quantum bit partition of the quantum chip.

[0047] For example, the qubit partition mapping module uses a SWAP-based bidirectional heuristic search (SABRE) algorithm to map the quantum circuit to the corresponding partition. Simultaneously, the SABRE (Swap-based Bidirectional Heuristic Search) algorithm asynchronously maps the quantum circuit to the entire physical qubit partition. Qubit mapping, as it is understood, maps the logical qubits (virtual bits defined in the circuit code) in the quantum circuit to the physical qubits (actual bits in the hardware) on the quantum chip. The core logic of the SABRE algorithm involves searching for the optimal SWAP gate (qubit swap operation) through a bidirectional search (looking forward several steps into the future and looking back through historical operations). This ensures that the logical bits match the physical bit connections without changing the circuit logic, while minimizing the number of SWAP gates (which increase circuit depth and introduce errors). For example, qubit mapping of the quantum circuit to the corresponding qubit partition is performed by using the SABRE algorithm to map the circuit's logical bits to the physical bits within the partition, within the assigned partition, ensuring that all quantum gates in the circuit can be executed on the physical bits (i.e., the two physical bits of the gate operation must be connected). Qubit mapping of the quantum circuit to the qubit partition of the quantum chip is performed by simultaneously executing the main mapping within the partition and initiating an independent SABRE algorithm process. Using the SABRE algorithm to map the circuit's logical bits to the physical bits within the partition, within the physical bits of the entire quantum chip, a full-bit-level mapping solution is generated.

[0048] The embodiment of the present invention uses the SABRE algorithm to map circuits to assigned partitions, ensuring that the circuits can be executed as scheduled in the parallel task set, avoiding circuit failure due to physical bit disconnection; asynchronously performs full-bit mapping and prepares mapping tables for independent execution in advance. When independent execution is determined to be required, there is no need to recalculate, saving time and cost; and through bidirectional heuristic search, the number of SWAP gates is reduced to avoid increased circuit depth and decreased fidelity due to excessive SWAP gates, meeting the high-fidelity requirements of quantum computing tasks.

[0049] See also Figure 3 , Figure 3 : is a flow chart of a quantum circuit adjustment method provided by an embodiment of the present invention, the quantum circuit adjustment method comprising: S21, independently executing each quantum circuit in the parallel quantum circuit set to obtain an independent execution result of each quantum circuit; S22, merging and executing all quantum circuits in the parallel quantum circuit set according to the execution timing scheme of the parallel quantum circuit set to obtain a merged execution result of each quantum circuit; S23, adjusting the execution mode of the quantum circuit in the parallel quantum circuit cluster according to the independent execution result and the combined execution result.

[0050] For example, a single circuit in a parallel quantum circuit set is run independently on the hardware (other circuits are temporarily disabled). This execution is repeated s times, with the qubit state recorded for each execution and the frequency of each state counted. It is understood that during independent execution, only the current circuit is loaded, not other circuits in the parallel set, to avoid crosstalk and measurement interference, ensuring that the frequency reflects the true probability distribution when the circuits are free of interference. All circuits in the parallel quantum circuit set are run simultaneously on the hardware, again repeating s times. The qubit state of the current circuit is recorded for each execution, and the frequency of each state counted. It is understood that during the combined execution, the synchronized measurement strategy (after inserting the ID gate) must be strictly followed to ensure consistency with the subsequent formal parallel execution environment, ensuring that the frequency reflects the true probability distribution when the circuits are subject to interference. The actual probability distribution is compared with the true probability distribution to adjust the execution of the quantum circuits in the parallel quantum circuit set. Through actual execution comparison, the embodiments of the present invention can capture unrepresentable errors such as crosstalk and measurement interference; differentiated judgments on different lines ensure the parallel efficiency of most lines while avoiding unreliable results due to the merging of individual lines; and by setting a smaller s, while obtaining valid samples, it avoids occupying too many hardware resources, meeting the requirements of efficient quantum computing processing.

[0051] Specifically, step S23 includes: S231, calculating the probability distribution of the quantum bit states in the independent execution results and the combined execution results of each quantum circuit; S232, calculating the difference between the probability distribution of the combined execution result and the probability distribution of the independent execution results to obtain the fidelity loss of the combined execution; S233, if the fidelity loss is greater than a preset fidelity threshold, independently executing each quantum circuit in the parallel quantum circuit set; S234: If the fidelity loss is not greater than the preset fidelity threshold, all quantum circuits in the parallel quantum circuit set are combined and executed.

[0052] For example, the quantum circuits in the parallel quantum circuit set are executed separately Second-rate, Can be set between 50-60 to get each quantum circuit The measurement results of times, where the number of executions The setting should be much smaller than the normal execution times, taking into account the effectiveness of the sample and the time cost; then merge the execution quantum circuit times, and each quantum circuit is also obtained The measurement results of each quantum circuit are counted separately in the independent execution and combined execution results. The probability distribution of quantum bit states and , with the probability distribution of the results of independent execution As a benchmark, the probability distribution of the combined execution results is calculated and The gap To express the fidelity loss of the merge execution, compare the gap With the preset fidelity threshold ,like , it means that the fidelity of the quantum circuit is affected when it is combined and executed, and it needs to be executed independently; otherwise, the combined execution continues. is an empirical constant that can be derived through testing in benchmark quantum circuits. This enables flexible adjustment of quantum circuit parallelism and ensures high fidelity in parallel processing of quantum computing tasks.

[0053] The fidelity loss formula is as follows: , Where, For the independent execution results The probability distribution of the quantum bit states; The merged execution result The probability distribution of the quantum bit states.

[0054] Furthermore, before independently executing each quantum circuit in the parallel quantum circuit set, the method further includes: S201, determining a benchmark execution timing of the parallel quantum circuit set according to the depth of each quantum circuit in the parallel quantum circuit set; S202 , inserting a quantum ID gate at the front end of a quantum circuit that is shorter than the benchmark execution timing according to the benchmark execution timing, to obtain an execution timing scheme for the parallel quantum circuit set.

[0055] For example, compare the depth of each quantum circuit in the parallel quantum circuit set , at maximum depth The quantum circuit is used as a reference, and the front ends of other quantum circuits are inserted The quantum ID gate (no operation), where To correspond to the depth of quantum circuits, the execution of quantum circuits with lower depths is postponed, the measurement operations of each quantum circuit are synchronized, and the interference of the measurement operation of one quantum circuit on the fidelity of other quantum circuits is reduced.

[0056] like Figure 2As shown in the figure, in a specific implementation, the topological structure of the physical quantum bits in the quantum chip is first determined; based on the topological structure, a hierarchical partitioning method is used (such as gradually building from a single-bit layer to a multi-bit layer) to divide the physical quantum bits into different "quantum bit hierarchical partitions", covering partition combinations with different bit numbers and connectivity characteristics to adapt to the needs of diverse quantum circuits. For each partition layer, a comprehensive quality score is calculated based on dimensions such as connectivity, measurement fidelity, and quantum gate operation fidelity. , sort the same-layer partitions by score, output the hierarchical evaluation results, select the top tasks in the queue as the task benchmark for the list of quantum computing tasks to be processed, and use the combined evaluation formula to calculate the combined evaluation results of other tasks and the benchmark tasks ,according to Filter quantum computing tasks and generate a set of parallel quantum circuits so that adapted tasks can run in parallel and coordinate to improve efficiency. Combined with the hierarchical evaluation results (high-quality partition sorting), assign quantum bit partitions with corresponding bit scale and quality standards to each circuit in the parallel quantum circuit set, so that the circuit can run on adapted hardware resources. Through algorithms such as SABRE, map the logical quantum bits of the circuit to the physical quantum bits of the assigned partitions, generate the main (for combined execution) and backup (for independent execution) mapping tables, and build a bridge between logic and hardware. For the mapped quantum circuits, perform independent execution (single-circuit running, measuring basic fidelity) and combined execution (multiple-circuit parallel running, measuring synergy effects) respectively. Compare the fidelity loss of the two execution methods. ,like , select merge execution to improve processing efficiency; if , then independent execution ensures fidelity and enables flexible scheduling. While ensuring computing quality, the embodiments of the present invention maximize the efficiency advantages of quantum parallel computing and adapt to the diverse needs of quantum computing tasks.

[0057] like Figure 4 As shown, Figure 4 This is a framework diagram of a quantum computing task parallel processing mechanism provided by an embodiment of the present invention. Figure 4 It includes four modules: quantum computing task parallel management module, quantum bit partition mapping module, quantum circuit scheduling execution module and quantum circuit flexible parallel module. The logical relationship between the modules is as follows: Figure 4As shown in the figure, the functions of each module are introduced as follows: Quantum computing task parallel management module: responsible for managing and scheduling the quantum computing task list, and combining it to obtain a parallel quantum circuit set; Quantum bit partition mapping module: responsible for dividing the physical quantum bits in the preparation stage and providing quantum bit partitions for the parallel quantum circuit set; Quantum computing task parallel processing stage is responsible for allocating partitions to quantum circuits and quantum bit mapping; Quantum circuit scheduling execution module: responsible for scheduling the start time of each quantum circuit in the parallel quantum circuit set; Quantum circuit flexible parallel module: responsible for inserting independent execution of quantum circuits when merging and executing quantum circuits, and comparing the results of merging and independent executions to make flexible adjustments to the execution of quantum circuits.

[0058] A quantum circuit adjustment method provided by an embodiment of the present invention independently executes each quantum circuit in a parallel quantum circuit set to obtain an independent execution result for each quantum circuit. Based on the execution timing scheme of the parallel quantum circuit set, all quantum circuits in the parallel quantum circuit set are combined and executed to obtain a combined execution result for each quantum circuit. The execution mode of the quantum circuits in the parallel quantum circuit set is adjusted based on the independent and combined execution results. By comparing actual execution results, this method can directly capture the impact of difficult-to-quantify errors such as crosstalk and decoherence on fidelity, reversely optimize the parallelization strategy from the execution stage, and ultimately ensure the high-fidelity requirements of parallel processing of multiple quantum computing tasks.

[0059] See also Figure 5 , Figure 5 1 is a schematic structural diagram of a quantum bit partitioning device 10 provided in an embodiment of the present invention. The quantum bit partitioning device 10 includes: A qubit partitioning module 11 is configured to partition the physical qubits in the quantum chip into qubit partitions according to the topological structure of the physical qubits in the quantum chip using a hierarchical partitioning method; wherein the hierarchical partitioning method is a partitioning strategy that divides the physical qubits in the quantum chip into qubit partitions layer by layer according to a hierarchical progressive logic and the connectivity relationship of the qubits in the topological structure of the physical qubits; A bit partition evaluation module 12 is used to perform quality evaluation on all qubit partitions in each layer and obtain partition evaluation results for all qubit partitions in each layer; The quantum circuit allocation module 13 is configured to allocate the quantum bit partitions to the quantum circuits in the parallel quantum circuit set according to the partition evaluation results and the complexity of the quantum circuits.

[0060] Furthermore, the quantum bit partitioning device 10 further includes: The quantum task combination module is used to perform combination evaluation on the quantum computing tasks in the task list to obtain a set of parallel quantum circuits for the quantum computing tasks.

[0061] Furthermore, the quantum bit partitioning device 10 further includes: The quantum bit mapping module is used to use the SABRE algorithm to perform quantum bit mapping on the quantum circuit to the corresponding quantum bit partition, and to perform quantum bit mapping on the quantum circuit to the quantum bit partition of the quantum chip.

[0062] A quantum bit partitioning device 10 provided in an embodiment of the present invention can implement all the processes of the quantum bit partitioning method of the above embodiment. The functions of each module in the device and the technical effects achieved are respectively the same as the functions and technical effects achieved by the quantum bit partitioning method of the above embodiment, and will not be repeated here.

[0063] See also Figure 6 , Figure 6 1 is a schematic structural diagram of a quantum circuit adjustment device 20 provided in an embodiment of the present invention. The quantum circuit adjustment device 20 includes: The circuit independent execution module 21 is used to independently execute each quantum circuit in the parallel quantum circuit set to obtain an independent execution result of each quantum circuit; a circuit merging execution module 22, configured to merge and execute all quantum circuits in the parallel quantum circuit set according to the execution timing scheme of the parallel quantum circuit set, and obtain a merge execution result for each quantum circuit; The circuit execution adjustment module 23 is configured to adjust the execution mode of the quantum circuits in the parallel quantum circuit cluster according to the independent execution results and the combined execution results.

[0064] Furthermore, the quantum circuit adjustment device 20 further includes: The execution timing determination module is used to determine the benchmark execution timing of the parallel quantum circuit set according to the depth of each quantum circuit in the parallel quantum circuit set; based on the benchmark execution timing, a quantum ID gate is inserted at the front end of the quantum circuit with a timing less than the benchmark execution timing to obtain an execution timing scheme for the parallel quantum circuit set.

[0065] A quantum circuit adjustment device 20 provided in an embodiment of the present invention can implement all the processes of the quantum circuit adjustment method of the above embodiment. The functions and technical effects achieved by each module in the device are respectively the same as those of the quantum circuit adjustment method of the above embodiment, and will not be repeated here.

[0066] See also Figure 7 , Figure 7The figure is a schematic diagram of the structure of a terminal device 30 provided in an embodiment of the present invention. The terminal device 30 in this embodiment includes a processor 31, a memory 32, and a computer program stored in the memory 32 and executable on the processor 31. When the processor 31 executes the computer program, it implements the steps of the aforementioned quantum bit partitioning method embodiment or the aforementioned quantum circuit adjustment method embodiment. Alternatively, when the processor 31 executes the computer program, it implements the functions of the modules in the aforementioned quantum bit partitioning device embodiment or the aforementioned quantum circuit adjustment device embodiment.

[0067] Exemplarily, the computer program may be divided into one or more modules, which are stored in the memory 32 and executed by the processor 31 to implement the present invention. The one or more modules may be a series of computer program instruction segments capable of implementing specific functions, and the instruction segments are used to describe the execution process of the computer program in the terminal device 30.

[0068] The terminal device 30 may be a computing device such as a desktop computer, laptop, PDA, or cloud server. The terminal device 30 may include, but is not limited to, a processor 31 and a memory 32. Those skilled in the art will appreciate that the schematic diagram is merely an example of the terminal device 30 and does not limit the terminal device 30. The terminal device 30 may include more or fewer components than shown, or may combine certain components or different components. For example, the terminal device 30 may also include input / output devices, network access devices, buses, and the like.

[0069] The processor 31 may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor. The processor 31 is the control center of the terminal device 30 and connects various components of the terminal device 30 using various interfaces and lines.

[0070] The memory 32 can be used to store the computer programs and / or modules. The processor 31 implements the various functions of the terminal device 30 by running or executing the computer programs and / or modules stored in the memory 32 and accessing the data stored in the memory 32. The memory 32 may primarily include a program storage area and a data storage area. The program storage area may store an operating system and at least one application required for a function (such as a sound playback function or an image playback function); the data storage area may store data generated based on the use of the mobile phone (such as audio data and a phone book). Furthermore, the memory 32 may include high-speed random access memory (RAM) and non-volatile memory, such as a hard disk, internal memory, a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, at least one disk storage device, a flash memory device, or other volatile solid-state storage device.

[0071] If the module integrated into the terminal device 30 is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present invention can implement all or part of the process steps in the above-mentioned method embodiments by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium. When executed by the processor 31, the computer program can implement the steps of each of the above-mentioned method embodiments. The computer program includes computer program code, which can be in source code form, object code form, executable file, or some intermediate form. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording medium, USB flash drive, mobile hard drive, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal, and software distribution medium. It should be noted that the content of the computer-readable medium can be appropriately increased or decreased based on the requirements of legislation and patent practice within a jurisdiction. For example, in some jurisdictions, based on legislation and patent practice, computer-readable media does not include electric carrier signals and telecommunication signals.

[0072] It should be noted that the device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed across multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment. In addition, in the drawings of the device embodiments provided by the present invention, the connection relationship between the modules indicates that there is a communication connection between them, which may be specifically implemented as one or more communication buses or signal lines. A person of ordinary skill in the art can understand and implement the present invention without inventive effort.

[0073] An embodiment of the present invention also provides a computer-readable storage medium, which includes a stored computer program, wherein when the computer program is running, the device where the computer-readable storage medium is located is controlled to execute the quantum bit partitioning method of the above embodiment, or the quantum circuit adjustment method of the above embodiment.

[0074] In addition, an embodiment of the present invention also provides a computer program product, which is stored in a storage medium and is executed by at least one processor to implement the steps of the quantum bit partitioning method of the above embodiment, or the steps of the quantum circuit adjustment method of the above embodiment.

[0075] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A quantum bit partitioning method, characterized in that: include: Based on the topological structure of the physical qubits in the quantum chip, the physical qubits are hierarchically partitioned using a hierarchical partitioning method; wherein the hierarchical partitioning method is a partitioning strategy that divides the physical qubits in the quantum chip into qubit partitions layer by layer according to a hierarchical progressive logic and the connectivity relationship of the qubits in the topological structure of the physical qubits; Performing quality assessment on all qubit partitions in each layer to obtain partition assessment results for all qubit partitions in each layer; The quantum bit partitions are allocated to the quantum circuits in the parallel quantum circuit set according to the partition evaluation results and the complexity of the quantum circuits.

2. The quantum bit partitioning method according to claim 1, wherein: The method of hierarchically partitioning the physical quantum bits in the quantum chip using a hierarchical partitioning method according to the topological structure of the physical quantum bits includes: Obtaining a topological structure of physical qubits in a quantum chip, and using a hierarchical partitioning method based on the topological structure to treat each physical qubit in the quantum chip as a single qubit partition, and grouping all single qubit partitions into single-bit layers; Starting from the single-bit layer, according to the connectivity relationship of the quantum bits in the topological structure, the corresponding bit layers are constructed layer by layer in the order of increasing number of bits until all physical quantum bits are divided into one quantum bit partition, thereby completing the hierarchical partitioning of the physical quantum bits.

3. The quantum bit partitioning method according to claim 2, wherein: Starting from the single-bit layer, according to the connectivity relationship of the qubits in the topological structure, corresponding bit layers are constructed layer by layer in the order of increasing number of bits until all physical qubits are divided into one qubit partition, thereby completing the hierarchical partitioning of the physical qubits, including: Combining all single-qubit partitions in the single-bit layer in pairs, taking each pair of combinations having the connectivity of the topological structure as a two-qubit partition, and classifying all the two-qubit partitions into a two-bit layer; Combining two-qubit partitions having the same qubit in the two-bit layer to obtain a three-qubit layer; If all physical quantum bits are not divided into one bit partition, the quantum bit partitions of the current bit layer are combined in order of increasing number of bits to obtain the next bit layer, until all physical quantum bits are divided into one bit partition, and the hierarchical partitioning of the physical quantum bits is completed.

4. The quantum bit partitioning method according to claim 1, wherein: The quality assessment of all qubit partitions in each layer is performed to obtain partition assessment results of all qubit partitions in each layer, including: The quality of all quantum bit partitions in each layer is evaluated according to the quality evaluation formula, and the partitions are sorted from large to small according to the quality evaluation results to obtain the partition evaluation results of all quantum bit partitions in each layer.

5. The quantum bit partitioning method according to claim 1, wherein: Allocating the quantum bit partitions to the quantum circuits in the parallel quantum circuit set according to the partition evaluation results and the complexity of the quantum circuits includes: Sort the quantum circuits in the parallel quantum circuit set according to the complexity of the quantum circuits; The quantum bit partitions are sequentially allocated to the quantum circuit according to the partition evaluation results and the sorting results.

6. The quantum bit partitioning method according to claim 5, wherein: The allocating the quantum bit partitions to the quantum circuit in sequence according to the partition evaluation results and the sorting results includes: According to the partition evaluation result and the sorting result, the optimal quantum bit partition in the bit layer corresponding to the quantum circuit to be currently allocated is selected according to the number of quantum bits required by the quantum circuit to be currently allocated; If the optimal quantum bit partition is already occupied by the previous quantum circuit, then a suboptimal quantum bit partition in the corresponding bit layer is selected; If all qubit partitions in the corresponding bit layer have been occupied by the previous quantum circuit, then reselect the suboptimal qubit partition in the corresponding bit layer for the last allocated quantum circuit, and release the occupied optimal qubit partition; Then, the optimal quantum bit partition is allocated to the quantum circuit to be currently allocated until all quantum circuits in the parallel quantum circuit set are allocated to the quantum bit partition.

7. The quantum bit partitioning method according to claim 1, wherein: Before evaluating the partition results and the complexity of the quantum circuit, the method further includes: The quantum computing tasks in the task list are combined and evaluated to obtain a set of parallel quantum circuits for the quantum computing tasks.

8. The quantum bit partitioning method according to claim 7, wherein: The combined evaluation of the quantum computing tasks in the task list to obtain a parallel quantum circuit set of the quantum computing tasks includes: Taking the quantum computing task that is queued at the top of the task list as the benchmark task, performing a combined evaluation on the other quantum computing tasks in the task list, and sorting them from largest to smallest according to the combined evaluation results; The quantum circuit corresponding to the benchmark task is added to the parallel quantum circuit set. If the number of quantum bits in the parallel quantum circuit set is less than a preset threshold, quantum circuits corresponding to other quantum computing tasks are selected from the sorted task list and added to the parallel quantum circuit set until the number of quantum bits in the parallel quantum circuit set is no less than the preset threshold.

9. A quantum circuit adjustment method, characterized in that: include: Execute each quantum circuit in the parallel quantum circuit set independently to obtain the independent execution results of each quantum circuit; performing a combined execution on all quantum circuits in the parallel quantum circuit set according to the execution timing scheme of the parallel quantum circuit set to obtain a combined execution result of each quantum circuit; An execution mode of the quantum circuit in the parallel quantum circuit concentration is adjusted according to the independent execution results and the combined execution results.

10. The quantum circuit adjustment method according to claim 9, characterized in that: The adjusting the execution mode of the parallel quantum circuit centralized quantum circuit according to the independent execution result and the combined execution result includes: Statistically calculate the probability distribution of quantum bit states in the independent execution results and combined execution results of each quantum circuit; Calculating a difference between a probability distribution of the combined execution result and a probability distribution of the independent execution results to obtain a fidelity loss of the combined execution; If the fidelity loss is greater than a preset fidelity threshold, each quantum circuit in the parallel quantum circuit set is independently executed; If the fidelity loss is not greater than the preset fidelity threshold, all quantum circuits in the parallel quantum circuit set are combined and executed.

11. A quantum bit partitioning device, characterized in that: include: a qubit partitioning module for partitioning the physical qubits in the quantum chip into qubit partitions based on the topological structure of the physical qubits in the quantum chip using a hierarchical partitioning method; wherein the hierarchical partitioning method is a partitioning strategy for partitioning the physical qubits in the quantum chip into qubit partitions layer by layer according to a hierarchical progressive logic and the connectivity relationship of the qubits in the topological structure of the physical qubits; A bit partition evaluation module is used to perform quality evaluation on all quantum bit partitions in each layer and obtain partition evaluation results for all quantum bit partitions in each layer; The quantum circuit allocation module is used to allocate the quantum bit partitions to the quantum circuits in the parallel quantum circuit set according to the partition evaluation results and the complexity of the quantum circuit.

12. A quantum circuit adjustment device, characterized in that: include: The circuit independent execution module is used to independently execute each quantum circuit in the parallel quantum circuit set and obtain the independent execution result of each quantum circuit; a circuit merging execution module, configured to merge and execute all quantum circuits in the parallel quantum circuit set according to the execution timing scheme of the parallel quantum circuit set, and obtain a merged execution result of each quantum circuit; a circuit execution adjustment module, configured to adjust an execution mode of the quantum circuit in the parallel quantum circuit cluster according to the independent execution result and the combined execution result; According to the partition evaluation result and the complexity of the quantum circuit, quantum bit partitions are allocated to the quantum circuits in the parallel quantum circuit set.

13. A terminal device, characterized in that: The method comprises a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein when the processor executes the computer program, the method for quantum bit partitioning as described in any one of claims 1 to 8 or the method for quantum circuit adjustment as described in any one of claims 9 to 10 is implemented.

14. A computer-readable storage medium, characterized in that The computer-readable storage medium includes a stored computer program, wherein, when the computer program is run, the device where the computer-readable storage medium is located is controlled to execute the quantum bit partitioning method according to any one of claims 1 to 8, or the quantum circuit adjustment method according to any one of claims 9 to 10.

15. A computer program product, characterized in that The computer program product is stored in a storage medium, and the program product is executed by at least one processor to implement the quantum bit partitioning method as described in any one of claims 1 to 8, or the quantum circuit adjustment method as described in any one of claims 9 to 10.

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