Quantum gate scheduling methods, devices, equipment, storage media, and program products

Abstract

This embodiment discloses a quantum gate scheduling method, apparatus, device, storage medium, and program product. The method includes: generating a DAG based on the dependencies of quantum gates in a quantum circuit, wherein the nodes of the DAG are quantum gate nodes; and heuristically selecting quantum gate nodes in the DAG based on the probability of a node being selected, thereby obtaining a scheduling result, wherein the scheduling result includes quantum gate nodes arranged in the selection order.

Description

Technical Field

[0001] This application belongs to the field of quantum computing and relates to, but is not limited to, a quantum gate scheduling method, apparatus, device, storage medium, and program product. Background Technology

[0002] In related technologies, qubit mapping and quantum gate scheduling support the execution of quantum circuits by quantum processors. Qubit mapping allocates hardware resources for quantum circuits, mapping logical qubits in the quantum circuit to physical qubits in the quantum chip; quantum gate scheduling plans the execution of quantum gates in the quantum circuit. However, the scheduling process for quantum gates is relatively complex, and for complex quantum circuits, it is difficult to obtain optimal scheduling results in a short time. Summary of the Invention

[0003] This application provides a quantum gate scheduling method, apparatus, device, storage medium, and program product.

[0004] This application proposes a quantum gate scheduling method, the method comprising:

[0005] A directed acyclic graph (DAG) is generated based on the dependencies of quantum gates in the quantum circuit, and the nodes of the DAG are quantum gate nodes;

[0006] Based on the probability of a node being selected in the DAG, quantum gate nodes are heuristically selected in the DAG to obtain a scheduling result, which includes quantum gate nodes arranged in the selection order.

[0007] This application also proposes a quantum gate scheduling device, the device comprising:

[0008] The first processing module is used to generate a DAG based on the quantum gate dependencies in the quantum circuit, wherein the nodes of the DAG are quantum gate nodes;

[0009] The second processing module is used to heuristically select quantum gate nodes in the DAG based on the probability of a node being selected, and obtain a scheduling result, wherein the scheduling result includes quantum gate nodes arranged in the selection order.

[0010] This application also provides an electronic device, which includes a processor and a memory for storing a computer program that can run on the processor; wherein the processor is used to run the computer program to execute any of the above-described quantum gate scheduling methods.

[0011] This application also provides a computer storage medium storing a computer program that, when executed by a processor, implements any of the above-described quantum gate scheduling methods.

[0012] This application also provides a computer program product, including a computer program that, when executed by a processor, implements any of the above-described quantum gate scheduling methods.

[0013] As can be seen, in the embodiments of this application, after generating a DAG based on the dependency relationship of quantum gates in the quantum circuit, the selection of quantum gate nodes in the DAG can be guided by a heuristic selection method based on the probability of the nodes being selected. In this way, by using a heuristic selection method, the scheduling result can be avoided from getting trapped in a local optimum to a certain extent, which is beneficial to quickly obtaining a better quantum gate scheduling result. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the atomic array in a quantum processor;

[0015] Figure 2 This is a flowchart of a quantum gate scheduling method according to an embodiment of this application;

[0016] Figure 3 This is a schematic diagram of the previously selected single-bit gate node and the currently scheduled single-bit gate node in this embodiment of the application.

[0017] Figure 4 This is a flowchart illustrating the process of obtaining scheduling results in this application embodiment;

[0018] Figure 5 This is a flowchart of a quantum bit mapping and quantum gate scheduling method in an embodiment of this application;

[0019] Figure 6 This is a schematic diagram of the structure of the quantum gate scheduling device according to an embodiment of this application;

[0020] Figure 7 This is a schematic diagram of the composition structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0021] Neutral atom quantum computing technology has made significant progress in recent years. Due to its high fidelity, long coherence time, good scalability, and flexible configuration, it is widely regarded by researchers as the most promising candidate for realizing quantum computers. In the field of neutral atom quantum computing, reconfigurable atom arrays (RAAs) are a promising new technology route. They allow the creation and manipulation of logical qubits through the reconfiguration of physical qubits, and feature high-fidelity two-qubit gates and arbitrary connectivity.

[0022] In related technologies, for RAA quantum processors, the atomic array can be divided into a storage region and a manipulation region. (See reference...) Figure 1 Storage area 101 is used to store qubits, and manipulation area 102 is used to perform quantum gate operations. When performing a quantum gate operation, the corresponding qubit can be moved from storage area 101 to an empty location in manipulation area 102 via a move operation to apply the gate operation. Figure 1 In this context, Q0 and Q1 represent the two qubits that need to be moved from storage area 101 to manipulation area 102.

[0023] For RAA quantum processors, in order to ensure fidelity, all quantum gate operations in the control region 102 should be global operations, and only one quantum gate operation can be executed at a time. Therefore, how to schedule the execution order of quantum gates in the quantum circuit is crucial.

[0024] In related technologies, neutral atom qubit mapping and quantum gate scheduling methods are designed for fixed atom arrays (FAAs). Unlike resonant atom arrays (RAAs), FAAs cannot satisfy the requirement of full qubit connectivity (i.e., any two physical qubits are connected). Therefore, during qubit mapping, swap gates need to be inserted into the quantum circuit to satisfy the execution constraints of two-qubit gates, resulting in additional gate operations and reduced execution fidelity. For this reason, most qubit mapping methods in related technologies focus on optimizing the number of inserted swap gates. Regarding quantum gate scheduling, FAA quantum processors support the simultaneous operation of multiple quantum gates. Therefore, scheduling only needs to consider the dependencies between quantum gates. A directed atom graph (DAG) is generated through the quantum circuit, and then the DAG is searched to obtain the quantum gate scheduling order with the shortest execution time.

[0025] To provide a qubit mapping and quantum gate scheduling method for RAA quantum processors, the following aspects need to be considered: First, since the control region can only execute one type of quantum gate at a time, executing quantum gate operations serially will lead to a waste of quantum hardware resources. Therefore, rationally scheduling the execution order of quantum gates in the quantum circuit will help reduce qubit movement and improve the fidelity and efficiency of quantum circuit execution. Second, based on the characteristic that the control region can only execute one type of quantum gate at a time, it is necessary to merge identical quantum gates as much as possible, which will help improve the execution efficiency of the quantum circuit. Third, due to the limitations of noisy intermediate-scale quantum (NISQ) hardware, the fidelity of quantum circuit execution is often difficult to guarantee. Rational qubit mapping will help ensure the fidelity of quantum circuit execution. Fourth, the quantum gate scheduling process is relatively complex, and for some quantum circuits, such as complex quantum circuits, it is difficult to obtain a good scheduling result in a short time.

[0026] To address the technical problems existing in related technologies, this application proposes a technical solution based on embodiments of the present application. This application provides a technical solution for quantum circuit execution in RAAs, with execution efficiency and fidelity as optimization objectives.

[0027] The embodiments of this application will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the embodiments provided herein are merely illustrative of the embodiments of this application and are not intended to limit the embodiments of this application. Furthermore, the embodiments provided below are some embodiments for implementing this application, and not all embodiments for implementing this application. Unless otherwise specified, the technical solutions described in the embodiments of this application can be implemented in any combination.

[0028] It should be noted that, in the embodiments of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a method or apparatus that includes a list of elements includes not only the elements expressly described, but also other elements not expressly listed, or elements inherent to implementing the method or apparatus. Without further limitations, an element defined by the phrase "comprising a..." does not exclude the presence of other related elements (e.g., steps in the method or units in the apparatus, such as portions of circuitry, processors, programs, or software, etc.) in the method or apparatus that includes that element.

[0029] The quantum gate scheduling method provided in this application includes a series of steps, but the quantum gate scheduling method provided in this application is not limited to the steps described. Similarly, the quantum gate scheduling device provided in this application includes a series of modules, but the device provided in this application is not limited to the modules explicitly described, but may also include modules that need to be set up for obtaining relevant information or processing based on information.

[0030] Figure 2 This is a flowchart of a quantum gate scheduling method according to an embodiment of this application, as follows: Figure 2 As shown, the process includes:

[0031] Step 201: Generate a DAG based on the quantum gate dependencies in the quantum circuit. The nodes of the DAG are quantum gate nodes.

[0032] Quantum circuits, also known as quantum circuits, are abstract computational models based on the principles of quantum mechanics, used to describe the operation of quantum information storage units (such as qubits). In the computational model of quantum circuits, a quantum gate can be considered as a quantum circuit that operates on a small number of qubits. Quantum gates can be represented using matrices and can be single-qubit or two-qubit gates.

[0033] The quantum gate dependency represents the relationship between logical qubits and quantum gates. Based on the quantum gate dependency, a DAG containing quantum gate nodes can be constructed. Here, DAG refers to a directed graph without loops. The quantum gate nodes in a DAG can be single-qubit gate nodes built based on single-qubit gates, or two-qubit gate nodes built based on two-qubit gates.

[0034] Step 202: Based on the probability of a node being selected in the DAG, heuristically select quantum gate nodes in the DAG to obtain the scheduling result, which includes the quantum gate nodes arranged in the selection order.

[0035] In this embodiment, the probability of selecting a single-bit gate node and the probability of selecting a two-bit gate node in a DAG can be determined separately. Then, based on these probabilities, quantum gate nodes are heuristically selected within the DAG. In practical applications, a heuristic algorithm can be used to select quantum gate nodes in the DAG based on the probability of node selection. By repeatedly selecting quantum gate nodes in the DAG using the heuristic algorithm, the selection order can be determined, thus obtaining quantum gate nodes arranged in the selection order.

[0036] In practical applications, steps 201 to 202 can be implemented based on a processor, which can be at least one of the following: Application Specific Integrated Circuit (ASIC), Digital Signal Processor (DSP), Digital Signal Processing Device (DSPD), Programmable Logic Device (PLD), Field Programmable Gate Array (FPGA), Central Processing Unit (CPU), Controller, Microcontroller, and Microprocessor.

[0037] As can be seen, in the embodiments of this application, after generating a DAG based on the dependency relationship of quantum gates in the quantum circuit, the selection of quantum gate nodes in the DAG can be guided by a heuristic selection method based on the probability of the nodes being selected. In this way, by using a heuristic selection method, the scheduling result can be avoided from getting trapped in a local optimum to a certain extent, which is conducive to quickly obtaining a better quantum gate scheduling result.

[0038] In this embodiment, heuristic selection of quantum gate nodes can be performed during the quantum gate scheduling stage without the need for time-consuming optimization algorithms. Therefore, the possibility of finding the optimal solution at a low time cost can be increased while avoiding getting trapped in local optima, thereby helping to reduce the time complexity of the quantum gate scheduling scheme.

[0039] To ensure the fidelity of quantum gate operations in a quantum circuit, high-quality qubit mapping is required before quantum gate scheduling. In some embodiments, before generating a DAG based on the quantum gate dependencies in the quantum circuit, the logical qubits can be sorted in descending order of the number of quantum gates applied to each logical qubit in the quantum circuit; based on the sorting results of the logical qubits, each logical qubit is sequentially mapped to multiple physical qubits arranged in descending order of fidelity, and the mapping relationship between the logical qubits and the physical qubits is a one-to-one mapping relationship.

[0040] To determine the fidelity of multiple physical qubits, in some embodiments, a preset reference quantum circuit can be mapped onto different physical qubits, quantum gate operations can be performed on the different physical qubits, and then the fidelity of the different physical qubits can be obtained by comparing the execution results with the theoretical results. Thus, the multiple physical qubits can be sorted in descending order of fidelity.

[0041] The quantum gates applied to a logical qubit can be quantum gates in a quantum circuit, or they can be basic quantum gates obtained by decomposing quantum gates in a quantum circuit. In some embodiments, quantum gates in a quantum circuit can be decomposed into basic quantum gates that can be directly executed in a quantum processor, and then the number of basic quantum gates applied to each logical qubit in the quantum circuit can be counted; in other embodiments, the number of quantum gates applied to each logical qubit in the quantum circuit can be counted.

[0042] Based on the aforementioned sorting methods for logical and physical qubits, after sorting the logical and physical qubits, each logical qubit can be sequentially mapped to multiple physical qubits arranged in descending order of fidelity, thus establishing a one-to-one mapping relationship between logical and physical qubits. In this application, embodiments can reasonably map physical qubits to logical qubits based on the fidelity of the physical qubits and the number of quantum gates applied to the logical qubits in the quantum circuit.

[0043] As can be seen, the embodiments of this application can map each logical qubit sequentially to multiple physical qubits arranged in descending order of fidelity based on the sorting result of each logical qubit. Since the sorting result of the logical qubits is determined based on the number of quantum gates applied to the logical qubits, and the number of quantum gates applied to the logical qubits can reflect the number of quantum gate operations in which the logical qubits participate, the embodiments of this application can improve the fidelity of quantum gate operations in quantum circuits by mapping logical qubits that participate in more quantum gate operations to high-quality physical qubits, thereby improving the overall fidelity of quantum circuit execution schemes.

[0044] After mapping logical qubits to physical qubits, a Directed Acyclic Graph (DAG) can be generated based on the dependencies of quantum gates in the quantum circuit. For example, a DAG's quantum gate nodes include single-qubit gate nodes, which consist of multiple consecutive single-qubit gates acting on the same qubit. In practical applications, multiple consecutive single-qubit gates acting on the same qubit can be merged into a single single-qubit gate node, which can be denoted as node_s.

[0045] It can be seen that by merging consecutive single-bit gates acting on the same qubit in a quantum circuit as single-bit gate nodes, the complexity of subsequent single-bit gate calls can be reduced, which is beneficial to reducing the time complexity of quantum gate scheduling.

[0046] Quantum gate nodes in a DAG also include two-bit gate nodes. In practical applications, each two-bit gate in a quantum circuit can be considered as a two-bit gate node. A two-bit gate node in a DAG can be denoted as node_m.

[0047] After generating the Directed Acyclic Graph (DAG), the nodes to be scheduled can be determined from the quantum gate nodes of the DAG. For example, the in-degree of each quantum gate node in the DAG can be calculated first, where the in-degree represents the number of edges pointing to that node. Then, the quantum gate nodes with an in-degree of 0 are identified as the nodes to be scheduled; here, the quantum gate nodes with an in-degree of 0 are the top-level nodes in the DAG. After determining the nodes to be scheduled, quantum gate nodes can be heuristically selected from the nodes to be scheduled based on the probability of each node being selected, thus obtaining the scheduling result.

[0048] In this embodiment, the selection of quantum gate nodes among the nodes to be scheduled is guided by a heuristic selection method based on the probability of a node being selected in the DAG. In this way, the scheduling result can be avoided from getting trapped in a local optimum to a certain extent by using a heuristic selection method, which is conducive to quickly scheduling the nodes to be scheduled.

[0049] In some embodiments, to obtain the scheduling result, after each selection of a quantum gate node from the nodes to be scheduled, the selected quantum gate node is added to the scheduling result, and the selected quantum gate node is deleted from the quantum gate nodes with an in-degree of 0. The nodes to be scheduled are then re-determined, and the step of selecting a quantum gate node from the nodes to be scheduled is repeated until the number of nodes to be scheduled is 0.

[0050] Understandably, after adding the selected quantum gate node to the scheduling result, if the selected quantum gate node is deleted from the quantum gate node with an in-degree of 0 and the node to be scheduled is re-determined, the number of nodes to be scheduled will gradually decrease. When the number of nodes to be scheduled is 0, it means that the scheduling of all quantum gate nodes with an in-degree of 0 has been completed. That is, the embodiments of this application can perform comprehensive scheduling for quantum gate nodes with an in-degree of 0.

[0051] In some embodiments, when determining the probability of selecting a quantum gate node in a node to be scheduled, the quantum gate node is selected based on a first probability of selecting each single-bit gate node and a second probability of selecting each two-bit gate node in the node to be scheduled during the initial selection of the quantum gate node. The first probability is determined based on the number of quantum gates contained in each single-bit gate node in the node to be scheduled and the sum of the number of quantum gates contained in each single-bit gate node in the node to be scheduled, and the second probability is determined based on the number of two-bit gate nodes in the node to be scheduled.

[0052] Here, the probability of each single-bit gate node being selected in the nodes to be scheduled is positively correlated with the number of quantum gates contained in the corresponding single-bit gate node, and negatively correlated with the sum of the number of quantum gates contained in all the single-bit gate nodes in the nodes to be scheduled.

[0053] The first node to be scheduled The number of quantum gates contained in a single-qubit gate node can be denoted as: The sum of the number of quantum gates contained in each single-bit gate node in the node to be scheduled can be denoted as: The first node in the pending scheduling The probability of a single-bit gate node being selected can be denoted as: For example, when making the first selection of a quantum gate node among the nodes to be scheduled, the first quantum gate node can be calculated according to formula (1). The probability of a single-bit gate node being selected .

[0054] (1)

[0055] in, This represents the set global factor. The value of is between 0 and 1.

[0056] The probability of each two-bit gate node being selected in the nodes to be scheduled is negatively correlated with the number of two-bit gate nodes in the nodes to be scheduled.

[0057] The number of two-bit gate nodes among the nodes to be scheduled can be denoted as: For example, during the initial selection of quantum gate nodes in the node to be scheduled, the probability of each two-bit gate node being selected in the node to be scheduled can be calculated according to formula (2). .

[0058] (2)

[0059] When making the first selection of a quantum gate node in a node to be scheduled, if the number of quantum gates in a single-bit gate node is greater, the chance of merging with the next node is considered to be greater. At the same time, it is necessary to give the possibility of selecting a two-bit gate node in order to seek the global optimal solution. Therefore, formulas (1) and (2) are used to calculate the probability of each quantum gate node in the scheduling node being selected.

[0060] As can be seen, during the initial selection of quantum gate nodes in the node to be scheduled, this embodiment of the application can determine the probability of each single-bit gate node in the node to be scheduled being selected relatively accurately by comprehensively considering the number of quantum gates contained in each single-bit gate node in the node to be scheduled, and the sum of the number of quantum gates contained in the single-bit gate nodes in the node to be scheduled. During the initial selection of quantum gate nodes in the node to be scheduled, this embodiment of the application can determine the probability of each two-bit gate node in the node to be scheduled being selected relatively accurately based on the number of two-bit gate nodes in the node to be scheduled.

[0061] In some embodiments, in order to determine the probability of selecting a quantum gate node among the nodes to be scheduled, in response to the fact that the last selected quantum gate node among the nodes to be scheduled was a two-bit gate node, the quantum gate node is selected among the nodes to be scheduled based on a third probability of selecting each two-bit gate node among the nodes to be scheduled and a fourth probability of selecting each single-bit gate node among the nodes to be scheduled; wherein the third probability is determined based on the number of two-bit gate nodes among the nodes to be scheduled, and the fourth probability is determined based on the number of quantum gates contained in each single-bit gate node among the nodes to be scheduled and the sum of the number of quantum gates contained in each single-bit gate node among the nodes to be scheduled.

[0062] Here, the probability of each two-bit gate node being selected in the nodes to be scheduled is negatively correlated with the number of two-bit gate nodes in the nodes to be scheduled.

[0063] For example, the first quantum gate node is performed in the node to be scheduled. The second choice, and When the value is greater than 1, the probability of each two-bit gate node being selected among the nodes to be scheduled can be calculated according to formula (3). .

[0064] (3)

[0065] The probability of each single-bit gate node being selected in the nodes to be scheduled is positively correlated with the number of quantum gates contained in the corresponding single-bit gate node, and negatively correlated with the sum of the number of quantum gates contained in all the single-bit gate nodes in the nodes to be scheduled.

[0066] For example, the first quantum gate node is performed in the node to be scheduled. The second choice, and When the value is greater than 1, the first node to be scheduled can be calculated according to formula (4). The probability of a single-bit gate node being selected .

[0067] (4)

[0068] If the last selected quantum gate node in the node to be scheduled is a two-bit gate node, the two-bit gate node can be merged with the previous node for execution. However, in order to seek the global optimal solution, it is necessary to give the possibility of selecting a single-bit gate node. Therefore, formulas (3) and (4) can be used to calculate the probability of each quantum gate node in the scheduling node being selected.

[0069] As can be seen, when the last selected quantum gate node among the nodes to be scheduled was a two-qubit gate node, this embodiment of the application can determine the probability of each single-qubit gate node being selected in the node to be scheduled relatively accurately by comprehensively considering the number of quantum gates contained in each single-qubit gate node in the node to be scheduled, and the sum of the number of quantum gates contained in the single-qubit gate nodes in the node to be scheduled. When the last selected quantum gate node among the nodes to be scheduled was a two-qubit gate node, this embodiment of the application can determine the probability of each two-qubit gate node being selected in the node to be scheduled relatively accurately by considering the number of two-qubit gate nodes in the node to be scheduled.

[0070] In some embodiments, when determining the probability of a quantum gate node being selected from the nodes to be scheduled, if the previously selected quantum gate node in the nodes to be scheduled is a single-bit gate node, in response to the existence of at least one candidate single-bit gate node in the nodes to be scheduled, the node containing the most quantum gates among the at least one candidate single-bit gate node is determined as the node to be selected this time; in response to the existence of no candidate single-bit gate node in the nodes to be scheduled, the fifth probability of selecting the quantum gate node this time is determined according to the method used to determine the probability of node selection when the quantum gate node in the nodes to be scheduled was first selected, and the quantum gate node is selected from the nodes to be scheduled according to the fifth probability; wherein, the candidate single-bit gate node and the previously selected single-bit gate node have multiple consecutive quantum gates in the same order.

[0071] In this embodiment of the application, if there are multiple consecutive quantum gates in the single-bit gate node of the node to be scheduled that have the same order as the single-bit gate node selected in the previous one, then the corresponding single-bit gate node is determined as a candidate single-bit gate node. The number of candidate single-bit gate nodes in the node to be scheduled can be one or more.

[0072] The following is combined with Figure 3 Several scenarios for candidate single-bit gate nodes are illustrated by examples, refer to Figure 3Node s0 represents the previously selected single-bit gate node, node s1 represents a single-bit gate node among the currently scheduled nodes, H, X, Y, and Z represent different quantum gates, Q0 and Q1 represent two different qubits, H Q0, X Q0, Y Q0, and Z Q0 represent applying quantum gates H, X, Y, and Z to Q0 respectively; H Q1, X Q1, Y Q1, and Z Q1 represent applying quantum gates H, X, Y, and Z to Q1 respectively. Figure 3 It can be seen that, for case one, there are four consecutive quantum gates X, H, Y and Z with the same order in nodes s0 and s1; for case two, there are four consecutive quantum gates H, Y, Z and H with the same order in nodes s0 and s1; and for case three, there are three consecutive quantum gates Y, Z and H with the same order in nodes s0 and s1.

[0073] For example, if the last selected quantum gate node in the node to be scheduled is a single-bit gate node, and there is no candidate single-bit gate node in the node to be scheduled, then the probability of selecting a quantum gate node in the current node to be scheduled can be determined by formulas (1) and (2).

[0074] As can be seen, when the last selected quantum gate node among the nodes to be scheduled was a single-bit gate node, if there is no candidate single-bit gate node among the nodes to be scheduled, the embodiments of this application can determine the probability of selecting a quantum gate node this time in a more accurate manner, in accordance with the method of determining the probability of a node being selected when selecting a quantum gate node among the nodes to be scheduled for the first time.

[0075] In this embodiment, in response to the fact that the last selected quantum gate node among the nodes to be scheduled was a single-bit gate node, and there is at least one candidate single-bit gate node among the nodes to be scheduled, the node containing the most quantum gates among the at least one candidate single-bit gate node can be determined as the node to be selected this time. This is beneficial to prioritize the execution of quantum gate operations on nodes containing more quantum gates, thereby improving the execution efficiency of quantum circuits.

[0076] In this embodiment of the application, a strategy combining the Kahn algorithm and a heuristic search algorithm can be used to schedule and sort the nodes in the DAG. The following describes the node scheduling scheme using the Kahn algorithm and the heuristic search algorithm in conjunction with the accompanying drawings.

[0077] Reference Figure 4 The process for obtaining scheduling results may include:

[0078] Step 401: Determine the top-level quantum gate nodes in the DAG.

[0079] Here, the top-level quantum gate node represents a quantum gate node with an in-degree of 0.

[0080] Step 402: Assign a probability to each node in the top-level quantum gate nodes.

[0081] The implementation of step 402 has been described in the foregoing. In this embodiment, by executing step 402, quantum gate nodes that may be merged and executed can be selected heuristically.

[0082] Step 403: Heuristically select quantum gate nodes.

[0083] Step 404: Add the selected node to the scheduling results and remove the selected node from the top level.

[0084] Step 405: Recalculate the in-degree of the nodes in the DAG and update the top-level quantum gate nodes.

[0085] Step 406: Determine if the top-level quantum gate node is empty. If it is, proceed to step 407; otherwise, return to step 402.

[0086] Here, if the number of top-level quantum gate nodes is 0, then proceed to step 407; if the number of top-level quantum gate nodes is greater than 0, then return to step 402.

[0087] Step 407: Output the scheduling results.

[0088] When the number of quantum gate nodes at the top level is 0, it means that the scheduling of quantum gate nodes in the quantum circuit has been completed.

[0089] To obtain more accurate scheduling results, in some embodiments, steps 401 to 407 can be repeated m times to obtain m sets of scheduling results, where m is an integer greater than 1. Then, the m sets of scheduling results can be evaluated to obtain evaluation results, and the optimal scheduling result can be selected from the m sets of results based on the evaluation results.

[0090] In summary, in this embodiment of the application, the selection of quantum gate nodes in the DAG can be guided by a strategy that combines the Kahn algorithm and heuristic search. This can avoid the scheduling result from getting stuck in a local optimum to a certain extent, and a probabilistic approach can be used to heuristically select quantum gate nodes that can be merged and executed.

[0091] To optimize the scheduling results, after obtaining the scheduling results, if the adjacent nodes in the scheduling results are all single-bit gate nodes and there are multiple consecutive quantum gates with the same order in the adjacent nodes, the execution strategy of the quantum gates of the adjacent nodes can be determined as: the strategy of merging and executing the quantum gates with the same order in the adjacent nodes; if the adjacent nodes in the scheduling results are all two-bit gate nodes, the execution strategy of the quantum gates of the adjacent nodes can be determined as: the strategy of merging and executing the adjacent nodes.

[0092] Here, when all adjacent nodes in the scheduling result are single-bit gate nodes and there are multiple consecutive quantum gates with the same order in the adjacent nodes, the execution strategy of the quantum gates of the adjacent nodes can be determined as follows, provided that the execution order of the quantum gates in each single-bit gate node of the adjacent nodes is satisfied: the strategy of merging and executing the same quantum gates of the adjacent nodes.

[0093] For example, the four consecutive nodes in the scheduling result are node_s0, node_s1, node_m0, and node_m1, where node_m0 and node_m1 are different two-bit gate nodes. The quantum gates in node_s0, arranged in execution order, are HQ0, XQ0, and HQ0; the quantum gates in node_s1, arranged in execution order, are XQ1 and HQ1. When the two bits in node_m0 are Q0 and Q1, node_m0 can be represented as CX Q0Q1; when the two bits in node_m1 are Q2 and Q3, node_m1 can be represented as CX Q2Q3.

[0094] After optimizing the execution order of the quantum gates for node_s0, node_s1, node_m0, and node_m1, the following execution order can be obtained:

[0095] 1) H Q0

[0096] 2) X Q0; X Q1

[0097] 3) H Q0; H Q1

[0098] 4) CX Q0Q1; CX Q2Q3.

[0099] As can be seen, the embodiments of this application propose a merged execution strategy to optimize and parse the node scheduling results. Without generating additional mov operations, it can maximize the merging of the same quantum gate operations. Compared with the scheme that does not optimize the scheduling results, it can reduce the number of mov operations that need to be executed for the scheduling results, and effectively ensure the overall fidelity of the quantum circuit execution scheme.

[0100] As can be seen from the foregoing description, the technical solution of this application embodiment can effectively optimize the execution efficiency of quantum circuits. By proposing a strategy that combines the Kahn algorithm and heuristic search to guide the selection of quantum gate nodes that can be merged and executed, and by maximizing the merging of identical quantum gate operations through the merging execution strategy, the execution order of quantum gates is rationally scheduled, which greatly reduces the number of quantum gate operations and the number of required mov operations, and effectively improves the reliability and efficiency of quantum circuit execution.

[0101] Figure 5This is a flowchart of a quantum bit mapping and quantum gate scheduling method in an embodiment of this application, as shown below. Figure 5 As shown, the process includes:

[0102] Step 501: Map logical qubits to physical qubits.

[0103] Step 502: Generate a DAG based on the quantum gate dependencies in the quantum circuit.

[0104] Step 503: Heuristically select quantum gate nodes in the DAG to obtain the scheduling result.

[0105] Step 504: Determine the merging execution strategy for adjacent nodes.

[0106] The implementation methods of steps 501 to 504 have been explained in the aforementioned content and will not be repeated here.

[0107] Step 505: Add mov and shift-back (bac) operations according to the execution order of the quantum gates.

[0108] In this embodiment, before performing a quantum gate operation, it is necessary to check whether there are any qubits in the control region that are unrelated to the quantum gate to be operated on. If so, a bac operation is added to move them back to the storage region. The mov operation is performed to move the qubits corresponding to the quantum gate to an empty position in the control region. If it is a two-qubit gate, it is necessary to ensure that the corresponding qubits are in adjacent positions in the control region.

[0109] An exemplary quantum gate execution sequence is: H Q0, X Q1, and CX Q0Q1. For this quantum gate execution sequence, step 505 can be executed. For this quantum gate execution sequence, the operations to be performed in the order of execution are: movQ0, execute quantum gate H on Q0, bacQ0, movQ1, execute quantum gate X on Q1, movQ0, and execute quantum gate operation on the two-bit gate node containing Q0 and Q1.

[0110] Step 506: Evaluate the scheduling results using the number of mov operands and the optimized number of quantum gates as indicators.

[0111] Here, the number of mov operations added in step 505 and the number of optimized quantum gates in step 504 can be used as evaluation metrics. In practical applications, the above m sets of scheduling results can be evaluated based on these evaluation metrics.

[0112] Step 507: Select the optimal solution from multiple scheduling results using a non-dominated sorting algorithm.

[0113] Here, based on the evaluation results of the m groups of scheduling results, a non-dominated sort can be performed on the m groups of scheduling results. For example, the optimal solution for the m groups of scheduling results can be determined from the Pareto front with the mov operand as the first priority. Of course, in other embodiments, other optimization algorithms can also be used to determine the optimal solution for the m groups of scheduling results.

[0114] In summary, to achieve the measurement and control of RAA quantum processors, this application proposes a method for qubit mapping and quantum gate scheduling of reconfigurable neutral atom arrays. This application provides a solution for the execution of quantum circuits in RAA quantum processors, effectively improving the efficiency and fidelity of quantum circuit execution, and has high practical value. The technical solution of this application can be used to realize the measurement and control of RAA quantum processors, and the hardware conditions for RAA quantum processors are already available; therefore, obtaining the measurement and control information of the quantum processor is relatively easy.

[0115] Those skilled in the art will understand that, in the above-described method of the specific implementation, the order in which each step is written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.

[0116] Figure 6 This is a schematic diagram of the structure of the quantum gate scheduling device according to an embodiment of this application, as shown below. Figure 6 As shown, the device includes:

[0117] The first processing module 601 is used to generate a DAG based on the quantum gate dependencies in the quantum circuit, wherein the nodes of the DAG are quantum gate nodes;

[0118] The second processing module 602 is used to heuristically select quantum gate nodes in the DAG based on the probability of a node being selected, and obtain a scheduling result, wherein the scheduling result includes quantum gate nodes arranged in the selection order.

[0119] In some embodiments, the second processing module 602 is specifically used to determine the quantum gate nodes with an in-degree of 0 in the DAG as nodes to be scheduled; and to heuristically select quantum gate nodes among the nodes to be scheduled based on the probability of each node being selected, thereby obtaining a scheduling result.

[0120] In some embodiments, the second processing module 602 is further configured to add the selected quantum gate node to the scheduling result each time the quantum gate node is selected in the nodes to be scheduled, delete the selected quantum gate node from the quantum gate nodes with an in-degree of 0, redetermine the nodes to be scheduled, and repeat the step of selecting the quantum gate node in the nodes to be scheduled until the number of nodes in the nodes to be scheduled is 0.

[0121] In some embodiments, the first processing module 601 is further configured to, after generating a DAG based on the dependencies of quantum gates in the quantum circuit, select the quantum gate node in the scheduled node during the initial selection of the quantum gate node in the scheduled node based on a first probability of each single-bit gate node being selected and a second probability of each two-bit gate node being selected in the scheduled node; wherein the first probability is determined based on the number of quantum gates contained in each single-bit gate node in the scheduled node and the sum of the number of quantum gates contained in each single-bit gate node in the scheduled node, and the second probability is determined based on the number of two-bit gate nodes in the scheduled node.

[0122] In some embodiments, the first processing module 601 is further configured to, after generating a DAG based on the quantum gate dependencies in the quantum circuit, select the quantum gate node in the scheduling node according to a third probability of selecting each two-bit gate node in the scheduling node and a fourth probability of selecting each single-bit gate node in the scheduling node, if the previously selected quantum gate node in the scheduling node is a two-bit gate node; wherein the third probability is determined based on the number of two-bit gate nodes in the scheduling node, and the fourth probability is determined based on the number of quantum gates contained in each single-bit gate node in the scheduling node and the sum of the number of quantum gates contained in each single-bit gate node in the scheduling node.

[0123] In some embodiments, the first processing module 601 is further configured to, after generating a DAG based on the quantum gate dependencies in the quantum circuit, if the previously selected quantum gate node among the nodes to be scheduled is a single-bit gate node, in response to the existence of at least one candidate single-bit gate node among the nodes to be scheduled, determine the node containing the most quantum gates among the at least one candidate single-bit gate node as the node to be selected this time; in response to the existence of no candidate single-bit gate node among the nodes to be scheduled, determine a fifth probability for selecting the quantum gate node this time in the same manner as determining the probability of a node being selected when the quantum gate node among the nodes to be scheduled is first selected, and select the quantum gate node among the nodes to be scheduled according to the fifth probability; wherein, the candidate single-bit gate node and the previously selected single-bit gate node have multiple consecutive quantum gates in the same order.

[0124] In some embodiments, the second processing module 602 is further configured to, after obtaining the scheduling result, determine the execution strategy of the quantum gates of the adjacent nodes as follows: when the adjacent nodes in the scheduling result are all single-bit gate nodes and the adjacent nodes have multiple consecutive quantum gates with the same order; and when the adjacent nodes in the scheduling result are all two-bit gate nodes, determine the execution strategy of the quantum gates of the adjacent nodes as follows: when the adjacent nodes are all two-bit gate nodes.

[0125] In some embodiments, the first processing module 601 is further configured to, before generating a DAG based on the quantum gate dependencies in the quantum circuit, sort the logical qubits in descending order of the number of quantum gates applied to each logical qubit in the quantum circuit; and, based on the sorting result of the logical qubits, map each logical qubit sequentially onto a plurality of physical qubits arranged in descending order of fidelity.

[0126] In some embodiments, the quantum gate nodes in the DAG include single-bit gate nodes, which include multiple consecutive single-bit gates acting on the same quantum bit.

[0127] In practical applications, the first processing module 601 and the second processing module 602 can be implemented based on a processor.

[0128] It should be noted that the description of the above device embodiments is similar to the description of the above method embodiments, and has similar beneficial effects. For technical details not disclosed in the device embodiments of this application, please refer to the description of the method embodiments of this application for understanding.

[0129] It should be noted that, in the embodiments of this application, if the above-described methods are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiments of this application, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a terminal, server, etc.) to execute all or part of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), magnetic disks, or optical disks. Thus, the embodiments of this application are not limited to any specific hardware and software combination.

[0130] Correspondingly, this application embodiment further provides a computer program product, the computer program product including computer executable instructions, which are used to implement any of the quantum gate scheduling methods provided in this application embodiment.

[0131] Accordingly, this application embodiment further provides a computer storage medium storing computer-executable instructions, which are used to implement any of the quantum gate scheduling methods provided in the above embodiments.

[0132] This application also provides an electronic device. Figure 7 This is a schematic diagram of the composition structure of an electronic device provided in an embodiment of this application, as shown below. Figure 7 As shown, the electronic device 70 may include:

[0133] Memory 701 is used to store executable instructions;

[0134] The processor 702 is used to implement any of the above-described quantum gate scheduling methods when executing executable instructions stored in the memory 701.

[0135] The processor 702 mentioned above can be at least one of ASIC, DSP, DSPD, PLD, FPGA, CPU, controller, microcontroller, and microprocessor.

[0136] The aforementioned computer-readable storage medium and memory 701 may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic random access memory (FRAM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM), etc.; it may also be various terminals that include one or any combination of the above-mentioned memories, such as mobile phones, computers, tablet devices, personal digital assistants, etc.

[0137] In some embodiments, the functions or modules of the apparatus provided in this application can be used to perform the methods described in the above method embodiments. The specific implementation can be referred to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0138] The description of the various embodiments above tends to emphasize the differences between the various embodiments. The similarities or similarities between them can be referred to, and for the sake of brevity, they will not be repeated here.

[0139] The methods disclosed in the various method embodiments provided in this application can be arbitrarily combined to obtain new method embodiments without conflict.

[0140] The features disclosed in the various product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0141] The features disclosed in the various method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0142] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0143] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the scope of protection of this application. All of these forms are within the protection scope of this application.

Claims

1. A quantum gate scheduling method, characterized in that, The method includes: A directed acyclic graph (DAG) is generated based on the quantum gate dependencies in the quantum circuit of a reconfigurable atom array (RAAs) quantum processor. The nodes of the DAG are quantum gate nodes. The quantum gate nodes are either single-bit gate nodes built based on single-bit gates or two-bit gate nodes built based on two-bit gates. The quantum gate nodes with an in-degree of 0 in the DAG are identified as nodes to be scheduled. Based on the probability of each node being selected among the nodes to be scheduled, quantum gate nodes are heuristically selected among the nodes to be scheduled to obtain a scheduling result, which includes quantum gate nodes arranged in the order of selection. Specifically, during the initial selection of the quantum gate node in the node to be scheduled, or when the previously selected quantum gate node in the node to be scheduled was a two-bit gate node, the probability of selecting each single-bit gate node in the node to be scheduled is positively correlated with the number of quantum gates contained in the corresponding single-bit gate node and negatively correlated with the sum of the number of quantum gates contained in all single-bit gate nodes in the node to be scheduled; the probability of selecting each two-bit gate node in the node to be scheduled is negatively correlated with the number of two-bit gate nodes in the node to be scheduled; when the previously selected quantum gate node in the node to be scheduled was a single-bit gate node and there are no candidate single-bit gate nodes in the node to be scheduled, the probability of selecting the quantum gate node this time is determined in the same way as when the node was first selected in the node to be scheduled.

2. The quantum gate scheduling method according to claim 1, characterized in that, After each selection of the quantum gate node from the nodes to be scheduled, the method further includes: The selected quantum gate node is added to the scheduling result, and the selected quantum gate node is deleted from the quantum gate nodes with an in-degree of 0. The nodes to be scheduled are re-determined, and the step of selecting a quantum gate node in the nodes to be scheduled is repeated until the number of nodes in the nodes to be scheduled is 0.

3. The quantum gate scheduling method according to claim 2, characterized in that, After generating a DAG based on the dependencies of quantum gates in a quantum circuit, the method further includes the following during the initial selection of the quantum gate node in the node to be scheduled: The quantum gate node is selected from the nodes to be scheduled based on a first probability of selecting each single-bit gate node and a second probability of selecting each two-bit gate node; wherein the first probability is determined based on the number of quantum gates contained in each single-bit gate node and the sum of the number of quantum gates contained in each single-bit gate node in the nodes to be scheduled, and the second probability is determined based on the number of two-bit gate nodes in the nodes to be scheduled.

4. The quantum gate scheduling method according to claim 2, characterized in that, After generating a DAG based on the quantum gate dependencies in the quantum circuit, if the previously selected quantum gate node among the nodes to be scheduled is a two-qubit gate node, the method further includes: The quantum gate node is selected from the nodes to be scheduled based on a third probability of selecting each two-bit gate node and a fourth probability of selecting each single-bit gate node. The third probability is determined based on the number of two-bit gate nodes in the nodes to be scheduled, and the fourth probability is determined based on the number of quantum gates contained in each single-bit gate node in the nodes to be scheduled and the sum of the number of quantum gates contained in each single-bit gate node in the nodes to be scheduled.

5. The quantum gate scheduling method according to claim 2, characterized in that, After generating a DAG based on the quantum gate dependencies in the quantum circuit, if the previously selected quantum gate node among the nodes to be scheduled is a single-bit gate node, the method further includes: In response to the existence of at least one candidate single-bit gate node among the nodes to be scheduled, the node containing the most quantum gates among the at least one candidate single-bit gate node is determined as the node to be selected this time; in response to the existence of no candidate single-bit gate node among the nodes to be scheduled, the fifth probability of selecting the quantum gate node this time is determined according to the method of determining the probability of node selection when the quantum gate node among the nodes to be scheduled is selected for the first time, and the quantum gate node is selected among the nodes to be scheduled according to the fifth probability; wherein, the candidate single-bit gate node has multiple consecutive quantum gates in the same order as the single-bit gate node selected in the previous time.

6. The quantum gate scheduling method according to claim 1, characterized in that, After obtaining the scheduling result, the method further includes: when the adjacent nodes in the scheduling result are all single-bit gate nodes, and the adjacent nodes have multiple consecutive quantum gates with the same order, the execution strategy of the quantum gates of the adjacent nodes is determined as: the strategy of merging and executing the same quantum gates in the adjacent nodes; When all adjacent nodes in the scheduling result are two-bit gate nodes, the execution strategy of the quantum gates of the adjacent nodes is determined as: the strategy of merging the execution of the adjacent nodes.

7. The quantum gate scheduling method according to claim 1, characterized in that, Before generating a DAG based on the quantum gate dependencies in the quantum circuit, the method further includes: The logical qubits are sorted in descending order of the number of quantum gates applied to each logical qubit in the quantum circuit. Based on the sorting results of the logical qubits, the logical qubits are sequentially mapped to multiple physical qubits arranged in descending order of fidelity.

8. The quantum gate scheduling method according to claim 1, characterized in that, The quantum gate nodes in the DAG include single-bit gate nodes, which consist of multiple consecutive single-bit gates acting on the same quantum bit.

9. A quantum gate scheduling device, characterized in that, The device includes: The first processing module is used to generate a directed acyclic graph (DAG) based on the quantum gate dependencies in the quantum circuit of the reconfigurable atom array (RAAs) quantum processor, wherein the nodes of the DAG are quantum gate nodes; the quantum gate nodes are either single-bit gate nodes built based on single-bit gates or two-bit gate nodes built based on two-bit gates. The second processing module is used to determine the quantum gate nodes with an in-degree of 0 in the DAG as nodes to be scheduled, and to heuristically select quantum gate nodes from the nodes to be scheduled based on the probability of each node being selected, so as to obtain a scheduling result. The scheduling result includes quantum gate nodes arranged in the order of selection. Specifically, during the initial selection of the quantum gate node in the node to be scheduled, or when the previously selected quantum gate node in the node to be scheduled was a two-bit gate node, the probability of selecting each single-bit gate node in the node to be scheduled is positively correlated with the number of quantum gates contained in the corresponding single-bit gate node and negatively correlated with the sum of the number of quantum gates contained in all single-bit gate nodes in the node to be scheduled; the probability of selecting each two-bit gate node in the node to be scheduled is negatively correlated with the number of two-bit gate nodes in the node to be scheduled; when the previously selected quantum gate node in the node to be scheduled was a single-bit gate node and there are no candidate single-bit gate nodes in the node to be scheduled, the probability of selecting the quantum gate node this time is determined in the same way as when the node was first selected in the node to be scheduled.

10. An electronic device, characterized in that, The electronic device includes a processor and a memory for storing computer programs capable of running on the processor; wherein, The processor is used to run the computer program to perform the quantum gate scheduling method according to any one of claims 1 to 8.

11. A computer storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the quantum gate scheduling method according to any one of claims 1 to 8.

12. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the quantum gate scheduling method according to any one of claims 1 to 8.

Images