Cleaning method and preparation method of groove type semiconductor device

Abstract

The invention relates to the technical field of semiconductors, particularly provides a cleaning method and a preparation method of a groove type semiconductor device, and aims to optimize an existing cleaning process so as to improve the qualified rate of products. In order to achieve the purpose, the cleaning method of the groove type semiconductor device comprises the steps that an etched wafer is cleaned through a DHF solution, an SPM solution, an SC1 solution and a BOE solution so as to remove pollutants on the surface of the wafer; wherein a groove structure is formed in the wafer, the pollutants comprise etching products generated in the process of etching to form the groove structure, and the BOE solution is cleaned after the DHF solution is cleaned or after the SC1 solution is cleaned in sequence. According to the cleaning method, the BOE solution cleaning step is introduced on the basis of the conventional cleaning process, the etching product can be effectively removed, especially the etching product in the wave-shaped groove can be effectively removed, and the qualified rate of the groove type semiconductor device is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a cleaning method and a preparation method for a trench-type semiconductor device. Background Art

[0002] Currently, in the field of semiconductor technology, in order to ensure a more uniform electric field in trench-type semiconductor devices, such as trench MOS barrier Schottky diodes (TMBS), a commonly used solution is to etch the peripheral terminal trench into a wavy shape to ensure that the distance between the terminal trench and the cellular trench structure is equal. Specifically, the cross-section of the cellular trench is circular, and the side of the terminal trench close to the cellular trench is composed of multiple arc-shaped sidewalls with the same radius. Some of the outermost cellular trenches are located at the center of the circle where the arc-shaped sidewalls are located. The distance between the center of the cross-section of the remaining outermost cellular trenches and the adjacent arc-shaped sidewalls is equal to the radius of the circle where the arc-shaped sidewalls are located. Through this structural design, leakage uniformity is improved.

[0003] However, during the processing of semiconductor devices with the above structure, after the trench etching is completed, if a conventional cleaning process is used, etching products will remain in the terminal trench of the semiconductor device, resulting in abnormal product parameters, and thus the product qualification rate does not meet expectations.

[0004] Therefore, how to optimize the existing cleaning process, especially optimizing the cleaning process for the above-mentioned wavy grooves, in order to improve the qualified rate of products, is a technical problem that needs to be solved urgently. Summary of the Invention

[0005] In order to overcome the above-mentioned defects, the present application is proposed to provide a solution or at least partially solve the technical problem that the existing cleaning process for trench-type semiconductor devices is difficult to completely clean and remove etching products in the wavy grooves.

[0006] In a first aspect, the present application provides a method for cleaning a trench-type semiconductor device, comprising the following steps:

[0007] The etched wafer is cleaned with DHF solution, SPM solution, SC1 solution and BOE solution respectively to remove contaminants on the wafer surface; wherein a trench structure is formed in the wafer, and the contaminants include etching products generated during the process of etching to form the trench structure; the cleaning order of BOE solution is after DHF solution cleaning or after SC1 solution cleaning.

[0008] In one technical solution of the above-mentioned method for cleaning trench-type semiconductor devices, the following steps are included:

[0009] The wafer is cleaned in sequence using DHF solution, SPM solution, SC1 solution and BOE solution, and then in sequence using SPM solution and SC1 solution.

[0010] In one technical solution of the above-mentioned method for cleaning trench-type semiconductor devices, the following steps are included:

[0011] The wafer is cleaned in sequence using DHF solution, BOE solution, SPM solution and SC1 solution.

[0012] In one technical solution of the above-mentioned trench type semiconductor device cleaning method,

[0013] The DHF solution is prepared by mixing hydrofluoric acid and water in a volume ratio of 1:(30-110). When the DHF solution is used to clean the etched wafer, the cleaning time is controlled to be 60 to 120 seconds and the cleaning temperature is controlled to be 22 to 25°C.

[0014] The SPM solution is prepared by mixing sulfuric acid and hydrogen peroxide in a volume ratio of (3-6):1, wherein the volume fraction of sulfuric acid is 98% and the volume fraction of hydrogen peroxide is 30%. During the cleaning of the etched wafer using the SPM solution, the cleaning temperature is controlled to be 110 to 130° C., and the cleaning time is controlled to be more than 600 seconds.

[0015] The SC1 solution is prepared by mixing ammonia water, hydrogen peroxide and water in a volume ratio of 1:(1-2):(25-50). When the etched wafer is cleaned using the SC1 solution, the cleaning temperature is controlled to be 60 to 70° C. and the cleaning time is controlled to be more than 300 seconds.

[0016] In the BOE solution, the mass concentration of HF is 6-7%, and the mass concentration of NH4F is 30-45%. When using the BOE solution to clean the etched wafer, the cleaning temperature is controlled at 20 to 25°C and the cleaning time is 150 to 160 seconds.

[0017] In one technical solution of the above-mentioned method for cleaning trench-type semiconductor devices, during the process of using BOE solution to clean the etched wafer, the flow rate of the BOE solution is controlled to be 15 L / min to 25 L / min.

[0018] In one technical solution of the above-mentioned method for cleaning trench-type semiconductor devices, a surfactant is further added to the BOE solution.

[0019] In one technical solution of the above-mentioned trench semiconductor device cleaning method, the surface tension of the BOE solution to which the surfactant is added is 20 to 40 dyne / cm.

[0020] In one technical solution of the above-mentioned trench semiconductor device cleaning method, after each time the wafer is cleaned with DHF solution, SPM solution, SC1 solution or BOE solution, the wafer is cleaned with deionized water.

[0021] In one technical solution of the above-mentioned method for cleaning trench-type semiconductor devices, after the wafer is cleaned with SC1 solution, the wafer is dried.

[0022] In one technical solution of the above-mentioned method for cleaning a trench-type semiconductor device, the trench structure includes a wavy trench.

[0023] In a second aspect, the present application provides a method for preparing a trench semiconductor device, comprising:

[0024] forming a hard mask layer on the surface of the wafer, wherein the hard mask layer exposes the surface of the wafer where the trench structure is to be formed;

[0025] Etching the wafer along the thickness direction of the wafer to form a groove structure; the groove structure includes a wavy groove;

[0026] Cleaning the wafer using the cleaning method described in any one of the technical solutions for cleaning the trench-type semiconductor device, and removing the hard mask layer during the cleaning process;

[0027] A gate dielectric layer and a gate are selectively formed in a portion of the trench structure.

[0028] The above one or more technical solutions of this application have at least one or more of the following beneficial effects:

[0029] The cleaning method of the trench-type semiconductor device provided in the present application introduces a BOE solution cleaning step on the basis of the conventional cleaning process, which can effectively remove etching products, especially effectively remove etching products in the wavy grooves, and improve the qualification rate of the trench-type semiconductor devices.

[0030] On this basis, by adding surfactants to the BOE solution, the surface tension of the BOE solution can be reduced, the wetting effect can be improved, and the BOE solution can be promoted to enter the groove structure smoothly and evenly, which is more conducive to the complete removal of etching products.

[0031] Moreover, precisely because BOE solution is used for cleaning, the silicon dioxide hard mask can be removed simultaneously during the cleaning process, saving a step of removing the hard mask, thereby shortening the process, improving production efficiency, and reducing processing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The disclosure of this application will become more easily understood with reference to the accompanying drawings. Those skilled in the art will readily appreciate that these drawings are for illustrative purposes only and are not intended to limit the scope of protection of this application. Among them:

[0033] Figure 1 This is the MAP image of two wafers after the conventional cleaning process;

[0034] Figure 2 This is the SEM photo of the die with abnormal parameters;

[0035] Figure 3 1 is a flow chart of the main steps of a method for cleaning a trench-type semiconductor device according to the first embodiment of the present application;

[0036] Figure 4 This is a MAP image of two wafers obtained using the cleaning method for trench semiconductor devices provided in Example 1 of the present application;

[0037] Figure 5 This is a SEM image of a tube die obtained using the cleaning method for a trench-type semiconductor device provided in Example 1 of the present application;

[0038] Figure 6 is an EDS spectrum diagram of the terminal trench sidewall detection area according to one embodiment of the present application;

[0039] Figure 7 1 is a flow chart of the main steps of a method for cleaning a trench-type semiconductor device according to the second embodiment of the present application;

[0040] Figure 8 It is a schematic diagram of the main process of a method for preparing a trench semiconductor device according to an embodiment of the present application. DETAILED DESCRIPTION

[0041] To make the above-mentioned objects, features, and advantages of the present application more clearly understood, the specific embodiments of the present application are described in detail below with reference to the accompanying drawings. The following description sets forth many specific details to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways than those described herein, and those skilled in the art can make similar improvements without violating the scope of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0042] As described in the background technology, in order to ensure that the electric field of trench-type semiconductor devices such as TMBS is more uniform, the commonly used solution is to etch the peripheral terminal groove into a wave shape to ensure that the distance between the terminal groove and the cellular groove structure is equal. Specifically, the groove structure includes a terminal groove and a cellular groove, wherein the terminal groove is located at the edge of the device, the cellular groove is surrounded by the terminal groove, and the cellular groove is arranged in an array, such as an equilateral triangle array. The cross section of the cellular groove is circular, and the side of the terminal groove close to the cellular groove is composed of multiple arc-shaped sidewalls with the same radius, forming a wavy structure, and some of the outermost cellular grooves are located at the center of the circle where the arc-shaped sidewall is located, and the distance between the cross-section center of the remaining outermost cellular grooves and the adjacent arc-shaped sidewall is equal to the radius of the circle where the arc-shaped sidewall is located. Through such a structural design, the electric field distribution at the edge of the device can be optimized, thereby improving the withstand voltage of the device while also improving the leakage uniformity.

[0043] However, in the process of manufacturing the semiconductor device with the above structure, after the trench etching is completed, if a conventional cleaning process is used, etching products will remain in the terminal trench of the semiconductor device. Figure 1 This is the MAP of two wafers after the conventional cleaning process, in which the die with abnormal parameters are shown in darker small squares. Figure 1 As shown, using conventional cleaning processes, there are a large number of dies with abnormal parameters in the two wafers, making it difficult to meet product inspection standards.

[0044] Figure 2 This is a SEM photo of a die with abnormal parameters. Figure 2 As shown, under SEM observation, the terminal groove of the die with abnormal parameters has etching products remaining (see Figure 2 As shown in the white dotted ellipse in the middle, a properly cleaned groove should be black rather than grayish white). In particular, the terminal groove closest to the cell groove is more likely to have etching products remaining, which is why this phenomenon is judged to be the cause of abnormal product parameters.

[0045] To address this issue, whether optimizing the etching process or, based on conventional cleaning processes, extending the cleaning time, adjusting the cleaning temperature, or adjusting the concentration of the cleaning solution, it remains difficult to completely remove the residual etching products. Therefore, optimizing existing cleaning processes, particularly for the aforementioned wavy grooves, to improve product yields remains a pressing technical challenge.

[0046] According to the inventors' analysis, in the process of processing groove-type semiconductor devices, especially those with wavy grooves as described above, the reasons why the conventional cleaning process fails to achieve the expected effect after etching the wafer may include the following aspects:

[0047] (1) Compared with traditional grooves with relatively smooth surfaces, the specific surface area of ​​the wavy terminal groove is larger. During the etching process, more etching products (by-products) will remain, especially at the corners of the terminal groove (i.e., the junction of adjacent arc-shaped side walls), where by-products are more likely to accumulate. As a result, it is difficult to completely remove the above-mentioned etching products using traditional cleaning processes. Even if measures such as extending the cleaning time in some steps are adopted, it is still difficult to completely remove the etching products, and it may affect the normal graphics;

[0048] (2) Since the terminal groove is wavy, the flow of the cleaning liquid used in the cleaning process is obstructed, and it is difficult for the cleaning liquid to fully react with the etching products attached to the side walls of the groove, and the reaction products of the two are also difficult to be discharged, resulting in the reaction not being able to proceed in the expected direction, and ultimately resulting in the cleaning effect not meeting expectations.

[0049] In order to solve the above problems, the present application provides a method for cleaning trench-type semiconductor devices, which adds a BOE solution cleaning step on the basis of the traditional cleaning process.

[0050] See attached Figure 3 , Figure 3 FIG. 1 is a flow chart of the main steps of the cleaning method of the trench semiconductor device according to the first embodiment of the present application. Figure 3 As shown, the cleaning method of the trench semiconductor device in the first embodiment mainly includes the following steps.

[0051] Step S10: Cleaning the dry-etched wafer with a DHF solution.

[0052] Before dry etching, the surface of the wafer is covered with a hard mask layer, and the hard mask layer exposes the area to be etched to form the groove. During the etching process, the wafer is etched to form grooves in the wafer, wherein the grooves include the aforementioned wavy grooves. After the etching is completed, the hard mask layer can be temporarily retained on the surface of the wafer.

[0053] DHF (Dilute Hydrofluoric Acid) solution, also known as DHF cleaning fluid, is a mixture of hydrofluoric acid and deionized water in a specific ratio. In this step, dilute hydrofluoric acid is used to clean the dry-etched wafer to remove metal impurities (such as Al, Fe, Zn, Ni, etc.), any native oxide film, and some impurity particles. It also removes metal hydroxides attached to the native oxide film. Furthermore, DHF cleaning also suppresses the formation of a native oxide film on the wafer surface.

[0054] In this embodiment, the DHF cleaning solution is prepared by mixing hydrofluoric acid and deionized water in a volume ratio of 1:(30-110). Usually, the volume ratio of the two is 1:(50-100), for example, 1:50, 1:100, etc.

[0055] In this step, the etched wafer can be immersed in the DHF inner tank for 60 to 120 seconds using the immersion method. The cleaning temperature is 22 to 25°C. The processing temperature is usually controlled at 23±0.5°C. At the same time, the DHF solution circulates between the inner tank carrying the wafer and the outer tank for auxiliary liquid storage to ensure the uniformity and efficiency of the cleaning process.

[0056] Step S20: Cleaning the dry-etched wafer with a SPM (Sulfuric-Peroxide Mixture) solution.

[0057] SPM solution, also known as SPM cleaning fluid, is obtained by mixing sulfuric acid and hydrogen peroxide in a certain proportion. It uses its oxidizing ability to oxidize organic matter into carbon dioxide and water to remove heavy organic contaminants and some metal impurities such as Cu that may exist on the wafer surface.

[0058] In this embodiment, the volume ratio of sulfuric acid to hydrogen peroxide is (3-6):1, wherein the sulfuric acid is concentrated sulfuric acid with a volume fraction of 98%, and the volume fraction of hydrogen peroxide is 30%; the cleaning temperature can be controlled at 110-130° C., and the cleaning time is preferably controlled at more than 600 seconds, generally 600-1800 seconds.

[0059] Step S30: Cleaning the dry-etched wafer with SC1 solution.

[0060] SC1 (Standard Clean 1) solution, also known as SC1 cleaning fluid, is a mixture of ammonia, hydrogen peroxide, and deionized water in a certain proportion. It removes particulate contaminants on the wafer surface through oxidation and electrostatic repulsion mechanisms.

[0061] In this embodiment, the volume ratio of ammonia water, hydrogen peroxide and deionized water is 1:(1-2):(25-50), the cleaning temperature can be controlled at 60-70°C, and the cleaning time can be controlled at more than 300 seconds, generally 300-600 seconds.

[0062] Step S40: Cleaning the dry-etched wafer with a BOE solution.

[0063] BOE (Buffered Oxide Etchant) solution, also known as BOE cleaning solution or BOE solution, is a buffered oxide etchant mainly made of a mixture of hydrofluoric acid (HF) and ammonium fluoride (NH4F). It is commonly used to remove oxide layers in semiconductor manufacturing.

[0064] In the BOE cleaning solution used in this embodiment, the mass concentration of HF is 6-7%, and the mass concentration of NH4F is 30-45%. Specifically, the mass ratio of HF to NH4F can be controlled to be 1:(5-7). In practice, it can be purchased commercially or prepared by yourself, without any particular limitation.

[0065] In this step, the wafer is cleaned with BOE cleaning solution. Specifically, the wafer can be immersed in BOE cleaning solution. The cleaning time can be controlled within 150 to 160 seconds, and the temperature can be controlled within 20 to 25° C., particularly within the range of 22.5 to 23.5° C.

[0066] Practice has shown that, in addition to the BOE cleaning solution's concentration, immersion time, and temperature, the BOE cleaning solution's circulation flow rate can also influence cleaning effectiveness. A typical flow rate is 15 to 25 L / min. Under these BOE cleaning solution composition ratios, the combined effects of the cleaning solution's temperature, cleaning time, and circulation flow rate can effectively and thoroughly remove etching products generated during dry etching to form trench structures. The inventors speculate that during this process, the BOE cleaning solution can soften or directly remove these etching products.

[0067] Step S50: Cleaning the dry-etched wafer with an SPM solution.

[0068] Step S60: Cleaning the dry-etched wafer with SC1 solution.

[0069] After the wafer is cleaned with BOE cleaning solution, BOE cleaning solution and residual contaminants on the wafer surface may remain on the wafer surface. For example, if the process gas used in etching the trench structure contains bromide such as hydrogen bromide, the residual contaminants may contain semi-reaction products of bromide and HF (such as SiFBrO). Therefore, by sequentially cleaning the wafer with SPM cleaning solution and SC1 cleaning solution, the contaminants on the wafer surface can be completely removed.

[0070] It should be noted that the composition ratio of the SPM solution used in step S50 also falls within the range specified in step S20, but the specific composition of the SPM solution used in the two steps can be the same or different. Similarly, the specific cleaning process in step S50, such as temperature and time, can also fall within the conditions specified in step S20, but the cleaning process in step S50 is not required to be exactly the same as that in step S20. Similarly, the composition ratio of the SC1 solution used in step S60 and step S30 can be the same or different, and the specific cleaning process can also be the same or different.

[0071] It should also be noted that after any of steps S10 to S60, the wafer may be rinsed with deionized water. The specific cleaning conditions can be referenced to existing general cleaning processes and will not be described in detail here. Furthermore, after rinsing the wafer with the SC1 solution, the wafer may be dried before proceeding to the subsequent steps.

[0072] Practice has shown that the above cleaning method can completely remove the products generated during the trench etching process. Figure 4 This is a MAP image of two wafers obtained using the cleaning method for trench semiconductor devices provided in Example 1 of the present application; Figure 5 This is a SEM image of a tube core obtained by using the cleaning method of a trench type semiconductor device provided in Example 1 of the present application. Figure 4 and Figure 5 As shown, the number of tube cores with abnormal parameters in the two wafers is very small and the etching products in the grooves are cleaned, meeting the quality inspection requirements, which shows that the cleaning method provided by this application can effectively remove the etching products of groove-type semiconductor devices, especially the etching products deposited in the wavy grooves.

[0073] To further investigate the mechanism by which the aforementioned cleaning method completely removes etching products within the wavy trenches, the inventors conducted EDS (Energy Dispersive X-ray Spectroscopy) analysis of the etching products. The process gas used during trench etching contained hydrogen bromide (HBr), sulfur hexafluoride (SF6), and oxygen (O2) in a volume ratio of (7.4-9.0):8:(13-14). The hard mask layer used was made of silicon dioxide.

[0074] Figure 6This is an EDS spectrum of the terminal trench sidewall inspection area according to one embodiment of the present application. The horizontal axis, Energy (keV), represents the X-ray energy, corresponding to the element's characteristic peak, while the vertical axis, Intensity (Kcounts), represents the X-ray counts, reflecting the element's concentration. Peak height is proportional to the relative concentration.

[0075] like Figure 6 As shown in the figure, oxygen (O), chlorine (Cl), potassium (K), and bromine (Br) were detected in the detection area on the sidewall of the terminal trench. It is speculated that Cl and K are impurity elements introduced in the previous process; O and Br are consistent with the process gas used for etching and are speculated to be the main components of the etching reaction products. Br includes Br-Lr, Br-Lλ, Br-Lβ, Br-Lα, Br-Kα, and Br-Kβ (the characteristic peaks corresponding to Br-Kα and Br-Kβ are very unclear, which may be the etching reaction products or the result of environmental contamination); Si should come from the silicon oxide hard mask layer; Cu-L, Cu-Kα, and Cu-Kβ have low contents and are speculated to be caused by environmental contamination, such as contamination introduced during the sample preparation process.

[0076] Combining the composition of the process gas used in the etching process and the EDS spectrum, it can be preliminarily inferred that the etching products may contain bromides (such as Si-Br-O). These etching products adhere to the inner wall of the wavy groove and are difficult to completely remove using traditional cleaning processes. However, this application adds a BOE solution cleaning step on the basis of the traditional cleaning process, which can completely remove the etching products. Preliminary inferences may be that: on the one hand, the polarity of F in the BOE solution is stronger than that of Br, and the competitive reaction makes the etching products easier to remove; on the other hand, the F in the NH4F in the BOE solution provides fluoride ions F - It can also stabilize HF activity and avoid excessive corrosion.

[0077] On this basis, the inventors have found that by changing the process gas used in the dry etching process to a fluorine-containing gas, such as a process gas whose main components are SF6, He, O2 and CH3F, and still using the cleaning method in the above-mentioned embodiment 1 to clean the wafer after dry etching, the wafer can also be completely cleaned. When observed under SEM, no etching products remain in the wavy grooves, and the inspection pass rate of the wafer can also meet the quality inspection requirements. Therefore, the relevant mechanism still needs to be further explored and improved.

[0078] Furthermore, due to the characteristics of the BOE solution, if silicon oxide is used as a hard mask layer, the BOE solution can strip the hard mask layer during the cleaning process, thereby increasing the trench opening to a certain extent and facilitating the removal of etching products. Therefore, in specific implementations, during the cleaning process, especially when the BOE solution is used to clean the wafer, the hard mask layer covering the wafer surface can be removed simultaneously, thereby eliminating the step of removing the hard mask layer, shortening the process, improving production efficiency, and reducing processing costs.

[0079] Figure 7 This is a flow chart of the main steps of the cleaning method of the trench type semiconductor device according to the second embodiment of the present application. Figure 7 As shown, the cleaning method provided in this embodiment includes: sequentially using DHF solution, BOE solution, SPM solution and SC1 solution to clean the etched wafer. That is, compared with the first embodiment, the cleaning method provided in the second embodiment omits steps S20 and S30.

[0080] The experimental results show that the cleaning method of Example 2 can also effectively remove the etching products attached to the wafer surface after etching. Compared with Example 1, Example 2 has fewer cleaning steps and higher efficiency. The product inspection yield can still meet the requirements but is slightly lower than that of Example 1.

[0081] Embodiment 3 of the present application provides a method for cleaning a trench-type semiconductor device, which is improved based on the cleaning methods of the aforementioned embodiments 1 and 2, specifically by adding a surfactant (or wetting agent) to the BOE solution.

[0082] Practice has shown that the addition of surfactants to the BOE solution can further improve the cleaning effect. This is presumably because the addition of surfactants reduces the surface tension of the BOE solution, making it easier for the BOE solution to enter the grooves smoothly and evenly, especially into the wavy grooves, thereby facilitating the complete removal of etching products.

[0083] This embodiment does not impose any particular restrictions on the type and amount of surfactant, as long as the aforementioned effects are achieved. For example, in one feasible embodiment, Triton X-100 is used as the surfactant, but this is not a limitation. The amount of surfactant added is preferably such that the surface tension of the BOE solution is within the range of 20 to 40 dyne / cm, preferably 23 to 37 dyne / cm. This does not affect the cleaning effect of the BOE cleaning solution, but also ensures that the BOE cleaning solution can enter the groove smoothly.

[0084] The experimental results show that the cleaning method of Example 3 can also completely remove the etching products attached to the wafer surface after etching, and compared with Examples 1 and 2, the cleaning step time of the BOE solution can be slightly shortened, and still achieve similar results.

[0085] The present application also provides a method for preparing a trench-type semiconductor device.

[0086] Figure 8 FIG. 1 is a schematic diagram of the main process of a method for preparing a trench semiconductor device according to an embodiment of the present application. Figure 8 As shown, the preparation method mainly includes the following steps S81 to S84.

[0087] Step S81: forming a hard mask layer on the surface of the wafer.

[0088] Specifically, a hard mask material layer can be formed on the surface of a semiconductor substrate (wafer) by chemical vapor deposition (CVD) or physical vapor deposition (PVD), and then a photoresist layer is coated on the hard mask material layer. After exposure and development, a patterned photoresist layer is formed. Subsequently, under the protection of the patterned photoresist, the hard mask material layer is etched to obtain a patterned hard mask material layer, i.e., a hard mask layer. The hard mask layer exposes the wafer surface where the trench structure is to be formed, and finally, the patterned photoresist layer is removed. In addition, the material of the hard mask layer can particularly be silicon dioxide.

[0089] Step S82: dry-etching the wafer along the thickness direction of the wafer to form a groove structure; wherein the groove structure includes a wavy groove.

[0090] In some embodiments, the dry etching may be plasma reactive etching, for example, and the process gas used in the dry etching process may be a mixture of HBr, SF6, and O2, or a mixture of SF6, He, O2, and CH3F.

[0091] Step S83: Cleaning the wafer using the cleaning method described in any one of the first to third embodiments to remove contaminants and the hard mask layer on the wafer surface.

[0092] Step S84: selectively forming a gate dielectric layer and a gate in a portion of the trench structure.

[0093] That is, after the wafer is cleaned and the hard mask layer is removed, subsequent processes can be continued according to normal processes.

[0094] For example, a gate dielectric layer and gate are formed within a portion of the trench, such as a cell trench. Specifically, a silicon dioxide layer or a high-k dielectric layer (such as HfO2) can be grown on the trench sidewalls through atomic layer deposition (ALD), CVD, thermal oxidation, or other methods to serve as the gate dielectric layer. The trench is then filled with a gate-capable material, such as doped polysilicon or metal, and then photolithography and etching are performed to form the gate. Subsequent manufacturing processes will be performed based on the specific device type and are not detailed here.

[0095] The above-described embodiment ensures complete removal of etching products within trenches, particularly wavy trenches, thereby improving product yield. Furthermore, because the silicon dioxide hard mask layer can be removed simultaneously during the cleaning process, compared to conventional semiconductor device fabrication processes that require separate hard mask layer removal, this eliminates the need for a hard mask removal step, thereby shortening the process, improving production efficiency, and reducing processing costs.

[0096] So far, the technical solution of the present application has been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the various technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the various technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0097] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A method for cleaning a trench-type semiconductor device, characterized in that: The steps include: The etched wafers are cleaned using a DHF solution, an SPM solution, an SC1 solution, and a BOE solution, respectively, to remove contaminants on the surface of the wafers; Wherein, a trench structure is formed in the wafer, and the contaminants include etching products generated during the process of etching to form the trench structure; The BOE solution cleaning sequence is after the DHF solution cleaning, or after the SC1 solution cleaning.

2. The cleaning method according to claim 1, wherein The steps include: The wafer is cleaned in sequence using a DHF solution, an SPM solution, an SC1 solution and a BOE solution, and then the wafer is cleaned in sequence using an SPM solution and an SC1 solution.

3. The cleaning method according to claim 1, wherein The steps include: The wafer was cleaned in sequence using DHF solution, BOE solution, SPM solution and SC1 solution.

4. The cleaning method according to any one of claims 1 to 3, characterized in that The DHF solution is prepared by mixing hydrofluoric acid and water in a volume ratio of 1:(30-110); in the process of using the DHF solution to clean the etched wafer, the cleaning time is controlled to be 60 to 120 seconds and the cleaning temperature is controlled to be 22 to 25°C; The SPM solution is prepared by mixing sulfuric acid and hydrogen peroxide in a volume ratio of (3-6):1, wherein the volume fraction of sulfuric acid is 98% and the volume fraction of hydrogen peroxide is 30%. During the process of cleaning the etched wafer using the SPM solution, the cleaning temperature is controlled to be 110 to 130° C., and the cleaning time is controlled to be more than 600 seconds. The SC1 solution is prepared by mixing ammonia water, hydrogen peroxide, and water in a volume ratio of 1:(1-2):(25-50); when the SC1 solution is used to clean the etched wafer, the cleaning temperature is controlled to be 60 to 70° C., and the cleaning time is controlled to be more than 300 seconds; In the BOE solution, the mass concentration of HF is 6-7%, and the mass concentration of NH4F is 30-45%. When the BOE solution is used to clean the etched wafer, the cleaning temperature is controlled to be 20-25° C., and the cleaning time is 150-160 seconds.

5. The cleaning method according to claim 4, wherein: When using the BOE solution to clean the etched wafer, the flow rate of the BOE solution is controlled to be 15 to 25 L / min.

6. The cleaning method according to any one of claims 1 to 5, characterized in that A surfactant is also added to the BOE solution.

7. The cleaning method according to claim 6, wherein: The surface tension of the BOE solution to which a surfactant is added is 20 to 40 dyne / cm.

8. The cleaning method according to any one of claims 1 to 7, characterized in that After each cleaning of the wafer with the DHF solution, the SPM solution, the SC1 solution, or the BOE solution, the wafer is cleaned with deionized water; And / or, after the wafer is cleaned with the SC1 solution, the wafer is dried.

9. The cleaning method according to any one of claims 1 to 7, characterized in that: The groove structure includes a wavy groove.

10. A method for preparing a trench semiconductor device, characterized in that: include: forming a hard mask layer on the surface of the wafer, wherein the hard mask layer exposes the surface of the wafer where the trench structure is to be formed; Etching the wafer along a thickness direction of the wafer to form a trench structure; The groove structure includes a wavy groove; Cleaning the wafer using the cleaning method according to any one of claims 1 to 9, and removing the hard mask layer during the cleaning process; A gate dielectric layer and a gate are selectively formed in a portion of the trench structure.

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