Method of manufacturing a semiconductor device

Abstract

The present disclosure provides a semiconductor device manufacturing method, comprising: disposing a barrier layer in a first wafer, the barrier layer being located between a trimming area and a center area; trimming the first wafer in the trimming area; bonding the first wafer with a second wafer; trimming the first wafer and the second wafer together to expose the barrier layer; and performing chemical mechanical polishing on the first wafer from a second surface, before the step of chemical mechanical polishing, a recess is formed along a radial direction of the first wafer, near an edge of the first wafer close to the first surface, towards the center of the first wafer, and the chemical mechanical polishing is stopped near the barrier layer. The barrier layer protects the edge of the first wafer during the chemical mechanical polishing, improves the problem of excessive edge grinding, and the recess blocks the movement of particles left in the polishing step towards the center of the first wafer surface, thereby improving the yield of the device.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor manufacturing, and in particular, to a manufacturing method of a semiconductor device. BACKGROUND

[0002] In the technical field of semiconductor manufacturing, wafer bonding technology is one of the key steps to realize complex integrated circuit design. By physically combining two or more wafers, a more complex chip structure can be constructed. However, after bonding two wafers, the upper wafer usually needs to be thinned to achieve the required thickness and surface flatness. Among them, the chemical mechanical polishing (CMP) process is a key technology for realizing wafer surface planarization in semiconductor manufacturing. This technology removes the excess material on the wafer surface through the combined action of chemical action and mechanical friction, so that the polished wafer reaches the required flatness and smoothness. However, in the CMP process, the wafer edge is a right angle, and due to the stress concentration of the right angle, the edge often has the problem of excessive grinding. This phenomenon causes the thickness of the wafer edge to be lower than expected, thereby affecting the performance and yield of the device.

[0003] Further, in the blow-drying step after the completion of the CMP process, the particles remaining on the edge of the wafer will move to the center area of the wafer surface during the drying process, further reducing the yield of the wafer. These particles may come from the polishing liquid in the CMP process, the wear of the polishing pad, or other contaminants, and their attachment on the wafer surface not only affects the subsequent process, but also can cause the device performance to decline, and even cause the device to fail.

[0004] Referring to Figure 1 , after CMP, the particles remaining on the edge of the wafer 11 and the wafer 12 appear on the wafer surface, Figure 1 The 10 photos below are the enlarged structures of different particles. After CMP, the thickness of the wafer 11 and the wafer 12 needs to be detected. Referring to Figure 2 , the horizontal axis represents the distance from the center of the wafer along the radial direction of the wafer, in millimeters (mm); the vertical axis represents the thickness of the wafer, in angstroms (Å); the white dots represent the measurement data of the wafer 11; the black dots represent the measurement data of the wafer 12. As can be seen from Figure 2 , at the edge of the wafer, the thickness decreases sharply. Therefore, it is desirable to improve the manufacturing process of the semiconductor device to improve the yield. SUMMARY

[0005] In view of the above problems, an improved manufacturing method of a semiconductor device is needed.

[0006] The manufacturing method of a semiconductor device provided by the present disclosure comprises:

[0007] providing a barrier layer in a first wafer, the first wafer comprising a center region and an edge region, the edge region comprising a trim region located at an outermost side of the first wafer, the barrier layer being located between the trim region and the center region;

[0008] trimming the first wafer at the trim region;

[0009] bonding the first wafer with a second wafer, the first wafer having opposite first and second surfaces, the first surface being proximate to the second wafer after the bonding;

[0010] trimming the first wafer and the second wafer together to expose the barrier layer; and

[0011] chemically mechanically polishing the first wafer from the second surface,

[0012] wherein, before the step of chemically mechanically polishing, an edge of the first wafer proximate to the first surface is recessed toward a center of the first wafer along a radial direction of the first wafer, so that the first wafer is in a mesa shape, and the barrier layer covers an inner surface of the recess, the chemically mechanical polishing stopping at a vicinity of the barrier layer.

[0013] Optionally, in the step of chemically mechanically polishing, a polishing liquid has a different selectivity ratio for the barrier layer and the first wafer, a polishing rate of the barrier layer being lower than a polishing rate of the first wafer.

[0014] Optionally, before the step of providing the barrier layer, the method further comprises: forming a trench in the first wafer, the trench being located in the edge region and between the trim region and the center region, the trench extending from the first surface into the first wafer,

[0015] the barrier layer covering an inner surface of the trench, and after the barrier layer is formed, a filling layer is filled in the trench.

[0016] Optionally, after the step of trimming together, the filling layer is exposed, and the method further comprises: removing the filling layer to expose a topography of the recess.

[0017] Optionally, the trench is in a continuous annular shape.

[0018] Optionally, a material of the barrier layer is silicon oxide, and a material of the filling layer is silicon nitride.

[0019] Optionally, before the step of bonding, the method further comprises:

[0020] forming at least part of a circuit structure based on the first wafer.

[0021] forming a first bonding layer above the first surface; and

[0022] forming a second bonding layer on the second wafer,

[0023] bonding the first bonding layer and the second bonding layer in the bonding step.

[0024] Optionally, after the bonding step and before the common edging step, the method further comprises rough thinning the first wafer from the second surface.

[0025] Optionally, after the polishing step, the method further comprises removing the barrier layer by a wet etching process,

[0026] wherein the etching rate of the barrier layer is greater than the etching rate of the first wafer.

[0027] Optionally, in the step of edging the first wafer in the edging region, the width of the first wafer removed comprises 1.3-1.6mm, and the total width of the edge region is not greater than 3.5mm.

[0028] One of the above technical solutions has the following unexpected technical effects:

[0029] By setting the barrier layer, the chemical mechanical polishing is stopped near the barrier layer, at this time the edge of the first wafer is surrounded by the barrier layer, and the stress originally concentrated on the right-angle edge of the first wafer is transferred to the barrier layer, thereby protecting the edge of the first wafer during the chemical mechanical polishing process and improving the problem of excessive edge grinding.

[0030] In some embodiments, since the grinding rate of the barrier layer is lower than the grinding rate of the first wafer, the barrier layer is almost impossible to grind during the chemical mechanical polishing process, further protecting the edge of the first wafer.

[0031] Further, before the chemical mechanical polishing step, a recess is formed in the edge of the first wafer near the bonding surface towards the center of the first wafer along the radial direction of the first wafer, and the barrier layer covering the inner surface of the recess also has a recessed topography, after the polishing step, the polishing liquid needs to be blown dry, and in the blowing dry process, the residual particles located in the edge of the first wafer will be blocked (contained in the recess) by the barrier layer so as not to be blown to the surface of the first wafer, thereby improving the yield of the device.

[0032] In some embodiments, the barrier layer is formed in the groove of the first surface of the first wafer, and the distance from the bottom of the groove to the second surface of the first wafer is the thickness of the wafer being thinned, so that the control of the thinning amount can be transferred to the control of the depth of the formed groove, and the operation is more convenient.

[0033] It should be noted that the above general description and the following detailed description are exemplary and explanatory only and do not limit this disclosure. Attached Figure Description

[0034] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0035] Figure 1 The image shows the detection images of the location and morphology of particles remaining on the wafer surface after the polishing and drying step in the related technology;

[0036] Figure 2 It shows Figure 1 The thickness measurement charts for the two wafers after polishing.

[0037] Figures 3 to 13 Cross-sectional views of a method for manufacturing a semiconductor device according to embodiments of the present disclosure are shown at some stages. Detailed Implementation

[0038] The present application will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown.

[0039] Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without following these specific details.

[0040] Furthermore, certain terms are used in this patent specification and claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This patent specification and claims do not distinguish components based on differences in name, but rather on differences in function.

[0041] It is also important to note that the use of relational terms such as first and second, and the like, are used solely to distinguish one from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0042] The application can take form in various aspects of which the following descriptions are examples.

[0043] Figures 3 to 13 Cross-sectional views of the method of manufacturing a semiconductor device according to embodiments of the present disclosure are shown in some stages.

[0044] As shown in Figure 3 , a trench 102 is formed in a first wafer 101. The first wafer 101 includes a center region 21 and an edge region 22 adjacent to each other, and the edge region 22 includes a trim region 22a located at the outermost side of the first wafer 101, and the trench 102 is located between the trim region 22a and the center region 21. In some specific embodiments, the total width of the edge region 22 is not greater than 3.5 mm. The first wafer 101 has opposite first and second surfaces 101a and 101b, and the trench 102 extends from the first surface 101a into the first wafer 101.

[0045] In this step, the trench 102 is formed by, for example, dry etching, and the trench 102 is optionally a continuous ring. The first wafer 101 can be a single wafer substrate, or a stacked structure including a wafer substrate and an epitaxial layer, and the material of the first wafer 101 is, for example, silicon. However, embodiments of the present disclosure are not limited thereto, and a person skilled in the art can make other settings to the material of the first wafer 101 as needed.

[0046] Further, a barrier layer 110 is formed covering the inner surface of the trench 102 and the first surface 101a, and a filling layer 120 is formed covering the barrier layer 110 and filling the trench 102, as shown in Figure 4 .

[0047] In this step, the barrier layer 110 and the fill layer 120 are formed, for example, by a process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), etc. In the trench 102, the profile of the barrier layer 110 is substantially consistent with the profile of the trench 102, and the fill layer 120 fills the trench 102. In this embodiment, the material of the barrier layer 110 is silicon oxide, and the material of the fill layer 120 is silicon nitride. However, the embodiments of the present disclosure are not limited thereto. In the subsequent steps, the barrier layer 110 is required to protect the first wafer 101 in the CMP step, and therefore the barrier layer 110 is preferably a material with a hardness greater than that of the first wafer 101, or in other words, the material of the barrier layer 110 should satisfy the following conditions: the selectivity ratio of the barrier layer 110 to the polishing liquid is different from that of the first wafer 101, and the polishing rate of the barrier layer 110 is lower than that of the first wafer 101. Alternatively, the etching selectivity ratios of the materials of the first wafer 101, the barrier layer 110, and the fill layer 120 are different.

[0048] Further, the barrier layer 110 and the fill layer 120 located above the first surface 101a are removed, as shown in FIG. 1C. Figure 5 In this step, the barrier layer 110 and the fill layer 120 above the first surface 101a are removed simultaneously, for example, by a CMP process, so as to re-expose the first surface 101a.

[0049] Further, at least part of a circuit structure is formed based on the first wafer 101, as shown in FIG. 1D. Figure 6 The circuit structure includes, for example, a doped region (not shown) formed in the central region 21 of the first wafer 101, a gate (not shown) formed above the first surface 101a, at least one interlayer dielectric layer 130, and at least one wiring layer 140, etc., wherein the specific components of the circuit structure can be set as required by those skilled in the art.

[0050] Further, a first bonding layer 150 is formed above the first surface 101a, as shown in FIG. 1E. Figure 6 The first bonding layer 150 covers the interlayer dielectric layer 130 and the wiring layer 140.

[0051] Further, the first wafer 101 and the interlayer dielectric layer 130 and the first bonding layer 150 are trimmed before bonding, and the trimming in this step is performed to the outside of the trench 102, and the depth of the trimming exceeds the bottom of the trench 102. In some specific embodiments, in this trimming step, the first wafer 101 and the interlayer dielectric layer 130 and the first bonding layer 150 are removed to a width range of 1.3-1.6 mm.

[0052] Further, a second bonding layer 210 is first formed on the surface of the second wafer 201, and then the first wafer 101 is bonded to the second wafer 201, as Figure 8 shown. In this step, the first bonding layer 150 is bonded to the second bonding layer 210. After bonding, the first surface 101a is close to the second wafer 201.

[0053] Further, the first wafer 101 is roughly thinned from the second surface 101b, as Figure 9 shown. In this step, for example, Mechanical Grinding is used to preliminarily thin the first wafer 101. In this step, the grinding stops above the bottom of the trench 102, with a certain preset distance from the bottom of the trench 102.

[0054] Further, the first wafer 101 and the second wafer 201 are jointly trimmed after bonding to expose the barrier layer 110 and the filling layer 120, as Figure 10 shown. After this trimming, the first wafer 101 is in an inverted boss shape. That is, along the radial direction of the first wafer 101, a depression 103 is formed on the edge of the first wafer 101 close to the first surface 101a towards the center of the first wafer 101. The depression 103 is formed by the trench 102 in the previous step.

[0055] Further, the filling layer 120 is removed by Wet Etching process, and the remaining barrier layer 110 covers the inner surface of the depression 103. In this step, for example, hot phosphoric acid is used to remove the silicon nitride material filling layer 120.

[0056] Further, the first wafer 101 is chemically mechanically polished from the second surface 101b, as Figure 12 shown. In this chemical mechanical polishing step, the selectivity ratio of the polishing liquid for the barrier layer 110 and the first wafer 101 is different. The polishing rate of the barrier layer 110 is lower than that of the first wafer 101, so that this chemical mechanical polishing stops near the surface of the barrier layer 110, thus improving the problem of over-polishing at the edge of the first wafer 101. After thinning the first wafer 101 by CMP, the polishing liquid is blown dry. Here, the bonded structure needs to be erected first, and then isopropanol (IPA) is used to blow dry. At this time, the barrier layer 110 is used to block the particles in the depression 103 from moving towards the second surface 101b.

[0057] Further, the barrier layer 110 is removed by Wet Etching process to re-expose the sidewall of the edge of the first wafer 101, as Figure 13The semiconductor structure is cleaned, for example, by using a tetramethylammonium hydroxide (TMAH) solution, in this step. The etching rate of the barrier layer 110 is greater than the etching rate of the first wafer 101.

[0058] Further, the first wafer 101 is continuously used to form other circuit structures, thereby completing the manufacturing process of the semiconductor device.

[0059] One of the above technical solutions has the following unexpected technical effects:

[0060] By setting the barrier layer, the chemical mechanical polishing is stopped near the barrier layer. At this time, the edge of the first wafer is surrounded by the barrier layer. The stress originally concentrated on the right-angle edge of the first wafer is transferred to the barrier layer, thereby protecting the edge of the first wafer during the chemical mechanical polishing process and improving the problem of excessive edge grinding.

[0061] In some embodiments, since the grinding rate of the barrier layer is lower than the grinding rate of the first wafer, the barrier layer is almost impossible to be ground during the chemical mechanical polishing process, further protecting the edge of the first wafer.

[0062] Further, before the chemical mechanical polishing step, a recess is formed in the edge of the first wafer close to the bonding surface towards the center of the first wafer along the radial direction of the first wafer. The barrier layer covering the inner surface of the recess also has a recessed topography. After the polishing step, the polishing liquid needs to be blown dry. During the blowing dry process, the residual particles located at the edge of the first wafer are blocked by the barrier layer (contained in the recess) and thus will not be blown to the surface of the first wafer, thereby improving the yield of the device.

[0063] In some embodiments, the barrier layer used to constitute the barrier layer is formed in the trench of the first surface of the first wafer, and the distance from the bottom of the trench to the second surface of the first wafer is the thickness of the wafer being thinned. Therefore, the control of the thinning amount can be transferred to the control of the depth of the formed trench, and the operation is more convenient.

[0064] In addition, the manufacturing method provided by the embodiments of the present disclosure is not limited to the bonding of two wafers, and can also be used for the bonding of multiple wafers.

[0065] According to the above embodiments of the present disclosure, these embodiments do not describe all the details, and the present disclosure is not limited to the specific embodiments. Obviously, many modifications and changes can be made according to the above description. The embodiments are selected and specifically described in this specification in order to better explain the principles and practical applications of the present disclosure, so that those skilled in the art can well utilize the present disclosure and make modifications based on the present disclosure. The protection scope of the present disclosure should be defined by the scope of the claims of the present disclosure and their equivalents.

Claims

1. A method for manufacturing a semiconductor device, comprising: A barrier layer is disposed in a first wafer, the first wafer having a first surface and a second surface opposite to each other, the barrier layer being close to the first surface, the first wafer including a central region and an edge region, the edge region including a trimmed area located on the outermost side of the first wafer, and the barrier layer being located between the trimmed area and the central region; The first wafer is trimmed in the trimming area, and the depth of the trimming of the first wafer exceeds the barrier layer along the direction from the first surface toward the second surface. The first wafer is bonded to the second wafer, and after bonding, the first surface is close to the second wafer; The first wafer and the second wafer are jointly trimmed to expose the barrier layer, and the bottom of the joint trimming is located in the second wafer along the direction from the second surface toward the first surface; as well as The first wafer is chemically and mechanically polished from the second surface. Prior to the chemical mechanical polishing step, a recess is formed along the radial direction of the first wafer, near the edge of the first wafer close to the first surface and towards the center of the first wafer. A barrier layer covers the inner surface of the recess, and the chemical mechanical polishing stops near the surface of the barrier layer. In the chemical mechanical polishing step, the selectivity of the polishing slurry for the barrier layer and the first wafer is different, and the polishing rate of the barrier layer is lower than that of the first wafer.

2. The manufacturing method according to claim 1, further comprising, before the step of setting the barrier layer: A trench is formed in the first wafer, the trench being located in the edge region and between the trimmed region and the center region, the trench extending from the first surface into the first wafer. The barrier layer covers the inner surface of the trench, and after the barrier layer is formed, a filler layer is filled into the trench.

3. The manufacturing method according to claim 2, wherein after the common trimming step, the filler layer is exposed, the manufacturing method further comprises: Remove the filling layer to expose the morphology of the depression.

4. The manufacturing method according to claim 2, wherein, The groove is in the form of a continuous ring.

5. The manufacturing method according to claim 2, wherein, The barrier layer is made of silicon oxide, and the filler layer is made of silicon nitride.

6. The manufacturing method according to claim 1, further comprising, before the bonding step: At least a portion of the circuit structure is formed based on the first wafer; A first bonding layer is formed above the first surface; as well as A second bonding layer is formed on the second wafer. In the bonding step, the first bonding layer is bonded to the second bonding layer.

7. The manufacturing method according to claim 1, further comprising, after the bonding step and before the common trimming step, coarsely thinning the first wafer from the second surface.

8. The manufacturing method according to claim 1, further comprising, after the polishing step, removing the barrier layer using a wet etching process. in, The barrier layer is etched at a rate greater than that of the first wafer.

9. The manufacturing method according to any one of claims 1 to 8, wherein, In the step of trimming the first wafer in the trimming area, the width range of the first wafer that is removed includes 1.3-1.6 mm, and the total width of the edge area is not greater than 3.5 mm.

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