An etching method for semiconductor devices

Abstract

This invention relates to an etching method for a semiconductor device. The semiconductor device includes a stacked structure, a bottom anti-reflective layer, and a mask layer arranged sequentially from bottom to top. The etching method includes the following steps: providing a first etching gas, which includes a main etching gas and a protective gas, and determining the gas ratio of the main etching gas and the protective gas; a first etching step: etching the mask layer and the bottom anti-reflective layer in the first etching gas atmosphere until the stacked structure is exposed, forming a mask layer with inclined sidewalls; wherein the inclined sidewalls are inclined outward from top to bottom. This invention provides an etching method for a semiconductor device that, by adjusting the gas ratio of the main etching gas and the protective gas, changes the amount of polymer deposited on the inclined sidewalls, and adjusts the inclination angle of the inclined sidewalls, can break through the line width of the stacked structure determined by the physical limit size of the rectangular mask layer, increase the line width of the stacked structure, and thus obtain a smaller trench.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing technology, and more specifically, to an etching method for semiconductor devices. Background Technology

[0002] To improve performance metrics such as processor speed and analog frequency response, the semiconductor manufacturing industry is moving towards smaller critical dimensions (CD). Photoresist (PR), as a type of mask, plays a crucial role in the critical dimensions of semiconductor devices. These critical dimensions include linewidth and trench width, which directly affect the device's conductivity and integration density.

[0003] In related technologies, lateral etching of the photoresist mask layer is typically used to directly reduce the size of the photoresist mask layer during the process, thereby reducing the linewidth of the semiconductor device. However, this technique still cannot overcome the physical size limit of the photoresist mask layer to adjust the linewidth of the semiconductor device. Summary of the Invention

[0004] The present invention aims to solve at least one technical problem existing in the related art, and proposes a method for fabricating a semiconductor device. By adjusting the tilt angle of the tilted sidewall of the mask layer, it is possible not only to increase the line width of the semiconductor device, but also to reduce the line width of the semiconductor device.

[0005] This invention provides an etching method for a semiconductor device, the semiconductor device comprising a stacked structure, a bottom anti-reflection layer, and a mask layer arranged sequentially from bottom to top;

[0006] The etching method includes the following steps:

[0007] A first etching gas is provided, the first etching gas comprising a main etching gas and a protective gas, and the gas ratio of the main etching gas and the protective gas is determined;

[0008] In the first etching step, the mask layer and the bottom anti-reflective layer are etched in the first etching gas atmosphere until the stacked structure is exposed, forming a mask layer with inclined sidewalls; wherein the inclined sidewalls are inclined outward from top to bottom.

[0009] Optionally, the gas ratio of the first etching gas is positively correlated with the slope of the inclined sidewall, positively correlated with the width of the trench in the stacked structure, and negatively correlated with the line width of the stacked structure.

[0010] And / or, the cross-sectional shape of the mask layer with inclined sidewalls in the vertical direction is an isosceles trapezoid or an isosceles triangle or a combination of an isosceles trapezoid and a rectangle or a combination of an isosceles triangle and a rectangle.

[0011] Optionally, the main etching gas is tetrafluoromethane, the protective gas is trifluoromethane, the flow rate of tetrafluoromethane is 0-300 sccm, the flow rate of trifluoromethane is 0-300 sccm, the gas ratio of tetrafluoromethane to trifluoromethane is 1:3-2:1, and the first etching time is 10-300 s.

[0012] Alternatively, the main etching gas is tetrafluoromethane, the protective gas is difluoromethane, the flow rate of tetrafluoromethane is 0-300 sccm, the flow rate of difluoromethane is 0-300 sccm, the gas ratio of tetrafluoromethane to difluoromethane is 1:2.5-1:1.2, and the first etching time is 10-300 s.

[0013] Optionally, the gas ratio of tetrafluoromethane to trifluoromethane is 1:3 to 1:1, and the slope of the inclined sidewall is between 0.4 and 0.6; or the gas ratio of tetrafluoromethane to trifluoromethane is 1:1 to 2:1, and the slope of the inclined sidewall is between 0.6 and 0.8.

[0014] Alternatively, the gas ratio of tetrafluoromethane to difluoromethane is 1:2.5-1:1.2, and the slope of the inclined sidewall is between 0.4 and 0.6; or the gas ratio of tetrafluoromethane to difluoromethane is 1:1.2-1.8:1, and the slope of the inclined sidewall is between 0.6 and 0.8.

[0015] Optionally, the first etching gas may further include an inert gas, the flow rate of which is 0-300 sccm.

[0016] Optionally, after the first etching step, the etching method further includes:

[0017] In the second etching step, based on the mask layer with inclined sidewalls, the stacked structure is etched to obtain a patterned stacked structure, wherein the line width of the patterned stacked structure is equal to the distance between the intersection point of the extension line of the inclined sidewall and the upper surface of the stacked structure.

[0018] Optionally, the stacked structure includes a first silicon oxide layer, which is located below the bottom antireflective layer;

[0019] The second etching step includes:

[0020] In a second etching gas atmosphere, the first silicon oxide layer is etched based on the mask layer with inclined sidewalls to form a patterned first silicon oxide layer; wherein the line width of the patterned first silicon oxide layer is equal to the distance between the intersection point of the extension line of the inclined sidewall and the upper surface of the first silicon oxide layer.

[0021] Optionally, the second etching gas includes tetrafluoromethane, oxygen, and an inert gas, wherein the flow rate of tetrafluoromethane is 0-300 sccm, the flow rate of oxygen is 0-300 sccm, the flow rate of the inert gas is 10-500 sccm, the ratio of tetrafluoromethane, oxygen, and inert gas is (1-7):(1-3):(6-17), and the second etching time is 5-300 s.

[0022] Optionally, the stacked structure includes a silicon bottom layer, a second silicon oxide layer, and a silicon top layer disposed sequentially from bottom to top, wherein the silicon top layer is located below the first silicon oxide layer;

[0023] After the step of etching the first silicon oxide layer, the second etching step further includes:

[0024] In the third etching gas atmosphere, using the patterned first silicon oxide layer as a mask, the top silicon layer and the second silicon oxide layer are etched sequentially until the bottom silicon layer is exposed, forming a patterned top silicon layer and a patterned second silicon oxide layer.

[0025] Optionally, the third etching gas includes tetrafluoromethane and an inert gas, wherein the flow rate of tetrafluoromethane is 0-300 sccm, the flow rate of the inert gas is 10-500 sccm, the ratio of tetrafluoromethane to inert gas is (1-7):(1-3), and the third etching time is 5-300 s.

[0026] This invention provides an etching method for semiconductor devices, which has at least the following beneficial technical effects:

[0027] On the one hand, by adjusting the gas ratio of the main etching gas and the protective gas, the amount of polymer deposited on the inclined sidewall is changed, thereby adjusting the transverse etching rate, which in turn adjusts the tilt angle of the inclined sidewall and the line width of the stacked structure.

[0028] On the other hand, it is possible to break through the physical limit of the rectangular mask layer and increase the line width of the stacked structure, thereby obtaining a smaller trench.

[0029] In addition, the line width of the stacked structure can be increased or decreased by exceeding the physical limit size of the rectangular mask layer. Attached Figure Description

[0030] Figure 1 A schematic diagram of the photoresist mask layer obtained in step S1 of a method for controlling mask size based on dry etching process provided for related technologies. Figure 1 ;

[0031] Figure 2 A schematic diagram of the photoresist mask layer obtained in step S2 of a method for controlling mask size based on dry etching process provided for related technologies. Figure 2 ;

[0032] Figure 3 A process flow of a semiconductor etching method provided in an embodiment of the present invention. Figure 1 ;

[0033] Figure 4 This is a structural diagram of a semiconductor device processed by a semiconductor etching method according to an embodiment of the present invention;

[0034] Figure 5 In a semiconductor etching method provided in an embodiment of the present invention, when the gas ratio of main etching gas to protective gas is low, the structure diagram of the mask layer with inclined sidewalls obtained in the first etching step is shown.

[0035] Figure 6 This is a schematic diagram of ion bombardment of a mask layer in a semiconductor etching method provided in an embodiment of the present invention;

[0036] Figure 7 A schematic diagram illustrating the shielding effect of a mask layer with tilted sidewalls on ion bombardment in a semiconductor etching method provided in an embodiment of the present invention;

[0037] Figure 8 A schematic diagram illustrating the determination of line width of a stacked structure based on the slope of the inclined sidewalls in a semiconductor etching method provided in this embodiment of the invention.

[0038] Figure 9 In a semiconductor etching method provided in an embodiment of the present invention, when the gas ratio of main etching gas to protective gas is high, the structure diagram of the mask layer with inclined sidewalls obtained in the first etching step is shown.

[0039] Figure 10 A process flow of a semiconductor etching method provided in an embodiment of the present invention. Figure 2 ;

[0040] Figure 11 This is a schematic diagram of the structure after etching the top silicon layer using a first silicon oxide layer as a mask in a semiconductor etching method provided in an embodiment of the present invention.

[0041] Figure 12This is a schematic diagram of the structure after etching the second silicon oxide layer using the first silicon oxide layer as a mask in a semiconductor etching method provided in an embodiment of the present invention.

[0042] Explanation of reference numerals in the attached figures:

[0043] 1. Substrate; 2. Photoresist mask layer; 10. Silicon bottom layer; 20. Second silicon oxide layer; 30. Silicon top layer; 40. First silicon oxide layer; 50. Bottom anti-reflection layer; 60. Mask layer; 70. Sloping sidewall. Detailed Implementation

[0044] See appendix Figures 1-2 The related technology discloses a method for controlling mask size based on dry etching process, including the following steps:

[0045] S1: Fabrication of photoresist mask layer 2, specifically including: coating a uniform photoresist layer on the surface of substrate 1 to form a photoresist layer; using optical exposure to generate corresponding patterned micro-nano structures on the surface of substrate to form photoresist mask layer 2;

[0046] S2: Using a dry etching process, the mask size of the photoresist mask layer prepared in S1 is processed according to the desired pattern size;

[0047] S3: Use the photoresist mask layer obtained in S2 for subsequent pattern transfer etching.

[0048] Therefore, in this related technology, the size of the photoresist mask layer 2 is directly reduced by lateral etching, thereby reducing the pattern transfer size, i.e., reducing the line width of the semiconductor device. The line width of the semiconductor device is equal to the line width of the photoresist mask layer 2 after lateral etching, which is equal to the physical limit size of the photoresist mask layer 2 after lateral etching. However, this related technology still cannot overcome the physical limit size of the photoresist mask layer 2 to adjust the line width of the semiconductor device.

[0049] In order to overcome the physical size limit of the mask layer and adjust the line width of the semiconductor device, this invention provides an etching method for semiconductor devices. By adjusting the tilt angle of the tilted sidewalls of the mask layer, the physical size limit of the mask layer can be overcome, thereby adjusting the line width of the semiconductor device.

[0050] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the following description is provided in conjunction with the accompanying drawings. Figures 3-12 Specific embodiments of the present invention will be described in detail below.

[0051] This invention provides an etching method for semiconductor devices, see attached figure. Figure 4The semiconductor device includes a stacked structure, a bottom anti-reflective layer 50, and a mask layer 60 arranged sequentially from bottom to top; the number of mask layers 60 is not limited, and can be one, two, or other numbers. For example, such as Figure 4 As shown, there are two mask layers 60, spaced apart in the lateral direction. The bottom anti-reflection layer 50 is primarily used to reduce light reflection during the photolithography process. When light shines on the surface of a semiconductor device, some light is reflected, while the rest penetrates the bottom of the stacked structure. The reflected light returns to the mask layer 60, potentially causing overexposure of the mask layer 60 and resulting in pattern blurring and distortion. Therefore, the bottom anti-reflection layer 50 is provided to reduce the impact of reflection.

[0052] See appendix Figure 3 and Figure 5 The etching method includes the following steps:

[0053] S100, providing a first etching gas, the first etching gas including a main etching gas and a protective gas, and determining the gas ratio of the main etching gas and the protective gas;

[0054] S110, First etching step, in a first etching gas atmosphere, etch the mask layer 60 and the bottom anti-reflection layer 5 until the stacked structure is exposed, forming a mask layer 60 with inclined sidewalls 70 and a patterned bottom anti-reflection layer 50; wherein the inclined sidewalls 70 are inclined outward from top to bottom.

[0055] It should be noted that the protective gas can form polymers on the inclined sidewalls 70 and the sidewalls of the patterned bottom anti-reflective layer 50, thereby reducing the lateral etching rate and adjusting the morphology of the mask layer 60. See Appendix Figure 6 Before etching, the mask layer 60 is a rectangular mask layer with right-angled regions. During etching, the incident direction of ions is perpendicular to the surface of the rectangular mask layer. Due to the high electric field intensity in the right-angled regions, these regions are more susceptible to ion bombardment, thus easily forming bevels. See Appendix. Figure 7 The mask layer 60 with inclined sidewalls 70 has a shielding effect on ion bombardment, thereby selectively etching the stacked structure. The region outside the intersection point of the extension line of the inclined sidewalls 70 and the upper surface of the stacked structure receives more ion bombardment (as shown in the attached image). Figure 7 In the image, the ions indicated by the red arrows are etched; as shown... Figure 8 As shown, the stacked structure located between the two mask layers 60 is etched away to form trenches; the area between the intersection of the extension of the inclined sidewall 70 and the upper surface of the stacked structure is masked and preserved; that is, as Figure 8As shown, the line width of the patterned stacked structure is equal to the distance between the intersection point of the extension line of the inclined sidewall 70 and the upper surface of the stacked structure. The line width of the patterned stacked structure is the lateral dimension of the stacked structure retained by the etched portion thickness.

[0056] The etching method for semiconductor devices provided in this invention, on the one hand, adjusts the ratio of the main etching gas and the protective gas to change the amount of polymer deposited on the inclined sidewall 70, thereby adjusting the lateral etching rate, and thus adjusting the tilt angle of the inclined sidewall 70, the line width of the stacked structure, and the trench width of the stacked structure; on the other hand, the bottom edge width of the mask layer 60 with the inclined sidewall 70 can be equal to the bottom edge width of the rectangular mask layer before etching. The bottom edge width of the mask layer 60 with the inclined sidewall 70 is amplified by a bottom anti-reflection layer 50 of a certain thickness, making the line width of the stacked structure greater than the bottom edge width of the rectangular mask layer, i.e. This allows for exceeding the physical limits of the rectangular mask layer in terms of line width of the stacked structure, thereby increasing the line width of the stacked structure and resulting in smaller trenches. Furthermore, the bottom width of the mask layer with inclined sidewalls 70 can be smaller than the bottom width of the rectangular mask layer before etching. The bottom width of the mask layer 60 with inclined sidewalls 70 is amplified by a bottom anti-reflective layer 50 of a certain thickness, allowing the line width of the stacked structure to be greater than or less than the bottom width of the rectangular mask layer. In other words, it allows for exceeding the physical limits of the rectangular mask layer in terms of line width of the stacked structure, thereby increasing or decreasing the line width of the stacked structure.

[0057] In this embodiment of the invention, the gas ratio of the first etching gas is positively correlated with the slope of the inclined sidewall 70, positively correlated with the width of the trenches in the stacked structure, and negatively correlated with the line width of the stacked structure. For details, see the appendix. Figure 9 When the ratio of primary etching gas to protective gas is high, there is relatively more primary etching gas, resulting in enhanced ion bombardment energy and a higher vertical etching rate. However, the protective gas is relatively scarce, leading to insufficient polymer coverage on the sidewalls of the mask layer 60. This results in a vertical etching rate greater than the lateral etching rate, forming steep, sloping sidewalls 70. Specifically, the slope of the sloping sidewalls 70 is relatively large, and the intersection point of the extension line of the sloping sidewalls 70 with the upper surface of the stacked structure is relatively close, meaning the line width of the stacked structure is small, but the trench width of the stacked structure is large. (See Appendix) Figure 5When the ratio of main etching gas to protective gas is low, there is relatively more protective gas, and the polymer on the sidewall of the mask layer 60 is uniform and dense, effectively suppressing the lateral etching rate. The main etching gas is relatively less, the ion bombardment energy is enhanced, and the vertical etching rate is reduced, resulting in a smaller difference between the vertical and lateral etching rates. This forms a gently sloping sidewall 70, meaning the slope of the sloping sidewall 70 is smaller. The intersection point between the extension line of the sloping sidewall 70 and the upper surface of the stacked structure is farther, meaning the line width of the stacked structure is larger, but the trench width of the stacked structure is smaller.

[0058] In this embodiment of the invention, for example, when the slope of the inclined sidewall 70 is a first slope, the bottom edge width of the mask layer 60 with the inclined sidewall 70 is the first bottom edge width, the line width of the corresponding stacked structure is the first line width, and the trench width of the corresponding stacked structure is the first trench width; when the slope of the inclined sidewall 70 is a second slope, the bottom edge width of the mask layer 60 with the inclined sidewall 70 is the second bottom edge width, the line width of the corresponding stacked structure is the second line width, and the trench width of the corresponding stacked structure is the second trench width; wherein, the first slope is greater than the second slope, and the first bottom edge width is greater than the second bottom edge width; since the first slope is greater than the first slope, the distance between the extension line of the inclined sidewall 70 with the first slope and the intersection point of the stacked structure is closer, that is, a larger first bottom edge width results in a smaller first line width, that is, a wider mask layer results in a smaller first line width, achieving a size reversal; conversely, a larger first trench width is obtained.

[0059] In this embodiment of the invention, the cross-sectional shape of the mask layer 60 with inclined sidewalls 70 in the vertical direction can take many forms. For example, it can be an isosceles trapezoid; or an isosceles triangle; or a combination of an isosceles trapezoid and a rectangle, i.e., the upper end is an isosceles trapezoid and the lower end is a rectangle; or a combination of an isosceles triangle and a rectangle, i.e., the upper end is an isosceles triangle and the lower end is a rectangle. The cross-sectional shape is not limited here.

[0060] In this embodiment of the invention, the main materials of the mask layer 60 and the bottom anti-reflection layer 50 are CH-based polymers, and the main etching gas and the protective gas are both fluorine-based gases, as detailed below:

[0061] For example, the main etching gas is tetrafluoromethane (CF4), and the protective gas is trifluoromethane (CHF3). In the plasma environment, tetrafluoromethane (CF4) decomposes to produce highly reactive substances such as fluorine radicals, which react with CH-based polymers to generate volatile products, such as carbon tetrafluoride (CF4), thereby achieving the etching of CH-based polymers. Trifluoromethane (CHF3) can form polymers on the inclined sidewalls 70 of the mask layer 60 and the sidewalls of the patterned bottom anti-reflection layer 50. Specifically, for example, it decomposes in the plasma environment to generate carbon-containing radicals (such as CF2). During the etching process, the carbon-containing radicals are deposited on the inclined sidewalls 70 of the mask layer 60 to form a fluorocarbon polymer film, thereby reducing the lateral etching rate of the mask layer 60. The flow rates of tetrafluoromethane and trifluoromethane are both 0-300 sccm, with a gas ratio of 1:3 to 2:1. The first etching time is 10-300 s. With this setup, by adjusting the gas flow rates and gas ratios of tetrafluoromethane and trifluoromethane, the vertical and horizontal etching rates can be adjusted, thereby adjusting the angle of the inclined sidewalls of the mask layer 60.

[0062] For example, the main etching gas is tetrafluoromethane (CF4), and the protective gas is difluoromethane (CH2F2). In the plasma environment, tetrafluoromethane (CF4) decomposes to produce highly reactive substances such as fluorine radicals, which react with CH-based polymers to generate volatile products, such as carbon tetrafluoride (CF4), thereby achieving the etching of CH-based polymers. Difluoromethane (CH2F2) can form polymers on the inclined sidewalls 70 of the mask layer 60 and the sidewalls of the patterned bottom anti-reflective layer 50. Specifically, for example, it decomposes in the plasma environment to generate carbon-containing radicals (such as CF2). During the etching process, the carbon-containing radicals are deposited on the inclined sidewalls 70 of the mask layer 60, thereby reducing the lateral etching rate of the mask layer 60. The flow rates of tetrafluoromethane and difluoromethane are both 0-300 sccm, with a gas ratio of 1:2.5 to 1:1.2. The first etching time is 10-300 s. With this setup, by adjusting the gas flow rates and gas ratios of tetrafluoromethane and difluoromethane, the vertical and horizontal etching rates can be adjusted, thereby adjusting the angle of the inclined sidewalls of the mask layer 60.

[0063] In this embodiment of the invention, the gas ratio of tetrafluoromethane to trifluoromethane is 1:3-1:1, and the slope of the inclined sidewall is between 0.4 and 0.6; the gas ratio of tetrafluoromethane to trifluoromethane is 1:1-2:1, and the slope of the inclined sidewall is between 0.6 and 0.8.

[0064] In this embodiment of the invention, the gas ratio of tetrafluoromethane to difluoromethane is 1:2.5-1:1.2, and the slope of the inclined sidewall is between 0.4 and 0.6; the gas ratio of tetrafluoromethane to difluoromethane is 1:1.2-1.8:1, and the slope of the inclined sidewall is between 0.6 and 0.8.

[0065] In this embodiment of the invention, the first etching gas further includes an inert gas with a flow rate of 0-300 sccm. The inert gas can be nitrogen, argon, or helium, used as a dilution gas to slow down the etching rate and prevent excessive etching due to over-reaction.

[0066] The etching method provided in this embodiment of the invention is described in the appendix. Figure 3 The method also includes step S120, a second etching step, in which the stacked structure is etched based on the mask layer 60 with inclined sidewalls 70 to obtain a patterned stacked structure. The line width of the patterned stacked structure is equal to the distance between the intersection point of the extension line of the inclined sidewalls 70 and the upper surface of the stacked structure. Compared to related technologies where the line width of the stacked structure is determined by the lateral dimensions of a rectangular mask layer, the etching method for a semiconductor device provided in this embodiment of the invention uses the slope of the inclined sidewalls 70 of the mask layer 60 and the bottom edge width of the mask layer 60 to determine the line width of the stacked structure. This allows the method to overcome the limitations of the physical dimensions of the mask layer 60 in determining the line width of the stacked structure, thus allowing for either an increase or decrease in the line width.

[0067] In this embodiment of the invention, see appendix. Figure 4 The stacked structure includes a first silicon oxide layer 40, which is located below the bottom antireflective layer 50; see appendix. Figure 3 Step S120 (second etching step) includes: Step S121, in a second etching gas atmosphere, based on the mask layer 60 having inclined sidewalls 70, etching the first silicon oxide layer 40 to form a patterned first silicon oxide layer 40; wherein, the line width of the patterned first silicon oxide layer 40 is equal to the distance between the intersection point of the extension line of the inclined sidewall 70 and the upper surface of the first silicon oxide layer 40. See Appendix Figure 7 The mask layer 60 with inclined sidewalls 70 has a shielding effect against ion bombardment, thereby selectively etching the first silicon oxide layer 40. The region outside the intersection point of the extension line of the inclined sidewalls 70 and the upper surface of the first silicon oxide layer 40 receives more ion bombardment (as shown in the attached figure). Figure 7 In the diagram, the ions indicated by the red arrows are etched; the area between the intersection of the extended line of the inclined sidewall 70 and the upper surface of the first silicon oxide layer 40 is masked and preserved; that is, see Appendix Figure 8The line width of the patterned first silicon oxide layer 40 is equal to the distance between the intersection point of the extension line of the inclined sidewall 70 and the upper surface of the first silicon oxide layer 40. The line width of the patterned first silicon oxide layer 40 is the lateral dimension of the stacked structure retained by the etched portion of the stacked structure. With this configuration, the first silicon oxide layer 40 is selectively etched by utilizing the shielding effect of the inclined sidewall 70 of the mask layer 60 against ion bombardment.

[0068] In this embodiment of the invention, the second etching gas includes tetrafluoromethane (CF4), oxygen (O2), and an inert gas. Tetrafluoromethane (CF4) serves as the main etching gas, dissociating in plasma to generate highly reactive fluorine radicals (F). These fluorine radicals (F) chemically react with the first silicon oxide layer 40 to generate volatile products silicon tetrafluoride (SiF4) and carbon dioxide (CO2). Oxygen (O2) promotes the dissociation of H atoms in the mask layer 60 of the CH-based polymer. These H atoms chemically react with the first silicon oxide layer 40 to generate water vapor. The etching rate of the first silicon oxide layer 40 is improved by using tetrafluoromethane (H2O) and silicon (Si). The flow rate of tetrafluoromethane is 0-300 sccm, the flow rate of oxygen is 0-300 sccm, and the flow rate of inert gas is 10-500 sccm. The inert gas can be nitrogen, argon, or helium. The ratio of tetrafluoromethane, oxygen, and inert gas is (1-7):(1-3):(6-17), for example, a ratio of 4:1:9. The second etching time is 5-300 s. With this setup, using tetrafluoromethane and oxygen, the etching of the first silicon oxide layer 40 is achieved. Oxygen can dissociate the H atoms in the CH-based polymer, thereby increasing the etching rate of the first silicon oxide layer 40.

[0069] In this embodiment of the invention, see appendix. Figure 4 The stacked structure includes, from bottom to top, a silicon bottom layer 10, a second silicon oxide layer 20, and a silicon top layer 30, with the silicon top layer 30 located below the first silicon oxide layer 40; see appendix. Figures 10-12 Step S120 (second etching step) further includes: Step S122, in a second etching gas atmosphere, using the patterned first silicon oxide layer 40 as a mask, sequentially etching the top silicon layer 30 and the second silicon oxide layer 20 until the bottom silicon layer 10 is exposed, forming the patterned top silicon layer 30 and the patterned second silicon oxide layer 20. This configuration, using the patterned first silicon oxide layer 40 as a mask, etches the top silicon layer 30 and the second silicon oxide layer 20 to transfer the pattern to the top silicon layer 30 and the second silicon oxide layer 20.

[0070] In this embodiment of the invention, the third etching gas includes tetrafluoromethane and an inert gas. The flow rate of tetrafluoromethane is 0-300 sccm, and the flow rate of the inert gas is 10-500 sccm. The inert gas can be nitrogen, argon, or helium. The ratio of tetrafluoromethane to inert gas is (1-7):(1-3). For example, the ratio of tetrafluoromethane to inert gas can be 4:1. The third etching time is 5-300 s.

[0071] In this embodiment of the invention, the line width of the patterned bottom anti-reflective layer 50 is less than or equal to the bottom edge width of the mask layer 60 with inclined sidewalls 70.

[0072] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. An etching method of a semiconductor device, characterized by, The semiconductor device comprises a layer stack, a bottom antireflection layer (50) and a mask layer (60) arranged in sequence from bottom to top; The etching method comprises the following steps: A first etching gas is provided, the first etching gas comprising a main etching gas and a protective gas, and the gas ratio of the main etching gas and the protective gas is determined; A first etching step, in the atmosphere of the first etching gas, etching the mask layer (60) and the bottom antireflection layer (50) until the layer stack is exposed, forming a mask layer (60) with an inclined side wall (70); wherein the inclined side wall (70) is inclined outward from top to bottom; the gas ratio of the first etching gas is positively correlated with the slope of the inclined side wall (70), positively correlated with the width of the trench of the layer stack, and negatively correlated with the line width of the layer stack; A second etching step, based on the mask layer (60) with the inclined side wall (70), etching the layer stack to obtain a patterned layer stack, wherein the line width of the patterned layer stack is equal to the distance between the intersection point of the extension line of the inclined side wall (70) and the upper surface of the layer stack.

2. The etching method of a semiconductor device according to claim 1, wherein The cross-sectional shape of the mask layer (60) with the inclined side wall (70) in the vertical direction is isosceles trapezoidal or isosceles triangular or a combination of isosceles trapezoidal and rectangular or a combination of isosceles triangular and rectangular.

3. The etching method of a semiconductor device according to Claim 1, wherein The main etching gas is tetrafluoromethane, the protective gas is trifluoromethane, the flow rate of tetrafluoromethane is 0-300sccm, the flow rate of trifluoromethane is 0-300sccm, the gas ratio of tetrafluoromethane and trifluoromethane is 1:3-2:1, and the first etching time is 10-300s; Or, the main etching gas is tetrafluoromethane, the protective gas is difluoromethane, the flow rate of tetrafluoromethane is 0-300sccm, the flow rate of difluoromethane is 0-300sccm, the gas ratio of tetrafluoromethane and difluoromethane is 1:2.5-1:1.2, and the first etching time is 10-300s.

4. The etching method of a semiconductor device according to Claim 3, wherein The gas ratio of tetrafluoromethane and trifluoromethane is 1:3-1:1, and the slope of the inclined side wall is between 0.4-0.6; Or, the gas ratio of tetrafluoromethane and difluoromethane is 1:2.5-1:1.2, and the slope of the inclined side wall is between 0.4-0.

6.

5. The etching method of a semiconductor device according to Claim 3, wherein The gas ratio of tetrafluoromethane and trifluoromethane is 1:1-2:1, and the slope of the inclined side wall is between 0.6-0.8; Or, the gas ratio of tetrafluoromethane and difluoromethane is 1:1.2-1.8:1, and the slope of the inclined side wall is between 0.6-0.

8.

6. The etching method of a semiconductor device according to Claim 3, wherein The first etching gas further comprises an inert gas, and the flow rate of the inert gas is 0-300sccm.

7. The etching method of a semiconductor device according to Claim 1, wherein The layer stack comprises a first silicon oxide layer (40) located below the bottom antireflection layer (50); The second etching step comprises: In a second etching gas atmosphere, based on the mask layer (60) with the inclined sidewall (70), the first silicon oxide layer (40) is etched to form a patterned first silicon oxide layer (40); wherein the line width of the patterned first silicon oxide layer (40) is equal to the distance between the intersection point of the extension line of the inclined sidewall (70) and the upper surface of the first silicon oxide layer (40).

8. The etching method of a semiconductor device according to Claim 7, wherein The second etching gas comprises tetrafluoromethane, oxygen and inert gas, the flow rate of tetrafluoromethane is 0-300sccm, the flow rate of oxygen is 0-300sccm, the flow rate of inert gas is 10-500sccm, and the ratio of tetrafluoromethane, oxygen and inert gas is (1-7):(1-3):(6-17), and the second etching time is 5-300s.

9. The etching method of a semiconductor device according to Claim 7, wherein The laminated structure comprises a silicon bottom layer (10), a second silicon oxide layer (20) and a silicon top layer (30) arranged in order from bottom to top, and the silicon top layer (30) is located below the first silicon oxide layer (40); After the step of etching the first silicon oxide layer (40), the second etching step further comprises: In a third etching gas atmosphere, the patterned first silicon oxide layer (40) is used as a mask to etch the silicon top layer (30) and the second silicon oxide layer (20) in order until the silicon bottom layer (10) is exposed, forming a patterned silicon top layer (30) and a patterned second silicon oxide layer (20).

10. The etching method of a semiconductor device according to Claim 9, wherein The third etching gas comprises tetrafluoromethane and inert gas, the flow rate of tetrafluoromethane is 0-300sccm, the flow rate of inert gas is 10-500sccm, and the ratio of tetrafluoromethane and inert gas is (1-7):(1-3), and the third etching time is 5-300s.

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