Rotary rectifier chip and method of production

Abstract

The application discloses a rotating rectifier chip and a production method, relates to the chip production field, and covers the whole process from preparing a substrate layer, forming a PN junction, manufacturing a metal electrode, passivation protection, wafer thinning and cutting, to final chip testing and sorting. In the chip testing and sorting link, advanced yield management and fault diagnosis mechanisms are integrated. Instead of relying on manual visual inspection of wafer maps and experience-based judgment, the application can automatically construct a wafer map image matrix and perform pattern recognition and attribution of yield space distribution based on the matrix through intelligent analysis of test results, especially when the wafer yield is lower than a preset threshold. This data-driven analysis method can efficiently and objectively identify failure points with specific spatial patterns, thereby significantly improving the production efficiency and product yield of the rotating rectifier chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of chip production, and more particularly, to a rotary rectifier chip and a production method. BACKGROUND

[0002] As a key component indispensable in modern electronic devices, rotary rectifier chips are widely used in the fields of automobiles, industrial control, power management, etc., and their performance and reliability directly affect the overall performance of terminal products. In the production process of rotary rectifier chips, since it involves multi-step, high-precision semiconductor manufacturing processes such as substrate layer preparation, PN junction formation, metal electrode fabrication, passivation protection, wafer thinning and cutting, and finally chip testing and sorting, any slight deviation in any link may lead to a decrease in chip performance or even failure. Therefore, how to build an efficient and reliable production method to ensure the yield and quality of chips is an important challenge currently faced by the semiconductor manufacturing field.

[0003] However, in the existing production method of rotary rectifier chips, although each process link has become mature, in the chip testing and sorting stage, especially when the wafer yield is lower than the expected threshold, the root cause diagnosis of failed chips is often inefficient. The traditional approach usually relies on experienced engineers to perform manual visual inspection and experience-based judgment on wafer maps to identify the spatial distribution pattern of failed chips. This manual map viewing method not only consumes time and effort, but also highly depends on the personal experience of engineers, is easily affected by subjective factors, and is difficult to quickly and accurately locate the problem source. For those failure points with a specific spatial pattern, such as concentrated failure in the edge area of the wafer, they often point to systematic upstream process problems rather than sporadic accidental defects, but manual analysis is difficult to efficiently extract these high-value information from massive data and attribute them.

[0004] In view of this, it is desirable to propose an innovative production method of rotary rectifier chips. SUMMARY

[0005] In view of the above limitations in application, according to an aspect of the present application, a production method of a rotary rectifier chip is provided, which comprises: preparing a substrate layer, the substrate layer comprising an N-type monocrystalline silicon wafer base layer and an epitaxial layer grown on the N-type monocrystalline silicon wafer base layer; forming a PN junction on the substrate layer; fabricating metal electrodes for conduction for the P region and the N region of the PN junction to obtain a rotary rectifier chip embryo; passivating the rotary rectifier chip embryo to obtain a rotary rectifier chip layout; thinning and cutting the rotary rectifier chip layout to obtain a plurality of rotary rectifier chips; and performing chip testing and sorting on the plurality of rotary rectifier chips.

[0006] According to another aspect of the present application, a rotating rectifier chip is provided, which is produced by the production method of the rotating rectifier chip as described above.

[0007] Compared with the prior art, the rotating rectifier chip and the production method provided by the present application cover the whole process from the preparation of the substrate layer, the formation of the PN junction, the production of the metal electrode, the passivation protection, the wafer thinning and cutting, to the final chip testing and sorting. In the traditional chip manufacturing process, especially in the chip testing and sorting link, advanced yield management and fault diagnosis mechanisms are integrated. Instead of relying on manual visual inspection and experience judgment of the wafer map, the test results are intelligently analyzed, especially when the wafer yield is lower than the preset threshold, the wafer map image matrix can be automatically constructed, and the pattern recognition and attribution of the yield space distribution map can be carried out based on this. This data-driven analysis method can efficiently and objectively identify failure points with specific spatial patterns, thereby accurately pointing to systematic upstream process problems. This significantly overcomes the defects of the prior art, such as relying on manual experience judgment, low efficiency, strong subjectivity and difficulty in quickly locating systematic problems, realizes the automation and intelligentization from problem discovery to root cause diagnosis, greatly shortens the fault troubleshooting time, and significantly improves the production efficiency and product yield of the rotating rectifier chip. BRIEF DESCRIPTION OF DRAWINGS

[0008] The above and other objects, features and advantages of the present application will become more apparent from the following detailed description of embodiments of the present application taken in conjunction with the accompanying drawings. The accompanying drawings are provided to aid in understanding the embodiments of the present application, and constitute a part of the specification. The embodiments of the present application are explained with reference to the drawings, and are used to explain the present application, but do not constitute a limitation on the present application. In the drawings, the same reference numerals generally represent the same components or steps.

[0009] Figure 1 A flowchart of the production method of the rotating rectifier chip according to the embodiments of the present application.

[0010] Figure 2 A flowchart of step S2 in the production method of the rotating rectifier chip according to the embodiments of the present application.

[0011] Figure 3 A flowchart of step S6 in the production method of the rotating rectifier chip according to the embodiments of the present application.

[0012] Figure 4 A flowchart of step S61 in the production method of the rotating rectifier chip according to the embodiments of the present application.

[0013] Figure 5 A flowchart of step S62 in the production method of the rotating rectifier chip according to the embodiments of the present application. DETAILED DESCRIPTION

[0014] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0015] To address the deficiencies in the aforementioned technical background, this application proposes a method for manufacturing a rotating rectifier chip. Figure 1 This is a flowchart of a method for manufacturing a rotating rectifier chip according to an embodiment of this application. Figure 1 As shown, the method for manufacturing a rotating rectifier chip according to an embodiment of this application includes: S1, preparing a substrate layer, the substrate layer including an N-type single-crystal silicon wafer substrate layer and an epitaxial layer grown on the N-type single-crystal silicon wafer substrate layer; S2, forming a PN junction on the substrate layer; S3, fabricating metal electrodes for conducting electricity in the P-region and N-region of the PN junction to obtain a rotating rectifier chip preform; S4, passivating and protecting the rotating rectifier chip preform to obtain a rotating rectifier chip panel; S5, performing wafer thinning and dicing on the rotating rectifier chip panel to obtain multiple rotating rectifier chips; S6, performing chip testing and sorting on the multiple rotating rectifier chips.

[0016] In step S1, a substrate layer is prepared, comprising an N-type single-crystal silicon wafer substrate and an epitaxial layer grown on the N-type single-crystal silicon wafer substrate. It should be understood that in semiconductor device manufacturing, the substrate layer is the foundation of the entire chip structure, and its material selection and structural design are crucial to the electrical performance of the device, especially the withstand voltage, conduction loss, and switching characteristics of the rotating rectifier chip. For rectifier devices that need to withstand high reverse voltage and effectively conduct forward current, the characteristics of the substrate directly determine the reliability and efficiency of the device. To optimize the performance of the rotating rectifier chip, especially to achieve high withstand voltage while maintaining low on-resistance and effectively controlling the electric field distribution of the PN junction, this method uses an N-type single-crystal silicon wafer substrate and an epitaxial layer grown on it when preparing the substrate layer. This composite structure provides a high-resistivity drift region to withstand high reverse voltage, while the precise control of the doping concentration and thickness of the epitaxial layer provides an ideal region for the subsequent formation of the PN junction, thereby ensuring high withstand voltage while reducing forward voltage drop and improving the overall efficiency and reliability of the device.

[0017] In one implementation, step S1 is as follows: First, a high-purity N-type single-crystal silicon wafer is selected as the substrate layer. This substrate layer has a high resistivity; for example, an N-type silicon wafer with a resistivity in the range of 10 ohm-cm to 100 ohm-cm can be selected to ensure that the device has sufficient withstand voltage capability under reverse bias. Then, an N-type epitaxial layer is grown on the surface of the N-type single-crystal silicon wafer substrate layer using epitaxial growth technology. Epitaxial growth is a technique for growing a single-crystal thin film with the same crystal orientation on a single-crystal substrate; commonly used methods include chemical vapor deposition. During epitaxial growth, precise control of the epitaxial layer thickness and doping concentration is crucial. For example, for a rotating rectifier chip, the thickness of the epitaxial layer can be set between 5 micrometers and 50 micrometers, and the doping concentration can be set between 1 x 10^15 cm^-3 and 1 x 10^16 cm^-3. The specific values ​​are optimized according to the withstand voltage level and conduction loss requirements of the target device.

[0018] In step S2, a PN junction is formed on the substrate. Correspondingly, in the field of semiconductor devices, the PN junction is the core structure for realizing basic electrical functions such as rectification and amplification. For a rotating rectifier chip, its main function is to convert alternating current (AC) to direct current (DC), and this conversion process is achieved through the unidirectional conductivity of the PN junction. The PN junction allows current to flow freely in one direction (forward bias) while blocking current in the other direction (reverse bias), thereby achieving current rectification. Therefore, the quality of the PN junction, including its junction depth, doping concentration distribution, and junction integrity, directly determines key electrical parameters of the rotating rectifier chip, such as on-state voltage drop, reverse leakage current, and reverse breakdown voltage. To ensure that the rotating rectifier chip can efficiently and reliably complete the rectification task and meet specific withstand voltage and conduction loss requirements, the precise formation of the PN junction on the substrate is a crucial step in this method.

[0019] In one implementation, Figure 2 This is a flowchart of step S2 in the method for manufacturing a rotating rectifier chip according to an embodiment of this application. Figure 2 As shown, step S2, forming a PN junction on the substrate layer, includes: S21, growing a layer of silicon dioxide on the surface of the substrate layer by thermal oxidation to obtain a masking layer; S22, coating the masking layer with photoresist, exposing it to ultraviolet light through a mask with a specific pattern, and then forming a window pattern on the masking layer by development; S23, etching away the silicon dioxide exposed in the window pattern to expose the substrate layer underneath; S24, incorporating P-type impurities into the epitaxial layer below the window pattern by high-temperature diffusion or ion implantation to obtain the PN junction.

[0020] The detailed procedure of step S2 is as follows: first, step S21 is performed. This process places the substrate layer in a high-temperature oxidation furnace and performs heating in an oxygen-rich atmosphere, for example, dry or wet oxygen oxidation at a temperature range of 900°C to 1100°C for several hours. Specifically, dry oxygen oxidation is usually performed in a pure oxygen atmosphere, with slower growth but higher quality of the oxide layer; wet oxygen oxidation is performed in a mixed atmosphere of water vapor and oxygen, with faster growth. The thickness of the silicon dioxide (SiO2) layer needs to be accurately controlled, for example, it can be set to 0.5 to 1.5 microns, to ensure that it can effectively block impurity diffusion and act as an etching mask in subsequent processes, while avoiding the increase in difficulty of subsequent etching due to excessive thickness.

[0021] Next, step S22 is performed. Photoresist is a polymer material sensitive to ultraviolet light, which is first uniformly coated on the surface of the silicon dioxide layer by spin coating or other methods, forming a thin film. Subsequently, the mask plate (which has the geometric shape of the PN junction region, such as a circle or a rectangle) is irradiated with ultraviolet light through high-precision alignment. The ultraviolet light passes through the transparent area of the mask plate, causing the photoresist to undergo a photochemical reaction, for example, positive photoresist becomes soluble in the developer after exposure, while negative photoresist becomes insoluble. Subsequently, the exposed or unexposed photoresist is selectively dissolved by the developer, thereby accurately replicating the desired window pattern on the silicon dioxide mask layer, which will define the final position and size of the PN junction, and its accuracy directly affects the integration and performance of the device.

[0022] Subsequently, step S23 is performed. The etching process uses wet etching (such as using dilute hydrofluoric acid solution) or dry etching (such as reactive ion etching). Wet etching has the advantages of low cost and simple operation, but may have isotropic etching leading to pattern distortion; dry etching has anisotropic etching capability and can achieve more precise pattern transfer, but has higher equipment cost. The etchant selectively etches away the silicon dioxide in the window area that is not covered by the photoresist, while preserving the area protected by the photoresist, thereby exposing the surface of the underlying N-type single crystal silicon wafer base layer or epitaxial layer, preparing for subsequent impurity doping. The end point control of etching is crucial, which needs to ensure that the silicon dioxide layer is completely removed without damaging the underlying silicon substrate.

[0023] Finally, step S24 is performed. If high temperature diffusion is used, the substrate layer is placed in an atmosphere containing a source of P-type impurities (e.g., boron) and heated at a high temperature, e.g., 950°C to 1150°C, to cause P-type impurity atoms to diffuse through the silicon lattice into the exposed N-type silicon region to form the PN junction. The diffusion time and temperature determine the junction depth and doping concentration, e.g., the diffusion time can be set to 30 minutes to 2 hours to achieve the desired junction depth and doping profile. If ion implantation is used, P-type impurity ions (e.g., boron ions) are accelerated and bombarded at high energy to the surface of the substrate layer to implant precisely to a predetermined depth. The energy and dose of the ion implantation can be precisely controlled, e.g., the implantation energy can be set to 20 keV to 100 keV and the dose can be set to 1 x 10^13 cm"2 to 1 x 10^15 cm"2 to form a PN junction with a specific junction depth and doping profile. Annealing is also needed after ion implantation to repair the lattice damage and activate the implanted impurities. Finally, a P-type region is formed in the N-type substrate to construct a PN junction with rectifying characteristics, the electrical characteristics of which will directly affect the performance of the spin rectifier chip.

[0024] In step S3, metal electrodes for conduction are fabricated for the P and N regions of the PN junction to obtain a spin rectifier chip embryo. It should be understood that although the successful formation of the PN junction endows the chip with basic electrical functions, to make it a truly usable electronic component and to effectively electrically connect with external circuits, the problem of current introduction and export also needs to be solved. The P and N regions of the PN junction are semiconductor materials themselves, and direct contact with external wires often forms unstable Schottky junctions or generates large contact resistance, resulting in energy loss, signal distortion, and even affecting the normal operation of the device. In order to ensure that the spin rectifier chip can efficiently collect and transmit current, minimize conduction loss, and ensure the stability and reliability of the device in actual application, it is an indispensable key step to fabricate metal electrodes for conduction for the P and N regions of the PN junction.

[0025] In one implementation, the specific process of step S3 is as follows: first, after the formation of the PN junction, contact holes are accurately opened above the P and N regions to expose the underlying silicon surface through photolithography and etching processes. Specifically, this includes uniformly coating a layer of photoresist on the wafer surface, then using a mask with a contact hole pattern for ultraviolet exposure, and removing the exposed or unexposed photoresist through development to form a photoresist mask. Subsequently, using plasma etching or wet chemical etching techniques, the medium layer such as silicon oxide or silicon nitride passivation layer under the photoresist mask is selectively removed, thereby accurately opening contact holes above the P and N regions with a size and position precisely aligned with the PN junction region to expose a clean silicon surface, e.g., the minimum line width of the contact hole can be set to 0.5 microns to meet the integration requirements of the device.

[0026] Subsequently, a thin metal film is uniformly deposited over the entire wafer surface by physical vapor deposition techniques such as sputtering or chemical vapor deposition. Sputtering in physical vapor deposition is a technique that bombards a target material with high-energy ions to cause atoms of the target material to detach and deposit onto the wafer surface, resulting in good film uniformity and density. Chemical vapor deposition, on the other hand, forms a thin film by a chemical reaction of gaseous precursors on the wafer surface. Commonly used metal materials include aluminum (Al) due to its low cost, ease of etching, and good electrical conductivity, or multilayer metal systems such as titanium / nickel / silver (Ti / Ni / Ag) or titanium / nickel / gold (Ti / Ni / Au), in which the titanium layer serves as an adhesion layer, the nickel layer as a barrier layer, and the silver or gold layer as a high-conductivity layer. These multilayer structures can provide superior adhesion, diffusion barrier capability, and ohmic contact properties. The total thickness of the metal layer needs to be precisely controlled, for example, it can be set between 0.5 microns and 2 microns to ensure sufficient electrical conductivity and mechanical strength while avoiding difficulties in subsequent etching or poor step coverage due to excessive thickness.

[0027] Next, the deposited metal layer is patterned again using photolithography and etching techniques. Specifically, a layer of photoresist is again applied on the deposited metal layer, and ultraviolet light exposure and development are performed through a mask with electrode patterns to form a precise photoresist mask that will define the final metal electrode pattern. Subsequently, a metal etching process is used, such as dry etching, for example, chlorine-based plasma etching for aluminum, or fluorine-based plasma etching for titanium, nickel, etc., or wet etching using a specific chemical solution, to selectively remove the metal regions not protected by the photoresist, thereby precisely forming the desired metal electrode pattern over the P and N regions. For example, the minimum line width and pitch of the electrodes can be controlled within 1 micron to meet the size requirements of the device.

[0028] Finally, an annealing process is performed, such as alloying annealing at a temperature of 400°C to 500°C for several minutes to tens of minutes. This step aims to promote the reaction between the metal and silicon, forming stable metal silicides such as TiSi2, NiSi, etc., thereby significantly reducing the contact resistance between the metal and the semiconductor, ensuring that the current can efficiently flow from the semiconductor region to the metal electrode and vice versa. In this way, a spin rectifier chip embryo with complete electrode structure is finally obtained.

[0029] In step S4, the rotating rectifier chip embryo is passivated to obtain a rotating rectifier chip. Accordingly, after the PN junction and metal electrode are completed, the surface of the chip embryo, especially the edge region of the PN junction and the metal electrode, is directly exposed to the air. This exposed state makes the chip extremely susceptible to environmental factors, such as moisture, dust, ionic contaminants, and mechanical stress in the air. These external factors can cause defect states on the semiconductor surface, increase the surface leakage current, reduce the reverse breakdown voltage of the PN junction, and even cause corrosion of the metal electrode, thereby seriously affecting the electrical performance, reliability, and long-term stability of the chip. In order to effectively isolate the sensitive internal structure of the chip from the external environment, suppress surface effects, improve the voltage withstand capability and anti-moisture and anti-pollution capability of the device, and provide necessary mechanical protection, the rotating rectifier chip embryo needs to be passivated.

[0030] In one implementation, the specific process of step S4 is as follows: first, after the metal electrode is completed, the wafer surface is thoroughly cleaned to remove possible residual organic matter, particles, metal ions, or process byproducts. This cleaning uses a multi-step wet chemical cleaning process, for example, a standard RCA cleaning process can be used, including ammonia-hydrogen peroxide mixed solution cleaning (SC-1) to remove organic matter and particles, hydrochloric acid-hydrogen peroxide mixed solution cleaning (SC-2) to remove metal ions, and dilute hydrofluoric acid cleaning to remove surface oxide layers, ensuring that the passivation layer can be well attached and have excellent electrical performance, avoiding the generation of interface defects.

[0031] Subsequently, a passivation layer is uniformly grown on the entire wafer surface by thin film deposition technology. Common passivation materials include silicon dioxide, silicon nitride, or polyimide, etc. For example, a silicon nitride thin film can be deposited using plasma enhanced chemical vapor deposition (PECVD) technology. PECVD technology uses radio frequency or microwave energy to generate plasma at low pressure, activates the reaction gas (such as silane and ammonia), and causes it to chemically react and deposit into a film on the wafer surface at a relatively low temperature, for example, 300°C to 400°C. This low-temperature deposition is crucial for protecting the metal electrode structure that has been formed, avoiding the adverse effects of high temperature on the metal layer, such as metal grain growth, increased stress, or undesirable reactions with silicon. During the deposition process, by precisely controlling the flow ratio of the reaction gases (such as silane and ammonia), radio frequency power, cavity pressure, and substrate temperature, a silicon nitride thin film with specific stress, density, refractive index, and dielectric constant can be obtained, thereby optimizing its passivation effect and mechanical performance. The thickness of the passivation layer needs to be set according to the voltage withstand requirement and mechanical protection requirement of the device, for example, it can be set between 0.5 microns and 1.5 microns, to ensure that it can effectively block impurity diffusion, provide sufficient dielectric strength and mechanical strength, while avoiding excessive thickness leading to subsequent etching difficulties or excessive stress.

[0032] After the passivation layer is deposited, a photolithography and etching process is needed to open a window in the area of the metal pad that needs to be bonded with external leads. Specifically, a layer of photoresist is first applied uniformly on the passivation layer, then exposed to UV light through a high-precision aligned mask with a pad opening pattern etched on it, and the exposed or unexposed photoresist is removed by developing to form a precise photoresist mask. Subsequently, dry etching such as reactive ion etching is used with a fluorine-based gas mixture such as SF6 or CF4 or wet etching technology to selectively remove the passivation layer above the pad area, exposing the underlying metal pad for subsequent lead bonding. The etching process needs to be precisely controlled to ensure that the pad is completely exposed without damaging the surrounding passivation layer, while maintaining good etching sidewall morphology to facilitate subsequent lead bonding. Finally, a rotary rectifier chip panel with a complete passivation protection layer is obtained, and the internal sensitive structure is effectively protected.

[0033] In step S5, the rotary rectifier chip panel is thinned and cut to obtain a plurality of rotary rectifier chips. Accordingly, the wafer usually has a thickness of several hundred microns, which poses a challenge to subsequent packaging, heat dissipation, and the size and weight of the final product. In particular, for power devices such as rotary rectifier chips, heat is generated during operation, and the thickness of the chip directly affects the heat dissipation efficiency. A too thick chip not only increases the packaging cost and volume, but more importantly, hinders the conduction of heat from the inside of the chip to the heat sink, causing the chip temperature to rise, thereby affecting the performance, reliability, and life of the device. In addition, in order to separate the thousands or even tens of thousands of independent chips on the wafer for independent testing, packaging, and application, the wafer needs to be cut into individual chips to meet the modern electronic product demand for miniaturization, lightweight, high-efficiency heat dissipation, and independent processing and application of individual chips.

[0034] In one implementation, the detailed procedure of step S5 is as follows: First, wafer thinning is performed. Before thinning, a protective film is attached to the front side (device side) of the wafer, for example, a UV-curable protective tape, which serves to prevent damage or contamination to the already fabricated device structure by grinding liquid, particles or mechanical stress during the thinning process. Subsequently, the wafer is placed with the back side facing up, and the back side of the wafer is thinned by mechanical grinding or chemical mechanical polishing techniques. Mechanical grinding uses a high-speed rotating diamond grinding wheel to remove silicon material by the mechanical action of the grinding particles, which can quickly coarsely thin the wafer thickness from the initial several hundred microns, for example, 700 microns, to near the target thickness. In order to obtain a finer surface and remove grinding damage, multi-stage grinding is used, gradually transitioning from coarse grinding wheels to fine grinding wheels. Chemical mechanical polishing combines the action of mechanical grinding and chemical corrosion, by the chemical components in the grinding liquid reacting with the silicon surface, while the mechanical action of the grinding pad removes the reaction products, thereby obtaining a more flat, damage-free surface, and effectively eliminating the subsurface damage and stress that may be introduced by mechanical grinding. The target thickness of the thinning depends on the application requirements of the final chip, for example, for a rotating rectifier chip, the thickness is thinned to between 50 microns and 200 microns, and the specific value is optimized according to the device heat dissipation requirements, mechanical strength and subsequent packaging method. For example, for high-power applications, a thinner chip such as 50 microns may be required to improve heat conduction efficiency, while for applications with higher requirements for mechanical strength, a thicker chip such as 150 microns may be selected. After thinning is completed, the protective film on the front side is removed, and the wafer is thoroughly cleaned to remove all residual grinding particles and chemicals.

[0035] Subsequently, wafer cutting is performed. Before cutting, the wafer is attached to a cutting tape with certain adhesion, which can fix the cut chips in place to prevent them from splashing or shifting during the cutting process, and then reduce the adhesion by means such as ultraviolet irradiation in the subsequent chip picking process to facilitate chip separation. The cutting process uses diamond blade cutting or laser cutting technology. Diamond blade cutting cuts the wafer into individual chips along the pre-designed cutting path (scribing path) by a high-speed rotating ultra-thin diamond blade, for example, with a thickness of 20-50 microns. The width of the blade, cutting speed, for example, 50-200 mm / s, and feed depth need to be precisely controlled to ensure the neatness of the cutting edge, minimize edge collapse and cracks, and ensure the integrity of the chip. Deionized water is sprayed during the cutting process for cooling and flushing to remove the debris and heat generated during cutting. Laser cutting uses a high-energy laser beam (for example, nanosecond or picosecond laser) to melt or vaporize silicon material, achieving non-contact cutting. This method has the advantages of fast cutting speed, narrow cutting path, no mechanical stress, no edge collapse and cracks, etc., and is especially suitable for ultra-thin wafers or chips sensitive to mechanical stress, and can achieve more complex cutting paths. The cutting path is a pre-planned device-free area during chip design, with a width of 50-100 microns to ensure that the adjacent chips are not damaged during cutting and provide enough space for the blade or laser beam. Finally, a complete rotary rectifier chip layout is divided into multiple independent, size-accurate rotary rectifier chips.

[0036] In step S6, the plurality of rotary rectifier chips are tested and sorted. That is, in the complex manufacturing process of semiconductor chips, although each process is strictly controlled, due to the microscopic characteristics of the material, the precision limitations of the equipment, and the uncontrollability of environmental factors, the thousands or even tens of thousands of chips produced on the wafer often have differences in electrical performance and reliability. After a series of precise processes such as substrate preparation, PN junction formation, metal electrode fabrication, passivation protection, and wafer thinning and cutting, the internal structure of a single chip may have minor defects, uneven doping, or stress concentration, which may cause the chip to fail to meet the expected electrical parameters or malfunction in actual application. In order to ensure that only rotary rectifier chips that meet the design specifications and performance requirements can enter the subsequent packaging link, avoid delivering unqualified products to customers, thereby protecting product quality, reducing production costs, and maintaining corporate reputation, the plurality of rotary rectifier chips need to be tested and sorted.

[0037] In one implementation, Figure 3 The flowchart of step S6 in the production method of the rotary rectifier chip according to the embodiment of the present application. As shown in FIG. 6, the step S6 includes steps S61-S63. Figure 3As shown, step S6, the chip testing and sorting of the plurality of rotary rectifier chips, comprising: S61, in response to the wafer yield being lower than the preset threshold, constructing a wafer map image matrix based on the test results of the plurality of rotary rectifier chips; S62, based on the wafer map image matrix, performing pattern recognition and attribution of the yield space distribution map to obtain a root cause diagnosis suggestion.

[0038] It can be understood that in the chip testing and sorting process, it is not enough to only know whether the overall yield of the wafer is qualified. When the wafer yield is lower than the preset threshold, it means that there is some kind of abnormality in the production process, but the yield value alone cannot reveal the specific root cause of the problem. For example, the yield drop may be due to the failure of a component of the equipment, resulting in local area chip failure, or it may be due to process parameter drift, resulting in a certain specific defect showing a specific spatial distribution pattern on the wafer. The traditional troubleshooting method often relies on the experience and manual analysis of engineers, which is low in efficiency and easy to miss key information. In order to more efficiently and accurately identify the spatial distribution pattern of unqualified chips on the wafer, so as to quickly locate and diagnose the root cause of the fault in the production process. Therefore, in order to convert discrete test data into visual information that can be processed and recognized by image, the wafer map image matrix is constructed.

[0039] In one implementation, Figure 4 The flow chart of step S61 in the production method of the rotary rectifier chip according to the embodiment of the present application is shown. As shown Figure 4 As shown, step S61, in response to the wafer yield being lower than the preset threshold, constructing a wafer map image matrix based on the test results of the plurality of rotary rectifier chips, comprising: S611, constructing a wafer map image element matrix; S612, traversing the test results of the plurality of rotary rectifier chips and performing the following operations: if the test result of the rotary rectifier chip is unqualified, filling zero in the corresponding position of the wafer map image element matrix, if the test result of the rotary rectifier chip is qualified, filling one in the corresponding position of the wafer map image element matrix.

[0040] The specific flow of step S61 is as follows: first, step S611 is performed. In specific implementation, the layout information of the wafer needs to be obtained, including the number of rows and columns of chips on the wafer. For example, if the arrangement of chips on a wafer is 100 rows and 100 columns, a 100x100 two-dimensional matrix will be constructed. Each element of this matrix will correspond to a chip position on the wafer. In the initial construction, all elements in the matrix can be assigned a default null value or placeholder, indicating that the chip state of the position has not been filled. The size of this matrix is determined in advance according to the wafer design and chip layout, for example, for a wafer with a diameter of 8 inches, if the size of a single chip is 2 mm x 2 mm, the wafer may contain thousands of chips, thus determining the exact dimensions of the matrix.

[0041] Subsequently, step S612 is performed. In specific implementation, after the test equipment completes the electrical performance test of all chips on the wafer, it will generate a detailed test report containing the unique identification of each chip (its row and column coordinates on the wafer) and its test results (pass or fail). The processing program will read each chip data in this test report one by one. For each chip, first parse its physical coordinates on the wafer, then update the value of the corresponding position in the wafer map image element matrix according to the test result of the chip. If the test result of the chip is determined to be unqualified, the element value of the corresponding position in the matrix is set to 0; if the test result of the chip is determined to be qualified, the element value of the corresponding position in the matrix is set to 1. For example, if the test report shows that the chip located at the 5th row and 10th column of the wafer passes the test, the value of the corresponding position in the matrix is set to 1; if the chip at the 5th row and 11th column fails the test, the value is set to 0. In this way, the entire wafer map image element matrix is filled with a binary image composed of 0 and 1, where 1 represents the pixel point of a qualified chip and 0 represents the pixel point of an unqualified chip, intuitively showing the yield spatial distribution of chips on the wafer.

[0042] Correspondingly, when the wafer yield is lower than the preset threshold, it means that there is some abnormality in the production process, but the yield value alone cannot reveal the specific root cause of the problem. For example, the yield drop may be due to the failure of a component of the equipment, causing local area chip failure, or it may be due to process parameter drift, causing a certain type of defect to exhibit a specific spatial distribution pattern on the wafer. In order to more efficiently and accurately identify the spatial distribution pattern of unqualified chips on the wafer, thereby quickly locating and diagnosing the root cause of the failure in the production process, the pattern recognition and attribution of the yield spatial distribution map based on the wafer map image matrix in this method is to convert discrete test data into visual information that can be processed and recognized by image patterns, and further extract meaningful features from it.

[0043] In one implementation,Figure 5 A flow chart of step S62 in the production method of the rotating rectifier chip according to the embodiments of the present application. As shown, step S62, based on the wafer map image matrix, pattern recognition and attribution of the yield spatial distribution map are performed to obtain the root cause diagnosis suggestion, including: S621, extracting wafer yield spatial distribution global features from the wafer map image matrix; S622, extracting wafer yield regional spatial distribution features from the wafer map image matrix; S623, extracting wafer yield distribution texture features from the wafer map image matrix; S624, splicing wafer yield spatial distribution global features, wafer yield regional spatial distribution features and wafer yield distribution texture features into wafer yield distribution feature vectors; S625, based on the wafer yield distribution feature vectors, generating the root cause diagnosis suggestion. Figure 5

[0044] The specific flow of step S62 is as follows: first, step S621 is performed. First, the overall yield of the wafer is calculated, that is, by counting the number of elements with a value of 1 (qualified chip) in the wafer map image matrix, and dividing it by the total number of all valid chip positions in the matrix. In addition, in order to capture the global distribution trend more meticulously, the wafer can be divided into multiple concentric regions. For example, for a wafer with a diameter of 200 mm, a series of radius values such as 50 mm, 90 mm and 100 mm can be predefined, so as to divide the wafer into a center circular region (radius 0-50 mm), a middle annular region (radius 50-90 mm) and an edge annular region (radius 90-100 mm). Then, the number of qualified chips in each region is counted respectively, and the respective regional yield is calculated. These regional yields can effectively identify whether there is a center effect such as the center region yield being significantly lower than the edge, or an edge effect such as the edge region yield being significantly lower than the center, which are often related to global process parameters such as temperature, gas flow or etching uniformity in the wafer processing process. These calculated overall yield and each concentric region yield together constitute the global features of the wafer yield spatial distribution.

[0045] ​Subsequently, step S622 is performed. This step employs a sliding window technique to traverse the wafer map image matrix with a pre-set window size, e.g., 5x5 or 10x10 chip units. For each sliding window, the local yield inside it is calculated, i.e., the proportion of good chips or the aggregation level of bad chips, i.e., the number of bad chips. By analyzing the yield variation of these local regions, the cluster distribution of bad chips (such as local contamination), linear distribution (such as scratches) or point distribution (such as random defects) can be identified. In addition, in order to more accurately quantify these local abnormalities, the connected component analysis method in image processing can also be used. This method can identify all regions composed of continuous 0 (bad chips) in the wafer map image matrix, and each independent continuous region is regarded as a connected component. For each identified connected component, its geometric features can be extracted, such as area, i.e., the number of bad chips contained, perimeter, aspect ratio, i.e., the ratio of the longest axis to the shortest axis, compactness, i.e., the ratio of the square of the perimeter to the area, and the principal axis direction. For example, a long and narrow low yield area, whose aspect ratio will be significantly greater than 1, may indicate a scratch defect generated during wafer transmission or processing; while a nearly circular low yield area, whose compactness is close to 1, may indicate particle contamination or local hot spot effect.

[0046] Next, step S623 is performed. Texture features are calculated by employing a gray level co-occurrence matrix (GLCM). For a binary wafer map image matrix (0 represents bad and 1 represents good), GLCM is constructed by counting the frequency of pixel pairs in a specific direction and distance, for example, a good chip next to a bad chip. From GLCM, various texture features can be derived, such as: contrast, reflecting the local gray level variation and the lightness and darkness of the texture, high contrast may indicate that there is a clear boundary between good and bad chips; energy, reflecting the uniformity of the image and the coarseness of the texture, high energy indicates that the uniformity of the image is better; homogeneity, reflecting the smoothness of local variation, high homogeneity indicates that the texture is more uniform; correlation, reflecting the linear dependence of pixel values in a specific direction in the image. In addition, the run length matrix (GLRLM) can also be used to extract the length distribution features of consecutive good or bad chips in different directions. GLRLM counts the length and number of continuous pixel strings (runs) with a specific gray value (0 or 1) in a given direction. This helps to identify periodic defects (such as periodic stripes caused by device vibration) or stripe-like defects (such as linear low yield areas caused by uneven cleaning).

[0047] Then, step S624 is performed. All the numerical features extracted in the previous three steps are integrated into a unified, high-dimensional numerical vector. For example, if the global feature extracts 5 numerical values, such as the overall yield, the yield of three concentric regions, and the total number of unqualified chips, the region feature extracts 10 numerical values, such as the maximum connected domain area, the average connected domain aspect ratio, the local yield standard deviation, etc., and the texture feature extracts 8 numerical values, such as the contrast, energy, homogeneity, correlation of GLCM, and short run emphasis, long run emphasis of GLRLM, etc., the wafer yield distribution feature vector finally spliced will contain 23 numerical values.

[0048] Finally, in step S625. In one implementation, step S625, based on the wafer yield distribution feature vector, the root cause diagnosis suggestion is generated, including: S6251, inputting the wafer yield distribution feature vector into a pre-trained SVM model to obtain a predicted pattern category; S6252, searching the predicted pattern category in a fault knowledge base to obtain a list of potential high-risk processes; S6253, based on the list of potential high-risk processes, extracting process deviation reports from the process history of the wafer object; S6254, based on the predicted pattern category and the process deviation reports, generating the root cause diagnosis suggestion.

[0049] The specific process of step S625 is as follows: first, step S6251 is performed. It can be understood that, in order to accurately identify the defect pattern of the wafer, the wafer yield distribution feature vector containing the local-global spatial distribution feature and the distribution texture feature will be input into a support vector machine (SVM) model. Considering the diversity of these input features and the complexity of the data distribution, the support vector machine preferably uses a radial basis function (RBF) as a kernel function to handle non-linear relationships and fit complex decision boundaries. However, even with the RBF kernel function, the numerical range, distribution pattern difference between different feature dimensions, and the potential inconsistency between local and global features can still affect the classification performance of the SVM model, resulting in insufficient fitting accuracy of the predicted pattern category. In order to further improve the decision consistency of the local-global spatial distribution feature and the distribution texture feature under the radial basis function framework of the support vector machine, thereby improving the fitting accuracy of the predicted pattern category, the wafer yield distribution feature vector needs to be further pre-adjusted for probability density distribution before being input into the support vector machine model.

[0050] Step S6251, inputting the wafer yield distribution feature vector into a pre-trained SVM model to obtain a predicted pattern category, includes: first, performing feature mean-based offset constraint reinforcement on the wafer yield distribution feature vector to obtain a reinforced wafer yield distribution feature vector, i.e. ; wherein, is each feature value in the wafer yield distribution feature vector, is the feature mean value of the wafer yield distribution feature vector, is each feature value in the reinforced wafer yield distribution feature vector. It should be understood that for each component in the wafer yield distribution feature vector, the reinforcement processing is performed on the basis of the mean value of all vector values, that is, the arithmetic mean of all component values of the feature vector, through a nonlinear function. The function acts like a nonlinear transformation with mean constraint, which can stretch or compress the feature value near the mean value , so as to effectively block the tail probability of the feature value deviating from the mean value, and avoid the reinforcement of extreme discrete distribution. For example, if a feature value is much greater or much smaller than the mean value , after the function processing, the reinforced value will be adjusted to be more close to the mean value in value, but the relative size relationship is still retained. In this way, the feature distribution of the wafer yield distribution feature vector achieves balanced mean probability field coverage in the high-dimensional feature space, avoids local overfitting or center sparsity deviating from the mean value, and makes the radial basis function more robust in spatial distribution.

[0051] Then, the distance directionality modulation is performed on the basis of the distance directionality modulation of the reinforced wafer yield distribution feature vector with respect to the wafer yield distribution feature vector to obtain a distance directionality modulation coefficient, that is: ; wherein, is the distance directionality modulation coefficient. Correspondingly, in order to correct the distance metric deviation in the feature space, especially the limitation of the Euclidean distance in processing direction-sensitive problems, so that the local features (such as local spatial distribution features and distribution texture features) and the direction distribution of the mean probability field are consistent, the distance directionality modulation coefficient is calculated in the present application. That is quantifies the overall directionality or offset change of the feature vector after the offset constraint reinforcement, which provides a global modulation factor for subsequent feature distribution space resonance, ensuring that the overall directionality of the local feature with respect to the original feature vector can be considered when adjusting the local feature.

[0052] Then, based on the distance directionality modulation coefficient, the feature distribution space resonance is performed on the reinforced wafer yield distribution feature vector and the wafer yield distribution feature vector to obtain an optimized wafer yield distribution feature vector, that is: ; wherein, is the exponential function value with the natural constant e as the base, is the optimized wafer yield distribution feature vector. It should be understood that by introducing the kernel function to resonate the feature distribution space, a probability aggregation effect can be formed in the decision boundary. This exponential function combines the distance directionality modulation coefficient and the square difference of the feature components before and after reinforcement. For those feature components that have a large difference after reinforcement, such as larger, will be significantly adjusted, thereby achieving a distance tuning effect in the feature space, so that similar patterns are more closely aggregated in the feature space while maintaining the synergy of the global probability field. This resonance processing makes the relationship between the local-global spatial distribution features and the distribution texture features of the feature vector more coordinated and unified before inputting the SVM model, thereby improving the separability of the data in the feature space.

[0053] Finally, the optimized wafer yield distribution feature vector is input into the pre-trained SVM model to obtain the predicted pattern class. That is, after the above probability density distribution pre-conditioning, the components of the wafer yield distribution feature vector are more balanced in numerical distribution, and the directionality between local and global features is also corrected, so that the distribution of data points in the feature space is more conducive to the classification of the SVM model with a radial basis function kernel. When this optimized wafer yield distribution feature vector is input into the pre-trained SVM model, the model can more accurately identify the defect pattern class it belongs to, thereby improving the fitting accuracy of the predicted pattern class and providing a more reliable input for subsequent fault diagnosis. The specific implementation is as follows: the SVM (Support Vector Machine) model is a supervised learning classifier that finds an optimal hyperplane in a high-dimensional feature space to maximize the separation between different class data points, thereby achieving effective classification of data. The SVM model has been pre-trained with a large amount of historical wafer data before being put into use. These historical data contain a variety of known wafer yield distribution feature vectors, and each vector has been manually labeled with its corresponding defect pattern class, such as center low yield pattern, edge high yield pattern, scratch pattern, cluster defect pattern, etc. When the optimized wafer yield distribution feature vector is input into this pre-trained SVM model, the model will calculate the position of the feature vector in the multi-dimensional space and determine which side of the classification hyperplane it is on. By calculating the distance of the vector to each class hyperplane, the model can determine the defect pattern class it is most likely to belong to and output the prediction result. For example, if the input feature vector shows that the center area yield is significantly lower than the edge, the SVM model may predict it as a center low yield pattern.

[0054] Subsequently, step S6252 is performed. It should be appreciated that the failure knowledge base is a structured database or expert system that stores a large amount of historical experience and domain knowledge, associating various known defect pattern categories with potential high-risk production processes that lead to these patterns. The knowledge base can be designed as a mapping table or a relational database, where each defect pattern category is associated with one or more production processes that can potentially lead to the pattern, such as the center low yield pattern corresponding to diffusion, ion implantation, thin film deposition, etc. processes; the edge high yield pattern corresponding to etching, cleaning, lithography, etc. processes; the scratch pattern corresponding to wafer transport, grinding, cutting, etc. processes. When a predicted pattern category is obtained from the SVM model, for example, the center low yield pattern, the process uses this category as a query key to perform an exact match or fuzzy match search in the failure knowledge base. The search operation traverses all entries in the knowledge base, finds the record corresponding to the input pattern category, and extracts the predefined list of potential high-risk processes in this record. For example, if the predicted pattern category is the center low yield pattern, the search result may return a list containing diffusion, ion implantation, thin film deposition, etc. processes.

[0055] Next, step S6253 is performed. Each wafer has a detailed process history record during the manufacturing process, including the equipment used in each process, the process parameters set, the actual measured parameter values, and any abnormal events or alarm information. The process will extract the detailed data of these specific processes from the complete process history database of the current wafer according to the list of potential high-risk processes, according to the unique identification of the current wafer. Then, compare these actual process parameters with the preset process control limits or standard values. Any parameter that exceeds the control limits, has abnormal fluctuations, or has significant deviations from the standard values will be recorded to form a process deviation report. For example, if the diffusion process is listed as high-risk, the process will check the temperature curve, gas flow, time, etc. parameters of the wafer in the diffusion furnace, and report specific deviations such as the diffusion furnace center area temperature exceeding the upper limit by 2°C at a certain time period or the diffusion gas flow has periodic fluctuations.

[0056] Finally, step S6254 is performed. In one implementation, step S6254, generating the root cause diagnosis suggestion based on the predicted pattern category and the process bias report, comprises: inputting the predicted pattern category and the process bias report into a pre-defined Prompt template, and then inputting it into a large language model to obtain the root cause diagnosis suggestion. In specific implementation, one or more pre-defined Prompt templates need to be defined first. These templates are structured text strings that contain placeholders for inserting the predicted pattern category and the process bias report. For example, a Prompt template can be designed as: "The wafer yield presents the following pattern: [predicted pattern category]. Meanwhile, the process history report shows the following bias: [process bias report]. Please provide detailed root cause diagnosis suggestions and preliminary troubleshooting directions based on this information." This template aims to provide a clear context and task instruction for the large language model. Subsequently, the predicted pattern category, such as center low yield pattern, and the process bias report, such as the center area temperature of the diffusion furnace exceeds the upper limit by 2°C at a certain time period, and the diffusion gas flow has periodic fluctuations, are injected into the corresponding placeholders in the pre-defined Prompt template. After injection, the complete Prompt string may become: "The wafer yield presents the following pattern: center low yield pattern. Meanwhile, the process history report shows the following bias: the center area temperature of the diffusion furnace exceeds the upper limit by 2°C at a certain time period, and the diffusion gas flow has periodic fluctuations. Please provide detailed root cause diagnosis suggestions and preliminary troubleshooting directions based on this information." Finally, this filled-in Prompt string is input into a pre-trained large language model. The large language model is built based on a deep neural network model with a Transformer architecture, and its core is a self-attention mechanism. This mechanism enables the model to dynamically evaluate the correlation strength and importance between different words in the input sequence when processing input text, thereby capturing long-range dependencies and complex contextual semantics. For example, when processing the center low yield pattern, the model can simultaneously focus on related words such as diffusion furnace temperature, understanding their potential causal relationships. The model contains multiple layers of stacked Transformer encoder or decoder blocks, each composed of a self-attention layer and a feedforward neural network. Through the complex interaction of these layers, the model can perform multi-level abstraction and feature extraction on the input information. The model has been pre-trained on a large amount of text data, learning rich language knowledge, world knowledge, and certain reasoning ability. After receiving the Prompt with specific information injected, the large language model uses its internal weights and bias parameters (obtained through large-scale unsupervised learning during pre-training, used to encode statistical rules and semantic information of language) to deeply understand and analyze the input text. It identifies the defect pattern and process bias mentioned in the Prompt, and based on the knowledge it learned during pre-training, performs logical reasoning and correlation analysis.Specifically, the model will predict the next most likely word based on the context of the input Prompt, and iterate this process until a coherent, reasonable, and professional root cause diagnosis recommendation is generated. For example, for the above Prompt, the large language model may generate the following recommendation: "Diagnosis: Low yield pattern in the center of the wafer, possibly due to abnormal temperature uniformity in the center area of the diffusion furnace during the diffusion process. Recommendation: Immediately check the diffusion furnace temperature control sensor and perform furnace temperature uniformity calibration. At the same time, review whether the diffusion gas flow control system has fluctuations to ensure its stability." This can integrate discrete, specialized information into easy-to-understand and implement recommendations, significantly improving the efficiency and accuracy of fault diagnosis.

[0057] In summary, the production method of the rotating rectifier chip based on the embodiments of the present application is illustrated, which covers the whole process from preparing the substrate layer, forming the PN junction, making the metal electrode, passivation protection, wafer thinning and cutting, to the final chip testing and sorting. In the traditional chip manufacturing process, especially in the chip testing and sorting link, advanced yield management and fault diagnosis mechanisms are integrated. Instead of relying solely on manual visual inspection of wafer maps and experience-based judgment, intelligent analysis of test results is performed, especially when the wafer yield is below the preset threshold, a wafer map image matrix can be automatically constructed, and based on this, pattern recognition and attribution of the yield space distribution map can be performed. This data-driven analysis method can efficiently and objectively identify failure points with specific spatial patterns, thereby accurately pointing to systematic upstream process problems. This significantly overcomes the defects of relying on manual experience judgment, low efficiency, strong subjectivity and difficulty in quickly locating systematic problems in the prior art, realizes the automation and intelligentization from problem discovery to root cause diagnosis, greatly shortens the fault troubleshooting time, and significantly improves the production efficiency and product yield of the rotating rectifier chip.

[0058] Specifically, in one specific example of the present application, a rotating rectifier chip is also included, which is prepared by the above-mentioned production method of the rotating rectifier chip.

[0059] The above has described various embodiments of the present disclosure, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes are obvious to those skilled in the art without departing from the scope and spirit of the described embodiments. The choice of terms used herein is intended to best explain the principles, practical applications, or improvements to the technology in the market of the embodiments, or to enable other ordinary skilled persons in the art to understand the embodiments disclosed herein.

Claims

1. A method for manufacturing a rotating rectifier chip, characterized in that, include: A substrate layer is prepared, the substrate layer comprising an N-type single-crystal silicon wafer substrate layer and an epitaxial layer grown on the N-type single-crystal silicon wafer substrate layer; A PN junction is formed on the substrate layer; Metal electrodes for conducting electricity are fabricated for the P and N regions of the PN junction to obtain a rotating rectifier chip blank. The rotating rectifier chip blank is passivated to obtain a rotating rectifier chip panel. The rotating rectifier chip panel is thinned and cut into wafers to obtain multiple rotating rectifier chips. The process of testing and sorting the multiple rotating rectifier chips includes: in response to a wafer yield rate lower than a preset threshold, constructing a wafer image matrix based on the test results of the multiple rotating rectifier chips; performing pattern recognition and attribution of the yield spatial distribution map based on the wafer image matrix to obtain root cause diagnosis suggestions; extracting global features, regional spatial distribution features, and texture features of the wafer yield spatial distribution from the wafer image matrix and concatenating them to obtain a wafer yield distribution feature vector; inputting the wafer yield distribution feature vector into a pre-trained SVM model to obtain a predicted pattern category; retrieving the predicted pattern category from a fault knowledge base to obtain a list of potentially high-risk processes; extracting process deviation reports from the process history of the wafer object based on the list of potentially high-risk processes; and generating the root cause diagnosis suggestions based on the predicted pattern category and the process deviation reports. Specifically, the wafer yield distribution feature vector is input into a pre-trained SVM model to obtain the predicted pattern category, including: The wafer yield distribution feature vector is enhanced by a bias constraint based on the feature mean to obtain an enhanced wafer yield distribution feature vector, namely: ;in, These are the eigenvalues ​​in the eigenvector of the wafer yield distribution. It is the characteristic mean of the characteristic vector of the wafer yield distribution. These are the eigenvalues ​​in the characteristic vector of the enhanced wafer yield distribution; The directional modulation is performed by using the distance directional modulation of the enhanced wafer yield distribution feature vector relative to the wafer yield distribution feature vector to obtain the distance directional modulation coefficient, i.e.: ;in, It is the range directional modulation coefficient; Based on the aforementioned distance-directivity modulation coefficient, the enhanced wafer yield distribution feature vector and the wafer yield distribution feature vector are subjected to feature distribution spatial resonance to obtain an optimized wafer yield distribution feature vector, namely: ;in, It is the value of an exponential function with the natural constant e as its base. These are the individual feature values ​​in the optimized wafer yield distribution feature vector; The optimized wafer yield distribution feature vector is input into the pre-trained SVM model to obtain the predicted pattern category.

2. The method for manufacturing a rotating rectifier chip according to claim 1, characterized in that, Forming a PN junction on the substrate includes: A masking layer is obtained by thermally oxidizing the surface of the substrate to grow a layer of silicon dioxide. Photoresist is coated on the masking layer and exposed to ultraviolet light through a mask with a specific pattern. Then, a window pattern is formed on the masking layer by development. The silicon dioxide exposed in the window pattern is etched away by an etching process to expose the substrate layer underneath. The PN junction is obtained by incorporating P-type impurities into the epitaxial layer beneath the window pattern using high-temperature diffusion or ion implantation processes.

3. The method for producing a rotating rectifier chip according to claim 2, characterized in that, In response to a wafer yield falling below a preset threshold, a wafer image matrix is ​​constructed based on the test results of the plurality of rotating rectifier chips, including: Construct the wafer image meta-matrix; The test results of the plurality of rotating rectifier chips are iterated and the following operations are performed: if the test result of the rotating rectifier chip is unqualified, zero is filled in the corresponding position of the wafer image pixel matrix; if the test result of the rotating rectifier chip is qualified, one is filled in the corresponding position of the wafer image pixel matrix.

4. The method for producing a rotating rectifier chip according to claim 3, characterized in that, The root cause diagnosis recommendations are generated based on the predicted pattern category and the process deviation report, including: After injecting the predicted pattern category and the process deviation report into the predefined Prompt template, they are input into the large language model to obtain the root cause diagnosis suggestions.

5. A rotating rectifier chip, characterized in that, The rotating rectifier chip is manufactured by the method for producing a rotating rectifier chip as described in any one of claims 1-4.

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