Stress isolation structure and preparation method thereof, semiconductor device and preparation method thereof, and stress isolation wafer

Abstract

The invention relates to a stress isolation structure and a preparation method thereof, a semiconductor device and a preparation method thereof, and a stress isolation wafer, and the method comprises the steps: providing a first wafer which comprises a first surface and a second surface, and the first surface is a bonding surface with a second wafer; an isolation groove and a through groove are formed in the first wafer from the first surface side, the isolation groove and the through groove extend into the first wafer from the first surface, and the depth of the through groove is smaller than that of the isolation groove; forming an isolation cavity in the first wafer from the second surface side; the first wafer comprises a stress isolation region and a first cutting channel region surrounding the periphery of the stress isolation region, the stress isolation region corresponds to a chip region of the second wafer, the first cutting channel region corresponds to a second cutting channel region of the second wafer, and the stress isolation region comprises a first isolation region and a second isolation region surrounding the periphery of the first isolation region; the isolation groove is formed in the second isolation area, the through groove extends from the first cutting channel area to the first isolation area to be communicated with the isolation groove, and the isolation cavity is formed in the first isolation area.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a stress isolation structure and a preparation method thereof, a semiconductor device and a preparation method thereof, and a stress isolation wafer. Background Art

[0002] The accuracy and stability of a chip in high-temperature environments (e.g., -40°C to 120°C) and complex mechanical conditions are key indicators of chip performance. However, the inevitable difference in thermal expansion coefficients between the chip and its packaging material creates thermal stress due to unequal volume changes during temperature cycling, which in turn causes chip deformation. In addition to temperature factors, mechanical vibration and shock during chip assembly and end-use applications can cause deformation of the PCB (Printed Circuit Board). The mechanical stress generated by PCB deformation is transmitted to the chip through the packaging tube and shell, causing abnormal chip deformation. Severe chip deformation can cause irreversible damage to the chip structure (such as microcracks, interface delamination, or structural fractures), resulting in chip failure.

[0003] Current solutions for stress isolation in this field primarily focus on die-level optimization, specifically the introduction of stress isolation structures (such as cantilever beams) during the chip packaging phase. However, designing stress isolation structures for individual chips requires high process precision, is costly, and inefficient. Furthermore, introducing stress isolation structures during the packaging process already exposes the chip to certain mechanical stresses, leading to performance degradation after packaging and limited improvement.

[0004] Therefore, how to better prevent stress from being transmitted to the chip and reduce the stress borne by the chip has become an urgent problem to be solved in this field. Summary of the Invention

[0005] In view of this, embodiments of the present application provide a stress isolation structure and a manufacturing method, a semiconductor device and a manufacturing method, and a stress isolation wafer to solve at least one problem existing in the background technology.

[0006] In a first aspect, an embodiment of the present application provides a method for preparing a stress isolation structure, the method comprising: Providing a first wafer, wherein the first wafer includes a first surface and a second surface opposite to each other, the first surface serving as a bonding surface for bonding with a second wafer, and the second wafer is a chip wafer; forming an isolation trench and a through-trench in the first wafer from the first surface side, wherein both the isolation trench and the through-trench extend from the first surface into the first wafer, and a depth of the through-trench is smaller than a depth of the isolation trench; forming an isolation cavity in the first wafer from the second surface side; In which, the first wafer includes a stress isolation area and a first cutting street area surrounding the stress isolation area, the stress isolation area corresponds to the chip area position on the second wafer, the first cutting street area corresponds to the second cutting street area position on the second wafer, the stress isolation area includes a first isolation area and a second isolation area surrounding the first isolation area, the isolation groove is formed in the second isolation area, the through groove extends from the first cutting street area to the direction of the first isolation area to connect with the isolation groove, and the isolation cavity is formed in the first isolation area.

[0007] In combination with the first aspect of the present application, in an optional embodiment, along the thickness direction of the first wafer, the projection of the isolation groove is a ring surrounding the periphery of the first isolation region, the projection of the through groove is a ring surrounding the periphery of the isolation groove, and the inner ring of the projection of the through groove overlaps with the outer ring of the projection of the isolation groove.

[0008] In combination with the first aspect of the present application, in an optional embodiment, the depth of the isolation trench accounts for a ratio of 40% to 60% of the thickness of the first wafer.

[0009] In conjunction with the first aspect of the present application, in an optional embodiment, after forming the isolation trench and the through trench in the first wafer from the first surface side, the method further includes: The first wafer is etched through the isolation groove to form an extended cavity; wherein, along the thickness direction of the first wafer, the projection of the extended cavity covers the projection of the isolation groove, and the projected area of ​​the extended cavity is larger than the projected area of ​​the isolation groove.

[0010] In conjunction with the first aspect of the present application, in an optional embodiment, forming an isolation cavity in the first wafer from the second surface side includes: forming a plurality of release holes in the first wafer from the second surface side, wherein the plurality of release holes extend from the second surface into the first wafer respectively; wherein the plurality of release holes are all formed in the first isolation region; The first wafer is etched through the release holes to form the isolation cavity; wherein, along the thickness direction of the first wafer, the projections of the plurality of release holes are all located within the range of the projection of the isolation cavity.

[0011] In combination with the first aspect of the present application, in an optional embodiment, the depth of the release hole accounts for a ratio of 40% to 60% of the thickness of the first wafer.

[0012] In combination with the first aspect of the present application, in an optional embodiment, after the first wafer is etched through the release hole to form the isolation cavity, a portion of the remaining first wafer constitutes a first support structure, and the first support structure runs through the isolation cavity.

[0013] In combination with the first aspect of the present application, in an optional embodiment, after etching the first wafer through the release hole to form the isolation cavity, part of the remaining first wafer constitutes a second support structure, and the second support structure is located between the isolation groove and the isolation cavity.

[0014] In combination with the first aspect of the present application, in an optional embodiment, the isolation groove is connected to the isolation cavity.

[0015] In conjunction with the first aspect of the present application, in an optional embodiment, etching the first wafer through the isolation trench to form an extended cavity includes: forming a first dielectric layer on all exposed surfaces of the first wafer; removing a portion of the first dielectric layer covering the bottom wall of the isolation trench, and retaining a portion of the first dielectric layer covering the sidewalls and bottom wall of the through trench, the sidewalls of the isolation trench, and the first surface to form a first mask; Using the first mask as a mask, the first wafer is etched through the isolation trench to form the extended cavity.

[0016] In conjunction with the first aspect of the present application, in an optional implementation manner, etching the first wafer through the release hole to form the isolation cavity includes: forming a second dielectric layer on all exposed surfaces of the first wafer; removing a portion of the second dielectric layer covering the bottom wall of the release hole, and retaining a portion of the second dielectric layer covering the sidewall of the release hole and the second surface to form a second mask; Using the second mask as a mask, the first wafer is etched through the release hole to form the isolation cavity.

[0017] In a second aspect, an embodiment of the present application provides a method for manufacturing a semiconductor device, the method comprising the steps in the method for manufacturing a stress isolation structure according to the first aspect; and further comprising: providing a second wafer; Bonding the first wafer and the second wafer, wherein the second wafer is located on the first surface side of the first wafer; performing a dicing process to form a plurality of semiconductor devices; The portion of the second wafer located in the chip area forms a chip, and the portion of the first wafer located in the stress isolation area forms a stress isolation structure corresponding to the chip.

[0018] In a third aspect, an embodiment of the present application provides a stress isolation structure, including: A first substrate comprising a first surface and a second surface opposite to each other, wherein the first surface serves as a bonding surface for bonding with the chip; an isolation trench extending from the first surface into the first substrate; a through groove extending from the first surface into the first substrate, wherein a depth of the through groove is smaller than a depth of the isolation groove; an isolation cavity, located in the first substrate, with an opening of the isolation cavity facing the second surface; The first substrate includes a stress isolation region corresponding to the chip position, the stress isolation region includes a first isolation region and a second isolation region surrounding the first isolation region, the isolation groove is located in the second isolation region, the through groove extends from a side of the second isolation region away from the first isolation region toward the first isolation region until it connects to the isolation groove, and the isolation cavity is located in the first isolation region.

[0019] In combination with the third aspect of the present application, in an optional embodiment, along the thickness direction of the first substrate, the projection of the isolation groove is a ring surrounding the periphery of the first isolation region, the projection of the through groove is a ring surrounding the periphery of the isolation groove, and the inner ring of the projection of the through groove overlaps with the outer ring of the projection of the isolation groove.

[0020] In conjunction with the third aspect of the present application, in an optional embodiment, the depth of the isolation trench accounts for a ratio of 40% to 60% of the thickness of the first substrate.

[0021] In conjunction with the third aspect of the present application, in an optional implementation manner, the method further includes: An extended cavity is located in the first substrate and is connected to the isolation groove through an end of the isolation groove away from the first surface; wherein, along the thickness direction of the first substrate, the projection of the extended cavity covers the projection of the isolation groove, and the projection area of ​​the extended cavity is larger than the projection area of ​​the isolation groove.

[0022] In conjunction with the third aspect of the present application, in an optional implementation manner, the method further includes: A plurality of release holes extend from the second surface into the first substrate and are connected to the isolation cavity; wherein the plurality of release holes are all located in the first isolation region, and along the thickness direction of the first substrate, the projections of the plurality of release holes are all located within the range of the projection of the isolation cavity.

[0023] In conjunction with the third aspect of the present application, in an optional embodiment, the depth of the release hole accounts for a ratio of 40% to 60% of the thickness of the first substrate.

[0024] In combination with the third aspect of the present application, in an optional embodiment, a portion of the first substrate constitutes a first supporting structure, and the first supporting structure runs through the isolation cavity.

[0025] In conjunction with the third aspect of the present application, in an optional embodiment, a portion of the first substrate constitutes a second supporting structure, and the second supporting structure is located between the isolation trench and the isolation cavity.

[0026] In combination with the third aspect of the present application, in an optional embodiment, the isolation groove is connected to the isolation cavity.

[0027] In a fourth aspect, an embodiment of the present application provides a stress isolation wafer comprising several stress isolation structures as described in the third aspect.

[0028] In a fifth aspect, an embodiment of the present application provides a semiconductor device, comprising the stress isolation structure and chip as described in the third aspect; or, prepared using the semiconductor device preparation method as described in the second aspect.

[0029] Compared with the prior art, the stress isolation structure and preparation method, semiconductor device and preparation method, and stress isolation wafer provided in the embodiments of the present application have the following beneficial effects: On the one hand, a dual stress isolation mechanism is formed by the isolation cavity, isolation groove and through groove. Under the synergistic effect of the three, the stress isolation structure can prevent stress from different directions and types from being transmitted to the chip, thereby reducing the stress borne by the chip. Specifically, the isolation cavity is located in the first isolation area and the isolation cavity opening faces outward, serving as a buffer zone under the chip. The isolation groove is located in the second isolation area outside the first isolation area. The through groove connects the isolation groove to the outside of the stress isolation area. The isolation groove and the through groove serve as a buffer zone outside the chip. The isolation cavity, isolation groove and through groove provide space for the elastic deformation of the stress isolation structure, effectively eliminating the stress transmitted from all directions, and preventing the stress from diffusing inward to the chip. The isolation cavity also serves as a heat dissipation cavity, so that the external heat dissipates laterally during the longitudinal transfer process, reducing heat transfer, and then reducing thermal stress, thereby reducing the stress borne by the chip.

[0030] On the other hand, by designing a stress isolation structure in the first wafer and achieving wafer-level bonding between the first wafer and the chip wafer before dicing, compared to designing a stress isolation structure for a single chip after dicing in the packaging stage, the embodiment of the present application prepares a stress isolation structure in the semiconductor front-end process, which has higher production efficiency and lower cost, and avoids the stress generated by the packaging from being directly transmitted to the chip before the stress isolation structure is formed, thereby reducing the stress borne by the chip.

[0031] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings: Figure 1 A schematic diagram of a process for preparing a stress isolation structure according to an embodiment of the present application; Figures 2 to 7 A schematic diagram of the cross-sectional structure of the stress isolation structure provided in an embodiment of the present application during the preparation process; Figure 8 is a schematic diagram of a projection of the release hole along the thickness direction of the first wafer in a specific example; Figure 9 is a schematic diagram of a projection of the first support structure along the thickness direction of the first wafer in a specific example; Figure 10 is a schematic diagram of a projection of the release hole along the thickness direction of the first wafer in a specific example; Figure 11 is a schematic diagram of a projection of the second support structure along the thickness direction of the first wafer in a specific example; Figure 12 is a schematic diagram of a projection of the release hole along the thickness direction of the first wafer in another specific example; Figure 13 is a schematic projection diagram of the second supporting structure along the thickness direction of the first wafer in another specific example; Figure 14 A schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application; Figures 15 to 17 A schematic diagram of the cross-sectional structure of a semiconductor device during the manufacturing process provided in an embodiment of the present application; Figure 18 A schematic cross-sectional view of a stress isolation structure provided in an embodiment of the present application; Figure 19 is a schematic diagram of a projection of the first support structure along the thickness direction of the first substrate in a specific example; Figure 20 is a schematic diagram of a projection of the second support structure along the thickness direction of the first substrate in a specific example; Figure 21 FIG. 4 is a schematic projection diagram of the second support structure along the thickness direction of the first substrate in another specific example.

[0033] Description of reference numerals: 100. First wafer; 101. First surface; 102. Second surface; 110. Stress isolation region; 111. First isolation region; 112. Second isolation region; 120. First cutting path region; 130. Isolation groove; 131. Through groove; 140. Release hole; 150. First dielectric layer; 160. Second dielectric layer; 151. First mask; 161. Second mask; 170. Isolation cavity; 180. Extension cavity; 191. First support structure; 192. Second support structure; 200. Second wafer; 210. Chip region; 220. Second cutting path region; 230. Interlayer dielectric layer; 240. First electrode layer; 250. Conductive connection structure; 260. Second electrode layer; 270. First bonding layer; 280. Second bonding layer; 290. Capping layer; 10. First substrate; 20. Second substrate. DETAILED DESCRIPTION

[0034] The following describes in more detail exemplary embodiments disclosed herein with reference to the accompanying drawings. While the accompanying drawings illustrate exemplary embodiments of the present application, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. Rather, these embodiments are provided to facilitate a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0035] In the drawings, the sizes of layers, regions, and elements and their relative sizes may be exaggerated. The same reference numerals denote the same elements.

[0036] When an element or layer is referred to as being "on," "adjacent," or "connected to" another element or layer, it can be directly on, adjacent, or connected to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent," or "directly connected to" another element or layer, there are no intervening elements or layers. Although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms, which are merely used to distinguish one element, component, region, layer, or section from another.

[0037] Spatially relative terms such as "below," "beneath," "beneath," "above," "upper," and the like may be used herein for convenience to describe the relationship of one element or feature to other elements or features shown in the figures. In addition to the orientations shown in the figures, the spatially relative terms are intended to encompass different orientations of the device in use and operation. For example, the exemplary terms "below" and "beneath" may encompass both an orientation of above and below.

[0038] The singular forms “a”, “an” and “the” are intended to include the plural forms as well.

[0039] The terms "comprising" and / or "including", when used in this specification, identify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0040] In order to fully understand the present application, detailed steps and structures will be presented in the following description. The preferred embodiments of the present application are described in detail below. However, in addition to these detailed descriptions, the present application may also have other implementation methods.

[0041] Figure 1 A schematic flow chart of a method for preparing a stress isolation structure provided in an embodiment of the present application is shown in the figure. The method includes: Step S1: providing a first wafer, the first wafer including a first surface and a second surface opposite to each other, the first surface serving as a bonding surface for bonding with a second wafer, the second wafer being a chip wafer; Step S2: forming an isolation trench and a through trench in the first wafer from the first surface side, wherein both the isolation trench and the through trench extend from the first surface into the first wafer, and the depth of the through trench is smaller than the depth of the isolation trench; Step S3: forming an isolation cavity in the first wafer from the second surface side.

[0042] Among them, the first wafer includes a stress isolation area and a first cutting road area surrounding the stress isolation area. The stress isolation area corresponds to the chip area position on the second wafer. The first cutting road area corresponds to the second cutting road area position on the second wafer. The stress isolation area includes a first isolation area and a second isolation area surrounding the first isolation area. The isolation groove is formed in the second isolation area. The through groove extends from the first cutting road area to the direction of the first isolation area to connect the isolation groove, and the isolation cavity is formed in the first isolation area.

[0043] Understandably, the current solutions for stress isolation in this field are mainly focused on chip-level improvements. Specifically, after the chip wafer is diced to form multiple chips, a corresponding stress isolation structure is set for each chip when the single chip is packaged. However, this solution faces several problems: First, the chip is in the packaging stage at this time and has been affected by the stress caused by the packaging; second, the stress isolation structure is prepared in the semiconductor back-end process stage of packaging. Compared with the semiconductor front-end process, the maturity and precision of the semiconductor back-end process are lower, and the difficulty of preparing the stress isolation structure is higher. In addition, major changes need to be made to the traditional packaging process, and the improvement difficulty and cost are higher; third, the stress isolation structure is prepared separately for each chip, which has lower production efficiency and high cost. It can be seen that the improvement effect of this solution is not ideal, and it is inefficient, costly, and difficult, which is not conducive to large-scale production. Therefore, the embodiment of the present application processes a stress isolation structure on the first wafer, realizes wafer-level bonding between the first wafer and the chip wafer before dicing, and prepares the stress isolation structure in the semiconductor front-end process, which has higher production efficiency and lower cost, and sets the stress isolation structure before the chip enters the packaging stage to avoid the stress generated by the packaging from being directly transmitted to the chip before the stress isolation structure is formed; thereby, the stress can be effectively blocked from being transmitted to the chip, achieving a better stress isolation effect, and being compatible with the existing packaging process, with low difficulty in improvement, and conducive to large-scale production.

[0044] It is understandable that using a package shell to encapsulate a chip is a common method in this field. The chip is fixedly connected to the package shell through its internal substrate. Since there is usually a certain difference in thermal expansion coefficient between the chip and the package shell, when the temperature changes, under the influence of the mismatched thermal expansion coefficients, thermal stress will be generated between the chip and the package shell. The thermal stress is specifically manifested as a force with the vertical direction as the main direction. Under the action of thermal stress, the chip will bulge upward or sag downward. The package shell is usually also provided with a filler, which is filled between the chip and the package shell and surrounds the chip. The filler and the chip usually also have a difference in thermal expansion coefficient. Thermal stress will also be generated between the chip and the filler. Specifically, it is manifested as a force with the horizontal direction as the main direction. Under the action of thermal stress, the chip will be compressed inward or stretched outward. It can be seen that the chip may be affected by thermal stress from different directions. In addition, temperature is an important factor affecting the magnitude of thermal stress.

[0045] In addition to thermal stress caused by temperature fluctuations and thermal expansion coefficient mismatches, chips are subject to mechanical stress caused by deformation of the printed circuit board (PCB). After packaging, the chip is soldered to the PCB to enable system-level connectivity with other chips. The PCB with the soldered chips is then used in the assembly and application of end devices. During this process, mechanical vibration and shock may occur, causing PCB deformation, typically manifesting as bending, twisting, or delamination. Mechanical stress caused by PCB deformation can occur in various directions and is transmitted to the chip through the package, causing abnormal deformations such as bending, twisting, and cracking.

[0046] Therefore, in the face of stresses from different directions and types that the chip may be subjected to, the embodiment of the present application sets up an isolation cavity, an isolation groove and a through groove to form a dual stress isolation mechanism. Under the synergistic effect of the three, it effectively blocks stresses from different directions and types from being transmitted to the chip, reducing the stress borne by the chip. Specifically, an isolation cavity with an opening facing outward is formed in the first isolation area, serving as a buffer zone under the chip, and an isolation groove is formed in the second isolation area. The through groove connects the isolation groove to the outside of the stress isolation area. The isolation groove and the through groove serve as a buffer zone around the chip, forming a stress isolation structure with an isolation cavity, an isolation groove and a through groove. External stress needs to be transmitted to the chip through the stress isolation structure. When stress is transmitted to the stress isolation structure, the stress isolation structure undergoes elastic deformation, and the isolation cavity, the isolation groove and the through groove provide space for the elastic deformation of the stress isolation structure. The stress transmitted from all directions is dissipated by the isolation cavity, the isolation groove and the through groove, so that the deformation of the part of the first isolation area bonded to the chip is reduced, effectively blocking the stress from being transmitted to the chip; the isolation cavity also serves as a heat dissipation cavity, so that the external heat is dissipated laterally during the longitudinal transfer process, reducing heat transfer and thereby reducing the magnitude of thermal stress. In this way, the stress can be better prevented from being transmitted to the chip, thereby reducing the stress borne by the chip.

[0047] First, please refer to Figure 2 and Figure 15 Step S1 is performed to provide a first wafer 100. The first wafer 100 includes a first surface 101 and a second surface 102 facing each other. The first surface 101 serves as a bonding surface for bonding with a second wafer, which is a chip wafer. The first wafer 100 includes a stress isolation region 110 and a first scribe line region 120 surrounding the stress isolation region 110. The stress isolation region 110 corresponds to the chip region on the second wafer. The first scribe line region 120 corresponds to the second scribe line region on the second wafer. The stress isolation region 110 includes a first isolation region 111 and a second isolation region 112 surrounding the first isolation region 111.

[0048] It is understandable that, compared to designing a stress isolation structure for a single chip after dicing during the packaging stage, the embodiment of the present application subsequently processes the isolation groove 130, the through groove 131, and the isolation cavity 170 on the first wafer 100, and the first wafer 100 is bonded to the chip wafer before dicing at the wafer level. The stress isolation structure is prepared in the semiconductor front-end process, which has higher production efficiency and lower cost. In addition, the stress isolation structure is set before the chip enters the packaging stage, preventing the stress generated by the packaging from being directly transmitted to the chip before the stress isolation structure is formed. This can better prevent stress from being transmitted to the chip, reducing the stress on the chip.

[0049] In some embodiments, the thermal expansion coefficient of the first wafer 100 matches the thermal expansion coefficient of the second wafer. This prevents thermal stress from being generated between the stress isolation structure formed by the first wafer 100 and the chip formed by the second wafer due to mismatched thermal expansion coefficients when the temperature changes, thereby reducing the stress on the chip. Those skilled in the art can select any suitable first wafer based on the material of the second wafer, and the present embodiment does not limit the material of the first wafer 100.

[0050] Next, please refer to Figure 2 , executing step S2, forming an isolation trench 130 and a through-trench 131 in the first wafer 100 from the first surface 101 side. Both the isolation trench 130 and the through-trench 131 extend from the first surface 101 into the first wafer 100, and the depth of the through-trench 131 is less than the depth of the isolation trench 130. The isolation trench 130 is formed in the second isolation region 112, and the through-trench 131 extends from the first scribe line region 120 toward the first isolation region 111 to connect to the isolation trench 130. It can be understood that the through groove 131 extends from the first cutting road area 120 in the direction of the first isolation area 111 to the connecting isolation groove 130, and the through groove 131 connects the isolation groove 130 to the outside of the stress isolation area 110. After dicing, the through groove 131 connects the isolation groove 130 with the outside world. The part of the stress isolation structure located on the outside of the isolation groove 130 is spaced from the chip through the through groove 131. The chip is only bonded to the part of the stress isolation structure located on the inside of the isolation groove 130. The outside of the isolation groove 130 is the side of the isolation groove 130 away from the first isolation area 111, and the inside of the isolation groove 130 is the side of the isolation groove 130 close to the first isolation area 111. As a result, the isolation groove 130 can provide space for the elastic deformation of the stress isolation structure, thereby avoiding the chip and the parts of the stress isolation structure located on both sides of the isolation groove 130 being bonded, making it difficult for the isolation groove 130 to accommodate deformation, thereby blocking stress from being transmitted to the chip.

[0051] It should be noted that Figure 2The situation in which the through groove 131 extends from the side of the first cutting street region 120 close to the second isolation region 112 toward the first isolation region 111 is only schematically shown. The present application does not exclude the situation in which the through groove 131 extends from the inside of the first cutting street region 120 toward the first isolation region 111, and the situation in which the through groove 131 extends from the side of the first cutting street region 120 away from the second isolation region 112 toward the first isolation region 111.

[0052] In some embodiments, along the thickness direction of the first wafer 100, the projection of the isolation groove 130 is a ring surrounding the outer periphery of the first isolation region 111, and the projection of the through groove 131 is a ring surrounding the outer periphery of the isolation groove 130, and the inner ring of the projection of the through groove 131 overlaps with the outer ring of the projection of the isolation groove 130. This is beneficial to blocking the stress transmitted in all directions and reducing the stress borne by the chip. It should be noted that in this embodiment, the projection of the isolation groove 130 surrounds the projection of the first isolation region 111, and the present application does not exclude the situation where the projection of the isolation groove 130 is located on the outer periphery of the projection of part of the first isolation region 111. In a specific example, along the thickness direction of the first wafer 100, the projection of the first isolation region 111 is a rectangle, and the projection of the isolation groove 130 is adjacent to both sides of the projection of the first isolation region 111. Furthermore, the two sides of the projection of the first isolation region 111 are symmetrical to each other.

[0053] In some embodiments, forming the isolation trench 130 in the first wafer 100 can be achieved through a photolithography-etching process. Specifically, forming the isolation trench 130 in the first wafer 100 from the first surface 101 side can include: forming a first photoresist layer (not shown in the figure) covering the first surface 101; performing an exposure process and a development process to form a patterned first photoresist layer; and etching the first wafer 100 using the patterned first photoresist layer as a mask to form the isolation trench 130. In this embodiment, the process for forming the through-groove 131 is the same as that for forming the isolation trench 130. It should be noted that this embodiment does not limit the order in which the isolation trench 130 and the through-groove 131 are prepared.

[0054] Optionally, the depth of the through-groove 131 accounts for less than or equal to 10% of the thickness of the first wafer 100. It is understood that the through-groove 131 is used to connect the isolation groove 130 to the outside world. The portion of the stress isolation structure located outside the isolation groove 130 is spaced apart from the chip by the through-groove 131. The chip is bonded only to the portion of the stress isolation structure located inside the isolation groove 130. The outside of the isolation groove 130 is the side of the isolation groove 130 away from the first isolation region 111, and the inside of the isolation groove 130 is the side of the isolation groove 130 close to the first isolation region 111. This allows the isolation groove 130 to provide space for elastic deformation of the stress isolation structure, avoiding bonding of the chip to the portions of the stress isolation structure located on both sides of the isolation groove 130. If the depth of the through-groove 131 is too large, the thickness of the remaining first wafer 100 below the through-groove 131 will be too small, resulting in reduced mechanical strength, which is more conducive to ensuring the stress isolation effect.

[0055] Optionally, the depth of the isolation trench 130 accounts for a ratio of 40% to 60% of the thickness of the first wafer 100. It is understandable that if the depth of the isolation trench 130 accounts for too small a ratio of the thickness of the first wafer 100, the isolation trench 130 provides insufficient space for elastic deformation, which will reduce the stress isolation effect of the isolation trench 130. If the depth of the isolation trench 130 accounts for too large a ratio of the thickness of the first wafer 100, the isolation trench 130 is too deep, and the thickness of the remaining first wafer 100 below the isolation trench 130 is too small, resulting in reduced mechanical strength. When the stress transmitted from the outside is too large, structural fracture may occur, and the etching time is long, affecting production efficiency. Therefore, controlling the ratio of the depth of the isolation trench 130 to the thickness of the first wafer 100 within this range is conducive to ensuring the stress isolation effect.

[0056] Furthermore, the depth of the isolation trench 130 accounts for 50% of the thickness of the first wafer 100 , which is more conducive to ensuring the stress isolation effect.

[0057] In some embodiments, please refer to Figure 6 After forming isolation trench 130 and through-groove 131 in first wafer 100 from first surface 101, the method may further include etching first wafer 100 through isolation trench 130 to form an extended cavity 180; wherein, along the thickness direction of first wafer 100, the projection of extended cavity 180 overlaps the projection of isolation trench 130, and the projected area of ​​extended cavity 180 is larger than the projected area of ​​isolation trench 130. Thus, the formation of extended cavity 180, which is connected to isolation trench 130, provides more space for elastic deformation of the stress isolation structure, thereby better dissipating stress, more effectively preventing stress from being transmitted to the chip, and reducing the stress on the chip.

[0058] Optionally, the depth of the extended cavity 180 accounts for a ratio of 25% to 30% of the thickness of the first wafer 100. Understandably, if the depth of the extended cavity 180 is too small, the stress isolation effect is poor; if the depth of the extended cavity 180 is too large, the mechanical strength of the first wafer 100 is reduced, making it prone to warping. Therefore, controlling the ratio of the depth of the extended cavity 180 to the thickness of the first wafer 100 within this range helps ensure stress isolation.

[0059] In some embodiments, please refer to Figures 4 to 6 Etching the first wafer 100 through the isolation trench 130 to form the extended cavity 180 may include: forming a first dielectric layer 150 on all exposed surfaces of the first wafer 100; removing the portion of the first dielectric layer 150 covering the bottom wall of the isolation trench 130, and retaining the portion of the first dielectric layer 150 covering the sidewalls and bottom wall of the through-groove 131, the sidewalls of the isolation trench 130, and the first surface 101 to form a first mask 151; using the first mask 151 as a mask, etching the first wafer 100 through the isolation trench 130 to form the extended cavity 180. By forming a first dielectric layer 150 on all exposed surfaces of the first wafer 100, damage to other locations of the first wafer 100 can be avoided during the etching process of the first wafer 100. When forming the first dielectric layer 150, the thickness of the first dielectric layer 150 formed on the bottom wall of the isolation trench 130 is relatively small. Therefore, in the same process, the first dielectric layer 150 on the bottom wall of the isolation trench 130 is removed first, and only a portion of the first dielectric layer 150 at other locations is removed to form a first mask 151. There is no need to set up an additional mask plate to prepare the first mask 151.

[0060] The material of the first dielectric layer 150 may include an oxide material or a nitride material.

[0061] The process of forming the first dielectric layer 150 on all exposed surfaces of the first wafer 100 may include a thermal oxidation process or a nitridation process.

[0062] In some embodiments, after forming a first dielectric layer 150 on all exposed surfaces of the first wafer 100 , the method may further include: forming a third dielectric layer (not shown) covering the sidewalls and bottom wall of the through-grooves 131 , the sidewalls and bottom wall of the isolation trenches 130 , and the first surface 101 , wherein the third dielectric layer and the first dielectric layer 150 are made of the same material; The portion of the first dielectric layer 150 covering the bottom wall of the isolation trench 130 is removed, and the portion of the first dielectric layer 150 covering the sidewalls and bottom wall of the through-trench 131, the sidewalls of the isolation trench 130, and the first surface 101 is retained to form a first mask 151, including: removing the portions of the first dielectric layer 150 and the third dielectric layer covering the bottom wall of the isolation trench 130, and the portion of the first dielectric layer 150 and the third dielectric layer covering the sidewalls and bottom wall of the through-trench 131, the sidewalls of the isolation trench 130, and the first surface 101 is retained to form the first mask 151.

[0063] It can be understood that when the third dielectric layer is formed, the thickness of the third dielectric layer formed on the bottom wall of the isolation groove 130 is relatively small. Therefore, in the same process, the third dielectric layer on the bottom wall of the isolation groove 130 is removed first, and only part of the thickness of the third dielectric layer at other positions of the first wafer 100 is removed, and can be formed into a first mask 151 together with the remaining first dielectric layer 150, without the need to additionally set up a mask plate to prepare the first mask 151; the thickness of the first mask 151 is increased by the third dielectric layer, which is conducive to ensuring the shielding effect of the first mask 151.

[0064] In a specific example, the thickness of the first dielectric layer 150 is 0.5 μm, and the thickness of the third dielectric layer is 2 μm.

[0065] The process of forming the third dielectric layer may include a deposition process.

[0066] Next, please refer to Figure 6 , execute step S3, and form an isolation cavity 170 in the first wafer 100 from the side of the second surface 102. The isolation cavity 170 is formed in the first isolation area 111. It can be understood that the first isolation area 111 corresponds to the chip area, and the isolation cavity 170 is formed in the first isolation area 111. After dicing, the isolation cavity 170 serves as a stress buffer and heat release area under the chip, which not only provides space for the elastic deformation of the stress isolation structure, but also promotes the lateral dissipation of heat during the longitudinal transfer process, reduces heat transfer, and then reduces thermal stress; thereby better blocking stress from being transmitted to the chip and reducing the stress borne by the chip. The isolation cavity 170, the isolation groove 130 and the through groove 131 constitute a dual stress isolation mechanism. Under the synergistic effect of the three, stress from all directions is blocked, reducing the stress borne by the chip.

[0067] It should be noted that although Figure 1 The arrow in the figure shows the order of executing step S2 first and then executing step S3, but the present application does not exclude the situation where step S3 is executed before step S2.

[0068] In some embodiments, forming the isolation cavity 170 in the first wafer 100 from the second surface 102 side may include: forming a second photoresist layer (not shown in the figure) covering the second surface 102; performing an exposure process and a development process to form a patterned second photoresist layer; and etching the first wafer 100 using the patterned second photoresist layer as a mask to form the isolation cavity 170.

[0069] Along the thickness direction of the first wafer 100, the projected area of ​​the isolation cavity 170 is greater than or equal to 50% of the projected area of ​​the stress isolation region 110. This helps provide sufficient elastic deformation space for the stress isolation structure.

[0070] In some embodiments, please refer to Figures 3 to 6 Forming the isolation cavity 170 in the first wafer 100 from the second surface 102 side can include: forming a plurality of release holes 140 in the first wafer 100 from the second surface 102 side, wherein the plurality of release holes 140 extend from the second surface 102 into the first wafer 100; wherein the plurality of release holes 140 are all formed in the first isolation region 111; etching the first wafer 100 through the release holes 140 to form the isolation cavity 170; wherein, along the thickness direction of the first wafer 100, the projections of the plurality of release holes 140 are all located within the projection of the isolation cavity 170. This helps to enhance the mechanical strength of the stress isolation structure; and compared to etching the first wafer 100 directly from the second surface 102, the etching amount of the first wafer 100 in this embodiment is relatively small, thereby improving production efficiency.

[0071] The process of etching the first wafer 100 may include a wet etching process, which is more efficient than a dry etching process.

[0072] Optionally, the depth of the release hole 140 accounts for a ratio of 40% to 60% of the thickness of the first wafer 100. It is understandable that if the depth of the release hole 140 accounts for too little of the thickness of the first wafer 100, after the isolation cavity 170 is formed, the remaining thickness of the first wafer 100 below the isolation cavity 170 is too small, reducing mechanical strength and easily causing cracking when the stress transmitted from the outside is too great. If the depth of the release hole 140 accounts for too much of the thickness of the first wafer 100, after the isolation cavity 170 is formed, the remaining thickness of the first wafer 100 between the isolation cavity 170 and the chip is too small, reducing the heat blocking effect, and prolonging the etching time, resulting in low production efficiency. Therefore, controlling the depth of the release hole 140 to the thickness of the first wafer 100 within this range is beneficial to ensuring the stress isolation effect.

[0073] Furthermore, the depth of the release hole 140 accounts for 50% of the thickness of the first wafer 100, which is more conducive to ensuring the stress isolation effect.

[0074] Optionally, the depth of the isolation cavity 170 accounts for a ratio of 25% to 30% of the thickness of the first wafer 100. Understandably, if the depth of the isolation cavity 170 is too small, the isolation effect is poor; if the depth of the isolation cavity 170 is too large, the mechanical strength of the first wafer 100 is reduced, making it prone to warping. Therefore, controlling the ratio of the depth of the isolation cavity 170 to the thickness of the first wafer 100 within this range helps ensure stress isolation.

[0075] In some embodiments, please refer to Figure 9 After etching the first wafer 100 through the release hole 140 to form the isolation cavity 170, a portion of the remaining first wafer 100 forms a first support structure 191, which penetrates the isolation cavity 170. Thus, the first support structure 191 connects the remaining first wafers 100 on the upper and lower sides of the isolation cavity 170, thereby enhancing the mechanical strength and preventing the remaining first wafer 100 below the isolation cavity 170 from cracking.

[0076] The number of the first support structure 191 may be one. In some embodiments, along the thickness direction of the first wafer 100, the projection of the first support structure 191 is located at the center of the projection of the isolation cavity 170. Thus, the first support structure 191 is subjected to more uniform force and has a better support effect.

[0077] There can be multiple first support structures 191. In some embodiments, along the thickness direction of the first wafer 100, the projections of the first support structures 191 are centrally symmetric with respect to the projection center of the isolation cavity 170. This allows the multiple first support structures 191 to receive more uniform force and provide better support.

[0078] Understandably, reference Figure 8 In actual production, the position of the first support structure 191 can be set by distributing multiple release holes 140. Specifically, the release holes 140 can be omitted at some locations of the first isolation region 111. These locations will be retained during the subsequent etching process to form the first support structure 191.

[0079] In some embodiments, please refer to Figure 6 After etching the first wafer 100 through the release holes 140 to form the isolation cavity 170, a portion of the remaining first wafer 100 forms a second support structure 192, which is located between the isolation trench 130 and the isolation cavity 170. The second support structure 192 connects the remaining first wafers 100 on the upper and lower sides of the isolation cavity 170, thereby enhancing mechanical strength and preventing the remaining first wafer 100 below the isolation cavity 170 from cracking.

[0080] There may be multiple second support structures 192. In some embodiments, along the thickness direction of the first wafer 100, the projections of the second support structures 192 are centrally symmetric about the projection center of the isolation cavity 170. This allows the multiple second support structures 192 to receive more uniform force and provide better support.

[0081] Please refer to Figure 11 In a specific example, along the thickness direction of the first wafer 100 , the projection of the isolation trench 130 is in the shape of a rectangular ring, and the projection of the second support structure 192 is adjacent to the four corners of the projection of the isolation trench 130 .

[0082] Please refer to Figure 13 In another specific example, along the thickness direction of the first wafer 100 , the projection of the isolation trench 130 is in the shape of a rectangular ring, and the projection of the second support structure 192 is adjacent to two opposite corners of the projection of the isolation trench 130 .

[0083] It should be noted that Figures 10 to 13 Specifically shown are cases where the number of second support structures 192 is 2 and 4, and this application does not exclude cases where the number of second support structures 192 is 1, 3, 5, etc.

[0084] Understandably, reference Figure 10 and Figure 12 In actual production, the position of the second support structure 192 can be set by distributing multiple release holes 140. Specifically, the release holes 140 can be omitted at some locations of the first isolation region 111. These locations will be retained during the subsequent etching process to form the second support structure 192.

[0085] In some embodiments, please refer to Figures 4 to 6Etching the first wafer 100 through the release hole 140 to form the isolation cavity 170 may include: forming a second dielectric layer 160 on all exposed surfaces of the first wafer 100; removing the portion of the second dielectric layer 160 covering the bottom wall of the release hole 140, and retaining the portion of the second dielectric layer 160 covering the sidewall of the release hole 140 and the second surface 102 to form a second mask 161; using the second mask 161 as a mask, etching the first wafer 100 through the release hole 140 to form the isolation cavity 170. By forming a second dielectric layer 160 on all exposed surfaces of the first wafer 100, damage to other locations of the first wafer 100 can be avoided during the subsequent etching process. When forming the second dielectric layer 160, the thickness of the second dielectric layer 160 formed on the bottom wall of the release hole 140 is relatively small. Therefore, in the same process, the second dielectric layer 160 on the bottom wall of the release hole 140 is removed first, and only a portion of the second dielectric layer 160 at other locations of the first wafer 100 is removed to form the second mask 161. There is no need to set up an additional mask plate to prepare the second mask 161.

[0086] The material of the second dielectric layer 160 may include an oxide material or a nitride material.

[0087] The process of forming the second dielectric layer 160 on all exposed surfaces of the first wafer 100 may include a thermal oxidation process or a nitridation process.

[0088] In some embodiments, after forming a second dielectric layer 160 on all exposed surfaces of the first wafer 100 , the method may further include: forming a fourth dielectric layer (not shown) covering the sidewalls and bottom wall of the release hole 140 and the second surface 102 , wherein the fourth dielectric layer is made of the same material as the second dielectric layer 160 ; The portion of the second dielectric layer 160 covering the bottom wall of the release hole 140 is removed, and the portion of the second dielectric layer 160 covering the side wall of the release hole 140 and the second surface 102 is retained to form a second mask 161, including: removing the portions of the second dielectric layer 160 and the fourth dielectric layer covering the bottom wall of the release hole 140, and the portion of the second dielectric layer 160 and the fourth dielectric layer covering the side wall of the release hole 140 and the second surface 102 is retained to form the second mask 161.

[0089] It can be understood that when the fourth dielectric layer is formed, the thickness of the fourth dielectric layer formed on the bottom wall of the release hole 140 is relatively small. Therefore, in the same process, the fourth dielectric layer on the bottom wall of the release hole 140 is removed first, and only part of the thickness of the fourth dielectric layer at other positions is removed, which can be formed together with the remaining second dielectric layer 160 to form the second mask 161, without the need to additionally set up a mask plate to prepare the second mask 161; the thickness of the second mask 161 is increased by the fourth dielectric layer, thereby ensuring the shielding effect of the second mask 161.

[0090] In a specific example, the thickness of the second dielectric layer 160 is 0.5 μm, and the thickness of the fourth dielectric layer is 2 μm.

[0091] The process of forming the fourth dielectric layer may include a deposition process.

[0092] In some embodiments, the first dielectric layer 150 and the second dielectric layer 160 are made of the same material and formed through the same process. In one specific example, a thermal oxidation process can be performed to form an oxide layer on all exposed surfaces of the first wafer 100. The oxide layer can serve as the first dielectric layer 150 for forming the first mask 151, and can also serve as the second dielectric layer 160 for forming the second mask 161.

[0093] It should be noted that Figures 4 to 6 Only a portion of the first wafer 100 is shown. The portion of the first dielectric layer 150 (the second dielectric layer 160 ) located outside the second isolation region 112 in the figure should be understood to cover the sidewall of the entire first wafer 100 .

[0094] In some embodiments, the isolation cavity 170 and the extension cavity 180 are fabricated in the same process. The process of forming the isolation cavity 170 and the extension cavity 180 may include a wet etching process. The etchant of the wet etching process may include XeF2 and / or nitroacetic acid.

[0095] Optionally, the isolation slot 130 is connected to the isolation cavity 170. Thus, the isolation slot 130 can also serve as a heat sink. After the external heat is transferred to the isolation cavity 170, it can be further conducted through the isolation slot 130, which is more conducive to reducing thermal stress.

[0096] Optionally, the isolation slot 130 is connected to the isolation cavity 170 through the expansion cavity 180 .

[0097] In some embodiments, the bottom wall of the isolation cavity 170 and the top wall of the expansion cavity 180 are in the same plane, and the top wall of the isolation cavity 170 and the bottom wall of the expansion cavity 180 are in the same plane.

[0098] Please refer to Figure 7 The method further includes removing the first mask 151 and the second mask 161 .

[0099] The present invention also provides a method for preparing a semiconductor device. Figure 14 The method includes the steps of the method for preparing the stress isolation structure in the above embodiment; and further includes: Step S4: providing a second wafer; Step S5: bonding the first wafer and the second wafer, with the second wafer being located on the first surface side of the first wafer; Step S6: performing a dicing process to form a plurality of semiconductor devices.

[0100] The portion of the second wafer located in the chip area forms a chip, and the portion of the first wafer located in the stress isolation area forms a stress isolation structure corresponding to the chip.

[0101] Therefore, compared with designing a stress isolation structure for a single chip after dicing in the packaging stage, the embodiment of the present application designs a stress isolation structure in the first wafer, and the first wafer is bonded to the chip wafer before dicing at the wafer level, and the stress isolation structure is prepared in the semiconductor front-end process, which has higher production efficiency and lower cost, and avoids the stress generated by the package from being directly transmitted to the chip before the stress isolation structure is formed; a dual stress isolation mechanism is formed by the isolation cavity, isolation groove and through groove. Under the synergistic effect of the three, the stress isolation structure can block stress from different directions and types from being transmitted to the chip, thereby reducing the stress borne by the chip. Specifically, the isolation cavity is located in the first isolation area and opens outward, serving as a buffer zone under the chip. The isolation groove is located in the second isolation area. The through groove extends from the first cutting area to connect to the isolation groove. The isolation groove and the through groove serve as a buffer zone around the chip. The isolation cavity, isolation groove and through groove provide space for the elastic deformation of the stress isolation structure, effectively dissipating the stress transmitted from all directions, and avoiding the stress from diffusing inward to the chip. The isolation cavity also serves as a heat dissipation cavity, so that the external heat is dissipated laterally during the longitudinal transfer process, reducing heat transfer and thereby reducing thermal stress. In this way, stress can be better prevented from being transmitted to the chip, the stress borne by the chip can be reduced, and the performance of the semiconductor device can be improved.

[0102] First, please refer to Figure 15 , step S4 is executed to provide a second wafer 200 . The second wafer 200 is a chip wafer, including a plurality of chip regions 210 and a second scribe line region 220 located outside the chip region 210 . Figure 15 Only one chip region 210 of the second wafer 200 is shown as an example.

[0103] In some embodiments, please refer to Figure 15The chip region 210 is formed with a chip structure layer, which includes an interlayer dielectric layer 230, a first electrode layer 240, a conductive connection structure 250, a second electrode layer 260, a first bonding layer 270, a second bonding layer 280 and a capping layer 290 stacked in sequence; wherein the first electrode layer 240 and the second electrode layer 260 are spaced apart and conductively connected by the conductive connection structure 250, and the second electrode layer 260 and the capping layer 290 are bonded by the first bonding layer 270 and the second bonding layer 280. It can be understood that Figure 15 The case where the chip wafer is a MEMS (Micro-Electro-Mechanical System) chip wafer is only exemplified. The chip wafer may be other chip wafers well known to those skilled in the art, and this application does not limit this.

[0104] Next, please refer to Figure 16 , execute step S5, bond the first wafer 100 and the second wafer 200, and the second wafer 200 is located on the first surface 101 side of the first wafer 100. The first surface 101 of the first wafer 100 serves as a bonding surface for bonding with the second wafer 200. It can be understood that compared to designing a stress isolation structure for a single chip after dicing in the packaging stage, the embodiment of the present application realizes wafer-level bonding of the first wafer 100 and the chip wafer before dicing, and prepares a stress isolation structure in the semiconductor front-end process, which has higher production efficiency and lower cost, and sets a stress isolation structure before the chip enters the packaging stage to avoid the stress generated by the package from being directly transmitted to the chip before the stress isolation structure is formed. In this way, the stress can be better blocked from being transmitted to the chip, reducing the stress on the chip.

[0105] In some embodiments, the thermal expansion coefficient of the first wafer 100 matches the thermal expansion coefficient of the second wafer 200. This prevents thermal stress from being generated between the stress isolation structure formed by the first wafer 100 and the chip formed by the second wafer 200 due to the mismatch in thermal expansion coefficients when the temperature changes, thereby reducing the stress on the chip. Those skilled in the art can select any suitable first wafer 100 based on the material of the second wafer 200, and the present embodiment does not limit the material of the first wafer 100.

[0106] In a specific example, the material of the first wafer 100 includes silicon, the material of the second wafer 200 includes silicon, and the first wafer 100 and the second wafer 200 achieve silicon-silicon bonding.

[0107] Finally, please refer to Figure 17, executing step S6, performing a scribing process to form a plurality of semiconductor devices. In the actual manufacturing process, scribing is performed through the first scribe line area 120 and the second scribe line area 220. The portion of the second wafer 200 located in the chip area 210 forms a chip, and the portion of the first wafer 100 located in the stress isolation area 110 forms a stress isolation structure corresponding to the chip.

[0108] Thus, a dual stress isolation mechanism is formed by the isolation cavity 170, the isolation groove 130, and the through groove 131. Under the synergistic effect of the three, the stress isolation structure can prevent stress from different directions and types from being transmitted to the chip, reducing the stress on the chip. Specifically, the isolation cavity 170 can serve as a buffer zone under the chip, and the isolation groove 130 and the through groove 131 can serve as a buffer zone outside the chip. The isolation cavity 170, the isolation groove 130, and the through groove 131 provide space for the elastic deformation of the stress isolation structure, effectively eliminating the stress transmitted from all directions and preventing the stress from diffusing inward to the chip. The isolation cavity 170 also serves as a heat dissipation cavity, allowing external heat to dissipate laterally during the longitudinal transfer process, reducing heat transfer and subsequently reducing thermal stress. As a result, stress transmission to the chip can be better blocked, the stress on the chip can be reduced, and the performance of the semiconductor device can be improved.

[0109] The present application also provides a stress isolation structure, please refer to Figure 18 ,include: The first substrate 10 includes a first surface 101 and a second surface 102 opposite to each other, wherein the first surface 101 serves as a bonding surface for bonding with the chip; an isolation trench 130 extending from the first surface 101 into the first substrate 10 ; A through groove 131 extends from the first surface 101 into the first substrate 10 , and a depth of the through groove 131 is less than a depth of the isolation groove 130 ; an isolation cavity 170 located in the first substrate 10 , with an opening of the isolation cavity 170 facing the second surface 102 ; Among them, the first substrate 10 includes a stress isolation region 110 corresponding to the chip position, the stress isolation region 110 includes a first isolation region 111 and a second isolation region 112 surrounding the first isolation region 111, the isolation groove 130 is located in the second isolation region 112, the through groove 131 extends from the side of the second isolation region 112 away from the first isolation region 111 toward the direction of the first isolation region 111 to connect the isolation groove 130, and the isolation cavity 170 is located in the first isolation region 111.

[0110] The embodiment of the present application forms a dual stress isolation mechanism through the isolation cavity 170, the isolation groove 130 and the through groove 131. Under the synergistic effect of the three, the stress isolation structure can prevent stress from different directions and types from being transmitted to the chip, thereby reducing the stress on the chip. Specifically, the isolation cavity 170 is located in the first isolation region 111 and opens outward, serving as a buffer zone below the chip. The isolation groove 130 is located in the second isolation region 112 outside the first isolation region 111. The through groove 131 extends from the side of the second isolation region 112 away from the first isolation region 111 to connect to the isolation groove 130. The isolation groove 130 and the through groove 131 serve as a buffer zone outside the chip. The isolation cavity 170, the isolation groove 130 and the through groove 131 provide space for the elastic deformation of the stress isolation structure, effectively eliminating the stress transmitted from all directions and preventing the stress from diffusing inward to the chip. The isolation cavity 170 also serves as a heat dissipation cavity, allowing external heat to dissipate laterally during the longitudinal transfer process, reducing heat transfer and subsequently reducing thermal stress. In this way, stress can be better prevented from being transmitted to the chip and the stress on the chip can be reduced.

[0111] In some embodiments, the chip includes a second substrate 20, to which the first substrate 10 is bonded; the thermal expansion coefficient of the first substrate 10 matches the thermal expansion coefficient of the second substrate 20. This prevents thermal stress generated by the stress isolation structure and the chip due to the mismatch in thermal expansion coefficients when the temperature changes, thereby reducing the stress on the chip. Those skilled in the art can select any suitable first substrate 10 based on the material of the second substrate 20, and the present embodiment does not limit the material of the first substrate 10.

[0112] In some embodiments, along the thickness direction of the first substrate 10, the projection of the isolation trench 130 is a ring circumferentially surrounding the outer periphery of the first isolation region 111, and the projection of the through-slot 131 is a ring circumferentially surrounding the outer periphery of the isolation trench 130. The inner ring of the projection of the through-slot 131 overlaps the outer ring of the projection of the isolation trench 130. This helps to block stress transmitted in all directions and reduce the stress on the chip.

[0113] In some embodiments, the depth of the through-groove 131 accounts for less than or equal to 10% of the thickness of the first substrate 10. It is understood that the through-groove 131 is used to connect the isolation trench 130 to the outside world. The portion of the stress isolation structure located outside the isolation trench 130 is spaced apart from the chip by the through-groove 131. The chip is bonded only to the portion of the stress isolation structure located inside the isolation trench 130. The outside of the isolation trench 130 is the side of the isolation trench 130 away from the first isolation region 111, and the inside of the isolation trench 130 is the side of the isolation trench 130 close to the first isolation region 111. This allows the isolation trench 130 to provide space for elastic deformation of the stress isolation structure, preventing the chip from bonding to both sides of the stress isolation structure located on the isolation trench 130. If the depth of the through-groove 131 is too large, the thickness of the remaining first wafer 100 below the through-groove 131 will be too small, resulting in reduced mechanical strength, which is more conducive to ensuring the stress isolation effect.

[0114] In some embodiments, the depth of the isolation trench 130 accounts for a ratio of 40% to 60% of the thickness of the first substrate 10. It is understood that if the depth of the isolation trench 130 is too small as a ratio of the thickness of the first substrate 10, the isolation trench 130 provides insufficient space for elastic deformation, which will reduce the stress isolation effect of the isolation trench 130. If the depth of the isolation trench 130 is too large as a ratio of the thickness of the first substrate 10, the thickness of the remaining first substrate 10 below the isolation trench 130 is too small, resulting in reduced mechanical strength. When the externally transmitted stress is too high, structural cracks may occur, and the etching time is prolonged, affecting production efficiency. Therefore, controlling the ratio of the depth of the isolation trench 130 to the thickness of the first substrate 10 within this range is conducive to ensuring the stress isolation effect.

[0115] Furthermore, the depth of the isolation trench 130 accounts for 50% of the thickness of the first substrate 10, thereby being more conducive to stress isolation.

[0116] In some embodiments, the stress isolation structure may further include an extended cavity 180 located within the first substrate 10 and connected to the isolation trench 130 via the end of the isolation trench 130 remote from the first surface 101. The projection of the extended cavity 180 along the thickness of the first substrate 10 overlaps the projection of the isolation trench 130, and the projected area of ​​the extended cavity 180 is larger than the projected area of ​​the isolation trench 130. Thus, the extended cavity 180, which is connected to the isolation trench 130, provides more space for elastic deformation of the stress isolation structure, thereby better relieving stress, preventing stress from being transmitted to the chip, and reducing the stress on the chip.

[0117] In some embodiments, the isolation cavity 170 extends from the second surface 102 into the first substrate 10 .

[0118] In some embodiments, the stress isolation structure may further include: a plurality of release holes 140 extending from the second surface 102 into the first substrate 10 and communicating with the isolation cavity 170; wherein the plurality of release holes 140 are all located within the first isolation region 111, and along the thickness direction of the first substrate 10, the projections of the plurality of release holes 140 are all located within the projection of the isolation cavity 170. This helps to enhance the mechanical strength of the stress isolation structure and improves production efficiency during actual manufacturing.

[0119] Optionally, the depth of the release hole 140 accounts for a ratio of 40% to 60% of the thickness of the first substrate 10. It is understood that if the depth of the release hole 140 is too small as a ratio of the thickness of the first substrate 10, after the isolation cavity 170 is formed, the remaining thickness of the first substrate 10 below the isolation cavity 170 is too small, resulting in reduced mechanical strength and a high risk of cracking when subjected to excessive external stress. If the depth of the release hole 140 is too large as a ratio of the thickness of the first substrate 10, after the isolation cavity 170 is formed, the remaining thickness of the first substrate 10 between the isolation cavity 170 and the chip is too small, reducing the heat blocking effect, increasing etching time, and reducing production efficiency. Therefore, controlling the ratio of the depth of the release hole 140 to the thickness of the first substrate 10 within this range is beneficial for ensuring the stress isolation effect of the isolation cavity 170.

[0120] Furthermore, the depth of the release hole 140 accounts for 50% of the thickness of the first wafer 100 , which is more conducive to ensuring the stress isolation effect of the isolation cavity 170 .

[0121] In some embodiments, please refer to Figure 19 Part of the first substrate 10 forms a first support structure 191, which runs through the isolation cavity 170. Thus, the first substrates 10 on the upper and lower sides of the isolation cavity 170 are connected by the first support structure 191, thereby enhancing the mechanical strength and preventing the portion of the first substrate 10 below the isolation cavity 170 from cracking.

[0122] The number of the first support structure 191 may be one. In some embodiments, along the thickness direction of the first substrate 10, the projection of the first support structure 191 is located at the center of the projection of the isolation cavity 170. Thus, the first support structure 191 is subjected to more uniform force and has a better supporting effect.

[0123] There may be multiple first support structures 191. In some embodiments, along the thickness direction of the first substrate 10, the projections of the first support structures 191 are centrally symmetric with respect to the projection center of the isolation cavity 170. This allows the multiple first support structures 191 to receive a more uniform force and provide a better support effect.

[0124] In some embodiments, a portion of the first substrate 10 forms a second support structure 192, which is located between the isolation trench 130 and the isolation cavity 170. The second support structure 192 connects the first substrates 10 on the upper and lower sides of the isolation cavity 170, thereby enhancing mechanical strength and preventing the portion of the first substrate 10 below the isolation cavity 170 from cracking.

[0125] There may be multiple second support structures 192. In some embodiments, along the thickness direction of the first wafer 100, the projections of the second support structures 192 are centrally symmetric about the projection center of the isolation cavity 170. This allows the multiple second support structures 192 to receive more uniform force and provide better support.

[0126] Please refer to Figure 20 In a specific example, along the thickness direction of the first substrate 10 , the projection of the isolation trench 130 is in the shape of a rectangular ring, and the projection of the second support structure 192 is adjacent to the four corners of the projection of the isolation trench 130 .

[0127] Please refer to Figure 21 In another specific example, along the thickness direction of the first substrate 10 , the projection of the isolation trench 130 is in the shape of a rectangular ring, and the projection of the second support structure 192 is adjacent to two opposite corners of the projection of the isolation trench 130 .

[0128] It should be noted that Figure 20 and Figure 21 Specifically shown are cases where the number of second support structures 192 is 2 and 4, and this application does not exclude cases where the number of second support structures 192 is 1, 3, 5, etc.

[0129] Optionally, the isolation slot 130 is connected to the isolation cavity 170. Thus, the isolation slot 130 can also serve as a heat sink. After the external heat is transferred to the isolation cavity 170, it can be further conducted through the isolation slot 130, which is more conducive to reducing thermal stress.

[0130] Optionally, the isolation slot 130 communicates with the isolation cavity 170 through the expansion cavity 180. In some embodiments, the bottom wall of the isolation cavity 170 and the top wall of the expansion cavity 180 are in the same plane, and the top wall of the isolation cavity 170 and the bottom wall of the expansion cavity 180 are in the same plane.

[0131] An embodiment of the present application also provides a stress isolation wafer, comprising several stress isolation structures in the above embodiments.

[0132] The stress isolation wafer can be bonded to the chip wafer before dicing at the wafer level, improving stress isolation from the chip level to the wafer level, resulting in higher production efficiency and lower costs. A dual stress isolation mechanism is formed by the isolation cavity, isolation groove, and through-groove. With the synergistic effect of the three, the stress isolation structure can prevent stress from different directions and types from being transmitted to the chip, reducing the stress on the chip. Specifically, the isolation cavity is located in the first isolation zone and opens outward, serving as a buffer zone below the chip. The isolation groove is located in the second isolation zone outside the first isolation zone. The through-groove connects the isolation groove to the outside of the stress isolation zone. The isolation groove and through-groove serve as a buffer zone outside the chip. The isolation cavity, isolation groove, and through-groove provide space for the elastic deformation of the stress isolation structure, effectively dissipating stress transmitted from all directions and preventing stress from diffusing inward to the chip. The isolation cavity also serves as a heat dissipation cavity, allowing external heat to dissipate laterally during longitudinal transfer, reducing heat transfer and, in turn, reducing thermal stress. This can better prevent stress from being transmitted to the chip and reduce the stress on the chip.

[0133] An embodiment of the present application further provides a semiconductor device, comprising the stress isolation structure and chip in the above embodiment; or prepared using the method for preparing the semiconductor device in the above embodiment.

[0134] Thus, a dual stress isolation mechanism is formed by the isolation cavity, isolation groove, and through groove. Under the synergistic effect of the three, the stress isolation structure can prevent stress from different directions and types from being transmitted to the chip, reducing the stress on the chip. Specifically, the isolation cavity is located in the first isolation area and opens outward, serving as a buffer zone under the chip. The isolation groove is located in the second isolation area outside the first isolation area. The through groove connects the isolation groove to the outside of the stress isolation area. The isolation groove and through groove serve as a buffer zone outside the chip. The isolation cavity, isolation groove, and through groove provide space for the elastic deformation of the stress isolation structure, effectively eliminating the stress transmitted from all directions and preventing the stress from diffusing inward to the chip. The isolation cavity also serves as a heat dissipation cavity, allowing external heat to dissipate laterally during the longitudinal transfer process, reducing heat transfer and subsequently reducing thermal stress. Thus, it is possible to better prevent stress from being transmitted to the chip, reduce the stress on the chip, and improve the performance of semiconductor devices.

[0135] It should be noted that the embodiments of the preparation method of the stress isolation structure, the preparation method of the semiconductor device, the stress isolation structure, the stress isolation wafer, and the semiconductor device embodiments provided in this application belong to the same concept; the various technical features in the technical solutions recorded in the embodiments can be arbitrarily combined without conflict. However, it should be further noted that the combination of the various technical features of the stress isolation structure provided in the embodiments of this application can already solve the technical problem to be solved by this application; therefore, the stress isolation structure provided in the embodiments of this application is not limited by the preparation method of the stress isolation structure provided in the embodiments of this application, and any stress isolation structure prepared by the preparation method that can form the stress isolation structure provided in the embodiments of this application is within the scope of protection of this application.

[0136] It should be understood that the above embodiments are exemplary and are not intended to include all possible implementation methods. Various modifications and changes may be made based on the above embodiments without departing from the scope of this application. Similarly, the various technical features of the above embodiments may be arbitrarily combined to form other embodiments of the present application that may not be explicitly described. The above embodiments merely express several implementation methods of the present application and do not limit the scope of protection of the present application.

Claims

1. A method for preparing a stress isolation structure, characterized in that: The method comprises: Providing a first wafer, wherein the first wafer includes a first surface and a second surface opposite to each other, the first surface serving as a bonding surface for bonding with a second wafer, and the second wafer is a chip wafer; forming an isolation trench and a through-trench in the first wafer from the first surface side, wherein both the isolation trench and the through-trench extend from the first surface into the first wafer, and a depth of the through-trench is smaller than a depth of the isolation trench; forming an isolation cavity in the first wafer from the second surface side; In which, the first wafer includes a stress isolation area and a first cutting street area surrounding the stress isolation area, the stress isolation area corresponds to the chip area position on the second wafer, the first cutting street area corresponds to the second cutting street area position on the second wafer, the stress isolation area includes a first isolation area and a second isolation area surrounding the first isolation area, the isolation groove is formed in the second isolation area, the through groove extends from the first cutting street area to the direction of the first isolation area to connect with the isolation groove, and the isolation cavity is formed in the first isolation area.

2. The method for preparing a stress isolation structure according to claim 1, wherein: Along the thickness direction of the first wafer, the projection of the isolation groove is a ring surrounding the periphery of the first isolation area, and the projection of the through groove is a ring surrounding the periphery of the isolation groove. The inner ring of the projection of the through groove overlaps with the outer ring of the projection of the isolation groove.

3. The method for preparing a stress isolation structure according to claim 1, wherein: The depth of the isolation trench accounts for 40% to 60% of the thickness of the first wafer.

4. The method for preparing a stress isolation structure according to claim 1, wherein: After forming the isolation trench and the through trench in the first wafer from the first surface side, the method further includes: The first wafer is etched through the isolation groove to form an extended cavity; wherein, along the thickness direction of the first wafer, the projection of the extended cavity covers the projection of the isolation groove, and the projected area of ​​the extended cavity is larger than the projected area of ​​the isolation groove.

5. The method for preparing a stress isolation structure according to claim 1, wherein: The step of forming an isolation cavity in the first wafer from the second surface side includes: forming a plurality of release holes in the first wafer from the second surface side, wherein the plurality of release holes extend from the second surface into the first wafer respectively; wherein the plurality of release holes are all formed in the first isolation region; The first wafer is etched through the release holes to form the isolation cavity; wherein, along the thickness direction of the first wafer, the projections of the plurality of release holes are all located within the range of the projection of the isolation cavity.

6. The method for preparing a stress isolation structure according to claim 5, wherein: The depth of the release hole accounts for 40% to 60% of the thickness of the first wafer.

7. The method for preparing a stress isolation structure according to claim 5, wherein: After the first wafer is etched through the release hole to form the isolation cavity, a portion of the remaining first wafer constitutes a first supporting structure, and the first supporting structure passes through the isolation cavity.

8. The method for preparing a stress isolation structure according to claim 5, wherein: After the first wafer is etched through the release hole to form the isolation cavity, a portion of the remaining first wafer constitutes a second support structure, and the second support structure is located between the isolation groove and the isolation cavity.

9. The method for preparing a stress isolation structure according to claim 1 or 8, characterized in that: The isolation groove is communicated with the isolation cavity.

10. The method for preparing a stress isolation structure according to claim 4, wherein: The etching the first wafer through the isolation trench to form an extended cavity includes: forming a first dielectric layer on all exposed surfaces of the first wafer; removing a portion of the first dielectric layer covering the bottom wall of the isolation trench, and retaining a portion of the first dielectric layer covering the sidewalls and bottom wall of the through trench, the sidewalls of the isolation trench, and the first surface to form a first mask; Using the first mask as a mask, the first wafer is etched through the isolation trench to form the extended cavity.

11. The method for preparing a stress isolation structure according to claim 5, wherein: The etching the first wafer through the release hole to form the isolation cavity includes: forming a second dielectric layer on all exposed surfaces of the first wafer; removing a portion of the second dielectric layer covering the bottom wall of the release hole, and retaining a portion of the second dielectric layer covering the sidewall of the release hole and the second surface to form a second mask; Using the second mask as a mask, the first wafer is etched through the release hole to form the isolation cavity.

12. A method for preparing a semiconductor device, characterized in that: The method comprises the steps of the method for preparing the stress isolation structure according to any one of claims 1 to 11; and further comprises: providing a second wafer; Bonding the first wafer and the second wafer, wherein the second wafer is located on the first surface side of the first wafer; performing a dicing process to form a plurality of semiconductor devices; The portion of the second wafer located in the chip area forms a chip, and the portion of the first wafer located in the stress isolation area forms a stress isolation structure corresponding to the chip.

13. A stress isolation structure, characterized in that: include: A first substrate comprising a first surface and a second surface opposite to each other, wherein the first surface serves as a bonding surface for bonding with the chip; an isolation trench extending from the first surface into the first substrate; a through groove extending from the first surface into the first substrate, wherein a depth of the through groove is smaller than a depth of the isolation groove; an isolation cavity, located in the first substrate, with an opening of the isolation cavity facing the second surface; The first substrate includes a stress isolation region corresponding to the chip position, the stress isolation region includes a first isolation region and a second isolation region surrounding the first isolation region, the isolation groove is located in the second isolation region, the through groove extends from a side of the second isolation region away from the first isolation region toward the first isolation region until it connects to the isolation groove, and the isolation cavity is located in the first isolation region.

14. The stress isolation structure according to claim 13, wherein: Along the thickness direction of the first substrate, the projection of the isolation groove is a ring surrounding the periphery of the first isolation region, the projection of the through groove is a ring surrounding the periphery of the isolation groove, and the inner ring of the projection of the through groove overlaps with the outer ring of the projection of the isolation groove.

15. The stress isolation structure according to claim 13, wherein: The depth of the isolation trench accounts for 40% to 60% of the thickness of the first substrate.

16. The stress isolation structure according to claim 13, wherein: Also includes: An extended cavity is located in the first substrate and is connected to the isolation groove through an end of the isolation groove away from the first surface; wherein, along the thickness direction of the first substrate, the projection of the extended cavity covers the projection of the isolation groove, and the projection area of ​​the extended cavity is larger than the projection area of ​​the isolation groove.

17. The stress isolation structure according to claim 13, wherein: Also includes: A plurality of release holes extend from the second surface into the first substrate and are connected to the isolation cavity; wherein the plurality of release holes are all located in the first isolation region, and along the thickness direction of the first substrate, the projections of the plurality of release holes are all located within the range of the projection of the isolation cavity.

18. The stress isolation structure according to claim 17, wherein: The depth of the release hole accounts for 40% to 60% of the thickness of the first substrate.

19. The stress isolation structure according to claim 17, wherein: A portion of the first substrate constitutes a first supporting structure, and the first supporting structure passes through the isolation cavity.

20. The stress isolation structure according to claim 17, wherein: A portion of the first substrate constitutes a second supporting structure, and the second supporting structure is located between the isolation trench and the isolation cavity.

21. The stress isolation structure according to claim 13 or 20, characterized in that: The isolation groove is communicated with the isolation cavity.

22. A stress isolation wafer, characterized in that: The method comprises a plurality of stress isolation structures according to any one of claims 13 to 21.

23. A semiconductor device, characterized in that: The stress isolation structure and chip comprise any one of claims 13 to 21; or, the stress isolation structure and chip are prepared by the method for preparing a semiconductor device according to claim 12.

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