Packaging structure and method

Abstract

The invention provides a packaging structure and method, and belongs to the technical field of ceramic packaging, the packaging structure comprises a ceramic shell and a ceramic cover plate, and the ceramic shell is connected with the ceramic cover plate; the ceramic shell comprises a plurality of first pins, a first ceramic body and a first bonding pad, the plurality of first pins are arranged on the lower surface of the first ceramic body, and the first bonding pad is arranged on the upper surface of the first ceramic body; the ceramic cover plate comprises second pins, a second ceramic body, a second bonding pad and a solder piece, the second pins are arranged on the upper surface of the second ceramic body, the second bonding pad is arranged on the lower surface of the second ceramic body, the solder piece is arranged between the ceramic shell and the ceramic cover plate, and the ceramic shell and the ceramic cover plate are welded through the solder piece. According to the packaging structure, a double-face electrode ceramic structure is achieved, air tightness is guaranteed, the product size is small, the electric signal transmission path is short, and reliability is high.

Description

Technical Field

[0001] The present invention relates to the technical field of ceramic packaging, and in particular to a packaging structure and method. Background Art

[0002] As a key solution in the electronic packaging field, ceramic packaging technology occupies a core position in high-power, high-frequency, and high-reliability applications due to its unique material properties and process advantages. However, traditional ceramic packaging mostly uses a single-sided electrode lead-out structure. Single-sided electrodes are difficult to meet the requirements of high-density interconnection. When stacked in multiple layers, the signal transmission path is long, limiting the flexibility of circuit design and integration density. In addition, existing sealing processes have stringent requirements for controlling stress at the ceramic-metal interface. The difference in thermal expansion coefficient between the metal cover and the ceramic base can easily lead to cracking of the seal, affecting airtightness and reliability. Summary of the Invention

[0003] The present invention aims to provide a packaging structure and method to achieve a chip packaging structure with high reliability, high flexibility and miniaturization.

[0004] In a first aspect, the present application provides a packaging structure comprising: a ceramic housing and a ceramic cover, wherein the ceramic housing is connected to the ceramic cover; the ceramic housing comprises a plurality of first lead pins, a first ceramic body, and a first solder pad, wherein the plurality of first lead pins are arranged on the lower surface of the first ceramic body, and the first solder pad is arranged on the upper surface of the first ceramic body; the ceramic cover comprises a plurality of second lead pins, a second ceramic body, a second solder pad, and a solder sheet, wherein the plurality of second lead pins are arranged on the upper surface of the second ceramic body, and the second solder pad is arranged on the lower surface of the second ceramic body, and the solder sheet is arranged between the ceramic housing and the ceramic cover, and the ceramic housing and the ceramic cover are welded via the solder sheet. Optionally, the first ceramic body can be a multilayer ceramic structure comprising: a first ceramic layer, a second ceramic layer, and a third ceramic layer, wherein the first ceramic layer serves as a substrate, the second ceramic layer is arranged on the upper surface of the first ceramic layer, and the third ceramic layer is arranged on the upper surface of the second ceramic layer.

[0005] Optionally, the first ceramic body is a multilayer ceramic structure, including: a first ceramic layer, a second ceramic layer and a third ceramic layer, the first ceramic layer serves as a substrate, the second ceramic layer is arranged on the upper surface of the first ceramic layer, and the third ceramic layer is arranged on the upper surface of the second ceramic layer.

[0006] Optionally, the second ceramic body is a double-layer ceramic structure, including: a fourth ceramic layer and a fifth ceramic layer, and the fifth ceramic layer is arranged on the lower surface of the fourth ceramic layer.

[0007] Optionally, the solder sheet is a double-ring annular solder sheet, including an outer ring-shaped solder sheet and an inner symmetrical double-arc solder sheet.

[0008] Optionally, the solder sheet is made of AuSn or tin-silver-copper alloy.

[0009] Optionally, each first lead pin can be cylindrical / square and made of Kovar alloy, and each first lead pin can be connected to the lower surface of the first ceramic body through silver-copper solder to lead out the signal; each second lead pin can be cylindrical / square and made of Kovar alloy, and each second lead pin can be connected to the upper surface of the second ceramic body through silver-copper solder to lead out the signal.

[0010] Optionally, the ceramic housing further includes a first cavity and a second cavity, wherein the first cavity is located inside the second ceramic layer, and the second cavity is located inside the third ceramic layer.

[0011] Optionally, the size of the first cavity is larger than that of the chip; the size of the second cavity is larger than that of the first cavity, and forms a step structure with the first cavity.

[0012] In a second aspect, the present application further provides a packaging method, using the packaging structure described in any one of the first aspects, comprising the following steps:

[0013] A high-temperature co-fired ceramic technology is used to punch holes in the first ceramic layer and print wiring; a via hole and a first cavity are punched in the second ceramic layer and print wiring; a via hole and a second cavity are punched in the third ceramic layer and print wiring, and then the first ceramic layer, the second ceramic layer, and the third ceramic layer are stacked and laminated to obtain a first green ceramic body, and the first green ceramic body is sintered at a high temperature to obtain a first ceramic body;

[0014] The fourth ceramic layer is punched with vias and printed with wiring using high-temperature co-fired ceramic technology; the fifth ceramic layer does not need to be punched or printed with wiring, and the fourth ceramic layer and the fifth ceramic layer are stacked and laminated to obtain a second green ceramic body, and the second green ceramic body is sintered at a high temperature to obtain a second ceramic body;

[0015] Electroplating the first ceramic body with nickel and gold to obtain a ceramic shell, electroplating the second ceramic body with nickel and gold to obtain a ceramic cover, soldering a plurality of first lead pins to a lower surface of the ceramic shell with silver-copper solder, and soldering a plurality of second lead pins to an upper surface of the ceramic cover with silver-copper solder;

[0016] Pre-place a solder sheet on the lower surface of the ceramic cover plate, and place the chip on the upper surface of the first ceramic layer;

[0017] Injecting epoxy resin glue into the first cavity and the second cavity of the ceramic housing by an automatic glue dispensing machine;

[0018] The solder sheet on the ceramic cover is baked to weld the ceramic housing and the ceramic cover together to achieve airtight packaging.

[0019] Optionally, a plurality of first via holes are punched out of the first ceramic layer, each of the first via holes is filled with metallization paste, and metal traces are printed on the first ceramic layer to form a basic path for signal transmission; a second via hole and a first cavity are punched out of the second ceramic layer, the second via hole is filled with metallization paste, and metal traces are printed on the second ceramic layer; a third via hole and a second cavity are punched out of the third ceramic layer, the third via hole is filled with metallization paste, and metal traces are printed on the third ceramic layer;

[0020] Optionally, a ceramic green sheet is selected as the fourth ceramic layer, and based on the high-temperature co-fired ceramic technology, a fourth via is punched out of the fourth ceramic layer, and the fourth via is filled with metallization slurry. At the same time, metal traces and insulating medium covering areas are printed on the fourth ceramic layer, and the insulating medium covering area is used to isolate subsequent solder sheets from the first pad and the second pad; the fifth ceramic layer does not need to be punched and printed with traces, and only serves as a structural support; the fourth ceramic layer and the fifth ceramic layer are stacked and laminated to form a second green ceramic body, and a second notch is cut on the side of the second green ceramic body, and its shape matches the first notch for packaging alignment.

[0021] The present application provides a packaging structure and method that utilizes high-temperature co-fired ceramic technology to achieve multi-layer ceramic stacking and metallized via and trace design, thereby constructing efficient vertical and horizontal signal transmission paths, shortening signal transmission distances, and meeting high-density interconnect requirements. Electroplating the ceramic body with nickel and gold enhances the conductivity and oxidation resistance of the pads, and using silver-copper solder to solder Kovar alloy pins to form a double-sided electrode structure. This structure enables bidirectional signal routing, improving circuit design flexibility and integration density. Pre-placement of solder pads on the ceramic cover plate and a bake-soldering process reduce the risk of seal cracking caused by differences in thermal expansion coefficients between ceramic and metal, ensuring package airtightness and reliability. An insulating dielectric covering area on the lower surface of the ceramic cover plate isolates the solder pads from the pads, preventing short circuits in high-voltage environments and improving structural safety. An automated dispensing machine injects epoxy resin glue to cover the chip and bonding wires, forming an internal protective layer that prevents mechanical damage, enhances insulation, and improves internal structural stability. Featured notches on the sides of the ceramic housing and cover plate enable precise mechanical alignment, improving packaging accuracy and yield, and ensuring accurate connection between the pads and signal transmission holes.

[0022] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0024] Figure 1 A schematic diagram of a packaging structure provided in one embodiment of the present application.

[0025] Figure 2 A schematic cross-sectional view of a packaging structure provided in one embodiment of the present application.

[0026] Figure 3 This is a schematic cross-sectional view of a ceramic cover plate in a packaging structure provided in one embodiment of the present application from a first perspective.

[0027] Figure 4 This is a cross-sectional schematic diagram from a second perspective of a ceramic cover plate in a packaging structure provided in one embodiment of the present application.

[0028] Figure 5 This is a flowchart of a packaging method provided in one embodiment of the present application.

[0029] In the figure: 1-ceramic housing, 2-ceramic cover, 3-chip, 11-first lead pin, 12-first ceramic body, 121-first ceramic layer, 122-second ceramic layer, 123-third ceramic layer, 13-first solder pad, 14-first notch, 15-chip mounting area, 16-bonding wire, 17-first cavity, 18-second cavity; 21-second lead pin, 22-second ceramic body, 221-fourth ceramic layer, 222-fifth ceramic layer, 23-second solder pad, 24-second notch, 25-solder sheet, 26-insulating medium covering area. DETAILED DESCRIPTION

[0030] To make the purpose and technical solutions of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the described embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0031] It should be understood that when an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it can be directly on, directly connected to, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present.

[0032] It should be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another region, layer, or portion. Therefore, the first element, component, region, layer, or portion discussed below may be referred to as a second element, component, region, layer, or portion without departing from the teachings of the present invention.

[0033] For ease of description, spatially relative terms such as "below," "beneath," "below," "above," and "upper" may be used herein to describe the relationship of one element or component to another element or components as shown in the figures. It should be understood that these spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or components would be oriented "above" the other elements or components. Thus, the exemplary terms "above" or "below" can encompass both above and below orientations. The device may also be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative terms used herein should be interpreted accordingly.

[0034] The terminology used herein is for the purpose of describing specific example embodiments only and is not intended to limit the present invention. Unless otherwise expressly stated herein, as used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well. It should be further understood that the terms "comprise" and / or "include" (when used in this specification) specify the presence of the recited features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0035] References throughout this specification to "one embodiment" or "an embodiment" mean that a particular component, structure, or feature described in connection with that embodiment is included in at least one embodiment. Therefore, appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, particular components, structures, or features may be combined in any suitable manner in one or more embodiments. It should be understood that the following figures are not drawn to scale and that these figures are for illustrative purposes only.

[0036] In one embodiment, see Figure 1 The present application provides a packaging structure, including a ceramic shell 1 and a ceramic cover plate 2, the ceramic shell 1 is connected to the ceramic cover plate 2; the ceramic shell 1 includes a plurality of first lead pins 11, a first ceramic body 12, and a first soldering pad 13, the plurality of first lead pins 11 are arranged on the lower surface of the first ceramic body 12, and the first soldering pad 13 is arranged on the upper surface of the first ceramic body 12; the ceramic cover plate 2 includes a plurality of second lead pins 21, a second ceramic body 22, a second soldering pad 23, and a solder sheet 25, the plurality of second lead pins 21 are arranged on the upper surface of the second ceramic body 22, the second soldering pad 23 is arranged on the lower surface of the second ceramic body 22, the solder sheet 25 is arranged between the ceramic shell 1 and the ceramic cover plate 2, and the ceramic shell 1 and the ceramic cover plate 2 are welded through the solder sheet 25 in the ceramic cover plate 2.

[0037] As an example, see Figure 2 The present application provides a packaging structure that also includes a chip 3. The chip 3 is installed in the ceramic housing 1. The size of the chip 3 is smaller than the size of the ceramic housing 1 to adapt to the chip installation.

[0038] As an example, each first lead pin 11 may be cylindrical / square and made of Kovar alloy. Each first lead pin 11 is connected to the lower surface of the first ceramic body 12 via silver-copper solder and may be used to lead out signals.

[0039] In an example, the ceramic housing 1 may include four first lead pins 11 .

[0040] As an example, see Figure 2 The first ceramic body 12 can be a multi-layer ceramic structure, including: a first ceramic layer 121, a second ceramic layer 122 and a third ceramic layer 123, the first ceramic layer 121 serves as a substrate, the second ceramic layer 122 is arranged on the upper surface of the first ceramic layer 121, and the third ceramic layer 123 is arranged on the upper surface of the second ceramic layer 122.

[0041] Optionally, each of the first ceramic layer 121, the second ceramic layer 122, and the third ceramic layer 123 includes multiple vias (not shown). These vias are filled with metallization slurry to form signal transmission holes between the first ceramic layer 121, the second ceramic layer 122, and the third ceramic layer 123. By constructing vertical and horizontal signal transmission paths between the multiple ceramic layers, the circuits in different ceramic layers can effectively interconnect electrical signals, providing a foundation for complex signal transmission within the package structure. The stacking and lamination of the multiple ceramic layers to form an integrated first ceramic body significantly reduces the package volume while improving structural stability.

[0042] As an example, the material of the first solder pad 13 is based on a metallization paste, which is firmly bonded to the third ceramic layer 123 after high-temperature sintering. The surface of the first solder pad 13 is also covered with a nickel layer and a gold layer through an electroplating process to enhance conductivity and oxidation resistance. As an example, the first solder pad 13 is located on the upper surface of the third ceramic layer 123. Its structure is tightly integrated with the metal traces and vias within the third ceramic layer 123. The vias are filled with metallization paste to form an integrated conductive path, ensuring the continuity of vertical and horizontal signal transmission in the multilayer ceramic structure. The first solder pad 13 forms a conductive path with the first lead pin 11 on the bottom surface of the ceramic housing 1 through the vias of the third ceramic layer 123, the second ceramic layer 122, and the first ceramic layer 121.

[0043] As an example, the ceramic housing 1 further includes a third pad (not shown), which is disposed at the connection between the lower surface of the first ceramic layer 121 and the first lead pin 11 .

[0044] As an example, see Figure 1 The ceramic housing 1 further includes a first notch 14 , which is integrally formed with the ceramic housing 1 and is disposed on the outer side of the ceramic housing 1 .

[0045] As an example, the first notch 14 provides a mechanical alignment reference during package welding to achieve precise positioning of the ceramic housing 1 and the ceramic cover 2, but has no signal transmission function.

[0046] As an example, see Figure 2 The ceramic housing 1 also includes a chip mounting area 15 and a bonding wire 16. The chip mounting area 15 is located on the upper surface of the first ceramic layer 121 and is used to mount the chip 3. The first end of the bonding wire 16 is connected to the chip 3, and the second end of the bonding wire 16 is connected to the fourth pad (not shown) on the upper surface of the second ceramic layer 122.

[0047] As an example, the surface material of the chip mounting area 15 may be ceramic or metal, and the chip mounting area 15 is connected to the third pad on the bottom surface of the ceramic housing 1 through the via hole of the first ceramic layer 121 to achieve signal connection.

[0048] As an example, the chip mounting area 15 can mount at least one chip 3 , which depends on the size of the ceramic housing 1 and the chip 3 and is not limited here.

[0049] As an example, bonding wire 16 can be made of metal conductors and can be used to interconnect chip 3 and ceramic housing 1, forming a stable electrical connection. This ensures that the chip's electrical signals can be effectively transmitted to ceramic housing 1 and then led out to the external circuit via first lead pin 11. This connection method flexibly adapts to the miniaturized design of the package structure, enabling signal transmission between the chip and internal circuits within a limited cavity space, helping to shorten the signal transmission path and improve the electrical performance and integrated reliability of the package structure.

[0050] As an example, see Figure 2 The ceramic shell 1 also includes a first cavity 17 and a second cavity 18. The first cavity 17 is located inside the second ceramic layer 122, and the second cavity 18 is located inside the third ceramic layer 123. The first cavity 17 and the second cavity 18 form a step structure. The height of the step structure is lower than the height of the ceramic shell 1. The step surface of the step structure is provided with a fourth pad for connecting the bonding wire 16.

[0051] As an example, the first cavity 17 can be a square cavity. The size of the first cavity 17 is larger than the size of the chip 3 and can be used to accommodate the chip 3 and epoxy resin glue. The space of the first cavity 17 avoids unnecessary contact between the chip 3 and other metal structures of the ceramic housing 1, ensuring stable electrical performance and thus reducing stress.

[0052] As an example, the second cavity 18 can be a circular cavity, the size of the second cavity 18 is larger than the size of the first cavity 17, and the second cavity 18 and the first cavity 17 form a step structure to facilitate exposure of the fourth pad located on the upper surface of the second ceramic layer 122, and the height of the step structure is lower than the height of the ceramic shell.

[0053] As an example, the first ceramic body 12 of the ceramic housing 1 is formed by stacking and laminating a first ceramic layer 121, a second ceramic layer 122, and a third ceramic layer 123 through high-temperature co-firing technology and sintering at high temperature. The punched vias in each layer are filled with metallization slurry and the metal traces printed in the layer realize vertical and horizontal electrical interconnection of the three ceramic layers. The first cavity 17 of the second ceramic layer 122 is used to place the chip 3. The second cavity 18 of the third ceramic layer 123 can expose the fourth pad located on the upper surface of the second ceramic layer 122. Multiple first lead pins 11 are connected to the lower surface of the first ceramic body 12 through silver-copper solder. The bonding wire 16 is located inside the first cavity 17 and the second cavity 18. One end is connected to the chip 3 in the chip mounting area 15, and the other end is connected to the fourth pad and forms a signal path with the first lead pin 11 through the internal metallization channel. The first notch 14 is formed by cutting on the side of the first ceramic body for mechanical interlocking to achieve welding alignment. The multilayer ceramic layer and the metallization paste form an efficient signal transmission channel. The first lead pin 11 is stably connected to the first pad 13 through the signal transmission channel to ensure signal lead-out. The first notch 14 ensures accurate packaging. The chip mounting area 15 and the bonding wire 16 adapt to the integration of the chip 3 and shorten the path, ultimately forming a high-voltage ceramic packaging structure with small size, excellent performance and high reliability.

[0054] As an example, see Figure 3 Each second lead pin 21 may be cylindrical / square and made of Kovar alloy. Each second lead pin 21 may be connected to the upper surface of the second ceramic body 22 via silver-copper solder to lead out the signal.

[0055] In an example, the ceramic cover plate 2 may include two second lead pins 21 .

[0056] As an example, see Figure 3 The second ceramic body 22 is a double-layer ceramic structure, including: a fourth ceramic layer 221 and a fifth ceramic layer 222 , and the fifth ceramic layer 222 is arranged on the lower surface of the fourth ceramic layer 221 .

[0057] Optionally, the fourth ceramic layer 221 is punched with vias and filled with metallization paste, while metal traces and insulating dielectric coverage areas are printed on the surface to create vertical and horizontal signal transmission paths. The fifth ceramic layer 222 does not require punching or trace printing and serves only as a structural support layer. The stacking and lamination of the two ceramic layers forms an integrated second ceramic body 22, significantly reducing the package size while improving the rigidity and sealing of the cover.

[0058] As an example, the second pad 23 is constructed from a metallized paste that, after high-temperature sintering, firmly bonds to the fourth ceramic layer 221. The surface is also electroplated with nickel and gold layers to enhance conductivity and oxidation resistance. Located on the underside of the fourth ceramic layer 221, the second pad 23 precisely mates with the first pad 13 of the ceramic housing 1 during packaging, establishing a complete signal transmission link between the chip and the upper and lower pins. This reduces signal transmission losses, improves electrical performance, and lays the structural foundation for subsequent airtight packaging.

[0059] As an example, the ceramic cover plate 2 further includes a fifth pad (not shown), which is disposed at the connection between the upper surface of the fourth ceramic layer 221 and the second lead pin 21 .

[0060] As an example, see Figure 4 The ceramic cover plate 2 also includes a second notch 24, a solder sheet 25 and at least one insulating medium covering area 26. The second notch 24 is arranged on the outer side of the ceramic cover plate 2 for welding and aligning with the first notch 14. The solder sheet 25 is located on the lower bottom surface of the ceramic cover plate 2 and is used to connect the ceramic cover plate 2 and the ceramic shell 1. The insulating medium covering area 26 is located on the lower surface of the ceramic cover plate 2, between the solder sheet 25 and the second pad 23.

[0061] As an example, the second notch 24 provides a mechanical alignment reference during package welding to achieve precise positioning of the ceramic housing 1 and the ceramic cover 2, but has no signal transmission function.

[0062] As an example, the shapes and sizes of the first notch 14 and the second notch 24 can be adjusted according to specific designs.

[0063] As an example, the solder sheet 25 can be a double-circle circular solder sheet, including an outer circular solder sheet and an inner symmetrical double-arc solder sheet. The material can be AuSn, tin-silver-copper alloy, etc. The ceramic shell 1 and the ceramic cover plate 2 can be welded together through the solder sheet 25. The solder sheet 25 is a key component for achieving airtight packaging, and the solder sheet 25 needs to be away from the wiring area to ensure electrical and sealing properties.

[0064] As an example, the insulating medium covering area 26 is a thin layer of insulating medium, non-ceramic material, covering the designated area on the lower surface of the ceramic cover plate 2. The designated area is between the solder sheet 25 and the first pad 13 / second pad 23. The insulating medium covering area 26 can isolate the solder sheet and the pad area, realize the solder resist function, and avoid short circuit between the welding area and the electrical connection area.

[0065] Optionally, the insulating medium covering area 26 can also isolate the inner circle and the outer circle of the solder sheet 25 to achieve solder resistance; the insulating medium covering area 26 can be of any shape.

[0066] As an example, the second ceramic body 22 is formed as an integral body by stacking and laminating the fourth ceramic layer 221 and the fifth ceramic layer 222 through high-temperature co-fired ceramic technology and then sintering at high temperature, wherein the fourth ceramic layer 221 is punched with a via and the hole is filled with metallization paste, and the metal traces and the second pad 23 are printed on the surface, and an insulating medium covering area 26 is provided. The fifth ceramic layer 222 serves as a structural support layer without vias and metal traces, and the two are tightly combined to form a double-layer structure; the via metallization paste of the fourth ceramic layer 221 is conductive to the metal traces, the second pad 23 is connected to the metal traces, and multiple second lead pins 21 are vertically welded to the upper surface of the fourth ceramic layer 221 through silver-copper solder, and the second notch 24 is located at the first The outer side surface of the second ceramic body 22 matches the first notch 14 of the ceramic shell 1. The solder sheet 25 is pre-soldered to the edge of the lower surface of the second ceramic body 22 and is isolated from the second pad 23 / first pad 13 by the insulating medium covering area 26. This structure enables the integrated design of the fourth ceramic layer 221 and the fifth ceramic layer 222 to improve the overall rigidity and sealing. The vias and metal traces cooperate with the second lead pin 21 to achieve efficient signal transmission. The insulating medium covering area 26 prevents solder overflow and short circuit. The second notch 24 ensures precise alignment with the ceramic shell 1, and the solder sheet 25 assists in airtight packaging, comprehensively achieving the effects of short signal transmission path, high reliability, and improved packaging accuracy and yield under high-voltage environment.

[0067] As an example, the packaging structure provided in the present application can be a circular ceramic packaging structure and include double-sided electrodes. Double-sided electrodes refer to a structural design in which electrodes are provided on both the upper side of the ceramic cover plate 2 and the lower side of the ceramic housing 1. The bottom of the ceramic housing 1 is connected to a plurality of first lead pins 11 as lower electrodes via silver-copper solder, and the top of the ceramic cover plate 2 is connected to a plurality of second lead pins 21 as upper electrodes via silver-copper solder. The upper and lower lead pins together serve as electrodes to simultaneously lead out electrical signals from the upper and lower sides of the packaging structure. This structure can shorten the signal transmission path, improve integration density and circuit design flexibility.

[0068] In the above packaging structure, a double-sided electrode is formed by the first lead pin at the bottom of the ceramic shell and the second lead pin at the top of the ceramic cover, which can realize the synchronous lead-out of the upper and lower bidirectional signals, shorten the transmission distance from the chip to the external circuit, and improve the electrical performance; the multi-layer ceramic co-fired structure of the ceramic shell and the ceramic cover and the welding seal of the annular solder sheet can avoid the risk of thermal mismatch between metal and ceramic and ensure the reliability of the airtight packaging; the first notch of the ceramic shell and the second notch of the ceramic cover are mechanically engaged and accurately aligned to ensure that the pads and the signal transmission holes are aligned one by one, thereby improving the packaging accuracy; The insulating medium covering area on the lower surface of the cover isolates the solder sheet and the pad, which can block the solder overflow path, prevent short circuit in high-voltage environment, and ensure electrical safety; the stepped cavity inside the ceramic shell can adapt to the curvature of the bonding wire to reduce mechanical stress, while accommodating epoxy resin glue to protect the chip and bonding wire, enhancing structural robustness; vertical interconnection is achieved through multi-layer ceramic stacking and through-hole metallization, which can significantly reduce the package volume, maintain structural stability and high integration, and ultimately form a high-voltage double-sided electrode ceramic airtight packaging structure with small size, short electrical signal transmission path and high reliability.

[0069] In one embodiment, see Figure 5 The present application also provides a packaging method, which is applied to the above-mentioned packaging structure. The packaging method includes the following steps: step S1 to step S6.

[0070] Step S1: Use high-temperature co-fired ceramic technology to punch through holes in the first ceramic layer and print wiring; punch through holes and a first cavity in the second ceramic layer and print wiring; punch through holes and a second cavity in the third ceramic layer and print wiring, then stack and laminate the first ceramic layer, the second ceramic layer, and the third ceramic layer to obtain a first green ceramic body, and sinter the first green ceramic body at a high temperature to obtain a first ceramic body.

[0071] Step S2: Using high-temperature co-fired ceramic technology, punch through holes and print wiring on the fourth ceramic layer; there is no need to punch holes and print wiring on the fifth ceramic layer, and then stack and laminate the fourth ceramic layer with the fifth ceramic layer to obtain a second green ceramic body, and sinter the second green ceramic body at a high temperature to obtain a second ceramic body.

[0072] Step S3: Electroplating the first ceramic body with nickel and gold to obtain a ceramic shell, electroplating the second ceramic body with nickel and gold to obtain a ceramic cover, welding multiple first lead pins to the lower surface of the ceramic shell with silver-copper solder, and welding multiple second lead pins to the upper surface of the ceramic cover with silver-copper solder.

[0073] Step S4: pre-place a solder sheet on the lower surface of the ceramic cover plate, and place the chip on the upper surface of the first ceramic layer.

[0074] Step S5: injecting epoxy resin glue into the first cavity and the second cavity of the ceramic housing by an automatic glue dispensing machine.

[0075] Step S6: baking the solder sheet on the ceramic cover to weld the ceramic housing and the ceramic cover together to achieve airtight packaging.

[0076] In the packaging method of the present application, by arranging metal lead pins on the upper and lower parts of the ceramic shell and the cover plate at the same time, double-sided electrode signal lead-out can be achieved, the interconnection distance can be shortened, and the electrical performance under high-voltage environment can be improved; by adopting the ceramic cover plate and the ceramic shell to weld and seal through solder sheets, the risk of cracking caused by the mismatch of metal-ceramic thermal expansion coefficient can be avoided, and the airtightness reliability can be guaranteed; by arranging an insulating medium covering area on the lower surface of the ceramic cover plate, the solder sheet and the signal pad can be isolated to prevent high-voltage short circuit; by arranging characteristic notches on the sides of the ceramic shell and the cover plate, precise mechanical alignment can be achieved, and the packaging accuracy and yield can be improved; finally, a high-voltage double-sided electrode ceramic airtight packaging structure with small size, short electrical signal transmission path and high reliability is formed.

[0077] In step S1, see Figure 5 , high-temperature co-fired ceramic technology is used to punch vias on the first ceramic layer and print routing; vias and a first cavity are punched on the second ceramic layer and routing is printed; vias and a second cavity are punched on the third ceramic layer and routing is printed, and then the first ceramic layer, the second ceramic layer, and the third ceramic layer are stacked and laminated to obtain a first green ceramic body, and the first green ceramic body is sintered at a high temperature to obtain a first ceramic body.

[0078] As an example, the first green ceramic body may include three ceramic layers, namely, a first ceramic layer 121 , a second ceramic layer 122 , and a third ceramic layer 123 .

[0079] Specifically, based on high-temperature co-fired ceramic technology, multiple first vias are punched out of the first ceramic layer 121, each first via is filled with metallization slurry, and metal traces are printed on the first ceramic layer 121 to form a basic path for signal transmission; second vias and a first cavity 17 are punched out of the second ceramic layer 122, the second via is filled with metallization slurry, and metal traces are printed on the second ceramic layer 122; third vias and a second cavity 18 are punched out of the third ceramic layer 123; the third via is filled with metallization slurry, and metal traces are printed on the third ceramic layer 123.

[0080] As an example, the first cavity 17 may be square in shape and larger than the chip 3 , and may be used to accommodate the chip 3 .

[0081] As an example, the first cavity 17 may serve as a chip mounting area 15 for placing the chip 3 .

[0082] As an example, the second cavity 18 can be circular in shape and sized to accommodate the chip 3. The second cavity 18 is larger than the first cavity 17 to expose the first solder pad 13 on the upper surface of the second ceramic layer 122, providing space for soldering connection between the ceramic housing 1 and the ceramic cover 2.

[0083] As an example, the first via hole, the second via hole, and the third via hole can be used as signal transmission holes to achieve electrical interconnection of the ceramic layers.

[0084] Furthermore, the first ceramic layer, the second ceramic layer, and the third ceramic layer are stacked and laminated to obtain a first green ceramic body, and then the side of the first green ceramic body is cut to form a first notch 14 for alignment, and finally the first green ceramic body is sintered at a high temperature to obtain a first ceramic body 12.

[0085] In step S2, see Figure 5 , high-temperature co-fired ceramic technology is used to punch through holes and print wiring on the fourth ceramic layer; there is no need to punch holes and print wiring on the fifth ceramic layer, and then the fourth ceramic layer and the fifth ceramic layer are stacked and laminated to obtain a second green ceramic body, and the second green ceramic body is sintered at a high temperature to obtain a second ceramic body.

[0086] As an example, the second ceramic body 22 is an integral structure of double-layer ceramics, which ensures the rigidity and sealing of the cover.

[0087] Specifically, in step S2, a ceramic green sheet is selected as the fourth ceramic layer 221, and based on the high-temperature co-fired ceramic technology, a fourth via is punched out of the fourth ceramic layer 221, and the fourth via is filled with metallization slurry. At the same time, metal traces and insulating medium covering areas are printed on the fourth ceramic layer 221. The insulating medium covering area is used to isolate the subsequent solder sheet 25 from the first pad 13 / second pad 23; the fifth ceramic layer 222 does not need to be punched and printed with traces, and only serves as a structural support; the fourth ceramic layer 221 and the fifth ceramic layer 222 are stacked and laminated to form a second green ceramic body, and a second notch 24 is cut on the side of the second green ceramic body, and its shape matches the first notch 14 for packaging alignment.

[0088] Furthermore, the second green ceramic body with the second notch is sintered at a high temperature to obtain a second ceramic body 22 .

[0089] In step S3, refer to 5, the first ceramic body is electroplated with nickel and gold to obtain a ceramic shell, the second ceramic body is electroplated with nickel and gold to obtain a ceramic cover, and a plurality of first lead pins are welded to the lower surface of the ceramic shell by silver-copper solder, and a plurality of second lead pins are welded to the upper surface of the ceramic cover by silver-copper solder.

[0090] Specifically, in step S3, the upper surface of the third ceramic layer in the first ceramic body 12 is electroplated with nickel and gold to form a first pad, and the lower surface of the fourth ceramic layer in the second ceramic body 22 is electroplated with nickel and gold to form a second pad. This enhances the electrical conductivity and oxidation resistance of the first and second pads, and the first and second pads are connected. The nickel and gold plating of the first ceramic body 12 yields the ceramic housing 1, and the nickel and gold plating of the second ceramic body 22 yields the ceramic cover 2.

[0091] Furthermore, silver-copper solder is used to weld multiple first lead pins 11 to the third pad on the lower surface of the ceramic shell 1 to realize bottom signal lead-out; silver-copper solder is used to weld the second lead pin 21 to the fifth pad on the upper surface of the ceramic cover 2 to realize top signal lead-out, and the first lead pin 11 and the second lead pin 21 are respectively connected to the first pad 13 and the second pad 23 in a one-to-one correspondence.

[0092] As an example, the first lead pin is made of Kovar alloy and has a cylindrical or square shape.

[0093] As an example, the second lead pin is made of Kovar alloy and has a cylindrical or square shape.

[0094] In step S4, see Figure 5 , pre-place a solder sheet on the lower surface of the ceramic cover plate, and place the chip on the upper surface of the first ceramic layer.

[0095] Specifically, in step S4, a solder sheet 25 is pre-placed on the lower surface of the ceramic cover plate 2, and the chip 3 is mounted on the chip mounting area 15 of the ceramic housing 1. The chip 3 can be fixed by conductive glue, and the chip 3 is interconnected with the inner pins of the ceramic housing through bonding wires / pads, etc. to form an electrical connection. The bonding wire 16 is connected to the third pad through the through hole of the ceramic housing 1 to form a signal path between the chip 3 and the first lead pin 11.

[0096] As an example, the solder sheet 25 can be a double-circle circular solder sheet, including an outer circular ring and an inner symmetrical arc. The material can be AuSn, tin-silver-copper alloy, etc., and can be welded to connect the ceramic shell 1 and the ceramic cover plate 2. It is a key component for achieving airtight packaging and needs to be away from the wiring area to ensure electrical and sealing properties.

[0097] In step S5, see Figure 5 , epoxy resin glue is injected into the first cavity and the second cavity of the ceramic shell through an automatic dispensing machine.

[0098] Specifically, in step S5, an automatic dispensing machine is used to inject epoxy resin glue into the first cavity and the second cavity of the ceramic shell 1 to ensure that the glue completely covers the chip 3 and the bonding wire 16; after curing, the epoxy resin glue forms an internal protective layer, which can prevent the chip 3 and the bonding wire 16 from being mechanically damaged during the subsequent packaging process, while enhancing the internal insulation.

[0099] In step S6, refer to Figure 5 ,The solder sheet on the ceramic cover is baked to weld the ceramic shell and the ceramic cover together to achieve airtight packaging.

[0100] Specifically, in step S6, the first notch 14 of the ceramic shell 1 and the second notch 24 of the ceramic cover plate 2 are mechanically aligned to ensure that the first pad corresponds to the second pad, as well as the signal transmission holes of the two. The solder sheet 25 is baked to melt the solder sheet 25, and the molten solder spreads along the upper surface edge of the ceramic shell 1 and the lower surface of the ceramic cover plate 2 to form a sealing solder ring. After welding is completed, the insulating medium covers the area to isolate the solder sheet 25 from the second pad 23 to prevent high-voltage short circuit, and at the same time, the solder ring is used to achieve airtight packaging of the chip mounting area 15.

[0101] Optionally, the first via, the second via, and the third via are all vertical signal transmission channels formed in the corresponding ceramic layers based on high-temperature co-fired ceramic technology. The first via is located in the first ceramic layer 121 and is formed by a punching process. The hole is filled with a special metallization paste for high-temperature co-fired ceramics. It is connected to the metal traces printed on the surface of the first ceramic layer 121, serving as a vertical interconnection basis, and provides an initial channel for signal transmission from the chip mounting area to the pins below. The second via is located in the second ceramic layer 122 and is also formed by punching and filled with a metallization paste. It is connected to the metal traces and the first via of the second ceramic layer 122. Because the second ceramic layer 122 is provided with a first cavity 17 for accommodating the chip, the second via needs to avoid the cavity area. It not only realizes signal conduction inside the second ceramic layer 122, but also transmits the signal transmitted from the chip to the second ceramic layer through the bonding wire 16 downward to the first ceramic layer 121 through cooperation with the first via. The third via, located in the third ceramic layer 123, is formed by punching and filled with metallization slurry, connecting to the metal traces of the third ceramic layer 123 and the corresponding second via. The metallization slurry and the metal traces of the corresponding ceramic layers work together to create a continuous electrical path from the chip mounting area 15 through each ceramic layer to the first lead pin 11, achieving efficient vertical interconnection of the multilayer ceramic structure. This not only ensures stable and low-loss signal transmission, but also supports the multi-layer integrated design of the package structure, laying the foundation for reducing package size and increasing integration density.

[0102] In the above-mentioned packaging method, high-temperature co-fired ceramic technology is used to achieve multi-layer ceramic stacking and metallized via and trace design, thereby constructing efficient vertical and horizontal signal transmission paths, shortening signal transmission distances and meeting high-density interconnect requirements. Nickel-gold electroplating on the ceramic body enhances the conductivity and oxidation resistance of the pads, and silver-copper solder is used to solder Kovar alloy pins to form a double-sided electrode structure, enabling bidirectional signal routing, improving circuit design flexibility and integration density. Pre-placement of solder pads on the ceramic cover plate and a bake-soldering process reduce the risk of seal cracking caused by the difference in thermal expansion coefficients between ceramic and metal, ensuring package airtightness and reliability. An insulating dielectric covering area on the lower surface of the ceramic cover plate isolates the solder pads from the pads, preventing short circuits in high-voltage environments and improving structural safety. Epoxy resin glue injected by an automatic dispensing machine covers the chip and bonding wires, forming an internal protective layer to prevent mechanical damage, enhance insulation, and improve internal structural stability. Featured notches on the sides of the ceramic housing and cover plate enable precise mechanical alignment, improving packaging accuracy and yield, and ensuring accurate connection between the pads and signal transmission holes.

[0103] It should be understood that although the steps in the flowcharts of the accompanying drawings are shown in sequence as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least some of the steps in the accompanying drawings may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The order of execution of these sub-steps or stages is not necessarily sequential, but can be executed in rotation or alternation with other steps or at least a portion of the sub-steps or stages of other steps.

[0104] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0105] Although the present application has been disclosed above with reference to the embodiments, they are not intended to limit the present application. Anyone with ordinary knowledge in the technical field may make slight changes and modifications without departing from the spirit and scope of the present application.

Claims

1. A packaging structure, characterized in that: include: A ceramic shell and a ceramic cover plate, wherein the ceramic shell is connected to the ceramic cover plate; the ceramic shell includes a plurality of first lead pins, a first ceramic body, and a first soldering pad, wherein the plurality of first lead pins are arranged on the lower surface of the first ceramic body, and the first soldering pad is arranged on the upper surface of the first ceramic body; the ceramic cover plate includes a plurality of second lead pins, a second ceramic body, a second soldering pad, and a solder sheet, wherein the plurality of second lead pins are arranged on the upper surface of the second ceramic body, the second soldering pad is arranged on the lower surface of the second ceramic body, the solder sheet is arranged between the ceramic shell and the ceramic cover plate, and the ceramic shell and the ceramic cover plate are welded via the solder sheet.

2. The packaging structure according to claim 1, wherein: The first ceramic body is a multilayer ceramic structure, including: a first ceramic layer, a second ceramic layer and a third ceramic layer. The first ceramic layer serves as a substrate, the second ceramic layer is arranged on the upper surface of the first ceramic layer, and the third ceramic layer is arranged on the upper surface of the second ceramic layer.

3. The packaging structure according to claim 1, wherein: The second ceramic body is a double-layer ceramic structure, including a fourth ceramic layer and a fifth ceramic layer, wherein the fifth ceramic layer is arranged on the lower surface of the fourth ceramic layer.

4. The packaging structure according to claim 1, wherein: The solder sheet is a double-ring annular solder sheet, comprising an outer ring-shaped solder sheet and an inner symmetrical double-arc solder sheet.

5. The packaging structure according to claim 1, wherein: The material of the solder sheet is AuSn or tin-silver-copper alloy.

6. The packaging structure according to claim 1, wherein: Each of the first lead pins is cylindrical or square, and is made of Kovar alloy; each of the second lead pins is cylindrical or square, and is made of Kovar alloy.

7. The packaging structure according to claim 1, wherein: The ceramic housing further includes a first cavity and a second cavity, wherein the first cavity is located inside the second ceramic layer, and the second cavity is located inside the third ceramic layer.

8. The packaging structure according to claim 7, wherein: The size of the first cavity is larger than the chip size, and the size of the second cavity is larger than the first cavity size.

9. A packaging method, characterized in that: Applying the packaging structure according to any one of claims 1 to 8 comprises the following steps: A high-temperature co-fired ceramic technology is used to punch holes in the first ceramic layer and print wiring; a via hole and a first cavity are punched in the second ceramic layer and print wiring; a via hole and a second cavity are punched in the third ceramic layer and print wiring, and then the first ceramic layer, the second ceramic layer, and the third ceramic layer are stacked and laminated to obtain a first green ceramic body, and the first green ceramic body is sintered at a high temperature to obtain a first ceramic body; Using high-temperature co-fired ceramic technology, punching holes and printing traces on the fourth ceramic layer; punching holes and printing traces on the fifth ceramic layer are not required; the fourth ceramic layer and the fifth ceramic layer are then stacked and laminated to obtain a second green ceramic body; the second green ceramic body is sintered at a high temperature to obtain a second ceramic body; Electroplating the first ceramic body with nickel and gold to obtain a ceramic shell, electroplating the second ceramic body with nickel and gold to obtain a ceramic cover, soldering a plurality of first lead pins to a lower surface of the ceramic shell with silver-copper solder, and soldering a plurality of second lead pins to an upper surface of the ceramic cover with silver-copper solder; Pre-place a solder sheet on the lower surface of the ceramic cover plate, and place the chip on the upper surface of the first ceramic layer; Injecting epoxy resin glue into the first cavity and the second cavity of the ceramic housing by an automatic glue dispensing machine; The solder sheet on the ceramic cover is baked to weld the ceramic housing and the ceramic cover together to achieve airtight packaging.

10. The packaging method according to claim 9, wherein: High-temperature co-fired ceramic technology is used to punch through holes and print traces on the fourth ceramic layer; punching and printing traces are not required for the fifth ceramic layer, and then the fourth ceramic layer and the fifth ceramic layer are stacked and laminated to obtain a second green ceramic body, and the second green ceramic body is sintered at a high temperature to obtain a second ceramic body, including: selecting a ceramic green sheet as the fourth ceramic layer, punching a fourth via hole on the fourth ceramic layer based on high-temperature co-fired ceramic technology, filling the fourth via hole with metallization slurry, and printing metal traces and an insulating dielectric covering area on the fourth ceramic layer, wherein the insulating dielectric covering area is used to isolate subsequent solder sheets from the first pad and the second pad; the fifth ceramic layer does not need to be punched or printed with traces and only serves as a structural support; The fourth ceramic layer and the fifth ceramic layer are stacked and laminated to form a second green ceramic body. A second notch is cut on the side of the second green ceramic body, and its shape matches the first notch. The second green ceramic body with the second notch is sintered at a high temperature to obtain a second ceramic body.

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