A current mode PWM controller

Abstract

The application belongs to the technical field of PWM controller circuit, and particularly relates to a current mode PWM controller. The current mode PWM controller comprises an oscillator module, a FB detection module, a CS detection module and a peak current detection module. The FB detection module inputs a feedback voltage signal FB through a FB port to control the conduction and cut-off of a triode Q1, and outputs three voltage signals to an overload protection module, a hiccup control module and a PWM comparator CMP1. The CS detection module inputs an inductor current signal of an off-chip loop through a CS port, converts the inductor current signal into a voltage signal CS through an off-chip sampling resistor Rd, and inputs the voltage signal into an on-chip after processing by a front porch blanking circuit to output a signal P876_G. The peak current detection module inputs a signal obtained by superimposing the voltage signal CS and a triangular wave signal N4_G output by the oscillator module after front porch blanking switching to the PWM comparator CMP1. The current mode PWM controller can realize fast load response through peak current detection and voltage / current double feedback.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of PWM controller circuit, and particularly relates to a current mode PWM controller. BACKGROUND

[0002] The current mode PWM controller is a core control technology in a switching power supply, and is mainly divided into three types of peak current mode (PCM), valley current mode (VCM) and hysteretic current mode (HCM), each of which has different advantages and disadvantages: (1) the peak current mode control mode has the advantages of fast dynamic response, is suitable for high-frequency switching, has self-periodic current limiting protection, is high in reliability, is not sensitive to input voltage variation, is easy to realize multi-phase parallel connection, and is suitable for large-current application; and the disadvantage is that slope compensation is required, otherwise subharmonic oscillation may occur when the duty cycle is greater than 50%, the control mode is sensitive to noise, the current detection precision affects stability, and the light load efficiency is relatively low; (2) the average current mode (VCM) control mode has the advantages of being suitable for synchronous Buck and other low-side switching topologies, being simpler in detection of lower tube current, being free of slope compensation, being better in stability, being high in light load efficiency, and being suitable for battery-powered devices; and the disadvantage is that the dynamic response is slower than that of PCM, the precision requirement of the valley value of inductance current is high, and the duty cycle adjustment range is limited; (3) the hysteretic current mode (HCM) control mode has the advantages of being free of fixed frequency clock, being adaptive to switching frequency (variable frequency control), being extremely fast in transient response, being suitable for high dynamic load (such as FPGA and ASIC power supply), being free of compensation network requirement, and simplifying design; and the disadvantage is that the switching frequency is not fixed, EMI is difficult to optimize, the frequency may be too low at light load, affecting the output ripple, and the current detection precision and noise resistance are weak.

[0003] The PWM controller in the prior art mainly has the defect of contradiction between dynamic response and stability. When the peak current mode (PCM) control mode is adopted, slope compensation is required to prevent subharmonic oscillation, but excessive compensation will reduce the dynamic response speed, and although the hysteretic control (HCM) is fast in response, the variable frequency characteristic leads to complex EMI design, and it is difficult to meet the high-precision power supply requirement. SUMMARY

[0004] The purpose of the present application is to provide a current mode PWM controller. The current mode PWM controller can realize fast load response through peak current detection and voltage / current double feedback. The current loop directly participates in PWM comparison, and the response speed is 5-10 times faster than that of pure voltage feedback, and is suitable for transient load scenarios (such as CPU dynamic frequency adjustment).

[0005] To solve the above technical problems, the present application provides a current mode PWM controller, which comprises:

[0006] The FB detection module inputs the feedback voltage signal FB through the FB port to control the conduction and cut-off of the transistor Q1, and outputs three voltage signals to the overload protection module, the hiccup control module and the PWM comparator CMP1;

[0007] The CS detection module inputs the inductor current signal of the off-chip loop through the CS port, converts the inductor current signal into a voltage signal CS through the off-chip sampling resistor Rd, and inputs the voltage signal CS into the chip, and outputs the signal P876_G after processing by the front porch blanking circuit;

[0008] The peak current detection module inputs the voltage signal CS and the triangular wave signal N4_G output by the oscillator module after superposition, and inputs the signal after front porch blanking switching to the PWM comparator CMP1, compares the signal with one of the voltage signals P879_G output by the FB detection module, and outputs the signal X835_YN;

[0009] The hiccup control module compares the voltage signal P872_G output by the FB detection module with the comparison threshold, processes the signal, and outputs the signal X840_SNN to control whether the oscillator module enters the hiccup mode;

[0010] The overload protection module compares the voltage signal R932_PLUS output by the FB detection module with the overload threshold, processes the signal, and outputs the signal X821_Y;

[0011] The overcurrent protection module compares the signal P876_G input into the overcurrent protection module with the overcurrent threshold, and outputs the signal X815_YN;

[0012] The PWM logic control module processes the input signals X835_YN, X821_Y and X815_YN, and outputs the signal X823_Y as the input control signal of the soft drive module to determine the duty cycle of the chip output drive signal.

[0013] Preferably, the FB detection module comprises: a triode Q1, resistors R0~R6 and a current source I1; one end of the current source I1 is connected to a power supply X2_D, the other end is connected to one end of a resistor R6, the other end of the resistor R6 is connected to one end of a resistor R1, one end of a resistor R2 and the base and collector of the triode Q1, the other end of the resistor R1 is connected to an FB port, the FB port is connected to an off-chip optocoupler U0 connected to a chip output voltage, a current signal is output to the resistor R1 of the FB port through the optocoupler U0 to form a voltage signal FB, the other end of the resistor R2 is connected to the power supply X2_D, the emitter of the triode Q1 is connected to one end of a resistor R3 and a resistor R4, the other end of the resistor R4 outputs a voltage signal P872_G, the other end of the resistor R3 is connected to one end of a resistor R0 and outputs a voltage signal R932_PLUS, the other end of the resistor R0 is connected to a grounded resistor R5 and outputs a voltage signal P879_G.

[0014] Preferably, the peak current detection module comprises: an operational amplifier OP1, resistors R7~R8 and an NMOS tube N1; the positive input end of the operational amplifier OP1 is connected to a triangular wave signal N4_G, the negative input end is connected to the output end and one end of a resistor R7, the other end of the resistor R7 is connected to one end of a resistor R8 and the drain of the NMOS tube N1 and outputs a blanked superimposed signal, the other end of the resistor R8 is connected to the voltage signal CS, the gate of the NMOS tube N1 is connected to a blanking control signal X824_Y of a rectangular wave, and the source of the NMOS tube N1 is grounded.

[0015] Preferably, the overload protection module comprises: a comparator CMP2, a NOT gate X1, a NOT gate X5, AND gates X2~X4, an AND gate X6, a T flip-flop TFF and a D flip-flop DFF; the positive input end of the comparator CMP2 is connected to a voltage signal R932_PLUS, the negative input end is connected to an overload threshold voltage P364_D, the output end is connected to input end one of the AND gate X2 through the NOT gate X1, input end two of the AND gate X2 is connected to a logic signal "1", the output end of the AND gate X2 is connected to input end one of the AND gates X3~X4, input end two of the AND gate X3 is connected to a logic signal "1", input end two of the AND gate X4 is connected to a signal X1255_Q of a rectangular wave, the output end of the AND gate X3 is connected to the Reset end of the T flip-flop TFF and the D flip-flop DFF, the output end of the AND gate X4 is connected to the CLK end of the T flip-flop TFF, the Q end of the T flip-flop TFF is connected to the CLK end of the D flip-flop DFF, the D end of the D flip-flop DFF is connected to a logic signal "1", the Q end of the D flip-flop DFF is connected to input end one of the AND gate X6 through the NOT gate X5, input end two of the AND gate X6 is connected to a logic signal "1", and the output end of the AND gate X6 outputs a signal X821_Y.

[0016] Preferably, the burp control module comprises: an operational amplifier OP2, a NOT gate X7 and a selector MUX; the positive input terminal of the operational amplifier OP2 is connected to a comparison threshold voltage X840_Y and a signal X840_SNN, the negative input terminal is connected to a voltage signal P872_G, the output terminal is connected to the S terminal of the selector MUX through the NOT gate X7, the A terminal of the selector MUX is connected to a voltage signal P191_G, the B terminal of the selector MUX is connected to a voltage signal R736_MINUS, and the Y terminal of the selector MUX outputs a signal X840_SNN.

[0017] Preferably, the CS detection module comprises: a sampling resistor Rd, a resistor R12 and an NMOS tube N3; an inductive current signal of an input off-chip loop is converted into a voltage signal CS by the sampling resistor Rd grounded, and input to one end of the resistor R12, the other end of the resistor R12 is connected to the drain of the NMOS tube N3 and outputs a signal P876_G, the gate of the NMOS tube N3 is connected to a blanking control signal X824_Y of a rectangular wave, and the source of the NMOS tube N3 is grounded.

[0018] Preferably, the overcurrent protection module comprises: a comparator CMP3 and NOT gates X8 and X9; the positive input terminal of the comparator CMP3 inputs a signal P876_G, the negative input terminal inputs an overcurrent threshold voltage R399_PLUS, and the output terminal outputs a signal X815_YN after being connected to the NOT gates X8 and X9 in sequence.

[0019] Preferably, it further comprises an overcurrent threshold voltage generation module, and the overcurrent threshold voltage generation module comprises: an operational amplifier OP3, an NMOS tube N2, a resistor R9 and a self-biased low-voltage cascode current mirror; the positive input terminal of the operational amplifier OP3 is connected to a reference voltage R736_MINUS, the negative input terminal is connected to the resistor R9 and the source of the NMOS tube N2 grounded, the output terminal is connected to the gate of the NMOS tube N2, and the drain of the NMOS tube N2 is connected to the input terminal of the self-biased low-voltage cascode current mirror.

[0020] Preferably, the self-biased low-voltage cascode current mirror comprises: PMOS tubes P1~P15 and resistors R10~R11; the sources of the PMOS tube P1, the PMOS tube P4, the PMOS tube P7, the PMOS tube P10 and the PMOS tube P13 are connected to a power supply VCC1, the gates of the PMOS tube P1 and the PMOS tube P13 are grounded, the drain of the PMOS tube P1 is connected to the source of the PMOS tube P2, the drain of the PMOS tube P2 is connected to the source of the PMOS tube P3, the drain of the PMOS tube P3 is connected to the gates of the PMOS tube P2, the PMOS tube P5, the PMOS tube P8, the PMOS tube P11 and the PMOS tube P14 and one end of the resistor R11, the other end of the resistor R11 is connected to the gates of the PMOS tube P3, the PMOS tube P6, the PMOS tube P9, the PMOS tube P12 and the PMOS tube P15 and serves as an input end, the gates of the PMOS tube P4, the PMOS tube P7 and the PMOS tube P10 are connected to control signals D1~D3 in sequence, the drain of the PMOS tube P4 is connected to the source of the PMOS tube P5, the drain of the PMOS tube P5 is connected to the source of the PMOS tube P6, the drain of the PMOS tube P7 is connected to the source of the PMOS tube P8, the drain of the PMOS tube P8 is connected to the source of the PMOS tube P9, the drain of the PMOS tube P10 is connected to the source of the PMOS tube P11, the drain of the PMOS tube P11 is connected to the source of the PMOS tube P12, the drain of the PMOS tube P13 is connected to the source of the PMOS tube P14, the drain of the PMOS tube P14 is connected to the source of the PMOS tube P15, the drain of the PMOS tube P7 is connected to the source of the PMOS tube P8, the drains of the PMOS tube P6, the PMOS tube P9, the PMOS tube P12 and the PMOS tube P15 are connected to the resistor R10 grounded and output an overcurrent threshold voltage R399_PLUS.

[0021] Preferably, the resistance ratio of the resistor R9 and the resistor R10 is 2:1; the current ratio of the left self-biased current mirror and the right four copied current mirrors in the self-biased low-voltage cascode current mirror is 4:4:2:1:1.

[0022] Compared with the prior art, the application has the following beneficial effects:

[0023] The application has dynamic response and stability characteristics; peak current detection and voltage / current double feedback can achieve fast load response. The current loop directly participates in PWM comparison, and the response speed is 5~10 times faster than that of pure voltage feedback, which is suitable for transient load scenarios (such as CPU dynamic frequency adjustment).

[0024] The application has low ripple and low noise characteristics; the front porch blanking current detection circuit is arranged to eliminate the current detection peak interference when the switch tube is turned on, improve the accuracy and stability of current detection, and ensure the normal operation of the power supply.

[0025] The application has high reliability and protection capability; through multiple periodic over-current protection (OCP), current is detected in each switching period to avoid inductor saturation explosion. Through overload protection (OLP), the voltage is forced to reduce or turn off when the feedback voltage exceeds the threshold, and the rear-end circuit is protected. Through adaptive current limiting, the external resistance sets the current limiting threshold, and flexibly adapts to different power levels. Through the built-in slope compensation function, the stability problem of current mode control when the duty cycle is greater than 50% is improved, and the stability and reliability of the power supply system are further improved. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 It is a principle block diagram of a current mode PWM controller provided by the application.

[0027] Figure 2 It is a circuit diagram of the FB detection module provided by the application.

[0028] Figure 3 It is a circuit diagram of the overload protection module provided by the application.

[0029] Figure 4 It is a circuit diagram of the peak current detection module provided by the application.

[0030] Figure 5 It is a circuit diagram of the hiccup control module provided by the application.

[0031] Figure 6 It is a circuit diagram of the CS detection module provided by the application.

[0032] Figure 7 It is a circuit diagram of the over-current protection module provided by the application.

[0033] Figure 8 It is a circuit diagram of the over-current threshold voltage generation module provided by the application.

[0034] Figure 9 It is a relationship diagram of the FB voltage corresponding to the chip working mode provided by the application. DETAILED DESCRIPTION

[0035] The application will be further described in detail below in combination with the drawings and specific embodiments. According to the following description, the advantages and characteristics of the application will be more apparent. It should be noted that the drawings are very simplified and all use non-precise proportions, only to facilitate, clearly assist in explaining the purpose of the embodiments of the application.

[0036] As Figures 1 to 9As shown, the embodiment of the present application specifically provides a current mode PWM controller, comprising:

[0037] The FB detection module inputs the feedback voltage signal FB through the FB port to control the conduction and cut-off of the triode Q1, and outputs three voltage signals to the overload protection module, the hiccup control module and the PWM comparator CMP1;

[0038] The CS detection module inputs the inductor current signal of the off-chip loop through the CS port, converts the inductor current signal into a voltage signal CS through the off-chip sampling resistor Rd, and sends the voltage signal into the chip after processing by the front porch blanking circuit and outputs the signal P876_G;

[0039] The peak current detection module inputs the voltage signal CS and the triangular wave signal N4_G output by the oscillator module after superposition and front porch blanking switching, and outputs the signal X835_YN after comparison with one voltage signal P879_G output by the FB detection module;

[0040] The hiccup control module outputs the signal X840_SNN after comparison and processing of one voltage signal P872_G output by the FB detection module and the comparison threshold, to control whether the oscillator module enters the hiccup mode;

[0041] The overload protection module outputs the signal X821_Y after comparison and processing of one voltage signal R932_PLUS output by the FB detection module and the overload threshold;

[0042] The overcurrent protection module outputs the signal X815_YN after comparison of the signal P876_G input into the overcurrent protection module and the overcurrent threshold;

[0043] The PWM logic control module processes the input signals X835_YN, X821_Y and X815_YN and outputs the signal X823_Y as the input control signal of the soft drive module to determine the duty cycle of the chip output drive signal.

[0044] The FB detection module includes: transistor Q1, resistors R0~R6, and current source I1; one end of current source I1 is connected to power supply X2_D, and the other end is connected to one end of resistor R6. The other end of resistor R6 is connected to one end of resistor R1, one end of resistor R2, and the base and collector of transistor Q1. The other end of resistor R1 is connected to the FB port. The FB port is connected to an external optocoupler U0 connected to the chip output voltage. The optocoupler U0 outputs a current signal to resistor R1 at the FB terminal to form a voltage signal FB. The other end of resistor R2 is connected to power supply X2_D. The emitter of transistor Q1 is connected to one end of resistors R3 and R4. The other end of resistor R4 outputs a voltage signal P872_G. The other end of resistor R3 is connected to one end of resistor R0 and outputs a voltage signal R932_PLUS. The other end of resistor R0 is connected to a grounded resistor R5 and outputs a voltage signal P879_G.

[0045] The voltage at the FB terminal reflects the external output load; a higher FB voltage indicates a heavier load. An external optocoupler converts the optical signal into a current signal, which is then converted into a voltage at the FB terminal by an internal resistor. The FB terminal is responsible for detecting the output voltage, which reflects the external load and affects the chip's operating state. Figure 9 As shown, when the FB terminal voltage is less than 1.5V (including FB ground short circuit), it is considered to be in a zero-load state, the oscillator frequency drops to its minimum, and the chip output OUT is low. As the FB terminal voltage gradually increases from 1.5V, it indicates that the load is gradually increasing, and the oscillator frequency gradually increases. When the FB terminal voltage reaches about 2.1V, the load is moderate, and the oscillator frequency is stable. However, as the load gradually increases, when the FB terminal voltage rises to 4.6V, the load is too heavy, triggering overload protection, and OUT outputs a low level. In particular, when the optocoupler is open-circuited, the open-circuit voltage at the FB terminal is 5.3V, OUT outputs a low level, and the optocoupler open-circuit protection is activated.

[0046] The peak current detection module includes: an operational amplifier OP1, resistors R7~R8, and an NMOS transistor N1; the positive input terminal of the operational amplifier OP1 is connected to a triangular wave signal N4_G, the negative input terminal is connected to the output terminal and connected to one end of resistor R7, the other end of resistor R7 is connected to one end of resistor R8 and the drain of NMOS transistor N1 and outputs a blanked superimposed signal, the other end of resistor R8 is connected to the voltage signal CS, the gate of NMOS transistor N1 is connected to a rectangular wave blanking control signal X824_Y, and the source of NMOS transistor N1 is grounded.

[0047] The chip adopts peak current detection mode, the FB detection module completes sampling of the voltage at the FB end, and sends the sampling into a PWM comparator to compare with a mixed signal of the inductance current signal and a triangular wave signal N4_G, so as to adjust the OUT output.

[0048] When the OUT end is still at a low level, a high level is generated at the blanking control signal X824_Y, the N1 transistor is turned on, and the output signal P876_G is pulled low to the ground. At this time, the external switch tube is cut off, the resistance on the sampling resistor Rd is 0, and the input from the CS end is also 0. When the OUT end changes from a low level 0 to a high level 1, the blanking control signal X824_Y becomes low, and the N1 transistor is cut off. At this time, the N1 transistor normally sends the voltage signal at the CS end into the slope compensation circuit (composed of the operational amplifier OP1 and the resistor R7) in the peak current detection module. That is, during the time when the external switch tube is turned on, the input signal at the CS end remains low, and this time is the front blanking time.

[0049] The overload protection module comprises a comparator CMP2, a NOT gate X1, a NOT gate X5, AND gates X2-X4, an AND gate X6, a T flip-flop TFF and a D flip-flop DFF. The positive input end of the comparator CMP2 is connected to a voltage signal R932_PLUS, the negative input end is connected to an overload threshold voltage P364_D output by a bandgap circuit BGR, and the output end is connected to input end one of the AND gate X2 through the NOT gate X1. Input end two of the AND gate X2 is connected to a logic signal "1", the output end of the AND gate X2 is connected to input end one of the AND gates X3-X4, input end two of the AND gate X3 is connected to the logic signal "1", input end two of the AND gate X4 is connected to a rectangular wave signal X1255_Q output by a frequency divider, the output end of the AND gate X3 is connected to the Reset end of the T flip-flop TFF and the D flip-flop DFF, the output end of the AND gate X4 is connected to the CLK end of the T flip-flop TFF, the Q end of the T flip-flop TFF is connected to the CLK end of the D flip-flop DFF, the D end of the D flip-flop DFF is connected to the logic signal "1", the Q end of the D flip-flop DFF is connected to input end one of the AND gate X6 through the NOT gate X5, input end two of the AND gate X6 is connected to the logic signal "1", and the output end of the AND gate X6 outputs a signal X821_Y.

[0050] The principle of the delay and protection is that when the voltage signal R932_PLUS exceeds the fixed threshold value P364_D of the comparator, the output signal P532_S of the comparator CMP2 is high, at this time the output of the AND gate X3 is 1, the reset ends of the T flip-flop TFF and the D flip-flop DFF are invalid, and the AND gate X4 will continue to output a rectangular wave with a period of 31.51 ms, which is used as the clock signal of the T flip-flop TFF. The characteristic of the T flip-flop TFF is that as long as the clock falling edge comes, the previous state is flipped, so according to the different trigger times of the overload, the time to wait for the falling edge will also be different, which leads to the fact that the total delay time is not accurate 30 ms, but the delay caused by the flip-flop structure is considered to be 30 ms, and the result is actually to re-divide the signal X1255_Q provided by the frequency divider. The output of the T flip-flop TFF is used as the clock signal of the D flip-flop DFF, when the clock falling edge comes, the D flip-flop DFF outputs a high level signal, and then through the NOT gate X5 and the AND gate X6, an overload protection signal with a low level is output into the PWM logic control module, so that the output OUT is pulled low to low, and the actual total delay time should be between 30 ms and 60 ms.

[0051] When the voltage at the FB end is higher, the system is closer to the overload condition. Overload is an abnormal operating state, and the overload protection module pulls down the OUT output when the voltage at the FB end exceeds 4.6V to prevent the occurrence of overload phenomenon.

[0052] The burp control module comprises an operational amplifier OP2, a NOT gate X7 and a selector MUX; the positive input end of the operational amplifier OP2 is connected to the comparison threshold voltage X840_Y and the signal X840_SNN, the negative input end is connected to the voltage signal P872_G, and the output end is connected to the S end of the selector MUX through the NOT gate X7; the A end of the selector MUX is connected to the voltage signal P191_G, the B end of the selector MUX is connected to the voltage signal R736_MINUS, the voltage of the voltage signal P191_G is slightly higher than that of the voltage signal R736_MINUS, and the Y end of the selector MUX outputs the signal X840_SNN.

[0053] The hiccup control module structure is mainly composed of an operational amplifier and a selector to form a hysteresis comparator, thereby corresponding to two FB voltages respectively. The signal P872_G is associated with the FB voltage, when the FB voltage increases from 0, the comparator output is high, the selector locks the high threshold, at this time S = 0, then SNN = 0, the oscillator is in the hiccup mode, at a fixed frequency of 21 kHz, OUT is pulled low, and the output is turned off. When the FB voltage rises to about 1.5V, the comparator can be flipped, at this time the low threshold is locked, and it is considered to be in a light load condition, and within a certain voltage range of about 1.5V~2.1V, the oscillator frequency increases with the increase of the load.

[0054] The hiccup control module determines whether the chip enters the green or hiccup mode according to the voltage signal provided by the FB detection module, and sends a signal to the oscillator module to determine the working mode of the chip. When entering the hiccup mode, the switching frequency of the power tube is greatly reduced, thereby reducing the system power consumption.

[0055] The CS detection module comprises a sampling resistor Rd, a resistor R12 and an NMOS tube N3; the inductor current signal of the input off-chip loop is converted into a voltage signal CS by the sampling resistor Rd connected to the ground, and the voltage signal CS is input to one end of the resistor R12; the other end of the resistor R12 is connected to the drain of the NMOS tube N3 and outputs a signal P876_G; the gate of the NMOS tube N3 is connected to the blanking control signal X824_Y of the rectangular wave; and the source of the NMOS tube N3 is grounded.

[0056] The overcurrent protection module comprises a comparator CMP3 and non-gates X8~X9; the positive input end of the comparator CMP3 inputs a signal P876_G, the negative input end inputs an overcurrent threshold voltage R399_PLUS, and the output end outputs a signal X815_YN after being connected to the non-gates X8~X9 in turn.

[0057] When the OUT end is still low, a high level is generated at the blanking control signal X824_Y, the N3 tube is turned on, and the output signal P876_G is pulled low to the ground. At this time, the off-chip switch tube is cut off, the resistance on the sampling resistor Rd is 0, and the input from the CS end is also 0. When the OUT end changes from low level 0 to high level 1, the blanking control signal X824_Y becomes low, and the N3 tube is cut off. At this time, the N3 tube normally sends the voltage signal of the CS end to the overcurrent protection module. That is, during the time when the off-chip switch tube is turned on, the input signal of the CS end remains low, and this period of time is the front porch blanking time.

[0058] When the input voltage of the CS end is processed by the front porch blanking circuit, the overcurrent protection module compares the signal P876_G outputted by the CS detection module with the overcurrent threshold voltage R399_PLUS. When the voltage of the signal P876_G is greater than the overcurrent threshold voltage R399_PLUS, it is considered that the current of the external switch tube is too large, and the overcurrent protection should be performed. The comparator CMP3 outputs a high level 1 through the signal X815_YN, and finally pulls down the OUT output after a period of time (Td_OCP) to play a protective role. When the voltage outputted by the CS detection module is lower than the overcurrent threshold voltage, the X815_YN output is low level 0, and it is considered that the current flowing through the external switch tube is appropriate, and the chip keeps normal working.

[0059] The overcurrent threshold voltage generating module comprises an operational amplifier OP3, an NMOS tube N2, a resistor R9 and a self-biased low-voltage cascode current mirror. The positive input end of the operational amplifier OP3 is connected to a reference voltage R736_MINUS, the negative input end is connected to the resistor R9 and the source of the NMOS tube N2, the output end is connected to the gate of the NMOS tube N2, and the drain of the NMOS tube N2 is connected to the input end of the self-biased low-voltage cascode current mirror.

[0060] The self-bias low-voltage cascode current mirror comprises PMOS tubes P1-P15 and resistors R10-R11; the sources of the PMOS tubes P1, P4, P7, P10 and P13 are connected to a power supply VCC1, the gates of the PMOS tubes P1 and P13 are grounded, the drain of the PMOS tube P1 is connected to the source of the PMOS tube P2, the drain of the PMOS tube P2 is connected to the source of the PMOS tube P3, the drain of the PMOS tube P3 is connected to the gates of the PMOS tubes P2, P5, P8, P11 and P14 and one end of the resistor R11, the other end of the resistor R11 is connected to the gates of the PMOS tubes P3, P6, P9, P12 and P15 and serves as an input terminal, the gates of the PMOS tubes P4, P7 and P10 are connected to control signals D1-D3 provided by a frequency divider in sequence, the drain of the PMOS tube P4 is connected to the source of the PMOS tube P5, the drain of the PMOS tube P5 is connected to the source of the PMOS tube P6, the drain of the PMOS tube P7 is connected to the source of the PMOS tube P8, the drain of the PMOS tube P8 is connected to the source of the PMOS tube P9, the drain of the PMOS tube P10 is connected to the source of the PMOS tube P11, the drain of the PMOS tube P11 is connected to the source of the PMOS tube P12, the drain of the PMOS tube P13 is connected to the source of the PMOS tube P14, the drain of the PMOS tube P14 is connected to the source of the PMOS tube P15, the drain of the PMOS tube P7 is connected to the source of the PMOS tube P8, the drains of the PMOS tubes P6, P9, P12 and P15 are connected to the resistor R10 grounded and output an overcurrent threshold voltage R399_PLUS.

[0061] The overcurrent threshold voltage generation module, the operational amplifier OP3 completes virtual short of the input signal through a negative feedback structure, so that the voltage at the inverting input terminal of the operational amplifier OP3 is equal to the voltage of R736_MINUS, which is a voltage generated by a linear power supply circuit. After the virtual short is completed, the potential of the signal R403_PLUS (i.e. the voltage on the resistor R9 in the equivalent circuit) is fixed, so that the current flowing through the resistor R9 also remains constant, and the generated current serves as a current source for the right half of the current mirror structure to copy, and finally the current generates the overcurrent threshold voltage R399_PLUS through the resistor R10.

[0062] The current ratio of the self-bias current mirror to the four right-side copied current mirror circuits is 4:4:2:1:1, and R9:R10=2:1.

[0063] In summary, the application fuses voltage / current double feedback, through real-time comparison logic of the voltage signal output by the FB detection module and the current sampling signal output by the peak current detection module in the PWM comparator CMP1, further adopts an adaptive slope compensation circuit, a compensation amount dynamic adjustment method (such as compensation slope changes with duty cycle) to prevent sub-harmonic oscillation; through a current detection circuit with leading edge blanking (LEB): LEB time setting technology (such as a 200ns blanking window) and anti-interference filter design (such as RC low-pass filter parameters); through the implementation of cycle-by-cycle current limiting: real-time comparison circuit of the current sampling signal and the dynamic threshold, namely the overcurrent threshold voltage R399_PLUS (set by an external resistor), flexible adaptation to different power levels; through the feedback mechanism of overload protection: overload threshold detection and execution logic of forced frequency reduction / shut down (such as by pulling down the PWM drive signal), protection of the back-end circuit; through the optimization of the peak current module: while reducing the switching frequency, the current loop quickly responds to load transients (such as dynamic adjustment of current sampling gain).

[0064] The above description is only a description of the preferred embodiments of the application, and does not limit the scope of the application in any way, and any changes and modifications made by those skilled in the art according to the above disclosure are within the protection scope of the claims.

Claims

1. A current mode PWM controller characterized by, The application relates to a chip output drive control circuit, which comprises the following modules: An FB detection module, which inputs a feedback voltage signal FB through an FB port to control the conduction and cutoff of a triode Q1 and outputs three voltage signals to an overload protection module, a hiccup control module and a PWM comparator CMP1; A CS detection module, which inputs an inductance current signal of an off-chip loop through a CS port, converts the inductance current signal into a voltage signal CS through an off-chip sampling resistor Rd, and outputs a signal P876_G after the voltage signal CS is processed by a front porch blanking circuit; A peak current detection module, which inputs a signal obtained by superimposing the voltage signal CS and a triangular wave signal N4_G output by an oscillator module after front porch blanking switching to the PWM comparator CMP1, compares the signal with a voltage signal P879_G output by the FB detection module, and outputs a signal X835_YN; The hiccup control module, which compares a voltage signal P872_G output by the FB detection module with a comparison threshold value, processes the voltage signal P872_G, and outputs a signal X840_SNN to control whether the oscillator module enters a hiccup mode; The overload protection module, which compares a voltage signal R932_PLUS output by the FB detection module with an overload threshold value, processes the voltage signal R932_PLUS, and outputs a signal X821_Y; An overcurrent protection module, which compares the signal P876_G input to the overcurrent protection module with an overcurrent threshold value, and outputs a signal X815_YN; A PWM logic control module, which processes the signals X835_YN, X821_Y and X815_YN, and outputs a signal X823_Y as an input control signal of a soft drive module to determine the duty cycle of a chip output drive signal.

2. A current mode PWM controller as claimed in claim 1, characterized in that The FB detection module comprises the triode Q1, resistors R0-R6 and a current source I1; one end of the current source I1 is connected to a power supply X2_D, the other end is connected to one end of a resistor R6, the other end of the resistor R6 is connected to one end of a resistor R1, one end of a resistor R2 and the base and collector of the triode Q1, the other end of the resistor R1 is connected to an FB port, the FB port is connected to an off-chip optocoupler U0 connected to a chip output voltage, a current signal is output to the resistor R1 of the FB port through the optocoupler U0 to form a voltage signal FB, the other end of the resistor R2 is connected to the power supply X2_D, the emitter of the triode Q1 is connected to one end of a resistor R3 and a resistor R4, the other end of the resistor R4 outputs a voltage signal P872_G, the other end of the resistor R3 is connected to one end of a resistor R0 and outputs a voltage signal R932_PLUS, the other end of the resistor R0 is connected to a resistor R5 grounded and outputs a voltage signal P879_G.

3. A current mode PWM controller as claimed in claim 1, wherein, The peak current detection module comprises an operational amplifier OP1, resistors R7-R8 and an NMOS tube N1; the positive input end of the operational amplifier OP1 is connected to a triangular wave signal N4_G, the negative input end and the output end are connected and one end of the resistor R7 is connected, the other end of the resistor R7 is connected to one end of the resistor R8 and the drain of the NMOS tube N1 and outputs a blanked superimposed signal, the other end of the resistor R8 is connected to the voltage signal CS, the gate of the NMOS tube N1 is connected to a blanking control signal X824_Y of a rectangular wave, and the source of the NMOS tube N1 is grounded.

4. A current mode PWM controller as claimed in claim 1, wherein, The overload protection module comprises a comparator CMP2, a NOT gate X1, a NOT gate X5, AND gates X2-X4, an AND gate X6, a T flip-flop TFF and a D flip-flop DFF; the positive input end of the comparator CMP2 is connected to a voltage signal R932_PLUS, the negative input end is connected to an overload threshold voltage P364_D, the output end is connected to input end one of the AND gate X2 through the NOT gate X1, input end two of the AND gate X2 is connected to a logic signal "1", the output end of the AND gate X2 is connected to input end one of the AND gates X3-X4, input end two of the AND gate X3 is connected to a logic signal "1", input end two of the AND gate X4 is connected to a signal X1255_Q of a rectangular wave, the output end of the AND gate X3 is connected to the Reset end of the T flip-flop TFF and the D flip-flop DFF, the output end of the AND gate X4 is connected to the CLK end of the T flip-flop TFF, the Q end of the T flip-flop TFF is connected to the CLK end of the D flip-flop DFF, the D end of the D flip-flop DFF is connected to a logic signal "1", the Q end of the D flip-flop DFF is connected to input end one of the AND gate X6 through the NOT gate X5, input end two of the AND gate X6 is connected to a logic signal "1", and the output end of the AND gate X6 outputs a signal X821_Y.

5. A current mode PWM controller as claimed in claim 1, wherein, The hiccup control module comprises an operational amplifier OP2, a NOT gate X7 and a selector MUX; the positive input end of the operational amplifier OP2 is connected to a comparison threshold voltage X840_Y and a signal X840_SNN, the negative input end is connected to a voltage signal P872_G, the output end is connected to the S end of the selector MUX through the NOT gate X7, the A end of the selector MUX is connected to a voltage signal P191_G, the B end of the selector MUX is connected to a voltage signal R736_MINUS, and the Y end of the selector MUX outputs a signal X840_SNN.

6. A current mode PWM controller as claimed in claim 1, wherein, The CS detection module comprises a sampling resistor Rd, a resistor R12 and an NMOS tube N3; an inductive current signal of an input off-chip loop is converted into a voltage signal CS by the sampling resistor Rd grounded and input to one end of the resistor R12, the other end of the resistor R12 is connected to the drain of the NMOS tube N3 and outputs a signal P876_G, the gate of the NMOS tube N3 is connected to a blanking control signal X824_Y of a rectangular wave, and the source of the NMOS tube N3 is grounded.

7. A current mode PWM controller as claimed in claim 6, wherein, The overcurrent protection module comprises a comparator CMP3 and a NOT gate X8~X9; the positive input end of the comparator CMP3 inputs a signal P876_G, the negative input end inputs an overcurrent threshold voltage R399_PLUS, and the output end outputs a signal X815_YN after being connected to the NOT gate X8~X9 in turn.

8. A current mode PWM controller as claimed in claim 7, wherein, The overcurrent threshold voltage generation module comprises an operational amplifier OP3, an NMOS tube N2, a resistor R9 and a self-biased low-voltage cascode current mirror; the positive input end of the operational amplifier OP3 is connected to a reference voltage R736_MINUS, the negative input end is connected to the source of the NMOS tube N2 and the resistor R9 grounded, the output end is connected to the gate of the NMOS tube N2, and the drain of the NMOS tube N2 is connected to the input end of the self-biased low-voltage cascode current mirror.

9. A current mode PWM controller as claimed in claim 8, wherein, The self-biased low-voltage cascode current mirror comprises PMOS tubes P1~P15 and resistors R10~R11; the sources of the PMOS tube P1, the PMOS tube P4, the PMOS tube P7, the PMOS tube P10 and the PMOS tube P13 are connected to a power supply VCC1, the gates of the PMOS tube P1 and the PMOS tube P13 are grounded, the drain of the PMOS tube P1 is connected to the source of the PMOS tube P2, the drain of the PMOS tube P2 is connected to the source of the PMOS tube P3, the drain of the PMOS tube P3 is connected to the gates of the PMOS tube P2, the PMOS tube P5, the PMOS tube P8, the PMOS tube P11 and the PMOS tube P14 and one end of the resistor R11, the other end of the resistor R11 is connected to the gates of the PMOS tube P3, the PMOS tube P6, the PMOS tube P9, the PMOS tube P12 and the PMOS tube P15 and serves as an input end, the gates of the PMOS tube P4, the PMOS tube P7 and the PMOS tube P10 are connected to control signals D1~D3 in turn, the drain of the PMOS tube P4 is connected to the source of the PMOS tube P5, the drain of the PMOS tube P5 is connected to the source of the PMOS tube P6, the drain of the PMOS tube P7 is connected to the source of the PMOS tube P8, the drain of the PMOS tube P8 is connected to the source of the PMOS tube P9, the drain of the PMOS tube P10 is connected to the source of the PMOS tube P11, the drain of the PMOS tube P11 is connected to the source of the PMOS tube P12, the drain of the PMOS tube P13 is connected to the source of the PMOS tube P14, the drain of the PMOS tube P14 is connected to the source of the PMOS tube P15, the drain of the PMOS tube P7 is connected to the source of the PMOS tube P8, and the drains of the PMOS tube P6, the PMOS tube P9, the PMOS tube P12 and the PMOS tube P15 are connected to the resistor R10 grounded and output an overcurrent threshold voltage R399_PLUS.

10. A current mode PWM controller as claimed in claim 9, wherein, The resistance value ratio of the resistance R9 and the resistance R10 is 2:1; the current ratio of the left self-bias current mirror and the right four copy current mirrors in the self-bias low-voltage common-source common-gate current mirror is 4:4:2:1:1.

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