Semiconductor device

Abstract

A semiconductor device according to an embodiment of the present invention is a semiconductor device in which a normally-on-driven first transistor is normally-off-driven. The semiconductor device includes a first circuit, a second circuit, and a first diode. The first circuit is connected to a power supply voltage and a ground voltage, detects the power supply voltage, and outputs a transition state of the power supply voltage. The second circuit is connected to the power supply voltage, the ground voltage, the first circuit, and the second transistor, and outputs a drive voltage of a second transistor connected in series to the first transistor on the basis of an output of the first circuit. The anode of the first diode is connected to the drive terminal of the first transistor, and the cathode is connected to the output terminal of the second transistor.

Description

[0001] This application is a divisional application with the application date of August 30, 2021, application number 202111001568.1, and invention name “Semiconductor Device”. Technical Field

[0002] Embodiments relate to a semiconductor device. Background Art

[0003] Power devices using GaN (gallium nitride) offer advantages over MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) using Si (silicon), such as faster switching speeds, lower recovery losses, and faster charging and discharging of output capacitance. While transistors using GaN are typically normally on, development of normally off transistors is underway to capitalize on these advantages.

[0004] However, when converting to such a normally-off circuit, the following problems arise depending on the conversion circuit: the gate drive capability cannot be adjusted, a dedicated negative power supply circuit and a dedicated gate driver are required, the gate current loop becomes longer due to the n-type MOSFET, or there is a large trade-off between preventing false start-up and standby power when the gate driver power supply is cut off. Summary of the Invention

[0005] Embodiments provide a semiconductor device capable of a normally-on operation.

[0006] According to one embodiment, a semiconductor device is a semiconductor device that causes a normally-on first transistor to be normally-off, and includes a first circuit, a second circuit, and a first diode. The first circuit is connected to a power supply voltage and a ground voltage, detects the power supply voltage, and outputs a transition state of the power supply voltage. The second circuit is connected to the power supply voltage, the ground voltage, the first circuit, and the second transistor, and outputs a drive voltage for the second transistor connected in series with the first transistor based on the output of the first circuit. The first diode has an anode connected to a drive terminal of the first transistor, and a cathode connected to an output terminal of the second transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 This is a circuit diagram showing an example of a semiconductor device according to one embodiment.

[0008] Figure 2 This is a circuit diagram showing an implementation example of a semiconductor device according to an embodiment.

[0009] Figure 3 It is a diagram showing the on / off state of a transistor according to one embodiment.

[0010] Figure 4 This is a circuit diagram showing an implementation example of a semiconductor device according to an embodiment.

[0011] Figure 5 It is a diagram showing the on / off state of a transistor according to one embodiment.

[0012] Figure 6 This is a circuit diagram showing an implementation example of a semiconductor device according to an embodiment.

[0013] Figure 7 This is a circuit diagram showing an implementation example of a semiconductor device according to an embodiment.

[0014] Figure 8 This is a circuit diagram showing an implementation example of a semiconductor device according to an embodiment.

[0015] Figure 9 This is a circuit diagram showing an implementation example of a semiconductor device according to an embodiment.

[0016] Figure 10 This is a circuit diagram showing an example of a semiconductor device according to one embodiment.

[0017] Figure 11 This is a circuit diagram showing an implementation example of a semiconductor device according to an embodiment.

[0018] Figure 12 This is a circuit diagram showing an implementation example of a semiconductor device according to an embodiment.

[0019] Figure 13 This is a circuit diagram showing an implementation example of a semiconductor device according to an embodiment. DETAILED DESCRIPTION

[0020] Hereinafter, the embodiment will be described with reference to the accompanying drawings. In the drawings, D represents the position of a drain unless otherwise indicated.

[0021] (First embodiment)

[0022] Figure 1 1 is a circuit diagram showing an example of the position of a semiconductor device according to one embodiment. The semiconductor device 1 is a circuit for driving a normally-on first transistor Q1 to normally be off.

[0023] The first transistor Q1 is a power device using, for example, GaN, and is a FET that performs a normally-on operation.

[0024] The second transistor Q2 is a p-type MOSFET connected in series with the first transistor Q1 and shares a source therewith. Due to the characteristics of the second transistor Q2, the first transistor Q1 performs a normally-off operation.

[0025] Hereinafter, the drains of the first transistor Q1 and the second transistor Q2 are defined as the drain and source of each transistor performing a normally-off operation. The semiconductor device 1 solves various problems associated with the normally-off operation of the first transistor Q1 by controlling the voltage applied to the source and the gate of each transistor.

[0026] When the first transistor Q1 performs normally-off operation via the semiconductor device 1, it is driven by the voltage applied to its gate and outputs a drain current from its source terminal SOURCE based on the potential difference between its drain terminal DRAIN and its source terminal SOURCE. For example, if an external load is connected to the drain terminal DRAIN, i.e., the drain side of the first transistor Q1, the first transistor Q1 operates as a circuit that switches the load based on the voltage applied to its gate.

[0027] Semiconductor device 1 is a circuit that controls the voltages of the gate of a first transistor Q1, the gate of a second transistor Q2, and the drain of the second transistor Q2. It is connected to a power supply voltage terminal VDD, a gate voltage application terminal GATE, and a ground terminal GND. This semiconductor device 1 includes a first diode 10, a first circuit 20, and a second circuit 30. Furthermore, the gate voltage application terminal GATE is connected to the gate of the first transistor Q1.

[0028] The power supply voltage terminal VDD is connected to a node shared by the source of the first transistor Q1 and the source of the second transistor Q2 via the semiconductor device 1, thereby applying the power supply voltage to the semiconductor device 1. The ground terminal GND sets the ground potential of the semiconductor device 1. In the drawings, the ground terminal GND is connected to a ground point within the semiconductor device 1, but this is not limiting; it may also be connected to a ground point external to the semiconductor device 1. This ground terminal GND is not limited to being connected to an actual ground; it may be connected to a potential of 0V or to a predetermined ground potential within the device. The ground terminal GND used in the following description should be interpreted similarly.

[0029] The first diode 10 is a protection circuit for the first transistor Q1 and the second transistor Q2. The anode of the first diode 10 is connected to the gate of the first transistor Q1, and the cathode is connected to the drain of the second transistor Q2.

[0030] The first circuit 20 is a circuit for detecting the voltage of the power supply voltage. The first circuit 20 is connected between the power supply voltage terminal VDD and the ground terminal GND. The first circuit 20 compares the state of the power supply voltage, more specifically, the power supply voltage with the threshold voltage of the first transistor Q1, detects the voltage difference, and outputs it to the second circuit 30.

[0031] The second circuit 30 is a circuit for low standby power and outputs a voltage that drives the second transistor Q2 to operate properly. The second circuit 30 is connected to the power supply voltage terminal VDD, the ground voltage GND, the first circuit 20, and the gate of the second transistor Q2. This second circuit 30 properly drives the second transistor Q2 upon receiving a signal from the first circuit 20 indicating the voltage status. Alternatively, a circuit 35 combining the first circuit 20 and the second circuit 30 may be provided. Circuit 35 does not require external signal input.

[0032] When the power supply voltage rises, the first circuit 20 detects that the voltage exceeds the absolute value of the threshold voltage of the first transistor Q1, that is, that the first transistor Q1 has turned off. The first circuit 20 outputs this voltage change to the second circuit 30. Upon receiving this signal, the second circuit 30 applies a drive voltage to the gate of the second transistor Q2 to turn on the second transistor Q2 after the first transistor Q1 has turned off.

[0033] Conversely, when the power supply voltage drops, the first circuit 20 outputs a signal indicating that the voltage is dropping to the second circuit 30 while the power supply voltage is higher than the absolute value of the threshold voltage of the first transistor Q1, that is, while the first transistor Q1 is turned off. Upon receiving this signal, the second circuit 30 applies a drive voltage to the gate of the second transistor Q2 to turn off the second transistor Q2 before the first transistor Q1 turns on.

[0034] By using such first circuit 20 and second circuit 30, even when the voltage applied to the power supply voltage terminal rises or falls at a high slew rate, it is possible to prevent the second transistor Q2 from being turned on while the first transistor Q1 is on. Furthermore, even when the power supply voltage fluctuates, such as when it oscillates around the threshold voltage of the first transistor Q1, it is possible to prevent both the first transistor Q1 and the second transistor Q2 from being turned on. Furthermore, by including a passive circuit connected to a power supply, circuit 35 can cause the first transistor Q1 to operate normally off without requiring an external signal input. In this embodiment, circuit 35 corresponds to first circuit 20 and second circuit 30.

[0035] Next, a specific mounting example of the semiconductor device 1 will be described.

[0036] (Installation Example 1)

[0037] Figure 2This is a circuit diagram of a semiconductor device 1 showing an exemplary embodiment. The semiconductor device 1 includes a first resistor 200, a second diode 201, a third transistor 202, a second resistor 203, a fourth transistor 300, and a third resistor 301. As shown in the figure, as an example, the first resistor 200, the second diode 201, the third transistor 202, and the second resistor 203 are configured as part of the first circuit 20, while the fourth transistor 300 and the third resistor 301 are configured as part of the second circuit 30.

[0038] The first resistor 200 is connected between the power supply voltage terminal VDD and the second diode 201 .

[0039] The anode of the second diode 201 is connected to the ground terminal GND, and the cathode is connected to the power supply voltage terminal VDD via the first resistor 200. The second diode 201 is a Zener diode having a Zener voltage that is equal to or greater than the absolute value of the threshold voltage of the first transistor Q1 and lower than a constant value Vdd of the power supply voltage (for example, the maximum value of the voltage applied to the power supply, approximately 15V).

[0040] When a voltage greater than the Zener voltage of the second diode 201 is applied to the power supply terminal VDD, the first resistor 200 and the second diode 201 operate as a circuit that outputs a constant voltage (Zener voltage) from the connection node. Otherwise, they operate as a circuit that outputs a voltage based on the voltage applied to the power supply voltage terminal VDD.

[0041] The third transistor 202 is, for example, a p-type MOSFET, with its source connected to the power supply voltage terminal VDD, its drain connected to the ground terminal GND via the second resistor 203, and its gate connected to the cathode of the second diode 201. The third transistor 202 has a negative threshold voltage whose absolute value is lower than (constant power supply voltage Vdd) - (Zener voltage of the second diode 201).

[0042] The second resistor 203 is connected between the drain of the third transistor 202 and the ground terminal GND. The potential of the drain of the third transistor 202 is defined by the resistance value of the second resistor 203 according to the current flowing through the third transistor 202. For example, the first circuit 20 outputs the voltage of the drain of the third transistor 202.

[0043] The fourth transistor 300 is, for example, a p-type MOSFET, with its source connected to the power supply voltage terminal VDD, its drain connected to the ground terminal GND via the third resistor 301, and its gate connected to the drain of the third transistor 202. The fourth transistor 300 has a negative threshold voltage whose absolute value is lower than the constant power supply voltage Vdd.

[0044] The third resistor 301 is provided between the drain of the fourth transistor 300 and the ground terminal GND.

[0045] According to this configuration, the first circuit 20 outputs a voltage based on the voltage applied to the power supply voltage terminal VDD, and the second circuit 30 outputs a voltage based on the voltage output from the first circuit 20 to the gate of the second transistor Q2.

[0046] Here, the operations of the first transistor Q1 and the second transistor Q2 when the voltage applied to the power supply voltage terminal VDD varies will be described.

[0047] First, let's describe the situation where the voltage applied to power supply voltage terminal VDD rises from 0 to voltage Vdd. When the voltage applied to power supply voltage terminal VDD exceeds the threshold voltage of first transistor Q1, first transistor Q1 turns off. At this point, since it does not exceed the Zener voltage of second diode 201, current does not flow through first resistor 200. The gate-source voltage of third transistor 202 reaches 0, and third transistor 202 remains in the off state. Furthermore, since current does not flow through second resistor 203, fourth transistor 300 turns on. The voltage generated by its drain current and third resistor 301 is applied to the gate of second transistor Q2, and second transistor Q2 remains in the off state.

[0048] Furthermore, when the voltage applied to the power supply voltage terminal VDD increases and becomes higher than the Zener voltage of the second diode 201, the gate-source voltage of the third transistor 202 becomes equal to the voltage across the terminals of the first resistor 200. In this state, when the voltage applied to the power supply voltage terminal VDD is lower than the sum of the Zener voltage and the absolute value of the threshold voltage of the third transistor 202, the states of the third transistor 202 and the fourth transistor 300 remain unchanged. Specifically, the third transistor 202 is turned off, the fourth transistor 300 is turned on, and the second transistor Q2 is turned off.

[0049] Furthermore, when the voltage applied to the power supply voltage terminal VDD increases and exceeds the sum of the Zener voltage and the absolute value of the threshold voltage of the third transistor 202, the gate-source voltage of the third transistor 202 falls below the threshold voltage of the third transistor 202, and the third transistor 202 turns on. When the third transistor 202 turns on, the voltage generated by the drain current of the third transistor 202 and the second resistor 203 is applied to the gate of the fourth transistor 300.

[0050] In this state, the voltage applied to the gate of the fourth transistor 300 increases as the voltage applied to the power supply voltage terminal VDD increases, gradually turning off the fourth transistor 300. When the voltage applied to the power supply voltage terminal VDD exceeds the absolute value of the threshold voltage of the fourth transistor 300, the fourth transistor 300 is turned off. In other words, the voltage applied to the gate of the second transistor Q2 decreases as the voltage applied to the power supply voltage terminal VDD increases, and when the voltage falls below the threshold voltage of the second transistor Q2, the second transistor Q2 is turned on.

[0051] To summarize the above, for example, when the voltage applied to the power supply voltage terminal VDD rises from 0 to the voltage Vdd, the first transistor Q1 first transitions from on to off, and then the second transistor Q2 transitions from off to on after the states of the third transistor 202 and the fourth transistor 300 transition. In this way, a time margin is provided between the turning off of the first transistor Q1 and the turning on of the second transistor Q2, so that these two transistors do not turn on at the same time.

[0052] Next, a case where the voltage applied to the power supply voltage terminal VDD drops from the voltage Vdd to 0 will be described.

[0053] When the voltage applied to the power supply voltage terminal VDD drops to Vdd-(Zener voltage of the second diode 201), that is, the voltage between the terminals of the first resistor 200 becomes lower than the threshold voltage of the third transistor 202, the third transistor 202 switches from the on state to the off state.

[0054] As a result, the fourth transistor 300 turns on, and when the voltage formed by the drain current of the fourth transistor 300 and the third resistor 301 exceeds the threshold voltage of the second transistor Q2, the second transistor Q2 turns off.

[0055] Thereafter, the voltage applied to the power supply voltage terminal VDD further decreases, and when it falls below the threshold voltage of the first transistor Q1 , the first transistor Q1 turns on.

[0056] To summarize the above, for example, when the voltage applied to the power supply voltage terminal VDD drops from voltage Vdd to 0, first, the second transistor Q2 transitions from on to off through the transitions in the states of the third transistor 202 and the fourth transistor 300, and then the first transistor Q1 transitions to on. In this way, a time margin is created between the off-state of the second transistor Q2 and the on-state of the first transistor Q1, so that these two transistors do not turn on at the same time.

[0057] The driving force for turning the second transistor Q2 on and off during the rising and falling periods of the voltage applied to the power supply voltage terminal VDD is determined by the value of the third resistor 301 and the on-resistance of the fourth transistor 300, respectively. By setting the resistance of the third resistor 301 to be greater than the on-resistance of the fourth transistor 300, the second transistor Q2 can be turned off faster than it is turned on.

[0058] Figure 3 It shows Figure 2 The solid line represents the voltage applied to the power supply voltage terminal VDD, the dotted line represents the gate-source voltage Vgs1 of the first transistor Q1, and the dashed line represents the gate-source voltage Vgs2 of the second transistor Q2.

[0059] Vth1 is the threshold voltage of the first transistor Q1, Vth2 is the threshold voltage of the second transistor Q2, and Vref is the voltage to be detected in the first circuit 20, that is, the Zener voltage of the second diode 201.

[0060] Regarding the on / off states in the lower portion, the upper portion shows the on / off state of the first transistor Q1 , and the lower portion shows the on / off state of the second transistor Q2 .

[0061] If the Figure 3 As shown, regardless of whether the voltage applied to the power supply voltage terminal VDD is rising or falling, the timing of turning on or off the first transistor Q1 and the second transistor Q2 is transitioned through a state where both transistors are off. Therefore, the two transistors are not turned on at the same timing.

[0062] exist Figure 2 In the circuit configuration, in a constant state where the first transistor Q1 is in an off state, the voltage Vdd is applied to the gate of the second transistor Q2, so that the second transistor Q2 can be driven with a low on-resistance.

[0063] As described above, even when the slew rate of the voltage applied to the power supply voltage terminal VDD is high or the voltage applied to the power supply voltage terminal VDD oscillates, the first transistor Q1 and the second transistor Q2 can be prevented from being turned on simultaneously.

[0064] Furthermore, in a constant state after the power supply voltage rises, since the fourth transistor 300 is in the off state, no standby current flows, and it is possible to achieve both a driving force difference for preventing the first transistor Q1 and the second transistor Q2 from being turned on at the same time and low power consumption. As a result, the standby power of the entire circuit is defined by the first resistor 200 and the current flowing through the second resistor 203. By setting these two resistance values ​​to larger values, the overall power consumption can also be reduced. Setting the resistance value to a larger value, for example, can be a resistance value of several tens of kΩ. In this case, when the power supply voltage is around 15V, it becomes ～ With a power consumption of approximately 1mA, it can be used as a transistor driver circuit with low current consumption.

[0065] (Installation Example 2)

[0066] Figure 4 1 is a circuit diagram showing the configuration of a semiconductor device 1 according to a second mounting example different from the first mounting example. The semiconductor device 1 includes a fifth transistor 210 and a third diode 211. The fifth transistor 210 and the third diode 211 form a Figure 1 The first circuit 20 and the second circuit 30 in.

[0067] The fifth transistor 210 is, for example, a normally-on transistor, with its drain connected to the power supply voltage terminal VDD, its source connected to the ground terminal GND via the third diode 211, and its gate connected to the ground terminal GND. This fifth transistor has a characteristic in that, for example, its threshold voltage is negative, with an absolute value greater than or equal to the absolute value of the threshold voltage of the first transistor Q1 and lower than the voltage Vdd.

[0068] The third diode 211 is, for example, a Zener diode, having an anode connected to the ground terminal GND and a cathode connected to the source of the fifth transistor 210. The Zener voltage of the third diode 211 is greater than or equal to the absolute value of the threshold voltage of the first transistor Q1 and less than the voltage Vdd- (the absolute value of the threshold voltage of the second transistor Q2).

[0069] A connection node between the source of the fifth transistor 210 and the cathode of the third diode 211 is connected to the gate of the second transistor Q2 , and a voltage at this node serves as a driving voltage for the second transistor Q2 .

[0070] Here, the operations of the first transistor Q1 and the second transistor Q2 when the voltage applied to the power supply voltage terminal VDD varies will be described.

[0071] First, the case where the voltage applied to the power supply voltage terminal VDD rises from 0 to voltage Vdd will be described. When the voltage applied to the power supply voltage terminal VDD exceeds the threshold voltage of the first transistor Q1, the first transistor Q1 turns off. At this timing, the fifth transistor 210 turns on, so the second transistor Q2 remains off.

[0072] When the voltage applied to the power supply voltage terminal VDD further increases and exceeds the absolute value of the threshold voltage of the fifth transistor 210 and the Zener voltage of the third diode 211, the fifth transistor 210 is turned off and the gate voltage of the second transistor Q2 is increased to the Zener voltage (or a voltage below the Zener voltage).

[0073] When the voltage applied to the power supply voltage terminal VDD further increases and the voltage between the gate and the source of the second transistor Q2 falls below the threshold voltage, the second transistor Q2 turns on.

[0074] To summarize the above, for example, when the voltage applied to the power supply voltage terminal VDD rises from 0 to voltage Vdd, the first transistor Q1 first switches from on to off. Through the fifth transistor 210 and the third diode 211, the gate of the second transistor Q2 reaches the Zener voltage of the third diode 211 (or a voltage lower than the Zener voltage). Then, the second transistor Q2 switches from off to on. This allows for a time margin between the first transistor Q1 turning off and the second transistor Q2 turning on, preventing both transistors from turning on simultaneously.

[0075] Next, a case where the voltage applied to the power supply voltage terminal VDD drops from the voltage Vdd to 0 will be described.

[0076] First, when the voltage applied to the power supply voltage terminal VDD is lower than the threshold voltage of the fifth transistor 210, the fifth transistor 210 is turned on. Since the fifth transistor 210 is turned on, the drain current causes the gate potential of the second transistor Q2 to exceed the threshold voltage, and the second transistor Q2 is turned off.

[0077] Thereafter, the voltage applied to the power supply voltage terminal VDD exceeds the threshold value of the first transistor Q1 , and the first transistor Q1 turns on.

[0078] To summarize the above, for example, when the voltage applied to the power supply voltage terminal VDD drops from voltage Vdd to 0, the fifth transistor 210 first turns on, and then the second transistor Q2 transitions from on to off. Thereafter, the first transistor Q1 transitions from off to on. This allows for a time margin between the first transistor Q1 turning off and the second transistor Q2 turning on, preventing both transistors from turning on simultaneously.

[0079] The driving force for turning the second transistor Q2 on and off during the rising and falling periods of the voltage applied to the power supply voltage terminal VDD is determined by the on-resistance value of the fifth transistor 210 and the operating resistance of the third diode 211, respectively. By configuring the operating resistance of the third diode 211 to have a value greater than the on-resistance of the fifth transistor 210, the second transistor Q2 can be turned off faster than it is turned on.

[0080] Figure 5 It shows Figure 4 The solid line represents the voltage applied to the power supply voltage terminal VDD, the dotted line represents the gate-source voltage Vgs1 of the first transistor Q1, and the dashed line represents the gate-source voltage Vgs2 of the second transistor Q2.

[0081] Vth1 is the threshold voltage of the first transistor Q1 , Vth2 is the threshold voltage of the second transistor Q2 , and Vref is the Zener voltage of the third diode 211 .

[0082] Regarding the ON and OFF states below, the upper section shows the ON / OFF state of the first transistor Q1 , and the lower section shows the ON / OFF state of the second transistor Q2 .

[0083] If the Figure 5 As shown, regardless of whether the voltage applied to the power supply voltage terminal VDD rises or falls, the timing of turning on or off the first transistor Q1 and the second transistor Q2 changes after both transistors are in the off state. Therefore, the two transistors will not turn on at the same timing.

[0084] In a constant state where the first transistor Q1 is turned off, a voltage equal to the difference between the voltage of the power supply voltage terminal VDD and the Zener voltage of the third diode 211 is applied to the gate of the second transistor Q2. Figure 2 Compared with the circuit structure of Figure 4 In the circuit configuration, the on-resistance of the second transistor Q2 becomes high.

[0085] Furthermore, in a constant state after the VDD voltage rises, the first transistor Q1 is in the off state, so no standby current flows. This allows for both a low drive force to prevent conduction and low power consumption. Compared to Implementation Example 1, this embodiment has the following characteristics: since the applied voltage for turning on the second transistor Q2 is lower, the on-resistance of the second transistor Q2 tends to increase. However, this embodiment utilizes fewer circuit components than Implementation Example 1 and achieves lower power consumption.

[0086] As described above, even when the slew rate of the voltage applied to the power supply voltage terminal VDD is high or the voltage applied to the power supply voltage terminal VDD oscillates, the first transistor Q1 and the second transistor Q2 can be prevented from being turned on simultaneously.

[0087] In the steady state after the power supply voltage rises, the fifth transistor 210 is in the off state, so no standby current flows. This allows for both a driving force difference for preventing the first transistor Q1 and the second transistor Q2 from being turned on simultaneously and low power consumption. Figure 4 The structure shown is Figure 2 Compared with the structure shown in FIG. 1 , the applied voltage for turning on the second transistor Q2 becomes lower, so the on-resistance of the second transistor Q tends to increase. However, fewer circuit components and lower power consumption can be achieved than in the embodiment 1.

[0088] (Installation Example 3)

[0089] Figure 6 1 is a circuit diagram showing the configuration of a semiconductor device 1 according to mounting example 3. A first circuit 20 includes a reference voltage generating circuit 21 and a voltage comparing circuit 22. A second circuit 30 includes an output buffer 31.

[0090] The reference voltage generation circuit 21 generates a reference voltage Vref. Figure 6 Although an example is shown, the present invention is not limited to this example, and any circuit may be used as long as it is configured as a circuit capable of outputting the reference voltage Vref.

[0091] The voltage comparator circuit 22 compares the voltage generated by the reference voltage generator circuit 21 with the voltage applied to the power supply voltage terminal VDD. For example, the input of a typical comparator is formed by inputting the output of the reference voltage generator circuit 21 and the voltage across a plurality of resistors distributed at a predetermined ratio between the power supply voltage terminal VDD and the ground terminal GND. The voltage comparator circuit 22 detects a voltage greater than the absolute value of the threshold voltage of the first transistor Q1 and outputs it to the output buffer 31.

[0092] The output buffer 31 controls the output of the voltage comparison circuit 22 and applies the output to the gate of the second transistor Q2.

[0093] Figure 7 FIG1 is a circuit diagram showing an implementation example of the output buffer 31. The output buffer 31 includes, for example, a sixth transistor M1, a seventh transistor M2, a fourth resistor R1, and a fifth resistor R2.

[0094] The sixth transistor M1 is a p-type MOSFET, a source of which is connected to the power supply voltage terminal VDD, and a gate of which is connected to the output of the voltage comparator circuit 22 .

[0095] The seventh transistor M2 is an n-type MOSFET, a source of which is connected to the ground terminal GND, and a gate of which is connected to the output of the voltage comparator circuit 22 .

[0096] The fourth resistor R1 is connected between the drain of the sixth transistor M1 and the output terminal.

[0097] The fifth resistor R2 is connected between the drain of the seventh transistor M2 and the output terminal.

[0098] The resistance value of the fifth resistor R2 is greater than the resistance value of the fourth resistor R1. By setting the resistance values ​​of the fourth resistor R1 and the fifth resistor R2 in this manner, the resistance value in the current path when the second transistor Q2 is turned on can be made greater than the resistance value in the current path when the second transistor Q2 is turned off. As a result, the driving force when the second transistor Q2 is turned off can be made higher than the driving force when the second transistor Q2 is turned on.

[0099] With such a resistor configuration, even when the slew rate of the voltage applied to the power supply voltage terminal VDD is high or the voltage vibrates, it is possible to prevent the first transistor Q1 and the second transistor Q2 from being turned on simultaneously.

[0100] Figure 8 3 is a circuit showing another implementation example of the output buffer 31. The output buffer 31 includes, for example, an eighth transistor M3 and a ninth transistor M4.

[0101] The eighth transistor M3 is a p-type MOSFET, a source of which is connected to the power supply voltage terminal VDD, and a gate of which is connected to the output of the voltage comparator circuit 22 .

[0102] The ninth transistor M4 is an n-type MOSFET, a source of which is connected to the ground terminal GND, a gate of which is connected to the output of the voltage comparator circuit 22 , and a drain of which is connected to the drain of the eighth transistor M8 .

[0103] As described above, the eighth transistor M3 and the ninth transistor M4 form a CMOS (Complementary MOSFET). In this implementation example, as an example, the gate width of the eighth transistor M3 is formed wider than the gate width of the ninth transistor M4.

[0104] By forming such a CMOS, the on-resistance value in the path where the second transistor Q2 is turned on can be made larger than the on-resistance value in the path where the second transistor Q2 is turned off. As a result, the driving force for turning off the second transistor Q2 can be made higher than the driving force for turning on the second transistor Q2.

[0105] With this configuration, even when the slew rate of the voltage applied to the power supply voltage terminal VDD is high or the voltage vibrates, it is possible to prevent the first transistor Q1 and the second transistor Q2 from being turned on simultaneously.

[0106] Figure 9 2 is a diagram showing another implementation example of the voltage comparison circuit 22. As shown in this diagram, a hysteresis comparator can also be used as the voltage comparison circuit.

[0107] (Installation Example 4)

[0108] Figure 10 : is a circuit diagram showing the structure of the semiconductor device 1 of the mounting example 3. Figure 1 In addition to the first circuit 20 and the second circuit 30 , the semiconductor device 1 further includes a third circuit 40 .

[0109] The third circuit 40 is a circuit that takes into account both preventing a charging current from flowing into the capacitor 50 connected between the power supply voltage and the ground voltage outside the semiconductor device 1 and preventing an overvoltage from being applied to the gate of the first transistor Q1 when a voltage is applied between the drain terminal DRAIN and the source terminal SOURCE before the VDD power supply is activated. The capacitor 50 is connected between the power supply voltage and the ground voltage outside the semiconductor device 1.

[0110] When capacitor 50 is charged, a current flows through the components of semiconductor device 1 based on the charged voltage. For example, this current flows in the order of drain terminal DRAIN, first transistor Q1, power supply voltage terminal VDD, capacitor 50, ground terminal GND, the body diode of the element that switches first transistor Q1 within third circuit 40, first diode 10, and source terminal SOURCE. Third circuit 40 prevents this current from flowing.

[0111] Figure 11 4 is a circuit diagram showing an implementation example of the third circuit 40. The third circuit 40 includes a first switch 400, a second switch 401, a sixth resistor 402, a fourth diode 403, and a fifth diode 404.

[0112] The first switch 400 is, for example, a p-type MOSFET, a source of which is connected to the power supply voltage terminal VDD, a gate of which is connected to the inverter output, and an inverter input of which is connected to the gate voltage application terminal GATE.

[0113] The second switch 401 is, for example, an n-type MOSFET, a source of which is connected to the ground terminal GND, a gate of which is connected to the inverter output, and an inverter input of which is connected to the gate voltage application terminal GATE.

[0114] One end of the sixth resistor 402 is connected to the drain of the first switch 400, and the other end is connected to the gate of the first transistor Q1. The sixth resistor 402 functions as a gate resistor for controlling the gate current of the first transistor Q1.

[0115] The anode of the fourth diode 403 is connected to the anode of the first diode 10 and the gate of the first transistor Q1 , and the cathode is connected to the power supply voltage terminal VDD.

[0116] The anode of the fifth diode 404 is connected to the drain of the first switch 400 and to the gate of the first transistor Q1 via the sixth resistor 402 , and the cathode is connected to the drain of the second switch 401 .

[0117] With this configuration, the fifth diode 404 connected between the second switch 401 and the second switch 400 and the sixth resistor 402 can prevent current from flowing through the body diode of the second switch 401, which serves to cut off the first transistor Q1. Furthermore, due to the connection of the fifth diode 404, when the gate voltage of the first transistor Q1 falls below the ground voltage GND, the gate voltage of the first transistor Q1 cannot be clamped by the body diode of the second switch 401. However, by connecting the fourth diode 403 between the gate of the first transistor Q1 and the power supply voltage terminal VDD, an overvoltage at the gate of the first transistor Q1 can be prevented.

[0118] As described above, according to the third circuit 40 of this implementation example, it is possible to achieve both prevention of the charging current to the capacitor 50 and prevention of an overvoltage at the gate voltage of the first transistor Q1 .

[0119] (Installation Example 5)

[0120] Figure 12 4 is a circuit diagram showing another implementation example of the third circuit 40. The third circuit 40 includes a first switch 400, a second switch 401, a sixth resistor 402, a fourth diode 403, and a sixth diode 405.

[0121] The first switch 400 is, for example, a p-type MOSFET, a source of which is connected to the power supply voltage terminal VDD, a gate of which is connected to the output of an inverter, and an input of the inverter of which is connected to the gate voltage application terminal GATE.

[0122] The second switch 401 is, for example, an n-type MOSFET, a source of which is connected to the ground terminal GND, a gate of which is connected to the output of an inverter, and an input of the inverter of which is connected to the gate voltage application terminal GATE.

[0123] One end of the sixth resistor 402 is connected to the drain of the first switch 400, and the other end is connected to the gate of the first transistor Q1. The sixth resistor 402 functions as a gate resistor for controlling the gate current of the first transistor Q1.

[0124] The anode of the fourth diode 403 is connected to the anode of the first diode 10 and the gate of the first transistor Q1 , and the cathode is connected to the power supply voltage terminal VDD.

[0125] The anode of the sixth diode 405 is connected to the gate of the first transistor Q1 , and the cathode is connected to the drain of the second switch 401 .

[0126] The sixth diode 405 connected between the second switch 401 and the gate of the first transistor Q1 prevents current from flowing through the body diode of the second switch 401, which is used to cut off the first transistor Q1. In the fourth embodiment, since the gate resistor is located in the gate current path for both turning on and off the first transistor Q1, it was difficult to independently adjust the driving force. However, in this embodiment, the sixth diode 405 alone allows the gate current path for turning on and off the first transistor Q1 to be independently adjusted, thereby adjusting the driving force. Furthermore, similar to the above embodiment, the capacitor charging current can be prevented.

[0127] (Installation Example 6)

[0128] Figure 13 4 is a circuit diagram showing another implementation example of the third circuit 40. The third circuit 40 includes a first switch 400, a second switch 401, a sixth resistor 402, a fourth diode 403, and a third switch 406.

[0129] The first switch 400 is, for example, a p-type MOSFET, a source of which is connected to the power supply voltage terminal VDD, a gate of which is connected to the inverter output, and an inverter input of which is connected to the gate voltage application terminal GATE.

[0130] The second switch 401 is, for example, an n-type MOSFET, has a source connected back-to-back with the third switch 406 , a gate connected to an inverter output, and an inverter input connected to a gate voltage application terminal GATE.

[0131] One end of the sixth resistor 402 is connected to the drain of the first switch 400, and the other end is connected to the gate of the first transistor Q1. The sixth resistor 402 functions as a gate resistor for controlling the gate current of the first transistor Q1.

[0132] The anode of the fourth diode 403 is connected to the anode of the first diode 10 and the gate of the first transistor Q1 , and the cathode is connected to the power supply voltage terminal VDD.

[0133] The third switch 406 is, for example, an n-type MOSFET, with a drain connected to the ground terminal GND, a gate connected to the gate voltage application terminal GATE, and a source connected back-to-back to the source of the second switch 401 .

[0134] The third switch 406 connected between the second switch 401 and the ground potential forms a bidirectional switch, thereby preventing current from flowing through the second switch 401 when the first transistor Q1 is cut off. In the fifth embodiment described above, when the first transistor Q1 is cut off, the driving force for the cutoff is reduced only by the forward voltage of the sixth diode 405 in the gate current path. However, with the configuration of this embodiment, when the first transistor Q1 is cut off, the voltage is the product of the on-resistance of the third switch 406 and the gate current. Therefore, by using a switching element with a low on-resistance as the third switch 406, the driving force for the cutoff can be enhanced.

[0135] Thus, even when a high voltage slew rate is applied between the drain and source of the first transistor Q1, the impedance of the cutoff current path formed by the second switch 401 and the third switch 406 is suppressed low, thereby preventing the first transistor Q1 from being falsely turned on.

[0136] According to the various embodiments described above, the first and second transistors Q1 and Q2 can be appropriately controlled to change the normally-on state of the first transistor Q1 to a normally-off state without increasing the gate current loop for driving the first transistor Q1. This semiconductor device 1 can provide a switch that can safely operate normally-off with high withstand voltages, such as those applied to an external load, such as approximately 140V to 400V.

[0137] In the above embodiments, the second transistor Q2 is disposed outside the semiconductor device 1. However, the second transistor Q2 may be included in the semiconductor device 1. In this case, the semiconductor device 1 may include an output terminal connected to the gate and source of the first transistor Q1 and outputting the drain current of the first transistor Q1.

[0138] While several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments may be implemented in various other forms and may be omitted, replaced, or modified without departing from the spirit of the invention. These embodiments and their variations are intended to be included within the scope and spirit of the invention and within the invention set forth in the claims and their equivalents.

Claims

1. A semiconductor device in which a first transistor that is normally-on is driven is normally-off driven, wherein: have: a first circuit connected to a power supply voltage and a ground voltage, detecting the power supply voltage and outputting a transition state of the power supply voltage; a second circuit connected to the power supply voltage, the ground voltage, the first circuit, and the second transistor, and outputting a drive voltage for the second transistor connected in series with the first transistor based on an output of the first circuit; a first diode having an anode connected to the driving terminal of the first transistor and a cathode connected to the output terminal of the second transistor; a fifth transistor having a drain connected to the power supply voltage and a gate connected to the ground voltage for normally-on driving; as well as The third diode, which is a Zener diode, has an anode connected to the ground voltage and a cathode connected to the source of the fifth transistor and the gate of the second transistor.

2. The semiconductor device according to claim 1, wherein The first transistor is a FET using gallium nitride (GaN) whose source is connected to the power supply voltage. The second transistor is a p-type MOSFET whose source is connected to the source of the first transistor.

3. The semiconductor device according to claim 1 or 2, wherein The device further includes a third circuit connected to the gate of the first transistor, which prevents a capacitor from charging current and controls a driving voltage when the power supply voltage is turned on.

4. A semiconductor device, wherein a first transistor that is normally-on driven is normally-off driven, wherein: have: a first circuit connected to a power supply voltage and a ground voltage, detecting the power supply voltage and outputting a transition state of the power supply voltage; a second circuit connected to the power supply voltage, the ground voltage, the first circuit, and the second transistor, and outputting a drive voltage for the second transistor connected in series with the first transistor based on an output of the first circuit; as well as a first diode having an anode connected to the driving terminal of the first transistor and a cathode connected to the output terminal of the second transistor; The first circuit has: A reference voltage generating circuit generates a reference voltage; as well as a voltage comparison circuit, which compares the reference voltage with the power supply voltage, The second circuit includes an output buffer that controls the output of the voltage comparison circuit and applies the output to the gate of the second transistor.

5. The semiconductor device according to claim 4, wherein The first transistor is a FET using gallium nitride (GaN) whose source is connected to the power supply voltage. The second transistor is a p-type MOSFET whose source is connected to the source of the first transistor.

6. The semiconductor device according to claim 4 or 5, wherein The device further includes a third circuit connected to the gate of the first transistor, which prevents a capacitor from charging current and controls a driving voltage when the power supply voltage is turned on.

7. The semiconductor device according to claim 4, wherein Also features: a third resistor and a fourth resistor connected in series between the power supply voltage and the ground voltage; and a fifth resistor and a switch connected in series between a node connected to the third resistor and the fourth resistor and the ground voltage; An output terminal of the voltage comparison circuit is connected to a control input terminal of the switch.

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