Capacitively isolated driving circuit based on sic mosfet

Abstract

The application discloses a capacitive isolation type driving circuit based on SiC MOSFET, which comprises an on-off key modulation circuit, the output end of the on-off key modulation circuit is connected with the input end of a three-order differential isolation transmission circuit, the output end of the three-order differential isolation transmission circuit is connected with the input end of a frequency selection amplifier circuit, and the output end of the frequency selection amplifier circuit is connected with the input end of a demodulation circuit. The capacitive isolation type driving circuit based on SiC MOSFET combines the three-order differential circuit with the isolation capacitor, accurately utilizes the rapid response and frequency selection characteristics of the differential circuit to high-frequency signals, optimally processes the input signals, and strengthens the signal coupling efficiency; meanwhile, through the unique circuit topology design, the interference signals generated by the common-mode transient electric stress are effectively inhibited, the system anti-interference ability is greatly enhanced, and the bottleneck of the traditional design in the common-mode transient anti-interference degree is successfully broken through.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of isolation drive circuit, and relates to a capacitive isolation type drive circuit based on SiC MOSFET. BACKGROUND

[0002] With the urgent needs of high efficiency, high power density and high frequency operation in the fields of electric vehicles, photovoltaic inverters and high-end power systems, SiC MOSFET (Silicon Carbide Metal-Oxide-Semiconductor Field-Effect Transistor) is gradually replacing traditional silicon-based devices and becoming a key device of the new generation of power electronic systems due to its excellent high breakdown voltage, fast switching speed and low on-resistance. However, SiC MOSFET is prone to generate strong common-mode interference signals under high dV / dT (Rate of Change of Voltage with Respect to Time) working state, and the voltage range required for SiC MOSFET gate drive, on and off time requirements and anti-interference ability are significantly higher than those of traditional silicon devices, which puts forward strict requirements on the common-mode transient immunity (CMTI), pulse width consistency, transmission delay and other performance indicators of the drive chip. Therefore, designing an isolation drive chip with high common-mode transient immunity, low delay, low power consumption, small pulse width distortion and stable reliability has become the core key to ensuring system performance.

[0003] In summary, the prior art has the problem of low common-mode transient immunity of SiC MOSFET drive circuit. SUMMARY

[0004] The purpose of the application is to provide a capacitive isolation type drive circuit based on SiC MOSFET, which solves the problem of low common-mode transient immunity of SiC MOSFET drive circuit in the prior art.

[0005] The technical solution adopted by the application is that the capacitive isolation type drive circuit based on SiC MOSFET comprises an on-off key modulation circuit, the output end of the on-off key modulation circuit is connected with the input end of a three-order differential isolation transmission circuit, the output end of the three-order differential isolation transmission circuit is connected with the input end of a frequency selection amplifier circuit, and the output end of the frequency selection amplifier circuit is connected with the input end of a demodulation circuit.

[0006] The application also has the following characteristics:

[0007] The on-off keying modulation circuit comprises a first differential comparator, an output terminal of the first differential comparator is connected with an input terminal of a NAND gate NAND1, an output terminal of the NAND gate NAND1 is connected with an input terminal of a first inverter, an output terminal of the first inverter is connected with an input terminal of a second inverter, an output terminal of the second inverter is connected with an input terminal of a third inverter, and the first inverter, the second inverter and the third inverter are in size increasing order.

[0008] The on-off keying modulation circuit further comprises a second differential comparator, an output terminal of the second differential comparator is connected with an input terminal of a NAND gate NAND2, an output terminal of the NAND gate NAND2 is connected with an input terminal of a fourth inverter, an output terminal of the fourth inverter is connected with an input terminal of a fifth inverter, an output terminal of the fifth inverter is connected with an input terminal of a sixth inverter, and the fourth inverter, the fifth inverter and the sixth inverter are in size increasing order.

[0009] The input terminals of the NAND gate NAND1 and the NAND gate NAND2 are connected with a control voltage signal V IN .

[0010] The third-order differential isolation transmission circuit comprises a capacitor C ISO1 , an upper plate of a capacitor C ISO1 is connected with the output terminal of the third inverter, a lower plate of a capacitor C ISO1 is connected with the upper plate of the capacitor C ISO2 , a lower plate of a capacitor C ISO2 is connected with one end of a resistor R 0, one end of a capacitor C 0, the other end of the resistor R 0 is grounded, the other end of the capacitor C 0 is connected with one end of a resistor R 1, one end of a capacitor C 1, the other end of the resistor R 1 is grounded, and the other end of the capacitor C 1 is connected with one end of a resistor R 2.

[0011] The third-order differential isolation transmission circuit comprises a capacitor C ISO3 , an upper plate of a capacitor C ISO3 is connected with the output terminal of the sixth inverter, a lower plate of a capacitor C ISO3 is connected with the upper plate of a capacitor C ISO4 , a lower plate of a capacitor C ISO4 is connected with a resistorR 3. One end, capacitor C 2. One end is connected, resistor R 3. The other end is grounded, capacitor C 2. The other end is connected to the resistor. R 4. One end, capacitor C 3. One end is connected, resistor R 4. The other end is grounded, capacitor C 3. The other end is connected to the resistor. R 5. Connect one end.

[0012] The frequency-selective amplifier circuit includes transistor M N3 transistor M N3 source and resistor R 2. Keep away from the ungrounded end and capacitor. C 1. Keep away from resistors R 2. One end, resistor R 8 One end is connected, resistor R 8. The other end is grounded, transistor M N3 Gate and transistor M N1 Gate, transistor M N1 The drain connection of transistor M N3 The drain and transistor M N2 The source connection;

[0013] Transistor M N1 Gate and transistor M N1 The drain connection of transistor M N1 Gate, transistor M N1 The drain and bias current source I bias1 One end is connected to the bias current source I. bias1 The other end is connected to the power supply VDD, transistor M N1 The source and transistor M N5 The source connection;

[0014] Transistor M N2 Gate and transistor M N4 Gate connection, transistor M N2 The drain and transistor M P1 The drain of the transistor M P0 gate, resistor R 7 One end is connected, resistor R 7. The other end is connected to the capacitor. C 5. One end is connected to the capacitor. C 5. The other end is connected to the power supply VDD;

[0015] Transistor M P1 The source of transistor M is connected to the power supply VDD. P1 gate and capacitor C5. The resistor should be kept away from the VDD power supply terminal. R 7. Away from transistor M N2 One end is connected;

[0016] Transistor M P0 The source of transistor M is connected to the power supply VDD. P0 gate and capacitor C a One end is connected to the capacitor. C a The other end is connected to transistor M P3 The drain of the transistor M N7 The drain connection of transistor M P0 Drain and capacitor C b One end, transistor M N0 Drain and resistor R 6. Connect one end;

[0017] Transistor M N0 gate and resistor R 6. Away from transistor M P0 One end, capacitor C 4. One end is connected to the capacitor. C 4. The other end is grounded, transistor M N0 The source electrode is grounded.

[0018] The frequency-selective amplifier circuit also includes transistor M. N5 transistor M N5 source and resistor R 5. Keep away from the ungrounded end and capacitor. C 3. Keep away from resistors R 4. One end, resistor R 9 is connected at one end, resistor R 9 is grounded at the other end, transistor M N5 Gate and transistor M N6 Gate, transistor M N6 The drain connection of transistor M N5 The drain and transistor M N4 The source connection;

[0019] Transistor M N6 Gate and transistor M N6 The drain connection of transistor M N6 Gate, transistor M N6 The drain and bias current source I bias2 One end is connected to the bias current source I. bias2 The other end is connected to the power supply VDD, transistor M N6 The source and transistor M N3 The source connection;

[0020] Transistor M N4 The drain and transistor M P2 The drain of the transistor M P3 gate, resistor R 10 One end connected, resistor R 10 The other end is connected to the capacitor. C 6 One end is connected, capacitor C 6. The other end is connected to the power supply VDD;

[0021] Transistor M P2 The source of transistor M is connected to the power supply VDD. P2 gate and capacitor C 6. Keep away from the VDD end of the power supply and the resistor. R 10 Away from transistor M N4 One end is connected;

[0022] Transistor M P3 The source of transistor M is connected to the power supply VDD. P3 gate and capacitor C b One end is connected to the capacitor. C b The other end is connected to transistor M P0 The drain of the transistor M N0 The drain connection of transistor M P3 Drain and capacitor C a One end, transistor M N7 Drain and resistor R 11 One end is connected;

[0023] Transistor M N7 gate and resistor R 11 Away from transistor M P3 One end, capacitor C 7 One end is connected, capacitor C 7. The other end is grounded, transistor M N7 The source electrode is grounded.

[0024] Transistor M P0 Source, bias current source I bias1 One end connected to the power supply VDD, capacitor C 5. Connect one end to the power supply VDD, transistor M P1 The source of the transistor M P2 source, capacitor C 6. Connect one end to the power supply VDD and the bias current source I. bias2 One end is connected to the power supply VDD, and the transistor MP3 source of transistor M

[0025] capacitor C 4 ground terminal, transistor M N0 source of transistor M, resistor R 8 ground terminal, resistor R 9 ground terminal, transistor M N7 source of transistor M, capacitor C 7 ground terminal is connected.

[0026] demodulation circuit includes capacitor C 8 and capacitor C 9, one end of capacitor C 8 is connected to resistor R 11 away from capacitor C 7 one end, drain of transistor M N7 drain of transistor M, capacitor P3 drain of transistor M C a transistor M P0 one end is connected, capacitor C 8 the other end is connected to resistor R 15 one end, gate of transistor M N12 is connected;

[0027] capacitor C 9 one end is connected to resistor R 6 away from capacitor C 4 one end, drain of transistor M N0 drain of transistor M, capacitor P0 drain of transistor M C b away from transistor M P3 one end is connected, capacitor C 9 the other end is connected to resistor R 16 one end, gate of transistor M N13 is connected;

[0028] drain of transistor M, drain of transistor M N12 drain of transistor M N13 drain of transistor M P10 drain of transistor M P10 gate of transistor M, gate of transistor M P11 is connected, source of transistor M N12 source of transistor M, source of transistor M N10 source of transistor M N13 source of transistor M N11 is connected;

[0029] resistor R 15 away from capacitor C8 One end, resistor R 16 Keep away from capacitors C 9-terminal transistor M P7 Drain and resistor R 14 One end connected, resistor R 14 The other end is grounded;

[0030] Transistor M P10 The drain of the transistor M P10 Gate connection, transistor M P10 The source of transistor M is connected to the power supply VDD. P11 The source of transistor M is connected to the power supply VDD. P11 The drain and transistor M N14 Drain connection;

[0031] Transistor M N10 The drain and transistor M P9 The drain of the transistor M P9 Gate, transistor M P8 Gate connection, transistor M N10 Gate and transistor M P6 Drain and resistor R 12 One end connected, resistor R 12 The other end is connected to the resistor R 13 One end connected, resistor R 13 The other end is grounded;

[0032] Transistor M P8 Gate, transistor M P9 Gate connection, transistor M P8 The source of the transistor M P9 The source of transistor M is connected to the power supply VDD. P8 The drain and transistor M N9 The drain of the transistor M N9 Gate connection;

[0033] Transistor M N14 The source is grounded, transistor M N14 Gate, transistor M N9 Gate, transistor M N9 The drain of the transistor M P8 The drain connection of transistor M N9 The source is grounded;

[0034] Transistor M N11 Gate and control voltage signalV b1 the source of transistor M N11 is connected to ground;

[0035] the source of transistor M P7 is connected to power supply VDD, the drain of transistor M P7 is connected to the gate of transistor M P6 , the gate of transistor M P5 , the gate of transistor M P4 , the gate of transistor M bias3 is connected to one end of bias current source I bias3 is grounded at the other end;

[0036] the source of transistor M P6 is connected to power supply VDD, the drain of transistor M P6 is connected to resistor R 12 is connected to resistor R 13 at one end, the gate of transistor M N10 is connected;

[0037] the source of transistor M P5 is connected to power supply VDD, the drain of transistor M P5 is connected to the gate of transistor M N8 , the drain of transistor M N8 is connected;

[0038] the source of transistor M P4 is connected to power supply VDD, the drain of transistor M P4 is connected to the gate of transistor M P4 , the drain of transistor M bias3 is connected to one end of bias current source I

[0039] the drain of transistor M N8 is connected to the gate of transistor M N8 , the source of transistor M N8 is grounded.

[0040] the source of transistor M P4 , the source of transistor M P5 , the source of transistor M P6 , the source of transistor M P7 , the source of transistor M P8 , the source of transistor M P9 , the source of transistor M P10 , the source of transistor M P11 is connected;

[0041] one end of bias current source I bias3 is grounded, the source of transistor M N8source of the resistor R 13 grounded end, resistor R 14 grounded end, transistor M N9 source of the resistor, transistor M N11 source of the resistor, transistor M N14 source of the resistor is connected.

[0042] The beneficial effects of the present application are: based on the analysis of the influence of common-mode transient electric stress on the capacitor isolation chip transmitter and receiver, an innovative isolation transmission structure based on a third-order differential circuit is proposed as a capacitor isolation scheme, which combines the third-order differential circuit with the isolation capacitor, accurately utilizes the rapid response and frequency selection characteristics of the differential circuit to high-frequency signals, optimizes the processing of the input signal, and strengthens the signal coupling efficiency; at the same time, through the unique circuit topology design, the interference signals generated by the common-mode transient electric stress are effectively suppressed, and the system anti-interference ability is greatly enhanced, which successfully breaks through the bottleneck of traditional design in common-mode transient anti-interference; the common-mode transient anti-interference performance of the system can be improved by several times, and the reliability of the system is greatly increased. BRIEF DESCRIPTION OF DRAWINGS

[0043] Figure 1 is the system circuit structure diagram of the capacitor isolation type driving circuit based on SiC MOSFET of the present application;

[0044] Figure 2 is the on-off key modulation circuit structure schematic diagram for generating a carrier signal in the present application;

[0045] Figure 3 is the third-order differential isolation transmission circuit structure schematic diagram for eliminating common-mode noise current in the present application;

[0046] Figure 4 is the frequency selective amplifier circuit structure schematic diagram for amplifying the carrier signal in the present application;

[0047] Figure 5 is the demodulation circuit structure schematic diagram for demodulating the carrier signal into a level signal in the present application.

[0048] In the figure, 1 is an on-off key modulation circuit; 2 is a third-order differential isolation transmission circuit; 3 is a frequency selective amplifier circuit; and 4 is a demodulation circuit. DETAILED DESCRIPTION

[0049] The present application will be described in detail below in combination with the drawings and specific embodiments.

[0050] Example 1

[0051] This embodiment proposes a capacitor isolation type driving circuit based on SiC MOSFET, as shown inFigure 1 As shown in the figure, it comprises an on-off keying modulation circuit 1, the output end of the on-off keying modulation circuit 1 is connected with the input end of a three-order differential isolated transmission circuit 2, the output end of the three-order differential isolated transmission circuit 2 is connected with the input end of a selective amplifier circuit 3, the output end of the selective amplifier circuit 3 is connected with the input end of a demodulation circuit 4.

[0052] Embodiment 2

[0053] This embodiment proposes a capacitive isolation type driving circuit based on SiC MOSFET, as shown in the figure, it comprises an on-off keying modulation circuit 1, the output end of the on-off keying modulation circuit 1 is connected with the input end of a three-order differential isolated transmission circuit 2, the output end of the three-order differential isolated transmission circuit 2 is connected with the input end of a selective amplifier circuit 3, the output end of the selective amplifier circuit 3 is connected with the input end of a demodulation circuit 4. Figure 1 As shown in the figure, it comprises an on-off keying modulation circuit 1, the output end of the on-off keying modulation circuit 1 is connected with the input end of a three-order differential isolated transmission circuit 2, the output end of the three-order differential isolated transmission circuit 2 is connected with the input end of a selective amplifier circuit 3, the output end of the selective amplifier circuit 3 is connected with the input end of a demodulation circuit 4.

[0054] In combination with Figure 2 As shown in the figure, the on-off keying modulation circuit 1 comprises a first differential comparator, the output end of the first differential comparator is connected with the input end of a NAND gate NAND1, the output end of the NAND gate NAND1 is connected with the input end of a first inverter, the output end of the first inverter is connected with the input end of a second inverter, the output end of the second inverter is connected with the input end of a third inverter; the sizes of the first inverter, the second inverter and the third inverter increase in turn. The on-off keying modulation circuit 1 further comprises a second differential comparator, the output end of the second differential comparator is connected with the input end of a NAND gate NAND2, the output end of the NAND gate NAND2 is connected with the input end of a fourth inverter, the output end of the fourth inverter is connected with the input end of a fifth inverter, the output end of the fifth inverter is connected with the input end of a sixth inverter; the sizes of the fourth inverter, the fifth inverter and the sixth inverter increase in turn; the input ends of the NAND gate NAND1 and the NAND gate NAND2 are connected with a control voltage signal V IN .

[0055] Embodiment 3

[0056] This embodiment proposes a capacitive isolation type driving circuit based on SiC MOSFET, as shown in the figure, it comprises an on-off keying modulation circuit 1, the output end of the on-off keying modulation circuit 1 is connected with the input end of a three-order differential isolated transmission circuit 2, the output end of the three-order differential isolated transmission circuit 2 is connected with the input end of a selective amplifier circuit 3, the output end of the selective amplifier circuit 3 is connected with the input end of a demodulation circuit 4. Figure 1 As shown in the figure, it comprises an on-off keying modulation circuit 1, the output end of the on-off keying modulation circuit 1 is connected with the input end of a three-order differential isolated transmission circuit 2, the output end of the three-order differential isolated transmission circuit 2 is connected with the input end of a selective amplifier circuit 3, the output end of the selective amplifier circuit 3 is connected with the input end of a demodulation circuit 4.

[0057] In combination with Figure 2As shown, the on-off keying modulation circuit 1 includes a first differential comparator, the output end of the first differential comparator is connected with the input end of the NAND gate NAND1, the output end of the NAND gate NAND1 is connected with the input end of a first inverter, the output end of the first inverter is connected with the input end of a second inverter, the output end of the second inverter is connected with the input end of a third inverter; the sizes of the first inverter, the second inverter and the third inverter increase in turn. The on-off keying modulation circuit 1 further includes a second differential comparator, the output end of the second differential comparator is connected with the input end of the NAND gate NAND2, the output end of the NAND gate NAND2 is connected with the input end of a fourth inverter, the output end of the fourth inverter is connected with the input end of a fifth inverter, the output end of the fifth inverter is connected with the input end of a sixth inverter; the sizes of the fourth inverter, the fifth inverter and the sixth inverter increase in turn; the input ends of the NAND gate NAND1 and the NAND gate NAND2 are connected with a control voltage signal V IN .

[0058] In combination Figure 3 As shown, the third-order differential isolation transmission circuit 2 includes a capacitor C ISO1 , the upper plate of the capacitor C ISO1 is connected with the output end of the third inverter, the lower plate of the capacitor C ISO1 is connected with the upper plate of the capacitor C ISO2 , the lower plate of the capacitor C ISO2 is connected with one end of a resistor R 0, one end of a capacitor C 0, the other end of the resistor R 0 is grounded, the other end of the capacitor C 0 is connected with one end of a resistor R 1, one end of a capacitor C 1, the other end of the resistor R 1 is grounded, the other end of the capacitor C 1 is connected with one end of a resistor R 2. The third-order differential isolation transmission circuit 2 includes a capacitor C ISO3 , the upper plate of the capacitor C ISO3 is connected with the output end of the sixth inverter, the lower plate of the capacitor C ISO3 is connected with the upper plate of the capacitor C ISO4 , the lower plate of the capacitor C ISO4 is connected with one end of a resistor R 3, one end of a capacitor C 2, the other end of the resistor R3. The other end is grounded, capacitor C 2. The other end is connected to the resistor. R 4. One end, capacitor C 3. One end is connected, resistor R 4. The other end is grounded, capacitor C 3. The other end is connected to the resistor. R 5. Connect one end.

[0059] Example 4

[0060] This embodiment proposes a capacitor-isolated drive circuit based on SiC MOSFETs, such as... Figure 1 As shown, it includes an on / off keying modulation circuit 1, the output of which is connected to the input of a third-order differential isolation transmission circuit 2, the output of which is connected to the input of a frequency selective amplifier circuit 3, and the output of which is connected to the input of a demodulation circuit 4.

[0061] Combination Figure 2 As shown, the on / off keying modulation circuit 1 includes a first differential comparator. The output of the first differential comparator is connected to the input of an AND gate NAND1. The output of the AND gate NAND1 is connected to the input of a first inverter. The output of the first inverter is connected to the input of a second inverter. The output of the second inverter is connected to the input of a third inverter. The sizes of the first, second, and third inverters increase sequentially. The on / off keying modulation circuit 1 also includes a second differential comparator. The output of the second differential comparator is connected to the input of an AND gate NAND2. The output of the AND gate NAND2 is connected to the input of a fourth inverter. The output of the fourth inverter is connected to the input of a fifth inverter. The output of the fifth inverter is connected to the input of a sixth inverter. The sizes of the fourth, fifth, and sixth inverters increase sequentially. Control voltage signals are connected to the inputs of the AND gates NAND1 and NAND2. V IN .

[0062] Combination Figure 3 As shown, the third-order differential isolation transmission circuit 2 includes a capacitor. C ISO1 ,capacitance C ISO1 The upper plate is connected to the output terminal of inverter number three, and the capacitor... C ISO1 The lower electrode and capacitor C ISO2 The upper plate is connected to the capacitor. C ISO2 The lower electrode and resistor R 0 terminal, capacitor C 0 is connected to the resistor. R0 other end grounded, capacitor C 0 other end connected to resistor R 1 one end, capacitor C 1 one end connected, resistor R 1 other end grounded, capacitor C 1 other end connected to resistor R 2 one end connected. Third order differential isolated transmission circuit 2 includes capacitor C ISO3 , capacitor C ISO3 upper plate connected to output of inverter 6, capacitor C ISO3 lower plate connected to upper plate of capacitor C ISO4 , capacitor C ISO4 lower plate connected to resistor R 3 one end, capacitor C 2 one end connected, resistor R 3 other end grounded, capacitor C 2 other end connected to resistor R 4 one end, capacitor C 3 one end connected, resistor R 4 other end grounded, capacitor C 3 other end connected to resistor R 5 one end connected.

[0063] in combination Figure 4 as shown, selective amplifier circuit 3 includes transistor M N3 , source of transistor M N3 connected to resistor R 2 away from ungrounded end, capacitor C 1 away from resistor R 2 one end, resistor R 8 one end connected, resistor R 8 other end grounded, gate of transistor M N3 connected to gate of transistor M N1 , drain of transistor M N1 connected to source of transistor M N3 , drain of transistor M N2 connected to source of transistor M N1 , gate of transistor M N1 connected to drain of transistor M N1 , gate of transistor M N1 , drain of transistor M bias1 one end connected to bias current source I bias1 other end connected to power supply VDD, source of transistor M N1 connected to source of transistor M N5 , source of transistor MN2 Gate and transistor M N4 Gate connection, transistor M N2 The drain and transistor M P1 The drain of the transistor M P0 gate, resistor R 7 One end is connected, resistor R 7. The other end is connected to the capacitor. C 5. One end is connected to the capacitor. C 5. The other end is connected to the power supply VDD; transistor M P1 The source of transistor M is connected to the power supply VDD. P1 gate and capacitor C 5. The resistor should be kept away from the VDD terminal of the power supply. R 7. Away from transistor M N2 One end is connected; transistor M P0 The source of transistor M is connected to the power supply VDD. P0 gate and capacitor C a One end is connected to the capacitor. C a The other end is connected to transistor M P3 The drain of the transistor M N7 The drain connection of transistor M P0 Drain and capacitor C b One end, transistor M N0 Drain and resistor R 6 is connected at one end; transistor M N0 gate and resistor R 6. Away from transistor M P0 One end, capacitor C 4. One end is connected to the capacitor. C 4. The other end is grounded, transistor M N0 The source electrode is grounded.

[0064] Example 5

[0065] This embodiment proposes a capacitor-isolated drive circuit based on SiC MOSFETs, such as... Figure 1 As shown, it includes an on / off keying modulation circuit 1, the output of which is connected to the input of a third-order differential isolation transmission circuit 2, the output of which is connected to the input of a frequency selective amplifier circuit 3, and the output of which is connected to the input of a demodulation circuit 4.

[0066] Combination Figure 2As shown, the on-off keying modulation circuit 1 includes a first differential comparator, the output end of the first differential comparator is connected with the input end of the NAND gate NAND1, the output end of the NAND gate NAND1 is connected with the input end of a first inverter, the output end of the first inverter is connected with the input end of a second inverter, the output end of the second inverter is connected with the input end of a third inverter; the sizes of the first inverter, the second inverter and the third inverter increase in turn. The on-off keying modulation circuit 1 further includes a second differential comparator, the output end of the second differential comparator is connected with the input end of the NAND gate NAND2, the output end of the NAND gate NAND2 is connected with the input end of a fourth inverter, the output end of the fourth inverter is connected with the input end of a fifth inverter, the output end of the fifth inverter is connected with the input end of a sixth inverter; the sizes of the fourth inverter, the fifth inverter and the sixth inverter increase in turn; the input ends of the NAND gate NAND1 and the NAND gate NAND2 are connected with a control voltage signal V IN .

[0067] In combination Figure 3 As shown, the third-order differential isolation transmission circuit 2 includes a capacitor C ISO1 , the upper plate of the capacitor C ISO1 is connected with the output end of the third inverter, the lower plate of the capacitor C ISO1 is connected with the upper plate of the capacitor C ISO2 , the lower plate of the capacitor C ISO2 is connected with one end of a resistor R 0, one end of a capacitor C 0, the other end of the resistor R 0 is grounded, the other end of the capacitor C 0 is connected with one end of a resistor R 1, one end of a capacitor C 1, the other end of the resistor R 1 is grounded, the other end of the capacitor C 1 is connected with one end of a resistor R 2. The third-order differential isolation transmission circuit 2 includes a capacitor C ISO3 , the upper plate of the capacitor C ISO3 is connected with the output end of the sixth inverter, the lower plate of the capacitor C ISO3 is connected with the upper plate of the capacitor C ISO4 , the lower plate of the capacitor C ISO4 is connected with one end of a resistor R 3, one end of a capacitor C 2, the other end of the resistor R3 the other end grounded, capacitor C 2 one end, resistor R 4 one end, capacitor C 3 one end connected, resistor R 4 the other end grounded, capacitor C 3 the other end, resistor R 5 one end connected.

[0068] in combination Figure 4 As shown, the selective amplifier circuit 3 includes a transistor M N3 , the source of transistor M N3 is connected to a resistor R 2 one end away from the ungrounded end, capacitor C 1 away from the resistor R 2 one end, resistor R 8 one end connected, resistor R 8 the other end grounded, the gate of transistor M N3 is connected to the gate of transistor M N1 , the drain of transistor M N1 is connected to the drain of transistor M N3 , the source of transistor M N2 is connected to the source of transistor M N1 , the gate of transistor M N1 is connected to the drain of transistor M N1 , the gate of transistor M N1 is connected to the drain of transistor M bias1 one end connected, bias current source I bias1 the other end connected to power supply VDD, the source of transistor M N1 is connected to the source of transistor M N5 , the gate of transistor M N2 is connected to the gate of transistor M N4 , the drain of transistor M N2 is connected to the drain of transistor M P1 , the gate of transistor M P0 , resistor R 7 one end connected, resistor R 7 the other end connected to capacitor C 5 one end connected, capacitor C 5 the other end connected to power supply VDD; the source of transistor M P1 is connected to power supply VDD, the gate of transistor M P1 is connected to capacitor C 5 one end away from power supply VDD, resistor R 7 one end connected away from transistor M N2 , the source of transistor M P0 is connected to power supply VDD, the gate of transistor M P0 is connected to capacitor Ca one end, capacitor C a the other end of the transistor M P3 , the drain of the transistor M N7 , the drain of the transistor M P0 , the drain of the transistor M C b one end, the drain of the transistor M N0 , the drain of the transistor M R 6one end; the gate of the transistor M N0 , the gate of the transistor M R 6away from the transistor M P0 one end, capacitor C 4one end, capacitor C 4the other end grounded, the source of the transistor M N0 .

[0069] The selective amplifier circuit 3 further includes a transistor M N5 , the source of the transistor M N5 , the source of the transistor M R 5away from the ungrounded end, capacitor C 3away from the resistor R 4one end, resistor R 9one end connected, resistor R 9the other end grounded, the gate of the transistor M N5 , the gate of the transistor M N6 , the drain of the transistor M N6 , the drain of the transistor M N5 , the source of the transistor M N4 , the gate of the transistor M N6 , the gate of the transistor M N6 , the drain of the transistor M N6 , the gate of the transistor M N6 , the drain of the transistor M bias2 one end connected, bias current source I bias2 the other end connected to the power supply VDD, the source of the transistor M N6 , the source of the transistor M N3 , the drain of the transistor M N4 , the drain of the transistor M P2 , the gate of the transistor M P3 , the gate of the transistor M R 10 one end connected, resistor R 10 the other end of the capacitor C 6one end connected, capacitor C 6the other end connected to the power supply VDD; the source of the transistor M P2 , the source of the transistor MP2 gate and capacitor C 6. Keep away from the VDD end of the power supply and the resistor. R 10 Away from transistor M N4 One end is connected; transistor M P3 The source of transistor M is connected to the power supply VDD. P3 gate and capacitor C b One end is connected to the capacitor. C b The other end is connected to transistor M P0 The drain of the transistor M N0 The drain connection of transistor M P3 Drain and capacitor C a One end, transistor M N7 drain, resistor R 11 One end is connected; transistor M N7 gate and resistor R 11 Away from transistor M P3 One end, capacitor C 7 One end is connected, capacitor C 7. The other end is grounded, transistor M N7 The source of transistor M is grounded. P0 Source, bias current source I bias1 One end connected to the power supply VDD, capacitor C 5. Connect one end to the power supply VDD, transistor M P1 The source of the transistor M P2 source, capacitor C 6. Connect one end to the power supply VDD and the bias current source I. bias2 One end is connected to the power supply VDD, and the transistor M P3 Source connection; capacitor C 4. Ground terminal, transistor M N0 source, resistor R 8. Grounding terminal, resistor R 9. Ground terminal, transistor M N7 source, capacitor C 7. Connect one end to the ground.

[0070] Example 6

[0071] This embodiment proposes a capacitor-isolated drive circuit based on SiC MOSFETs, such as... Figure 1As shown, including the on-off keying modulation circuit 1, the output end of the on-off keying modulation circuit 1 is connected with the input end of the third-order differential isolation transmission circuit 2, the output end of the third-order differential isolation transmission circuit 2 is connected with the input end of the selective amplifier circuit 3, the output end of the selective amplifier circuit 3 is connected with the input end of the demodulation circuit 4.

[0072] In combination Figure 2 As shown, the on-off keying modulation circuit 1 includes a first differential comparator, the output end of the first differential comparator is connected with the input end of the NAND gate NAND1, the output end of the NAND gate NAND1 is connected with the input end of the first inverter, the output end of the first inverter is connected with the input end of the second inverter, the output end of the second inverter is connected with the input end of the third inverter; the sizes of the first inverter, the second inverter and the third inverter are increased in turn.

[0073] The on-off keying modulation circuit 1 further includes a second differential comparator, the output end of the second differential comparator is connected with the input end of the NAND gate NAND2, the output end of the NAND gate NAND2 is connected with the input end of the fourth inverter, the output end of the fourth inverter is connected with the input end of the fifth inverter, the output end of the fifth inverter is connected with the input end of the sixth inverter; the sizes of the fourth inverter, the fifth inverter and the sixth inverter are increased in turn; the input ends of the NAND gate NAND1 and the NAND gate NAND2 are connected with the control voltage signal V IN .

[0074] In combination Figure 3 As shown, the third-order differential isolation transmission circuit 2 includes a capacitor C ISO1 , the upper plate of the capacitor C ISO1 is connected with the output end of the third inverter, the lower plate of the capacitor C ISO1 is connected with the upper plate of the capacitor C ISO2 , the lower plate of the capacitor C ISO2 is connected with one end of the resistor R 0, one end of the capacitor C 0, the other end of the resistor R 0 is grounded, the other end of the capacitor C 0 is connected with one end of the resistor R 1, one end of the capacitor C 1, the other end of the resistor R 1 is grounded, the other end of the capacitor C 1 is connected with one end of the resistor R 2.

[0075] The third-order differential isolation transmission circuit 2 includes a capacitor C ISO3 , the capacitor CISO3 upper plate is connected to the output of the inverter No. 6, and the lower plate of the capacitor C ISO3 upper plate is connected to the output of the inverter No. 6, and the lower plate of the capacitor C ISO4 upper plate is connected to the output of the inverter No. 6, and the lower plate of the capacitor C ISO4 lower plate is connected to the output of the inverter No. 6, and the upper plate of the capacitor R 3 one end, the capacitor C 2 one end is connected, and the resistor R 3 the other end is grounded, and the capacitor C 2 the other end is connected to the resistor R 4 one end, the capacitor C 3 one end is connected, and the resistor R 4 the other end is grounded, and the capacitor C 3 the other end is connected to the resistor R 5 one end is connected.

[0076] In conjunction with Figure 4 shown in FIG. 3, the selective amplifier circuit 3 includes a transistor M N3 , the source of the transistor M N3 is connected to the resistor R 2 far from the ungrounded one end, the capacitor C 1 far from the resistor R 2 one end, the resistor R 8 one end is connected, and the resistor R 8 the other end is grounded, and the gate of the transistor M N3 is connected to the gate of the transistor M N1 , and the drain of the transistor M N1 is connected to the source of the transistor M N3 , and the drain of the transistor M N2 is connected to the source of the transistor M N1 , and the gate of the transistor M N1 is connected to the drain of the transistor M N1 , and the gate of the transistor M N1 is connected to the drain of the transistor M bias1 one end is connected, and the other end of the bias current source I bias1 is connected to the power supply VDD, and the source of the transistor M N1 is connected to the source of the transistor M N5 , and the gate of the transistor M N2 is connected to the gate of the transistor M N4 , and the drain of the transistor M N2 is connected to the drain of the transistor M P1 , and the gate of the transistor M P0 , and the resistor R 7 one end is connected, and the resistor R 7 the other end is connected to the capacitor C 5 one end is connected, and the capacitor C5. The other end is connected to the power supply VDD; transistor M P1 The source of transistor M is connected to the power supply VDD. P1 gate and capacitor C 5. The resistor should be kept away from the VDD power supply terminal. R 7. Away from transistor M N2 One end is connected; transistor M P0 The source of transistor M is connected to the power supply VDD. P0 gate and capacitor C a One end is connected to the capacitor. C a The other end is connected to transistor M P3 The drain of the transistor M N7 The drain connection of transistor M P0 Drain and capacitor C b One end, transistor M N0 Drain and resistor R 6 is connected at one end; transistor M N0 gate and resistor R 6. Away from transistor M P0 One end, capacitor C 4. One end is connected to the capacitor. C 4. The other end is grounded, transistor M N0 The source electrode is grounded.

[0077] The frequency-selective amplifier circuit 3 also includes transistor M. N5 transistor M N5 source and resistor R 5. Keep away from the ungrounded end and capacitor. C 3. Keep away from resistors R 4. One end, resistor R 9 is connected at one end, resistor R 9 is grounded at the other end, transistor M N5 Gate and transistor M N6 Gate, transistor M N6 The drain connection of transistor M N5 The drain and transistor M N4 Source connection; transistor M N6 Gate and transistor M N6 The drain connection of transistor M N6 Gate, transistor M N6 The drain and bias current source I bias2 One end is connected to the bias current source I. bias2 The other end is connected to the power supply VDD, transistor M N6 The source and transistor M N3 Source connection; transistor M N4the drain of transistor M P2 the drain of transistor M P3 the gate of transistor M R 10 one end connected, resistor R 10 the other end connected to capacitor C 6 one end connected, capacitor C 6 the other end connected to power supply VDD; transistor M P2 the source of transistor M connected to power supply VDD, transistor M P2 the gate of transistor M connected to capacitor C 6 one end away from power supply VDD, resistor R 10 one end away from transistor M N4 connected; transistor M P3 the source of transistor M connected to power supply VDD, transistor M P3 the gate of transistor M connected to capacitor C b one end connected, capacitor C b the other end connected to transistor M P0 the drain of transistor M N0 connected, transistor M P3 the drain of transistor M connected to capacitor C a one end, transistor M N7 the drain of transistor M, resistor R 11 connected; transistor M N7 the gate of transistor M connected to resistor R 11 one end away from transistor M P3 one end, capacitor C 7 one end connected, capacitor C 7 the other end connected to ground, transistor M N7 the source of transistor M connected to ground. Transistor M P0 the source of transistor M, bias current source I bias1 one end connected to power supply VDD, capacitor C 5 one end connected to power supply VDD, transistor M P1 the source of transistor M, transistor M P2 the source of transistor M, capacitor C 6 one end connected to power supply VDD, bias current source I bias2 one end connected to power supply VDD, transistor M P3 connected; capacitor C 4 one end connected to ground, transistor M N0 the source of transistor M, resistor R 8 one end connected to ground, resistor R 9 one end connected to ground, transistor M N7 the source of transistor M, capacitor C7. Connect one end to the ground.

[0078] Combination Figure 5 As shown, demodulation circuit 4 includes a capacitor. C 8 and capacitor C 9. Capacitors C 8 One end is connected to the resistor R 11 Keep away from capacitors C 7. One end, transistor M N7 The drain of the transistor M P3 drain, capacitor C a far from transistor M P0 One end is connected to the capacitor. C 8. The other end is connected to the resistor. R 15 One end, transistor M N12 Gate connection; capacitor C 9 One end is connected to the resistor R 6. Keep away from capacitors C 4. One end, transistor M N0 The drain of the transistor M P0 drain, capacitor C b Away from transistor M P3 One end is connected to the capacitor. C 9. The other end is connected to the resistor. R 16 One end, transistor M N13 Gate connection; transistor M N12 The drain of the transistor M N13 The drain of the transistor M P10 The drain of the transistor M P10 Gate, transistor M P11 Gate connection, transistor M N12 The source and transistor M N10 The source of the transistor M N13 The source of the transistor M N11 Drain connection; resistor R 15 Keep away from capacitors C 8 One end, resistor R 16 Keep away from capacitors C 9-terminal transistor M P7 Drain and resistor R 14 One end connected, resistor R 14 The other end is grounded; transistor M P10 The drain of the transistor M P10 Gate connection, transistor M P10 The source of transistor M is connected to the power supply VDD.P11 The source of transistor M is connected to the power supply VDD. P11 The drain and transistor M N14 Drain connection; transistor M N10 The drain and transistor M P9 The drain of the transistor M P9 Gate, transistor M P8 Gate connection, transistor M N10 Gate and transistor M P6 Drain and resistor R 12 One end connected, resistor R 12 The other end is connected to the resistor R 13 One end connected, resistor R 13 The other end is grounded; transistor M P8 Gate, transistor M P9 Gate connection, transistor M P8 The source of the transistor M P9 The source of transistor M is connected to the power supply VDD. P8 The drain and transistor M N9 The drain of the transistor M N9 Gate connection; transistor M N14 The source is grounded, transistor M N14 Gate, transistor M N9 Gate, transistor M N9 The drain of the transistor M P8 The drain connection of transistor M N9 The source of the transistor is grounded; transistor M N11 Gate and control voltage signal V b1 Connection, transistor M N11 The source of the transistor is grounded; transistor M P7 The source of transistor M is connected to the power supply VDD. P7 Gate and transistor M P6 Gate, transistor M P5 Gate, transistor M P4 Gate and bias current source I bias3 One end is connected to the bias current source I. bias3 The other end is grounded; transistor M P6 The source of transistor M is connected to the power supply VDD. P6 Drain and resistor R 12 Keep away from resistors R 13 One end, transistor M N10 Gate connection; transistor MP5 The source of transistor M is connected to the power supply VDD. P5 The drain and transistor M N8 Gate, transistor M N8 Drain connection; transistor M P4 The source of transistor M is connected to the power supply VDD. P4 The drain of the transistor M P4 Gate and bias current source I bias3 The ungrounded end is connected; transistor M N8 The drain of the transistor M N8 Gate connection, transistor M N8 The source electrode is grounded.

[0079] transistor M P4 The source of the transistor M P5 The source of the transistor M P6 The source of the transistor M P7 The source of the transistor M P8 The source of the transistor M P9 The source of the transistor M P10 The source of the transistor M P11 Source connection; bias current source I bias3 Ground terminal, transistor M N8 source, resistor R 13 Grounding end, resistor R 14 Ground terminal, transistor M N9 The source of the transistor M N11 The source of the transistor M N14 The source connection.

[0080] In this invention, the on / off keying modulation circuit 1 is used to generate a carrier signal and output a differential signal with strong driving capability. V 1+ Sum and differential signals V 1- The third-order differential isolation transmission circuit 2 is used to eliminate the influence of common-mode noise current on the frequency-selective amplifier circuit 3, and output a carrier signal with high common-mode transient immunity. V 2+ and carrier signal V 2- The frequency selective amplifier circuit 3 is used to convert the carrier signal... V 2+ and carrier signal V 2- Amplify and then amplify the differential signal V 3+ Sum and differential signals V 3-to the demodulation circuit 4 for demodulation; the demodulation circuit 4 is used to demodulate the amplified differential signal V 3+ and the differential signal V 3- into a level signal, i.e. an output signal V O .

[0081] The on-off keying modulation circuit 1 comprises two differential comparators, NAND gates NAND1 and NAND2, and three inverters with increasing sizes. The on-off keying modulation circuit 1 mixes the input PWM signal with the high-frequency signal generated by the oscillator. When the input is high, the on-off keying modulation circuit 1 modulates it into a carrier signal with the same frequency as the oscillator and transmits it to the lower plate of the isolation capacitor on the transmitter side; when the input is low, no carrier signal is output from the transmitter. The differential comparator converts the oscillation signal into a high-level oscillation signal with the input power supply voltage of the transmitting end as the high level. When the input signal PWM is high, the NAND gates NAND1 and NAND2 normally transmit the full-swing signal output by the differential comparator; the output stage of the on-off keying modulation circuit 1 is composed of inverters with increasing sizes, thereby increasing the current capacity of the output differential signal under the condition of the shortest delay, and finally the on-off keying modulation circuit 1 outputs a differential signal with strong driving capability V 1+ and V 1- .

[0082] The capacitance in the third-order differential isolation transmission circuit 2 module C ISO1 , the capacitance C ISO2 , the capacitance C ISO3 , the capacitance C ISO4 The isolation capacitor has a very small capacitance value, only a few tens of fF, and the capacitance C 0, the capacitance C 1, the capacitance C 2, the capacitance C 3 is a low-voltage capacitor with a larger capacitance value, the resistance R 0, the resistance R 1, the resistance R 2, the resistance R 3, the resistance R 4, the resistance R 5 is a low-voltage resistance. VDD is the positive power supply, and GND represents the ground, i.e. the zero potential point. In actual applications, the third-order differential circuit can be equivalent to a first-order differential circuit. The on-off keying modulation circuit 1 outputs a differential signal with strong driving capability V 1+ and the differential signal V 1-are connected to the upper plate of the capacitor C ISO1 , respectively. The capacitor C ISO3 , capacitor C ISO1 , capacitor C ISO2 and capacitor C ISO3 , capacitor C ISO4 use the dynamic change of the electric field between the two plates of the isolation capacitor to transmit signals, use metal as the plate material of the capacitor, and use silicon dioxide as the dielectric insulation layer in the capacitor. The insulation capacitor generates a common-mode current proportional to the rate of change of the transient voltage when a transient electric stress occurs. The low-voltage capacitor and the low-voltage resistor are used to eliminate the influence of the common-mode current on the selective amplifier of the receiver of the subsequent driving circuit. When the common-mode current is generated, the current will generate a voltage drop on the resistor R 0 and resistor R 3. At the moment when the voltage changes, displacement currents will also be generated on capacitor C 0 and capacitor C 2. The currents generate voltage drops on resistor R 0, resistor R 1 in the upper branch and resistor R 3, resistor R 4 in the lower branch. At the same time, displacement currents are induced on capacitor C 1 in the upper branch to generate a voltage drop on resistor R 2, and displacement currents are induced on capacitor C 3 in the lower branch to generate a voltage drop on resistor R 5. Since the capacitances of capacitor C 0, capacitor C 1, capacitor C 2 and capacitor C 3 are very large relative to the isolation capacitor, and when the rising and falling edges of the input signal at the transmitting end are very steep and can be regarded as step signals, capacitor V 1+ 0 and capacitor V 1- 1, capacitor C 2 and capacitor C 3 can be regarded as short circuits at the rising and falling edges of the input square wave signal, i.e. the differential signal C 1+ and the differential signal C 1- . In order to reduce the influence of the common-mode current on the transmitter and improve the common-mode transient immunity of the transmitter, and to reduce the area, the size of the isolation capacitor is only a few tens of fF. This makes the isolation capacitor and resistor R 0, resistor R3 between the time constant is small, so the resistance R 0, resistance R 3 on the voltage will be stable in a very short time, stable capacitor C 0, capacitor C 2 will not generate displacement current, and similarly capacitor C 1, capacitor C 3 will not generate displacement current, ultimately resulting in the phase of the common-mode transient electric stress, resistance R 2, resistance R 5 generated voltage will be restored in a very short time. Capacitor C 0, capacitor C 2 and resistance R 1, resistance R 4 reduced Figure 3 in V 2+ point and V 2- point of the time constant, so that the two points can be faster recovery of voltage. The above can be understood as in the common-mode transient electric stress occurs, the common-mode noise current generated by the isolation capacitor is essentially only through resistance R 0 and resistance R 3, third-order differential isolation transmission circuit 2 eventually output high common-mode transient immunity of the carrier signal V 2+ and carrier signal V 2- .

[0083] Frequency selective amplifier circuit 3 includes a cascade of two-stage amplifier, for the carrier signal V 2+ and carrier signal V 2- amplification and transmission to the demodulation circuit 4 for demodulation, carrier signal V 2+ and carrier signal V 2- are connected to the source of transistor M N3 and transistor M N5 . VDD is the positive power supply, GND indicates the ground. Bias current source I bias1 and bias current source I bias2 through transistor M N1 and transistor M N6 to the resistance R8 and resistance R9 branch provides a constant current, to ensure that the transistor M N3 and transistor M N5 open. The first stage of two-stage amplifier using common-gate amplifier, transistor M N1 and transistor M N6 using diode connection through resistanceR 8 and resistor R 9 is transistor M N3 With transistor M N5 Provides the gate bias voltage. Resistor R 7. Capacitors C 5. Transistor M P1 and resistance R 10 ,capacitance C 6. Transistor M P2 These two stages form an active inductor structure, generating one zero and two poles for the circuit, achieving a peak gain near the carrier frequency. The second stage employs a common-source amplifier structure; to mitigate the Miller effect, capacitor neutralization and other techniques are used to cancel the Miller capacitance. C a The two ends are respectively connected to transistor M P0 Gate and transistor M P3 drain, capacitor C b The two ends are respectively connected to transistor M P3 Gate and transistor M P0 The drain of the first stage is used to neutralize the capacitance. The second stage load uses the same method as the first stage, with resistors, capacitors, and transistors forming an active inductor to achieve peak amplification in the second stage. The two stages are cascaded together to achieve a large amplification capability, and finally output the amplified carrier signal. V 3+ and carrier signal V 3- .

[0084] Demodulation circuit 4 includes a current comparator that converts transistor M... N12 and transistor M N13 The current and transistor M N9 The current is compared with that of the current mirror, replicated by the current mirror, and finally passed through transistor M. N14 With transistor M P11 The output signal is determined by the magnitude of the current capability. V O The state is used to amplify the carrier signal. V 3+ and carrier signal V 3- Restore to a level signal. VDD is the positive power supply, GND indicates ground, and the bias current source I... bias3 Through current mirror transistor M P4 To subsequent transistor M P5 Transistor M P6 and transistor M P7 The branch provides a constant current and ensures its continuity. Carrier signal. V 3+and carrier signal V 3- respectively connected capacitor C 10 , capacitor C 11 upper plate. Wherein, transistor M P6 and resistance R 12 , resistance R 13 provide bias for the gate of transistor M N10 as threshold voltage V TH , transistor M P7 and resistance R 14 provide static bias voltage for transistor M N12 and transistor M N13 V CM , resistance R 15 and capacitor C 10 and resistance R 16 and capacitor C 9 respectively constitute two high-pass filters, filter out the direct current voltage of the output differential signal of the frequency selective amplifier. V b1 bias voltage, provide stable gate voltage for M N11 , make it work in saturation region as current source. In circuit design, ensure that the threshold voltage of MOS tube V TH is greater than the common mode voltage V CM , while the width-length ratio of transistor M N10 is twice the width-length ratio of transistor M N12 , the width-length ratio of transistor M N12 and transistor M N13 is equal, so that the current of the tail current source transistor M N11 flows through transistor M N10 basically under static conditions, that is, without carrier signal, while transistors M N12 and M N13 almost work in the cutoff region, at this time, through current mirror copying, transistor M N14 is on, transistor M P11 is off, so that the output signal V O is low under static. When the receiver receives the differential carrier signal, the frequency selective amplifier amplifies the signal to differential signal V 3+ and differential signal V ​3- , the amplified amplitude is much larger than the threshold voltage V TH , the transistor M N12 and the transistor M N13 are alternately turned on, the tail current source transistor M N11 flows only between the transistor M N12 and the transistor M N13 , and the transistor M N10 has substantially no current flowing therethrough, and the transistor M P11 is turned on, and the transistor M N14 is turned off, so that the output signal V O is pulled to a high level, that is, when the input PWM signal is high, the transmitter transmits a carrier signal, and the receiver amplifies and demodulates the carrier signal to restore a high level signal.

[0085] The application analyzes the time and form of common-mode transient electric stress, and proposes a SiC MOSFET capacitor isolation type driving circuit for improving the chip common-mode transient immunity, which couples and filters the common-mode noise current through an isolation capacitor and a third-order RC differential circuit, eliminates the influence of the common-mode noise current on the receiver frequency selective amplifier, effectively improves the system CMTI performance, and increases the reliability of the system. The isolation type driving circuit in the application has high anti-transient electric stress capability, which ensures that the driving chip can work normally and meet the requirements when the transient electric stress exceeds the common-mode transient immunity of the chip during the switching process of the power device.

Claims

1. A capacitor isolation type driving circuit based on SiC MOSFET, characterized by, The on-off keying modulation circuit (1) is connected with the input end of the third-order differential isolation transmission circuit (2), the output end of the third-order differential isolation transmission circuit (2) is connected with the input end of the frequency selective amplifier circuit (3), and the output end of the frequency selective amplifier circuit (3) is connected with the input end of the demodulation circuit (4). The on-off keying modulation circuit (1) comprises a first differential comparator, the output end of the first differential comparator is connected with the input end of an AND gate NAND1, the output end of the AND gate NAND1 is connected with the input end of a first inverter, the output end of the first inverter is connected with the input end of a second inverter, the output end of the second inverter is connected with the input end of a third inverter, and the output end of the third inverter is connected with the input end of a fourth inverter; the sizes of the first inverter, the second inverter and the third inverter are sequentially increased. The on-off keying modulation circuit (1) further comprises a second differential comparator, the output end of the second differential comparator is connected with the input end of an AND gate NAND2, the output end of the AND gate NAND2 is connected with the input end of a fourth inverter, the output end of the fourth inverter is connected with the input end of a fifth inverter, the output end of the fifth inverter is connected with the input end of a sixth inverter, and the output end of the sixth inverter is connected with the input end of a seventh inverter; the sizes of the fourth inverter, the fifth inverter and the sixth inverter are sequentially increased. The input terminals of the NAND gate NAND1 and the NAND gate NAND2 are connected with a control voltage signal V IN ; The third-order differential isolation transmission circuit (2) comprises a capacitor C ISO1 The upper plate of the capacitor C ISO1 is connected with the output end of the third inverter, the lower plate of the capacitor C ISO1 is connected with the upper plate of the capacitor C ISO2 , the lower plate of the capacitor C ISO2 is connected with the one end of the resistor R 0, the one end of the capacitor C 0, the other end of the resistor R 0 is grounded, the other end of the capacitor C 0 is connected with the one end of the resistor R 1, the one end of the capacitor C 1, the other end of the resistor R 1 is grounded, the other end of the capacitor C 1 is connected with the one end of the resistor R 2, the other end of the resistor R 2 is grounded, and the common end of the capacitor C 1 and the resistor R 2 is used as an output end. The third-order differential isolation transmission circuit (2) comprises a capacitor C ISO3 The upper plate of the capacitor C ISO3 is connected with the output end of the sixth inverter, the lower plate of the capacitor C ISO3 is connected with the upper plate of the capacitor C ISO4 , the lower plate of the capacitor C ISO4 is connected with one end of the resistor R 3 and one end of the capacitor C 2, the other end of the resistor R 3 is grounded, the other end of the capacitor C 2 is connected with one end of the resistor R 4 and one end of the capacitor C 3, the other end of the resistor R 4 is grounded, the other end of the capacitor C 3 is connected with one end of the resistor R 5, the other end of the resistor R 5 is grounded, and the common end of the capacitor C 3 and the resistor R 5 is taken as an output end.

2. The SiC MOSFET-based capacitive isolation type driving circuit according to claim 1, characterized by, The frequency selective amplifier circuit (3) comprises a transistor M N3 , a source of the transistor M N3 is connected with a resistor R 2 far from the ground end, a capacitor C 1 far from the resistor R1 end, a resistor R 8 one end, the other end of the resistor R 8 is grounded, a gate of the transistor M N3 is connected with a gate of the transistor M N1 , a drain of the transistor M N1 , a drain of the transistor M N3 is connected with a source of the transistor M N2 . The gate of the transistor M N1 is connected to the drain of the transistor M N1 , the gate of the transistor M N1 , the drain of the transistor M N1 is connected to one end of a bias current source I bias1 , the other end of the bias current source I bias1 is connected to a power supply VDD, and the source of the transistor M N1 is connected to the source of the transistor M N5 . The gate of the transistor M N2 is connected to the gate of the transistor M N4 , the drain of the transistor M N2 is connected to the drain of the transistor M P1 , the gate of the transistor M P0 , one end of the resistor R 7 is connected, the other end of the resistor R 7 is connected to one end of the capacitor C 5, the other end of the capacitor C 5 is connected to the power supply VDD. The source of the transistor M P1 is connected to the power supply VDD, and the gate of the transistor M P1 is connected to the capacitor C 5 far from the power supply VDD, the resistor R 7 is connected far from the transistor M N2 one end. The source of the transistor M P0 is connected to the power supply VDD, the gate of the transistor M P0 is connected to the one end of the capacitor C a , the other end of the capacitor C a is connected to the drain of the transistor M P3 , the drain of the transistor M N7 , and the drain of the transistor M P0 is connected to the one end of the capacitor C b , the other end of the capacitor R 6, the drain of the transistor M N0 , and the one end of the resistor The transistor M N0 gate and resistor R 6. Away from transistor M P0 One end, capacitor C 4 One end is connected, the capacitor C 4. The other end is grounded, and the transistor M N0 The source is grounded; The frequency-selective amplifier circuit (3) also includes transistor M. N5 The transistor M N5 source and resistor R 5. Keep away from the grounding end and capacitor C 3. Keep away from resistors R 4. One end, resistor R 9 is connected at one end, the resistor R 9 is grounded at the other end, and the transistor M N5 Gate and transistor M N6 Gate, transistor M N6 The drain connection of the transistor M N5 The drain and transistor M N4 The source connection; The gate of the transistor M N6 is connected to the drain of the transistor M N6 , the gate of the transistor M N6 , the drain of the transistor M N6 is connected to one end of a bias current source I bias2 , the other end of the bias current source I bias2 is connected to a power supply VDD, and the source of the transistor M N6 is connected to the source of the transistor M N3 . the drain of the transistor M N4 the drain of the transistor M P2 the gate of the transistor M P3 the resistor R 10 one end of the resistor R 10 the other end of the capacitor C 6 one end of the capacitor C 6 the other end of the capacitor is connected to the power supply VDD The source of the transistor M P2 is connected to the power supply VDD, and the gate of the transistor M P2 is connected to the capacitor C 6 far from the power supply VDD, the resistor R 10 far from the transistor M N4 is connected to one end. The source of the transistor M P3 is connected to a power supply VDD, the gate of the transistor M P3 is connected to a capacitor C b at one end, the other end of the capacitor C b is connected to the drain of the transistor M P0 , the drain of the transistor M N0 , and the drain of the transistor M P3 is connected to a capacitor C a at one end, the drain of the transistor M N7 , and a resistor R 11 at one end. gate of the transistor M N7 resistor R R 11 connected to one end of the transistor M P3 capacitor C C 7 connected to one end of the capacitor C C 7 connected to the other end of the capacitor C N7 source of the transistor M 3. The SiC MOSFET-based capacitive isolation type driving circuit according to claim 2, characterized by, source of the transistor M P0 bias current source I bias1 one end connected to the power source VDD, capacitor C 5 one end connected to the power source VDD, transistor M P1 source of the transistor M P2 source of the transistor M C 6 one end connected to the power source VDD, bias current source I bias2 source of the transistor M P3 source of the transistor M the capacitor C 4 ground one end, transistor M N0 source of the transistor, resistance R 8 ground one end, resistance R 9 ground one end, transistor M N7 source of the transistor, capacitor C 7 ground one end 4. The SiC MOSFET-based capacitive isolation type driving circuit according to claim 3, characterized by The demodulation circuit (4) comprises a capacitor C 8 and a capacitor C 9, one end of the capacitor C 8 being connected to a resistor R 11 remote from one end of the capacitor C 7, the drain of transistor M N7 , the drain of transistor M P3 , a capacitor C a remote from one end of transistor M P0 is connected, the other end of the capacitor C 8 being connected to a resistor R 15 remote from one end of transistor M N12 , the gate of transistor M the capacitor C 9 one end of the resistor R 6 the other end of the capacitor C 4 one end of the transistor M N0 the drain of the transistor M P0 the drain of the transistor M C b the other end of the capacitor P3 one end of the transistor M C 9 the other end of the resistor R 16 one end of the transistor M N13 the gate of the transistor M the drain of the transistor M N12 the drain of the transistor M N13 the drain of the transistor M P10 the drain of the transistor M P10 the gate of the transistor M P11 the gate of the transistor M N12 the source of the transistor M N10 the source of the transistor M N13 the source of the transistor M N11 the drain of the transistor M the resistance R 15 the drain of the transistor C 8 the end, the resistance R 16 the drain of the transistor C 9 the end, the transistor M P7 the drain of the transistor R 14 the end, the resistance R 14 the other end is grounded a drain of the transistor M P10 a gate of the transistor M P10 a source of the transistor M P10 a source of the transistor M P11 a source of the transistor M P11 a drain of the transistor M N14 a drain of the transistor M V O ; The drain of the transistor M N10 The drain of the transistor M P9 The gate of the transistor M P9 The gate of the transistor M P8 The gate of the transistor M N10 The drain of the transistor M P6 One end of the resistance R 12 The other end of the resistance R 12 One end of the resistance R 13 The other end of the resistance R 13 Grounded the gate of the transistor M P8 the gate of the transistor M P9 is connected, the source of the transistor M P8 is connected, the source of the transistor M P9 is connected to the power supply VDD, the drain of the transistor M P8 is connected to the drain of the transistor M N9 is connected, the gate of the transistor M N9 is connected. the source of the transistor M N14 the gate of the transistor M N14 the gate of the transistor M N9 the drain of the transistor M N9 the drain of the transistor M P8 the source of the transistor M N9 is grounded. the gate of the transistor M N11 with a control voltage signal V b1 connected, the source of the transistor M N11 is grounded; The transistor M P7 The source of transistor M is connected to the power supply VDD. P7 Gate and transistor M P6 Gate, transistor M P5 Gate, transistor M P4 Gate and bias current source I bias3 One end is connected, the bias current source I bias3 The other end is grounded; The source of the transistor M P6 is connected to the power supply VDD, and the drain of the transistor M P6 is connected to the resistor R 12 The other end of the resistor R 13 is connected to one end of the gate of the transistor M N10 . The transistor M P5 The source of transistor M is connected to the power supply VDD. P5 The drain and transistor M N8 Gate, transistor M N8 Drain connection; The source of the transistor M P4 is connected to the power supply VDD, the drain of the transistor M P4 , the gate of the transistor M P4 , the ungrounded end of the bias current source I bias3 is connected; The drain of the transistor M N8 is connected to the gate of the transistor M N8 , and the source of the transistor M N8 is grounded.

5. The SiC MOSFET-based capacitive isolation type driving circuit according to claim 4, characterized by, source of the transistor M P4 source of the transistor M P5 source of the transistor M P6 source of the transistor M P7 source of the transistor M P8 source of the transistor M P9 source of the transistor M P10 source of the transistor M P11 source of the transistor M The bias current source I bias3 The ground terminal of the transistor M N8 The source of the transistor M R 13 The ground terminal of the resistor R 14 The ground terminal of the transistor M N9 The source of the transistor M N11 The source of the transistor M N14 The source of the transistor M

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