A decision feedback equalizer and single-ended receiving device

Abstract

The application discloses a decision feedback equalizer and a single-ended receiving device, and relates to the technical field of integrated circuits, which comprises an adjustable inverter array formed by a plurality of tri-state gates, can realize a transconductance unit that can be adjusted, and thus can be used as a transconductance unit of a main path and a feedback path of a DFE adder; a load array formed by a plurality of tri-state gates that are short-circuited at input and output, can realize an adjustable load impedance; based on the two parts, in combination with inverters, a real single-ended DFE can be realized, and there are no DACs and passive devices, so that power consumption and area are significantly reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a decision feedback equalizer and a single-ended receiving device. BACKGROUND

[0002] In a high-speed SerDes receiver, the equalizer mainly includes a continuous-time linear equalizer (CTLE) and a decision feedback equalizer (DFE). The CTLE has obvious defects. It needs a large-capacity capacitor array and a peaking bandwidth to expand the bandwidth, resulting in a large area, which is difficult to meet the small area requirement of a compact receiver. Moreover, the CTLE operates on the signal in the analog domain, which synchronously amplifies the noise of the input signal, limits the equalization compensation effect, and needs additional noise processing, further increasing the area. In contrast, the DFE has more application potential. It uses the digital signal output by the comparator to directly feedback to the output superposition, only needs an adder, and does not need a capacitor array and an inductor, which can save area. At the same time, the digital domain comparator included in the DFE can shield the analog noise of the input signal, and does not need additional noise processing, which is more suitable for the requirements of a compact receiver.

[0003] However, the traditional DFE circuit structure has many problems. First, the adder adopts a differential structure based on current mode logic, which will cause power consumption and area waste when used in a single-ended SerDes receiver. Second, in order to realize the digital domain adjustable equalization coefficient h of the DFE, so as to control the equalization strength by the system upper protocol controller and leave an interface for adaptive control, an additional voltage domain digital-to-analog converter (DAC) or current domain DAC is needed, which undoubtedly increases the area. Third, the load is usually implemented by a resistor, which is not conducive to compressing the area of the receiver, and in order to ensure sufficient bandwidth and swing, a small load resistor combined with a large current needs to be used, resulting in high power consumption and being not conducive to multi-channel integration. SUMMARY

[0004] The present application provides a decision feedback equalizer and a single-ended receiving device to at least solve the problem of large area caused by the voltage domain DAC or current domain DAC needed to adjust the equalization coefficient h of the DFE in the digital domain in the related art.

[0005] The application provides a decision feedback equalizer, comprising: a main inverter array, a load array, a feedback inverter array and a comparison circuit, wherein the first end of the main inverter array is connected to a data signal, the second end of the main inverter array is connected to the first end of the load array, the third end of the main inverter array is connected to a first power supply voltage, the fourth end of the main inverter array is grounded, and the control end of the main inverter array is connected to a first control signal; the second end of the load array is connected to the first end of the comparison circuit, the third end of the load array is connected to a second power supply voltage, the fourth end of the load array is grounded, and the control end of the load array is connected to a load control word; the second end of the comparison circuit outputs the data signal, the third end of the comparison circuit is connected to the first end of the feedback inverter array; the second end of the feedback inverter array is connected to the second end of the main inverter array, the third end of the feedback inverter array is connected to a third power supply voltage, the fourth end of the feedback inverter array is grounded, and the control end of the feedback inverter array is connected to an equalization coefficient control word.

[0006] The application provides a single-ended receiving device, comprising: an isolation circuit, a self-biased receiver front-end circuit, a serial-parallel converter and the above decision feedback equalizer, wherein the first end of the isolation circuit is connected to a data signal, and the second end of the isolation circuit is connected to the first end of the self-biased receiver front-end circuit; the second end of the self-biased receiver front-end circuit is connected to the first end of the main inverter array; the first end of the main inverter array is connected to the data signal, the second end of the main inverter array is connected to the first end of the load array, the third end of the main inverter array is connected to a first power supply voltage, the fourth end of the main inverter array is grounded, and the control end of the main inverter array is connected to a first control signal; the second end of the load array is connected to the first end of the comparison circuit, the third end of the load array is connected to a second power supply voltage, the fourth end of the load array is grounded, and the control end of the load array is connected to a load control word; the second end of the comparison circuit is connected to the first end of the serial-parallel converter, and the third end of the comparison circuit is connected to the first end of the feedback inverter array; the second end of the feedback inverter array is connected to the second end of the main inverter array, the third end of the feedback inverter array is connected to a third power supply voltage, the fourth end of the feedback inverter array is grounded, and the control end of the feedback inverter array is connected to an equalization coefficient control word; and the second end of the serial-parallel converter outputs the data signal.

[0007] By using the adjustable inverter array composed of multiple tri-state gates, the adjustable transconductance unit can be realized, so as to be used as the transconductance unit of the DFE adder main path and feedback path; by using the load array composed of multiple input and output shorted tri-state gates, the adjustable load impedance can be realized; based on the above two parts, in combination with the inverter, the real single-ended DFE can be realized, and there is no DAC and passive device, so that the power consumption and area are significantly reduced. BRIEF DESCRIPTION OF DRAWINGS

[0008] In order to more clearly illustrate the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0009] Fig. 1(a) is a block diagram of a single-ended SerDes receiver with CTLE in the related art;

[0010] Fig. 1(b) is a block diagram of a single-ended SerDes receiver with DFE in the related art;

[0011] Fig. 2(a) is a circuit diagram of a DFE including a voltage-type DAC in the related art;

[0012] Fig. 2(b) is a circuit diagram of a DFE including a current-type DAC in the related art;

[0013] Figure 3 A decision feedback equalizer block diagram provided for the embodiments of the present application;

[0014] Figure 4 A circuit diagram of a main inverter unit, a load unit, and a feedback inverter unit provided for the embodiments of the present application;

[0015] Figure 5 A circuit diagram of a comparison circuit provided for the embodiments of the present application;

[0016] Figure 6 A block diagram of a single-ended receiving device provided for the embodiments of the present application;

[0017] Figure 7 Circuit diagrams of an isolation circuit, a gain circuit, and a gain compensation circuit provided for the embodiments of the present application. DETAILED DESCRIPTION

[0018] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0019] It should be noted that in the description of the present application, the terms "comprising", "containing" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or apparatus that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or inherent to such a process, method, article or apparatus. The terms "first", "second" and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0020] In order for those skilled in the art to better understand the present application, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0021] Compact single-ended SerDes receivers have wide application requirements in high-density inter-chip interconnection (D2D) interconnection interfaces, Chiplet integration, etc. At the same time, such SerDes receivers need an equalization circuit module to meet the channel attenuation compensation requirements of different channel lengths in different application scenarios, so as to open the eye diagram of the received data signal as much as possible to achieve low bit error rate data reception. In high-speed SerDes receivers, the equalizer includes a continuous-time linear equalizer (CTLE) and a decision feedback equalizer (DFE). As shown in FIG. 1(a) and FIG. 1(b), the continuous-time linear equalizer needs a large range of adjustable capacitor array and a peaking bandwidth to expand the bandwidth, so there is a problem of large area, which is difficult to meet the small area requirement of compact SerDes receivers; at the same time, the CTLE completely operates on the signal in the linear analog domain, and compensates the channel by enhancing and amplifying the high-frequency components, which will amplify the noise of the input data signal at the same time, on the one hand, limiting the effect of equalization compensation, on the other hand, additional processing is needed to reduce the influence of noise, which will also increase the area. The DFE is a digital signal output by the comparator that is directly fed back to the output end for superposition, only a summer is needed, and the summer does not need a capacitor array and an inductor, so compared with the CTLE, it can save a lot of area; at the same time, the decision feedback equalizer includes a digital domain comparator, which can shield the analog voltage / current noise of the input signal, that is, no additional processing of noise is needed, so it has good potential for application in compact SerDes receivers.

[0022] Figures 2(a) and 2(b) show the traditional DFE circuit structure, which has the following main problems: 1) The adder uses a differential structure based on current-mode logic, which results in wasted power consumption and area when used in scenarios such as single-ended SerDes receivers; 2) In order to enable the upper-layer protocol controller of the system to digitally control the equalization coefficient h of the DFE, thereby leaving an interface for adaptive control of the equalization strength, an additional voltage-domain digital-to-analog converter (DAC) is required to convert the digital control code into analog voltage, and then use the differential pair of the feedback branch to convert the feedback current, or use a current-domain DAC to adjust the current of the feedback branch to achieve the above-mentioned digital domain adjustable function of the DFE coefficient h, which will also increase the area.

[0023] The common practice of using resistors to implement loads is not only detrimental to the reduction of the SerDes receiver area, but also requires the use of small load resistors combined with large current to ensure sufficient bandwidth and swing, resulting in high power consumption of single-ended SerDes receivers and hindering multi-channel integration.

[0024] Furthermore, traditional single-ended SerDes receivers often use DC coupling to input data signals, requiring strict definition of the output common-mode level, power supply voltage, and swing of the single-ended SerDes transmitter. This results in poor adaptability and makes it difficult to meet the needs of different applications (different power supply voltages, different swings, different common-mode levels, etc.).

[0025] Based on this, embodiments of this application provide a decision feedback equalizer, such as... Figure 3 As shown, it includes: main inverter array 1, load array 2, feedback inverter array 3 and comparator circuit 4.

[0026] like Figure 3 As shown, the first terminal of the main inverter array 1 is connected to a data signal, the second terminal of the main inverter array 1 is connected to the first terminal of the load array 2, the third terminal of the main inverter array 1 is connected to the first supply voltage VCC1, the fourth terminal of the main inverter array 1 is grounded, and the control terminal of the main inverter array 1 is connected to the first control signal; the second terminal of the load array 2 is connected to the first terminal of the comparator circuit 4, the third terminal of the load array 2 is connected to the second supply voltage VCC2, the fourth terminal of the load array 2 is grounded, and the control terminal of the load array 2 is connected to the load control word r; the second terminal of the comparator circuit 4 outputs a data signal, the third terminal of the comparator circuit 4 is connected to the first terminal of the feedback inverter array 3; the second terminal of the feedback inverter array 3 is connected to the second terminal of the main inverter array 1, the third terminal of the feedback inverter array 3 is connected to the third supply voltage, the fourth terminal of the feedback inverter array 3 is grounded, and the control terminal of the feedback inverter array 3 is connected to the equalization coefficient control word h.

[0027] Specifically, the main inverter array 1 is connected to the data signal input end of the equalizer, the first end of the main inverter array 1 is directly connected to the data signal to be processed, and the main inverter array 1 is responsible for the preliminary signal processing and transmission of the input data signal; the second end of the main inverter array 1 is connected to the first end of the load array 2, forming a key path of signal transmission, and the processed signal is transmitted to the load array 2; the third end of the main inverter array 1 is connected to the first power supply voltage VCC1 to provide energy support for the operation of the main inverter array 1, and the third end of the main inverter array 1 is grounded to build a stable circuit loop; in addition, the control end of the main inverter array 1 is connected to the first control signal, and the working state of the main inverter array 1 can be adjusted through the first control signal to adapt to different signal processing requirements.

[0028] Specifically, the load array 2 plays a role of signal bearing and impedance matching in the circuit, the second end of the load array 2 is connected to the first end of the comparison circuit 4, and the signal adjusted by the load array 2 is transmitted to the comparison circuit 4 for subsequent processing; the third end of the load array 2 is connected to the second power supply voltage VCC2 to ensure the normal power supply of the circuit of the load array 2, and the fourth end of the load array 2 is grounded to form a complete power supply loop; the control end of the load array 2 is connected to the load control word r, and the impedance characteristics of the load array 2 can be flexibly adjusted through the load control word r, so as to optimize the signal transmission quality and ensure that the signal is reduced in attenuation and distortion in the transmission process.

[0029] Specifically, the comparison circuit 4 is a core module for realizing signal decision, and the second end of the comparison circuit 4 outputs a data signal, which is the final result after equalization processing and can be directly used for subsequent data interaction or processing; the third end of the comparison circuit 4 is connected to the first end of the feedback inverter array 3 to realize a feedback closed loop of the signal, and the decision reference of the comparison circuit 4 is dynamically adjusted by receiving the signal transmitted by the feedback inverter array 3, so as to improve the accuracy of the decision.

[0030] Specifically, the feedback inverter array 3 plays a role of feedback regulation in the circuit, the second end of the feedback inverter array 3 is connected to the second end of the main inverter array 1, and the feedback signal is transmitted to the main inverter array 1 to participate in the processing of the input data signal by the main inverter array 1; the third end of the feedback inverter array 3 is connected to the third power supply voltage to provide power for the operation of the feedback inverter array 3, and the fourth end of the feedback inverter array 3 is grounded to ensure the stable operation of the circuit; the control end of the feedback inverter array 3 is connected to the equalization coefficient control word h, and the feedback strength and phase characteristics can be accurately adjusted through the equalization coefficient control word h, so as to realize fine control of the equalization effect of the entire equalizer to meet the specific requirements of signal equalization in different scenarios.

[0031] In some optional embodiments, the main inverter array 1 comprises: a plurality of main inverter units, wherein the first end of each main inverter unit is connected to the data signal, the second end of the main inverter unit is connected to the first end of the load array 2 and the second end of the feedback inverter array 3, the third end of the main inverter unit is connected to the first power supply voltage VCC1, the fourth end of the main inverter unit is grounded, and the control end of the main inverter unit is connected to the first control signal.

[0032] Specifically, the main inverter array 1 is not a single circuit unit, but an array structure composed of multiple main inverter units. The design of multiple units working together can enhance the processing capacity and stability of the circuit for input data signals.

[0033] Each main inverter unit follows uniform specifications in circuit connection to ensure the coordination of the overall array function. Specifically, the first end of each main inverter unit is connected to the data signal, which means that the input data signal to be processed is transmitted to all main inverter units in the array at the same time, so that each unit can participate in the preliminary processing of the data signal. Through parallel processing of multiple units, the efficiency and reliability of signal processing can be effectively improved.

[0034] The second end of the main inverter unit has an important connection relationship, which is connected to the first end of the load array 2 and the second end of the feedback inverter array 3. This connection mode enables the processed signal of the main inverter unit to be transmitted to the load array 2, providing input signals for subsequent load adjustment links; at the same time, it can also form signal interaction with the feedback inverter array 3, receiving feedback signals from the feedback inverter array 3, so as to adjust its processing state according to the feedback information, ensuring the quality of the output signal.

[0035] In terms of power supply and grounding, the third end of each main inverter unit is connected to the first power supply voltage VCC1, providing necessary power support for the normal operation of the unit, ensuring that it has enough energy to complete signal processing work; at the same time, the third end of the main inverter unit is also grounded, building a stable circuit loop, so that the current can flow along the designated path, avoiding abnormal current interference in the circuit, and ensuring the stability of the unit work. In addition, the control end of each main inverter unit is connected to the first control signal. As a control instruction, the first control signal can simultaneously act on all main inverter units in the array. By changing the parameters of the control signal, the working mode, response speed and other characteristics of each unit can be uniformly adjusted, so that the entire main inverter array 1 can flexibly adjust the overall operating state according to different working scenarios and signal processing requirements, and then realize accurate processing of the input data signal, providing high-quality signal input for subsequent circuit links.

[0036] In some optional embodiments, such as Figure 4As shown, the main inverter unit includes: a first PMOS tube P1, a second PMOS tube P2, a first NMOS tube N1 and a second NMOS tube N2, wherein the source of the first PMOS tube P1 is connected to the first power supply voltage VCC1, the drain of the first PMOS tube P1 is connected to the source of the second PMOS tube P2, and the gate of the first PMOS tube P1 is grounded; the drain of the second PMOS tube P2 is connected to the drain of the first NMOS tube N1, the first end of the load array 2 and the second end of the feedback inverter array 3, and the gate of the second PMOS tube P2 is connected to the gate of the first NMOS tube N1; the source of the first NMOS tube N1 is connected to the drain of the second NMOS tube N2, and the gate of the first NMOS tube N1 is connected to the data signal; the source of the second NMOS tube N2 is grounded, and the gate of the second NMOS tube N2 is connected to the first control signal.

[0037] Specifically, the first PMOS tube P1 is the starting link of the power supply path, and its source is directly connected to the first power supply voltage VCC1 to provide stable voltage input for the entire main inverter unit; the drain is connected to the source of the second PMOS tube P2 to form a cascade structure, ensuring that the voltage can be sequentially transmitted to the subsequent transistor; and the gate is grounded, which makes the first PMOS tube P1 always in the on state to provide continuous voltage supply for the second PMOS tube P2, ensuring the stability of the basic power supply of the circuit.

[0038] The second PMOS tube P2 plays a dual role of signal transmission and logic control in the circuit, and its drain is connected to the drain of the first NMOS tube N1, the first end of the load array 2 and the second end of the feedback inverter array 3, becoming a key node for signal interaction between the main inverter unit and external circuits, which not only outputs the signals processed initially, but also receives adjustment signals from the feedback path; the gate is connected to the gate of the first NMOS tube N1, forming a common gate structure, which can respond to changes in the input data signal synchronously, ensuring the coordination of signal processing.

[0039] The first NMOS tube N1 is the core element for receiving and processing input data signals, and its source is connected to the drain of the second NMOS tube N2 to build a cascade path of NMOS tubes; the gate is specially connected to the data signal, which makes the high and low level changes of the data signal directly control the on and off states of the first NMOS tube N1, and further controls the signal transmission path of the entire unit; and the drain and the drain of the second PMOS tube P2 jointly form an output node to transmit the processed signals to the load array 2 and the feedback inverter array 3.

[0040] The second NMOS transistor N2 is a ground path control switch of the whole main inverter unit, the source thereof is directly connected to the ground to provide a stable ground reference for the circuit, the drain thereof is connected to the source of the first NMOS transistor N1 to form a current conduction path between the NMOS transistors, and the gate thereof is connected to the first control signal, and the conduction degree of the second NMOS transistor N2 can be controlled by the level change of the signal, so as to adjust the current size of the whole NMOS path and realize dynamic regulation of the working state of the main inverter unit to adapt to different data signal processing requirements.

[0041] Through the cooperative work of the four transistors, the main inverter unit can perform inversion processing on the input data signal under the regulation of the first control signal, accurately transmit the processed signal to the load array 2 and the feedback inverter array 3, and constantly optimize the signal output quality by interacting with the feedback path, thereby laying a foundation for the efficient operation of the whole decision feedback equalizer.

[0042] In some optional embodiments, the load array 2 comprises a plurality of load units, wherein the first end of the load unit is connected to the second end of the main inverter array 1, the second end of the load unit is connected to the first end of the comparison circuit 4, the third end of the load unit is connected to the second power supply voltage VCC2, the fourth end of the load unit is connected to the ground, and the control end of the load unit is connected to the load control word r.

[0043] Specifically, the load array 2 adopts a multi-unit cooperative architecture design and is composed of a plurality of load units. This structure can flexibly cope with signal load requirements in different scenarios and realize accurate regulation of signal transmission characteristics through cooperation between units.

[0044] Each load unit presents clear regularity and functionality in circuit connection. The first end of the load unit is connected to the second end of the main inverter array 1, and this connection point becomes the "entrance" of the output signal of the main inverter array 1 into the load array 2. The signal processed by the main inverter array 1 is transmitted to the load unit through this port, and the load unit then adjusts the signal load characteristics.

[0045] The second end of the load unit is connected to the first end of the comparison circuit 4, and the signal adjusted by the load unit is output from this port and flows to the comparison circuit 4 to provide an optimized input signal for the signal decision of the comparison circuit 4, thereby ensuring that the comparison circuit 4 can make accurate decisions based on stable and reliable signals.

[0046] In terms of power supply and grounding, the third end of the load unit is connected to the second power supply voltage VCC2 to provide energy support for the normal operation of the load unit, ensuring that it has sufficient driving force to complete the load adjustment of the signal; the fourth end is grounded to form a stable circuit loop, allowing current to flow along the intended path and avoiding abnormal interference in the circuit to ensure the stability of the load unit operation.

[0047] Particularly crucial is that the control end of the load unit is connected to the load control word r. The load control word r is a set of digital signals used to regulate the characteristics of the load unit. By changing the value of the load control word r, the impedance size and equivalent capacitance of the load unit can be accurately adjusted. When facing input signals of different frequencies and amplitudes, the load control word r can be adjusted to make the load unit exhibit adaptive load characteristics, thereby reducing signal reflection, attenuation, and other problems during transmission and optimizing signal integrity. Under the unified regulation of the load control word r, multiple load units can achieve coordinated changes in overall load characteristics, further improving the signal adjustment capability of the load array 2 and meeting the diversified needs of the decision feedback equalizer for signal load in different working states.

[0048] In some optional embodiments, as shown in Figure 4 The load unit includes a third PMOS tube P3, a fourth PMOS tube P4, a third NMOS tube N3, a fourth NMOS tube N4, and a first inverter U1. The source of the third PMOS tube P3 is connected to the second power supply voltage VCC2, the drain of the third PMOS tube P3 is connected to the source of the fourth PMOS tube P4, and the gate of the third PMOS tube P3 is connected to the output of the first inverter U1. The drain of the fourth PMOS tube P4 is connected to its gate, the drain of the third NMOS tube N3, the gate of the third NMOS tube N3, the second end of the main inverter array 1, and the first end of the comparison circuit 4. The drain of the fourth NMOS tube N4 is connected to the source of the third NMOS tube N3, the source of the fourth NMOS tube N4 is grounded, the gate of the fourth NMOS tube N4 is connected to the input of the first inverter U1, and the gate of the fourth NMOS tube N4 is connected to the load control word r.

[0049] Specifically, the third PMOS tube P3 plays an important role in the power supply path. Its source is connected to the second power supply voltage VCC2 to provide a stable power source for the load unit. The drain is connected to the source of the fourth PMOS tube P4 to transmit voltage to the fourth PMOS tube P4 and ensure energy supply for the subsequent circuit. The gate is connected to the output of the first inverter U1, which makes the conduction and cutoff state of the third PMOS tube P3 controlled by the output signal of the first inverter U1, thereby affecting the working state of the entire PMOS tube path.

[0050] The fourth PMOS tube P4 is connected in a special way, the drain thereof is connected with the gate thereof, the drain of the third NMOS tube N3, the gate of the third NMOS tube N3, the second end of the main inverter array 1 and the first end of the comparison circuit 4, and this node becomes the core hub for signal interaction between the load unit and the external circuit. The signal output by the main inverter array 1 is transmitted to this node through the second end of the main inverter array 1, and after processing by the load unit, is transmitted to the comparison circuit 4 through the first end of the comparison circuit 4. At the same time, the design of connecting the drain and the gate makes the fourth PMOS tube P4 form a special working state, which can cooperate with the third NMOS tube N3 to jointly determine the signal characteristics of the core node.

[0051] The drain and the gate of the third NMOS tube N3 are connected, and the drain is connected with the above-mentioned core node, and the source is connected with the drain of the fourth NMOS tube N4. Such connection makes the third NMOS tube N3 play a role of signal transmission and level adjustment in the circuit, and the working state thereof will change with the signal change of the core node, thereby affecting the current path of the entire load unit.

[0052] The fourth NMOS tube N4 is a key control element of the grounding path of the load unit, the drain thereof is connected with the source of the third NMOS tube N3 to provide an outflow path for the current of the third NMOS tube N3, and the source is directly grounded to build a stable grounding loop. The gate is connected with the input end of the first inverter U1 on one hand, and is connected with the load control word r on the other hand, which means that the working state of the fourth NMOS tube N4 is directly determined by the load control word r, and at the same time, the load control word r will also affect the third PMOS tube P3 through the first inverter U1, thereby realizing the cooperative control of the PMOS tube path and the NMOS tube path.

[0053] The first inverter U1 plays a role of signal inversion in the load unit, the input end thereof is connected with the gate of the fourth NMOS tube N4 and the load control word r, and after receiving the signal of the load control word r, outputs the opposite signal to the gate of the third PMOS tube P3. Through this inversion effect, the working states of the third PMOS tube P3 and the fourth NMOS tube N4 present opposite relationship, that is, when the fourth NMOS tube N4 is turned on, the third PMOS tube P3 is turned off; when the fourth NMOS tube N4 is turned off, the third PMOS tube P3 is turned on, thereby realizing the selective use of the PMOS tube path and the NMOS tube path in the load unit under the regulation of the load control word r, and further flexibly adjusting the impedance and other characteristics of the load unit to adapt to different signal processing requirements.

[0054] In some optional implementations, the feedback inverter array 3 includes: a plurality of feedback inverter units, wherein the first terminal of the feedback inverter unit is connected to the third terminal of the comparator circuit 4, the second terminal of the feedback inverter unit is connected to the second terminal of the main inverter array 1, the third terminal of the feedback inverter unit is connected to a third power supply voltage, the fourth terminal of the feedback inverter unit is grounded, and the control terminal of the feedback inverter unit is connected to the equalization coefficient control word h.

[0055] The feedback inverter array 3 is a circuit structure composed of multiple feedback inverter units. This multi-unit collaborative design can enhance the flexibility and accuracy of feedback adjustment, thereby better realizing the equalization function of the decision feedback equalizer.

[0056] Each feedback inverter unit has a clearly defined connection to ensure a smooth and efficient feedback link. Specifically, the first terminal of the feedback inverter unit is connected to the third terminal of the comparator circuit 4. This connection allows the signal output from the comparator circuit 4 to be smoothly transmitted to the feedback inverter unit, providing the original reference signal for feedback adjustment. These signals contain the decision information of the comparator circuit 4 regarding the input data. By receiving this information, the feedback inverter unit can accurately grasp the current state of signal processing.

[0057] The second terminal of the feedback inverter unit is connected to the second terminal of the main inverter array 1, which is a key node for realizing the feedback closed loop. The signal processed by the feedback inverter unit is transmitted to the second terminal of the main inverter array 1 through this connection, where it is superimposed or interacts with the signal output by the main inverter array 1, thereby affecting the signal processing process of the main inverter array 1. This feedback mechanism can promptly correct deviations that occur during signal processing, improving the overall signal processing accuracy of the equalizer.

[0058] The control terminal of the feedback inverter unit is connected to the equalization coefficient control word h. The equalization coefficient control word h is a set of key parameter signals used to adjust the feedback strength and inversion characteristics. It can precisely control the operating state of the feedback inverter unit. By changing the value of the equalization coefficient control word h, the degree of inversion of the input signal by the feedback inverter unit and the amplitude of the feedback signal can be adjusted, thereby changing the signal strength and characteristics fed back to the main inverter array 1.

[0059] Multiple feedback inverter units work synergistically under the unified control of the equalization coefficient control word h. When the input signal exhibits varying degrees of distortion or attenuation, the equalization coefficient control word h adjusts the feedback parameters of each feedback inverter unit accordingly, ensuring that the signal fed back to the main inverter array 1 precisely compensates for the effects of signal distortion. For example, when signal attenuation is severe, increasing the parameter corresponding to the equalization coefficient control word h strengthens the feedback signal, allowing the main inverter array 1 to achieve stronger compensation during signal processing. Conversely, when signal distortion is minimal, the feedback strength can be reduced to prevent overcompensation from causing new interference to the signal. This flexible adjustment method enables the entire decision feedback equalizer to adapt to different signal environments, effectively improving data transmission quality and reducing the bit error rate.

[0060] In some alternative implementations, such as Figure 4 As shown, the feedback inverter unit includes: a fifth PMOS transistor P5, a sixth PMOS transistor P6, a fifth NMOS transistor N5, a sixth NMOS transistor N6, and a second inverter U2. The source of the fifth PMOS transistor P5 is connected to the third power supply voltage; the drain of the fifth PMOS transistor P5 is connected to the source of the sixth PMOS transistor P6; and the gate of the fifth PMOS transistor P5 is connected to the output terminal of the second inverter U2. The drain of the sixth PMOS transistor P6 is connected to the drain of the fifth NMOS transistor N5 and the second terminal of the main inverter array 1; and the gate of the sixth PMOS transistor P6 is connected to the gate of the fifth NMOS transistor N5 and the third terminal of the comparator circuit 4. The drain of the sixth NMOS transistor N6 is connected to the source of the fifth NMOS transistor N5; the source of the sixth NMOS transistor N6 is grounded; and the gate of the sixth NMOS transistor N6 is connected to the input terminal of the second inverter U2. The gate of the sixth NMOS transistor N6 is connected to the equalization coefficient control word h.

[0061] Specifically, the fifth PMOS transistor P5 is an important component of the power supply path of the feedback inverter unit. Its source is directly connected to the third power supply voltage, providing a stable voltage input for the entire feedback inverter unit. Its drain is connected to the source of the sixth PMOS transistor P6, forming a cascaded PMOS transistor structure, ensuring that the voltage can be smoothly transmitted to the subsequent sixth PMOS transistor P6. Its gate is connected to the output terminal of the second inverter U2. This design allows the conduction and cutoff states of the fifth PMOS transistor P5 to be controlled by the output signal of the second inverter U2, thereby regulating the overall working state of the PMOS path.

[0062] The drain of the sixth PMOS transistor P6 is connected to both the drain of the fifth NMOS transistor N5 and the second terminal of the main inverter array 1, becoming a key node for the feedback signal output to the main inverter array 1. This allows the processed feedback signal to be accurately transmitted to the main inverter array 1, enabling the adjustment of the signal processing of the main inverter array 1. The gate of the PMOS transistor P6 is connected to the gate of the fifth NMOS transistor N5 and the third terminal of the comparator circuit 4, forming a common gate structure. This structure allows the PMOS transistor P6 and the fifth NMOS transistor N5 to synchronously receive the signal output from the comparator circuit 4, ensuring that the PMOS transistor P6 and the fifth NMOS transistor N5 can respond in unison to the signal changes of the comparator circuit 4, thus improving the consistency of the feedback adjustment.

[0063] The fifth NMOS transistor N5 is one of the core components of the feedback signal processing. Its drain is connected to the drain of the sixth PMOS transistor P6 and the second terminal of the main inverter array 1, participating in the transmission of the feedback signal to the main inverter array 1. Its source is connected to the drain of the sixth NMOS transistor N6, forming a cascaded path for the NMOS transistors. Its gate is connected to the gate of the sixth PMOS transistor P6 and the third terminal of the comparator circuit 4, enabling it to directly respond to the signal output by the comparator circuit 4. By changing its own on and off states, it regulates the transmission path and strength of the feedback signal.

[0064] The sixth NMOS transistor N6 serves as the control switch for the grounding path of the feedback inverter unit. Its source is directly grounded, providing a stable grounding reference for the circuit. Its drain is connected to the source of the fifth NMOS transistor N5, forming a current conduction path between the NMOS transistors. Its gate is connected to the input terminal of the second inverter U2 on one hand, and to the equalization coefficient control word h on the other. This connection method allows the operating state of the sixth NMOS transistor N6 to be directly regulated by the equalization coefficient control word h. At the same time, the equalization coefficient control word h affects the fifth PMOS transistor P5 through the second inverter U2, realizing the coordinated control of the PMOS path and the NMOS path.

[0065] The second inverter U2 functions as a signal inverter in the circuit. Its input is connected to the gate of the sixth NMOS transistor N6 and the equalization coefficient control word h. After receiving the equalization coefficient control word h, it outputs an opposite signal to the gate of the fifth PMOS transistor P5. Through this inversion, the operating states of the fifth PMOS transistor P5 and the sixth NMOS transistor N6 are reversed: when the sixth NMOS transistor N6 is on, the fifth PMOS transistor P5 is off; when the sixth NMOS transistor N6 is off, the fifth PMOS transistor P5 is on.

[0066] Under the control of the equalization coefficient control word h, the entire feedback inverter array 3 can flexibly adjust the strength and characteristics of the feedback signal. For example, when it is necessary to enhance the feedback adjustment, by adjusting the equalization coefficient control word h, the conduction levels of the sixth NMOS transistor N6 and the fifth PMOS transistor P5 can be changed accordingly, increasing the amplitude of the feedback signal and allowing the main inverter array 1 to receive stronger compensation. Conversely, when it is necessary to weaken the feedback adjustment, the amplitude of the feedback signal can be reduced to avoid excessive adjustment from adversely affecting signal processing. This precise control method enables the feedback inverter array 3 to provide just the right feedback adjustment according to different signal processing requirements, effectively improving the performance of the entire decision feedback equalizer.

[0067] In a practical application scenario, based on Figure 4 The circuit diagram of the single-ended compact DFE in this embodiment includes a main inverter array 1, a load array 2, a feedback inverter array 3, and a comparator circuit 4.

[0068] To enable direct digital adjustment of the DFE's equalization intensity and avoid using traditional voltage-domain or current-domain DAC structures, each feedback inverter unit in the feedback branch's feedback inverter array 3 employs an NMOS switch (NSW) and a PMOS switch (PSW) for control. When the control signal SW of each unit is 1, the inverter is turned on and connected to the feedback path; conversely, when the control signal SW is 1, the inverter unit is disconnected from the feedback branch, and the output is in a high-impedance state.

[0069] The equalization strength coefficient of the DFE is h / N, where h is the number of inverters in the feedback branch and M is the number of inverters in the main path. To accurately control the equalization strength, the number of main inverter units and feedback inverter units is the same. To ensure the equalization strength meets the maximum attenuation requirement of the channel, the maximum equalization strength (M / N) needs to be determined, thereby determining M (the number of inverter arrays in the feedback path) and N respectively. Since the main path and feedback path subtract from each other, the current flowing through the load is small when the equalization strength is high. Therefore, this embodiment proposes using an array of inverters connected to both input and output to form a load array 2 to adjust the load impedance. When the equalization strength is high, fewer inverters are connected to the load array 2 to increase the output impedance (controlled by the load impedance control word r) to ensure sufficient swing. When the equalization strength is weak, more inverters are connected to the load array to reduce the output impedance and avoid output signal saturation distortion.

[0070] Specifically, based on Figure 4By utilizing an adjustable inverter array composed of multiple tri-state gates, an adjustable transconductance unit can be achieved, which can then serve as the transconductance unit for the main path and feedback path of the DFE adder. By utilizing a load array 2 composed of multiple tri-state gates with shorted inputs and outputs, an adjustable load impedance can be achieved. Based on the above two parts, combined with inverters, a true single-ended DFE can be realized without any DAC or passive components, thereby significantly reducing power consumption and area.

[0071] Assuming the main path inverter array has N inverters, and the feedback inverter array 3 has M inverters, with h inverters being active, then the nth output of the DFE can be expressed as:

[0072] (1)

[0073] Where n is a positive integer.

[0074] After performing a z-transform on expression (1), we get:

[0075] (2)

[0076] As can be seen, the equalization strength coefficient of the DFE circuit in this embodiment is (h / N). h can be changed by changing the number of inverters in the open feedback branch, thereby changing the feedback strength. It also directly provides a digital control interface to the previous protocol controller, avoiding the additional power consumption and area overhead brought by the DAC.

[0077] In some optional implementations, the comparator circuit 4 includes a sensitive signal amplifier and a latch, wherein the first terminal of the sensitive signal amplifier is connected to the second terminal of the main inverter array 1, the second terminal of the sensitive signal amplifier is connected to the first terminal of the latch, and the third terminal of the sensitive signal amplifier is connected to the second terminal of the latch; the first terminal of the latch outputs a data signal.

[0078] The sensitive signal amplifier is the front-end processing unit of comparator circuit 4, undertaking the important functions of amplifying and initially comparing the input signal. Its first terminal is connected to the second terminal of the main inverter array 1, and it can directly receive the signal after processing by the main inverter array 1 and adjustment by the load array 2. Since the signal output by the main inverter array 1 may have problems such as small amplitude and noise interference, the sensitive signal amplifier, with its high gain characteristics, can quickly amplify the weak signal to a sufficient amplitude while suppressing noise, providing a clear and stable signal basis for subsequent signal decision-making.

[0079] The second terminal of the sensitive signal amplifier is connected to the first terminal of the latch. This connection enables the transmission of the amplified signal to the latch, allowing the latch to acquire the pre-processed signal for subsequent operations. The third terminal is connected to the second terminal of the latch. This connection is mainly used to transmit control or synchronization signals, ensuring that the operating rhythm between the sensitive signal amplifier and the latch is consistent, and avoiding signal processing errors due to timing deviations. Through this connection method, the sensitive signal amplifier can accurately and timely deliver the amplified signal to the latch, providing a reliable basis for the latch's decision-making action.

[0080] The latch is a key component for signal locking and output. Its first terminal not only receives the amplified signal from the second terminal of the sensitive signal amplifier, but also outputs the data signal. When the sensitive signal amplifier transmits the amplified signal to the latch, the latch judges the signal according to the preset decision threshold, determines the logic state of the signal (such as high level or low level), and locks and saves this decision result.

[0081] The second terminal of the latch is connected to the third terminal of the sensitive signal amplifier. By receiving the synchronization control signal transmitted by the sensitive signal amplifier, it can perform the signal locking action at the appropriate timing, ensuring the stability and accuracy of the output signal. For example, when the synchronization control signal is triggered, the latch will immediately lock the currently received signal state and continuously output a stable data signal through the first terminal, avoiding jitter or misjudgment of the output signal due to small fluctuations in the input signal.

[0082] Throughout the operation of comparator circuit 4, the sensitive signal amplifier and latch work together to form a complete "amplification-decision-locking-output" process. The sensitive signal amplifier is responsible for improving signal quality, creating conditions for accurate decision-making; the latch is responsible for locking the decision result and stabilizing the output at the appropriate time. Their close cooperation enables comparator circuit 4 to process the input signal quickly and accurately, outputting reliable data signals, which provides an important guarantee for the entire decision feedback equalizer to achieve low bit error rate data interaction.

[0083] In some alternative implementations, such as Figure 5As shown, the sensitive signal amplifier includes: a seventh PMOS transistor P7, an eighth PMOS transistor P8, a ninth PMOS transistor P9, a tenth PMOS transistor P10, a seventh NMOS transistor N7, an eighth NMOS transistor N8, a ninth NMOS transistor N9, a tenth NMOS transistor N10, an eleventh NMOS transistor N11, and a third inverter U3. The source of the seventh PMOS transistor P7 is connected to a fourth power supply voltage, and its drain is connected to the drains of the eighth PMOS transistor P8 and the tenth PMOS transistor P10, as well as the first terminal of the latch. The gate of the seventh PMOS transistor P7 is connected to a clock signal. The source of the eighth PMOS transistor P8 is connected to a fourth power supply voltage, and its gate is connected to the drain of the tenth PMOS transistor P10. The source of the ninth PMOS transistor P9 is connected to a fourth power supply voltage, and its gate is connected to the drain of the seventh PMOS transistor P7. The source of the tenth PMOS transistor P10 is connected to a fourth power supply voltage, and the tenth PMOS transistor P11... The gate of PMOS transistor P10 is connected to the clock signal; the drain of the seventh NMOS transistor N7 is connected to the drain of the seventh PMOS transistor P7 and the gate of the eighth NMOS transistor N8; the source of the seventh NMOS transistor N7 is connected to the drain of the ninth NMOS transistor N9; the gate of the seventh NMOS transistor N7 is connected to the drain of the eighth NMOS transistor N8, the drain of the ninth PMOS transistor P9, and the second terminal of the phase-locked loop; the source of the eighth NMOS transistor N8 is connected to the drain of the tenth NMOS transistor N10; the source of the ninth NMOS transistor N9 is connected to the drain of the eleventh NMOS transistor N11; the gate of the ninth NMOS transistor N9 is connected to the second terminal of the load array 2; the source of the tenth NMOS transistor N10 is connected to the drain of the eleventh NMOS transistor N11; the gate of the tenth NMOS transistor N10 is connected to the output terminal and the input terminal of the third inverter U3; the source of the eleventh NMOS transistor N11 is grounded; and the gate of the eleventh NMOS transistor N11 is connected to the second control signal.

[0084] The source of the seventh PMOS transistor P7 is connected to the fourth supply voltage, providing power to itself and related connected components. Its drain is connected to the drains of the eighth PMOS transistor P8, the ninth PMOS transistor P9, the tenth PMOS transistor P10, and the first terminal of the latch. This connection point is an important node where signals from multiple PMOS transistors converge and transmit signals to the latch. The gate is connected to a clock signal. The high and low levels of the clock signal control the conduction and cutoff of the seventh PMOS transistor P7, thereby affecting the signal state of this node.

[0085] The source of the eighth PMOS transistor P8 is also connected to the fourth power supply voltage, and its gate is connected to the drain of the tenth PMOS transistor P10. Its operating state is controlled by the drain signal of the tenth PMOS transistor P10. Its drain is connected to the drain of the seventh PMOS transistor P7 and other nodes mentioned above, participating in signal convergence and transmission.

[0086] The source of the ninth PMOS transistor P9 is connected to the fourth power supply voltage, and its gate is connected to the drain of the seventh PMOS transistor P7. This allows the signal change at the drain of the seventh PMOS transistor P7 to directly affect the conduction of the ninth PMOS transistor P9. Its drain is connected to the drain of the seventh PMOS transistor P7 and other nodes, and together they participate in signal processing and transmission.

[0087] The source of the tenth PMOS transistor P10 is connected to the fourth power supply voltage, and the gate is connected to the clock signal. Similar to the seventh PMOS transistor P7, the clock signal controls its conduction and cutoff. The drain is connected to the gate of the eighth PMOS transistor P8, and the working state of the eighth PMOS transistor P8 is regulated under the action of the clock signal.

[0088] Regarding the NMOS transistors, the drain of the seventh NMOS transistor N7 is connected to the drain of the seventh PMOS transistor P7 and the gate of the eighth NMOS transistor N8. The source is connected to the drain of the ninth NMOS transistor N9, and the gate is connected to the drain of the eighth NMOS transistor N8, the drain of the ninth PMOS transistor P9, and the second terminal of the phase-locked loop. These multiple connections enable it to receive and transmit signals from multiple nodes, acting as a bridge in the signal amplification process.

[0089] The source of the eighth NMOS transistor N8 is connected to the drain of the tenth NMOS transistor N10, and its drain is connected to the gate of the seventh NMOS transistor N7. The gate is controlled by the drain signal of the seventh NMOS transistor N7 and participates in signal transmission and processing.

[0090] The source of the ninth NMOS transistor N9 is connected to the drain of the eleventh NMOS transistor N11, and its gate is connected to the second end of the load array 2. It can receive signals from the load array 2. Changes in this signal will change the conduction level of the ninth NMOS transistor N9, thereby affecting the current of the entire NMOS transistor path. Its drain is connected to the source of the seventh NMOS transistor N7 to transmit signals.

[0091] The source of the tenth NMOS transistor N10 is connected to the drain of the eleventh NMOS transistor N11, and its gate is connected to the output and input of the third inverter U3. This connection method allows the operating state of the tenth NMOS transistor N10 to be controlled by the third inverter U3. Its drain is connected to the source of the eighth NMOS transistor N8 and participates in signal transmission.

[0092] The source of the eleventh NMOS transistor N11 is grounded, providing a ground reference for the entire NMOS transistor path. The gate is connected to the second control signal. The second control signal controls the conduction and cutoff of the eleventh NMOS transistor N11, thereby regulating the on / off state of the entire NMOS transistor path and thus affecting the operating state of the sensitive signal amplifier.

[0093] The input and output terminals of the third inverter U3 are both connected to the gate of the tenth NMOS transistor N10, forming a special feedback structure that can stabilize the signal state of the gate of the tenth NMOS transistor N10, ensure the stability of the operation of the tenth NMOS transistor N10, and thus ensure the consistency and reliability of the sensitive signal amplifier in signal amplification.

[0094] Under the combined action of the clock signal, the second control signal, and other signals, these PMOS transistors, NMOS transistors, and the third inverter U3 work together. The clock signal controls the conduction and cutoff of the seventh PMOS transistor P7 and the tenth PMOS transistor P10, regulating the signal transmission in the PMOS transistor paths; the second control signal controls the eleventh NMOS transistor N11, affecting the on / off state of the NMOS transistor paths; the signal interaction and feedback between the transistors enable the sensitive signal amplifier to effectively amplify the input signal, providing a high-quality signal for the subsequent latch decision and ensuring the accurate operation of the comparator circuit 4.

[0095] In some alternative implementations, to meet the DFE's requirement for an inverted output signal, the comparator can be structured with differential output functionality. The positive output is used to supply data to the DFE and is connected to a serial-to-parallel converter, while the inverted output is connected to the DFE's feedback input. This avoids introducing an additional inverter delay to the feedback terminal, thereby preventing a drop in the maximum operating speed.

[0096] like Figure 5As shown, the latch includes: an eleventh PMOS transistor P11, a twelfth PMOS transistor P12, a thirteenth PMOS transistor P13, a fourteenth PMOS transistor P14, a twelfth NMOS transistor N12, a thirteenth NMOS transistor N13, a fourteenth NMOS transistor N14, and a fifteenth NMOS transistor N15. The source of the eleventh PMOS transistor P11 is connected to the fifth power supply voltage, and its drain is connected to the drain of the twelfth PMOS transistor P12. The gate of the eleventh PMOS transistor P11 is connected to the second terminal of the sensitive signal amplifier. The source of the twelfth PMOS transistor P12 is connected to the fifth power supply voltage, and its gate is connected to the drain of the thirteenth PMOS transistor P13. The source of the thirteenth PMOS transistor P13 is connected to the fifth power supply voltage, and its gate is connected to the drain of the eleventh PMOS transistor P11. The source of the fourteenth PMOS transistor P14 is connected to the fifth power supply voltage, and the fifteenth PMOS transistor N15... The gate of the fourth PMOS transistor P14 is connected to the third terminal of the sensitive signal amplifier and the first terminal of the feedback inverter array 3; the drain of the twelfth NMOS transistor N12 is connected to the drain of the eleventh PMOS transistor P11 and the drain of the thirteenth NMOS transistor N13, the source of the twelfth NMOS transistor N12 is grounded, and the gate of the twelfth NMOS transistor N12 is connected to the second terminal of the sensitive signal amplifier; the source of the thirteenth NMOS transistor N13 is grounded, and the gate of the thirteenth NMOS transistor N13 is connected to the drain of the thirteenth PMOS transistor P13; the drain of the fourteenth NMOS transistor N14 is connected to the drain of the thirteenth PMOS transistor P13 and the drain of the fifteenth NMOS transistor N15, the source of the fourteenth NMOS transistor N14 is grounded, and the gate of the fourteenth NMOS transistor N14 is connected to the drain of the eleventh PMOS transistor P11; the source of the fifteenth NMOS transistor N15 is grounded, and the gate of the fifteenth NMOS transistor N15 is connected to the gate of the fourteenth PMOS transistor P14.

[0097] The source of the eleventh PMOS transistor P11 is connected to the fifth supply voltage, providing power to itself and connected components; its drain is connected to the drain of the twelfth PMOS transistor P12, forming an important signal node; its gate is connected to the second terminal of the sensitive signal amplifier, receiving the signal transmitted by the sensitive signal amplifier. Changes in this signal will control the conduction and cutoff of the eleventh PMOS transistor P11, thereby affecting the signal state of the drain node.

[0098] The source of the twelfth PMOS transistor P12 is connected to the fifth power supply voltage, and its gate is connected to the drain of the thirteenth PMOS transistor P13. Its operating state is regulated by the drain signal of the thirteenth PMOS transistor P13. Its drain is connected to the drain of the eleventh PMOS transistor and participates in the signal formation and transmission of the above signal nodes.

[0099] The source of the thirteenth PMOS transistor P13 is connected to the fifth power supply voltage, and its gate is connected to the drain of the eleventh PMOS transistor P11. This allows the signal change at the drain of the eleventh PMOS transistor P11 to directly affect the conduction of the thirteenth PMOS transistor P13. Its drain is connected to the gate of the twelfth PMOS transistor P12, etc., so that the signal generated by its own working state can be transmitted out and affect other components.

[0100] The source of the fourteenth PMOS transistor P14 is connected to the fifth supply voltage, and its gate is connected to the third terminal of the sensitive signal amplifier and the first terminal of the feedback inverter array 3. It can receive signals from these two parts, and these signals together control the conduction and cutoff of the fourteenth PMOS transistor P14, thereby playing a corresponding role in the circuit.

[0101] Regarding the NMOS transistors, the drain of the twelfth NMOS transistor N12 is connected to the drain of the eleventh PMOS transistor P11 and the drain of the thirteenth NMOS transistor N13, while the source is grounded, providing a grounding path for this node. The gate is connected to the second terminal of the sensitive signal amplifier and receives the same signal as the gate of the eleventh PMOS transistor P11. Under the action of this signal, the two exhibit complementary working states and jointly regulate the signal of the drain node.

[0102] The source of the thirteenth NMOS transistor N13 is grounded, and its gate is connected to the drain of the thirteenth PMOS transistor P13. It is controlled by the drain signal of the thirteenth PMOS transistor P13. Its drain is connected to the drain of the eleventh PMOS transistor P11 and the drain of the twelfth NMOS transistor N12. It participates in the signal composition of the signal node, and its on and off states will change the signal level of the node.

[0103] The drain of the fourteenth NMOS transistor N14 is connected to the drain of the thirteenth PMOS transistor P13 and the drain of the fifteenth NMOS transistor N15. The source is grounded, and the gate is connected to the drain of the eleventh PMOS transistor P11. It receives the signal from the drain of the eleventh PMOS transistor P11, which controls its conduction and cutoff, thereby affecting the signal state of the connected node.

[0104] The source of the fifteenth NMOS transistor N15 is grounded, and its gate is connected to the gate of the fourteenth PMOS transistor P14. Both NMOS transistors receive the same control signal, and their operating states are complementary, playing a role in signal transmission and regulation.

[0105] When the sensitive signal amplifier transmits the amplified signal to the latch, the relevant control signals cause changes in the conduction states of each PMOS and NMOS transistor. For example, the signal at the second terminal of the sensitive signal amplifier simultaneously acts on the gates of the eleventh PMOS transistor P11 and the twelfth NMOS transistor N12. When the signal is high, the eleventh PMOS transistor P11 is off, and the twelfth NMOS transistor N12 is on, causing the level of the drain node of the eleventh PMOS transistor P11 to be pulled down; conversely, when the signal is low, the situation is reversed. The interaction between the components forms a feedback mechanism. Once the input signal stabilizes, the latch can lock the current signal state. Regardless of subsequent minor fluctuations in the input signal, the latch output (the node connected to the drain of the eleventh PMOS transistor P11, etc.) maintains a stable signal, thus achieving stable data signal output and providing a reliable signal result for the entire decision feedback equalizer.

[0106] In a practical application scenario, based on Figure 5 To improve the comparator's response speed, the comparator input stage is implemented using a sensitive signal amplifier structure. The comparator's comparison threshold voltage V... TH The input and output are connected via an inverter, whose cell size is identical to that of the inverter array used in the DFE stage. This ensures that VTH equals the common-mode level of the DFE adder output signal, preventing comparator output erroneous toggling. Using an inverter to provide the threshold voltage avoids the increased area problem associated with using a resistor divider. The second stage of the comparator employs an RS latch structure, which quickly straightens the differential full-swing of the amplified sensitive signal, thus completing the comparator function. Because the sensitive signal amplifier and RS latch are differential structures, their positive output is the DFE. OUT As the output of DFE, its negative output is DFE. OUT_N This is used in the feedback path of the DFE, thereby avoiding the problems of increased delay and reduced maximum operating rate caused by using an additional inverter, and meeting the requirements of high-speed data reception.

[0107] This embodiment provides a single-ended receiving device, such as... Figure 6 As shown, it includes: isolation circuit 5, self-biased receiver front-end circuit 6, serial-to-parallel converter 7, and above decision feedback equalizers. A true single-ended DFE is achieved using an inverter array and directly connected to the digital interface, avoiding the use of a DAC. Utilizing CIN and the self-biased receiver front-end circuit 6, the transmitter and receiver do not need precise matching in terms of power supply voltage, swing, and signal common-mode level, improving application adaptability.

[0108] like Figure 6As shown, the first terminal of the isolation circuit 5 is connected to a data signal, and the second terminal of the isolation circuit 5 is connected to the first terminal of the self-biased receiver front-end circuit 6; the second terminal of the self-biased receiver front-end circuit 6 is connected to the first terminal of the main inverter array 1; the first terminal of the main inverter array 1 is connected to a data signal, the second terminal of the main inverter array 1 is connected to the first terminal of the load array 2, the third terminal of the main inverter array 1 is connected to the first supply voltage VCC1, the fourth terminal of the main inverter array 1 is grounded, and the control terminal of the main inverter array 1 is connected to the first control signal; the second terminal of the load array 2 is connected to the first terminal of the comparator circuit 4, and the load... The third terminal of array 2 is connected to the second power supply voltage VCC2, the fourth terminal of load array 2 is grounded, and the control terminal of load array 2 is connected to the load control word r; the second terminal of comparator circuit 4 is connected to the first terminal of serial-to-parallel converter 7, and the third terminal of comparator circuit 4 is connected to the first terminal of feedback inverter array 3; the second terminal of feedback inverter array 3 is connected to the second terminal of main inverter array 1, the third terminal of feedback inverter array 3 is connected to the third power supply voltage, the fourth terminal of feedback inverter array 3 is grounded, and the control terminal of feedback inverter array 3 is connected to the equalization coefficient control word h; the second terminal of serial-to-parallel converter 7 outputs a data signal.

[0109] Specifically, the isolation circuit 5 serves as the signal input terminal of the single-ended receiver. Its first terminal is connected to the data signal, playing a crucial role in initially isolating and buffering the input signal. In practical circuit applications, the input data signal may carry external noise or be interfered with by other circuit modules. The isolation circuit 5 can effectively block the transmission of these interference signals and simultaneously perform preliminary adjustments to the amplitude and waveform of the input signal, making it more suitable for processing by subsequent circuit modules. The second terminal of the isolation circuit 5 is connected to the first terminal of the self-biased receiver front-end circuit 6, smoothly transmitting the isolated signal to the self-biased receiver front-end circuit 6.

[0110] The self-biased receiver front-end circuit 6 is a key pre-processing module for signal reception, with its second terminal connected to the first terminal of the main inverter array 1 in the decision feedback equalizer. This circuit provides a stable bias voltage and current for the entire receiving device, ensuring that subsequent circuit modules operate at appropriate operating points. Simultaneously, the self-biased receiver front-end circuit 6 further amplifies and shapes the signal from the isolation circuit 5, improving signal quality and laying a solid foundation for the accurate processing of the decision feedback equalizer. Through its self-biasing characteristics, this circuit can adaptively adjust its operating state within a certain range to adapt to input signals of different intensities and frequencies, enhancing the adaptability of the single-ended receiver.

[0111] The serial-to-parallel converter 7 is a key module for signal format conversion. Its first terminal receives the decision signal from the comparator circuit 4, and its second terminal outputs the final data signal. In a single-ended receiving device, the signal output by the comparator circuit 4 is typically a serial signal, while subsequent digital circuits or data processing systems often require parallel signals for processing. The serial-to-parallel converter 7 can convert serial input signals into parallel output signals, greatly improving the efficiency of data transmission and processing. By appropriately setting the number of bits and timing of the serial-to-parallel conversion, the serial-to-parallel converter 7 can flexibly adapt to different subsequent processing requirements, ensuring that the output data signal can be accurately identified and processed.

[0112] During the operation of the single-ended receiver, the various circuit modules work together to form a complete signal processing flow: the input data signal is first isolated and buffered by the isolation circuit 5, and then enters the self-biased receiver front-end circuit 6 for preprocessing; the preprocessed signal is sent to the decision feedback equalizer, processed by the main inverter array 1, adjusted by the load array 2, decided by the comparator circuit 4, and dynamically adjusted by the feedback inverter array 3 to obtain a precise decision signal; this decision signal is converted into a parallel signal by the serial-to-parallel converter 7, and finally outputs a stable and reliable data signal. This collaborative working mechanism enables the single-ended receiver to effectively cope with various interference and distortion problems in the single-ended signal transmission process, significantly improving the accuracy and reliability of data reception, and is suitable for a variety of application scenarios with high signal quality requirements.

[0113] In some alternative implementations, the isolation circuit 5 includes an AC coupling capacitor CIN.

[0114] based on Figure 7 By using an AC coupling capacitor CIN, the external input data signal and the output signal of the receiver front-end circuit can be isolated, thereby meeting the requirements of different input swing and common-mode level. The common-mode level of the external input is usually positively correlated with the power supply voltage of the SerDes transmitter. Therefore, by using AC coupling, the receiver can be adapted to different transmitters, thereby flexibly meeting the needs of different applications.

[0115] In some optional implementations, the self-biased receiver front-end circuit 6 includes a gain circuit and a gain compensation circuit, wherein the first terminal of the gain circuit is connected to the second terminal of the isolation circuit 5, the second terminal of the gain circuit is connected to the first terminal of the gain compensation circuit, the second terminal of the gain compensation circuit is connected to the first terminal of the main inverter array 1, and the third terminal of the gain compensation circuit is connected to the gain control word A.

[0116] The gain circuit is the core module for signal amplification. Its first terminal is connected to the second terminal of the isolation circuit 5, allowing it to directly receive the signal processed by the isolation circuit 5. Since the signal output from the isolation circuit 5 may have a small amplitude, making it difficult to meet the processing requirements of subsequent circuits, the gain circuit, with its high gain characteristics, can amplify the amplitude of the input signal by a certain proportion. For example, when the input signal amplitude attenuates due to transmission loss, the gain circuit can effectively increase the voltage swing of the signal, making the difference between high and low levels more obvious, thereby reducing the difficulty of signal recognition for subsequent circuits. The second terminal of the gain circuit is connected to the first terminal of the gain compensation circuit, accurately transmitting the amplified signal to the gain compensation circuit and providing the basic signal source for its operation.

[0117] The gain compensation circuit plays a crucial role in compensating and optimizing the amplified signal. Its second terminal is connected to the first terminal of the main inverter array 1, enabling the compensated signal to be transmitted to the main inverter array 1, ensuring that the signal entering the decision feedback equalizer possesses good characteristics. During signal transmission, different frequency components may experience varying degrees of attenuation, resulting in an unbalanced frequency response. The gain compensation circuit addresses this by amplifying severely attenuated frequency components and appropriately suppressing less attenuated ones, thus flattening the frequency response of the output signal and improving signal integrity.

[0118] Crucially, the third terminal of the gain compensation circuit is connected to the gain control word A. This design gives the self-biased receiver front-end circuit 6 flexible adjustment capabilities. The gain control word A is a set of digital signals used to adjust the degree of gain compensation. By changing the value of the gain control word A, the compensation level of the gain compensation circuit for different frequency signals can be precisely adjusted. When the frequency characteristics of the input signal change, for example, at different data transmission rates where the high-frequency components of the signal attenuate at different rates, the gain control word A will adjust the parameters of the gain compensation circuit accordingly to ensure that it always provides optimal compensation for the signal.

[0119] In practical operation, the gain circuit and the gain compensation circuit work together. The gain circuit first amplifies the signal to address insufficient signal amplitude; then, the gain compensation circuit, according to the instructions of the gain control word A, compensates for the frequency response of the amplified signal, correcting the distortion generated during transmission. This collaborative "amplification-compensation" mechanism enables the self-biased receiver front-end circuit 6 to adapt to input signals of different intensities and frequency characteristics, outputting a signal with appropriate amplitude and balanced frequency response to the main inverter array 1, laying a solid foundation for the efficient operation of the entire single-ended receiver. Simultaneously, thanks to its self-biasing characteristic, the entire front-end circuit eliminates the need for an external bias circuit, simplifying the circuit structure, reducing power consumption, and improving the stability and reliability of the circuit operation.

[0120] In some alternative implementations, such as Figure 7 As shown, the gain circuit includes: a fifteenth PMOS transistor P15, a sixteenth NMOS transistor N16, and an adjustable resistor RF. The source of the fifteenth PMOS transistor P15 is connected to the sixth supply voltage VCC6. The drain of the fifteenth PMOS transistor P15 is connected to the drain of the sixteenth NMOS transistor N16, the first terminal of the adjustable resistor RF, and the first terminal of the gain compensation circuit. The gate of the fifteenth PMOS transistor P15 is connected to the gate of the sixteenth NMOS transistor N16, the first terminal of the adjustable resistor RF, and the second terminal of the isolation circuit 5. The source of the sixteenth NMOS transistor N16 is grounded.

[0121] Specifically, the source of the fifteenth PMOS transistor P15 is connected to the sixth supply voltage VCC6, providing a stable energy source for the entire gain circuit, ensuring that the circuit can operate normally and has sufficient driving capability to amplify the signal. Its drain is connected to the drain of the sixteenth NMOS transistor N16, the first terminal of the adjustable resistor RF, and the first terminal of the gain compensation circuit. This connection point becomes a key node for the output signal of the gain circuit, through which the amplified signal is transmitted to the gain compensation circuit. The gate of the fifteenth PMOS transistor P15 is connected to the gate of the sixteenth NMOS transistor N16, the first terminal of the adjustable resistor RF, and the second terminal of the isolation circuit 5. This connection method allows the signal output by the isolation circuit 5 to simultaneously control the conduction state of the fifteenth PMOS transistor and the sixteenth NMOS transistor N16, achieving coordinated control of the signal amplification process.

[0122] The source of the sixteenth NMOS transistor N16 is grounded, forming a ground loop for the circuit and providing a stable return path for the current. Its drain is connected to the drain of the fifteenth PMOS transistor P15 and other nodes mentioned above, participating in signal amplification and output. Its gate is connected to the gate of the fifteenth PMOS transistor P15 and other nodes, receiving the input signal from the isolation circuit 5. When the level of the input signal changes, the conduction level of the sixteenth NMOS transistor N16 will change accordingly, thus affecting the current magnitude of the entire circuit and ultimately achieving signal amplification.

[0123] The adjustable resistor RF plays a crucial role in the gain circuit, adjusting the amplification factor. Its first terminal is connected to nodes such as the drain of the fifteenth PMOS transistor P15 and the drain of the sixteenth NMOS transistor N16, while the other terminal is typically grounded (inferred from conventional circuit design). By changing the value of the adjustable resistor RF, the amplitude of current changes in the circuit can be adjusted, thereby changing the amplification factor of the gain circuit. When the resistance of the adjustable resistor RF increases, the current change in the circuit becomes more pronounced under the same input signal variation, resulting in a larger amplitude change in the output signal, i.e., an increased amplification factor; conversely, when the resistance of the adjustable resistor RF decreases, the amplification factor decreases. This adjustable characteristic allows the gain circuit to adapt to input signals of different amplitudes. When the input signal is weak, the amplification factor can be increased to ensure the signal can be recognized by subsequent circuits; when the input signal is strong, the amplification factor can be decreased to avoid signal distortion, thus flexibly meeting the signal amplification needs in different scenarios.

[0124] In actual operation, when the signal output from isolation circuit 5 is input to the gain circuit, it simultaneously affects the gates of the fifteenth PMOS transistor P15 and the sixteenth NMOS transistor N16. For example, when the input signal is high, the conduction level of the sixteenth NMOS transistor N16 increases, and the conduction level of the fifteenth PMOS transistor P15 changes accordingly. This alters the current flowing through the fifteenth PMOS transistor P15, the sixteenth NMOS transistor N16, and the adjustable resistor RF, thereby generating an amplified signal at the drain nodes of the fifteenth PMOS transistor P15 and the sixteenth NMOS transistor N16. The adjustable resistor RF precisely controls the gain of this amplification process by adjusting its resistance, ensuring that the signal amplitude output to the gain compensation circuit is appropriate, laying a good foundation for subsequent gain compensation processing. The coordinated operation of these three components enables the gain circuit to efficiently and flexibly amplify the input signal, significantly improving the adaptability of the self-biased receiver front-end circuit 6 to signals of different strengths.

[0125] In some alternative implementations, such as Figure 7As shown, the gain compensation circuit includes: a sixteenth PMOS transistor P16, a seventeenth PMOS transistor P17, a seventeenth NMOS transistor N17, an eighteenth NMOS transistor N18, and a fourth inverter U4. The source of the sixteenth PMOS transistor P16 is connected to the seventh supply voltage VCC7, the drain of the sixteenth PMOS transistor P16 is connected to the source of the seventeenth PMOS transistor P17, and the gate of the sixteenth PMOS transistor P16 is connected to the output of the fourth inverter U4. The drain of the seventeenth PMOS transistor P17 is connected to the source of the seventeenth NMOS transistor N18. The drain of transistor N17 is connected; the gate of the seventeenth PMOS transistor P17 is connected to the gate of the seventeenth NMOS transistor N17 and the second terminal of the gain circuit; the drain of the seventeenth PMOS transistor P17 is connected to the first terminal of the main inverter array 1; the source of the seventeenth NMOS transistor N17 is connected to the drain of the eighteenth NMOS transistor N18; the source of the eighteenth NMOS transistor N18 is grounded; the gate of the eighteenth NMOS transistor N18 is connected to the input terminal of the fourth inverter U4; and the gate of the eighteenth NMOS transistor N18 is connected to the gain control word A.

[0126] The source of the sixteenth PMOS transistor P16 is connected to the seventh supply voltage VCC7, providing stable power support for the entire gain compensation circuit. Its drain is connected to the source of the seventeenth PMOS transistor P17, forming a cascaded PMOS structure to ensure that the voltage can be transmitted to the seventeenth PMOS transistor P17 in an orderly manner. The gate is connected to the output terminal of the fourth inverter U4, and its conduction and cutoff states are controlled by the output signal of the fourth inverter U4, thus affecting the current of the entire PMOS path.

[0127] The drain of the seventeenth PMOS transistor P17 is connected to the drain of the seventeenth NMOS transistor N17. This drain is also a crucial node connecting to the first terminal of the main inverter array 1; the compensated signal is transmitted to the main inverter array 1 through this point. The gate is connected to the gate of the seventeenth NMOS transistor N17 and the second terminal of the gain circuit. This means that the seventeenth PMOS transistor P17 and the seventeenth NMOS transistor N17 synchronously receive signals from the gain circuit, and they respond collaboratively to signal changes, jointly determining the signal characteristics output to the main inverter array 1. The source is connected to the drain of the sixteenth PMOS transistor P16, receiving the voltage supply from it.

[0128] The source of the seventeenth NMOS transistor N17 is connected to the drain of the eighteenth NMOS transistor N18, forming a cascaded NMOS structure. Its drain is connected to the drain of the seventeenth PMOS transistor P17, participating in signal processing and output. The gate is connected to the gate of the seventeenth PMOS transistor P17 and the second terminal of the gain circuit. Together with the seventeenth PMOS transistor P17, it receives the signal output from the gain circuit. Its conduction level changes with the signal, thereby regulating the current in the NMOS path and affecting the amplitude of the output signal.

[0129] The source of the eighteenth NMOS transistor N18 is grounded, providing a stable ground reference for the NMOS transistor path. Its drain is connected to the source of the seventeenth NMOS transistor N17, a crucial link in current conduction within the NMOS transistor path. The gate is connected to the input of the fourth inverter U4 and also to the gain control word A. Its operating state is directly determined by the gain control word A. Simultaneously, it influences the sixteenth PMOS transistor P16 through the fourth inverter U4, achieving coordinated control of the PMOS and NMOS paths.

[0130] The fourth inverter U4 acts as a signal inverter in the circuit. Its input is connected to the gate of the eighteenth NMOS transistor N18 and the gain control word A. After receiving the gain control word A signal, it outputs an opposite signal to the gate of the sixteenth PMOS transistor P16. This inversion effect causes the sixteenth PMOS transistor P16 and the eighteenth NMOS transistor N18 to have opposite operating states: when the eighteenth NMOS transistor N18 is on, the sixteenth PMOS transistor P16 is off; when the eighteenth NMOS transistor N18 is off, the sixteenth PMOS transistor P16 is on.

[0131] In practical operation, the gain control word A adjusts the current in the PMOS and NMOS paths by controlling the eighteenth NMOS transistor N18 and the sixteenth PMOS transistor P16, thereby achieving signal gain compensation. When the gain control word A is in a certain state, the eighteenth NMOS transistor N18 is turned on, and the source potential of the seventeenth NMOS transistor N17 is pulled low. Under the action of the gate signal of the seventeenth NMOS transistor N17, the NMOS path current increases; at the same time, the fourth inverter U4 turns off the sixteenth PMOS transistor P16, reducing the PMOS path current, and the overall output signal gain is adjusted accordingly. Conversely, when the gain control word A changes, the operating states of each transistor are reversed, achieving different degrees of gain compensation.

[0132] After the signal from the gain circuit is input to the gates of the seventeenth PMOS transistor P17 and the seventeenth NMOS transistor N17, the two transistors adjust their conduction levels according to the signal level changes, forming a compensated signal at their drain nodes. For example, when a certain frequency component in the input signal is severely attenuated, by setting an appropriate gain control word A, the gain compensation circuit can amplify that frequency component additionally to compensate for the attenuation, making the gain of each frequency component of the signal output to the main inverter array 1 more balanced, providing a better signal source for the subsequent decision feedback equalizer. The coordinated operation of the sixteenth PMOS transistor P16, the seventeenth PMOS transistor P17, the seventeenth NMOS transistor N17, the eighteenth NMOS transistor N18, and the fourth inverter U4 enables the gain compensation circuit to flexibly respond to the commands of the gain control word A, accurately compensate for signal gain deviations, and significantly improve the adaptability and accuracy of the signal processing of the self-biased receiver front-end circuit 6.

[0133] By connecting the input and output terminals of the inverter using a feedback resistor (i.e., an adjustable resistor RF), a self-biased analog receiver front-end is formed. Combined with an AC coupling capacitor CIN, this allows the circuit to achieve its optimal common-mode input level without the need for an additional bias circuit. Furthermore, by adjusting the feedback coefficient, the input impedance can be changed to meet different impedance matching requirements in various application scenarios, improving the system's adaptability and flexibility. Its equivalent input impedance RIN = RF / (1+AV), where AV is the open-loop gain of the inverter. It is evident that RIN can be changed by altering RF.

[0134] In a practical application, a self-biased inverter structure using CIN combined with a feedback resistor can adaptively acquire the common-mode level of the analog front-end. This common-mode level is equal to the inverter's switching threshold, ensuring correct reception of the input signal without erroneous switching. RF is a digitally switched resistor array. Adjusting RF regulates the equivalent impedance of the analog front-end circuit, achieving impedance matching between the transmitter and the signal, ensuring high-quality data signal reception. Furthermore, the adjustable input impedance allows for increased input impedance in specific situations (such as short transmission distances) by selecting a higher RF value. This improves the received signal swing without significantly affecting signal transmission quality and reduces circuit power consumption. Since adjusting the input impedance by changing RF causes a decrease in the gain of the first-stage inverter, a variable gain stage circuit based on an inverter array is proposed to compensate for the gain variation caused by RF changes. Specifically, the larger the RF, the larger the first-stage gain; therefore, the number of inverters in the second stage is reduced to avoid output signal saturation. Conversely, the smaller the RF, the smaller the first-stage gain; therefore, the number of inverters in the second stage is increased to compensate for the gain loss in the first stage, thus ensuring sufficient output swing. Furthermore, since the input capacitance of the receiver's analog front-end circuit is small, typically only tens of fF, CIN only needs to be in the range of several hundred to 1 pF to meet application requirements without significantly affecting the output swing received by the receiver.

[0135] In some alternative implementations, the single-ended receiver further includes an adaptive bandwidth control circuit that monitors the frequency characteristics of the input signal in real time and dynamically changes the bandwidth of the receiver according to preset rules.

[0136] The foregoing has provided a detailed description of the decision feedback equalizer and single-ended receiving device provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A decision feedback equalizer, characterized in that, include: The circuit consists of a main inverter array, a load array, a feedback inverter array, and a comparator circuit. The first terminal of the main inverter array is connected to a data signal, the second terminal of the main inverter array is connected to the first terminal of the load array, the third terminal of the main inverter array is connected to a first power supply voltage, the third terminal of the main inverter array is grounded, and the control terminal of the main inverter array is connected to a first control signal. The second terminal of the load array is connected to the first terminal of the comparator circuit, the third terminal of the load array is connected to the second power supply voltage, the fourth terminal of the load array is grounded, and the control terminal of the load array is connected to the load control word. The second terminal of the comparator circuit outputs a data signal, and the third terminal of the comparator circuit is connected to the first terminal of the feedback inverter array. The second terminal of the feedback inverter array is connected to the second terminal of the main inverter array, the third terminal of the feedback inverter array is connected to the third power supply voltage, the fourth terminal of the feedback inverter array is grounded, and the control terminal of the feedback inverter array is connected to the equalization coefficient control word. The main inverter array includes: multiple main inverter units, wherein... The first terminal of each main inverter unit is connected to a data signal, the second terminal of the main inverter unit is connected to the first terminal of the load array and the second terminal of the feedback inverter array, the third terminal of the main inverter unit is connected to a first power supply voltage, the third terminal of the main inverter unit is grounded, and the control terminal of the main inverter unit is connected to a first control signal. The main inverter unit includes: a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor, wherein, The source of the first PMOS transistor is connected to the first power supply voltage, the drain of the first PMOS transistor is connected to the source of the second PMOS transistor, and the gate of the first PMOS transistor is grounded. The drain of the second PMOS transistor is connected to the drain of the first NMOS transistor, the first terminal of the load array, and the second terminal of the feedback inverter array; the gate of the second PMOS transistor is connected to the gate of the first NMOS transistor. The source of the first NMOS transistor is connected to the drain of the second NMOS transistor, and the gate of the first NMOS transistor is connected to a data signal. The source of the second NMOS transistor is grounded, and the gate of the second NMOS transistor is connected to the first control signal; The load array includes: multiple load units, wherein... The first terminal of the load unit is connected to the second terminal of the main inverter array, the second terminal of the load unit is connected to the first terminal of the comparator circuit, the third terminal of the load unit is connected to the second power supply voltage, the fourth terminal of the load unit is grounded, and the control terminal of the load unit is connected to the load control word. The load unit includes: a third PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a first inverter, wherein, The source of the third PMOS transistor is connected to the second power supply voltage, the drain of the third PMOS transistor is connected to the source of the fourth PMOS transistor, and the gate of the third PMOS transistor is connected to the output terminal of the first inverter. The drain of the fourth PMOS transistor is connected to its gate, the drain of the third NMOS transistor, the gate of the third NMOS transistor, the second terminal of the main inverter array, and the first terminal of the comparator circuit. The drain of the fourth NMOS transistor is connected to the source of the third NMOS transistor, the source of the fourth NMOS transistor is grounded, the gate of the fourth NMOS transistor is connected to the input of the first inverter, and the gate of the fourth NMOS transistor is connected to the load control word.

2. The decision feedback equalizer according to claim 1, characterized in that, The feedback inverter array includes: multiple feedback inverter units, wherein... The first terminal of the feedback inverter unit is connected to the third terminal of the comparator circuit, the second terminal of the feedback inverter unit is connected to the second terminal of the main inverter array, the third terminal of the feedback inverter unit is connected to the third power supply voltage, the fourth terminal of the feedback inverter unit is grounded, and the control terminal of the feedback inverter unit is connected to the equalization coefficient control word.

3. The decision feedback equalizer according to claim 2, characterized in that, The feedback inverter array includes: a fifth PMOS transistor, a sixth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a second inverter, wherein, The source of the fifth PMOS transistor is connected to the third power supply voltage, the drain of the fifth PMOS transistor is connected to the source of the sixth PMOS transistor, and the gate of the fifth PMOS transistor is connected to the output terminal of the second inverter. The drain of the sixth PMOS transistor is connected to the drain of the fifth NMOS transistor and the second terminal of the main inverter array, and the gate of the sixth PMOS transistor is connected to the gate of the fifth NMOS transistor and the third terminal of the comparator circuit. The drain of the sixth NMOS transistor is connected to the source of the fifth NMOS transistor, the source of the sixth NMOS transistor is grounded, the gate of the sixth NMOS transistor is connected to the input of the second inverter, and the gate of the sixth NMOS transistor is connected to the equalization coefficient control word.

4. The decision feedback equalizer according to claim 1, characterized in that, The comparison circuit includes: a sensitive signal amplifier and a latch, wherein... The first terminal of the sensitive signal amplifier is connected to the second terminal of the main inverter array, the second terminal of the sensitive signal amplifier is connected to the first terminal of the latch, and the third terminal of the sensitive signal amplifier is connected to the second terminal of the latch. The latch outputs a data signal at its first terminal.

5. The decision feedback equalizer according to claim 4, characterized in that, The sensitive signal amplifier includes: a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, and a third inverter, wherein... The source of the seventh PMOS transistor is connected to the fourth power supply voltage, the drain of the seventh PMOS transistor is connected to the drain of the eighth PMOS transistor, the drain of the ninth PMOS transistor, the drain of the tenth PMOS transistor, and the first terminal of the latch, and the gate of the seventh PMOS transistor is connected to the clock signal. The source of the eighth PMOS transistor is connected to the fourth power supply voltage, and the gate of the eighth PMOS transistor is connected to the drain of the tenth PMOS transistor. The source of the ninth PMOS transistor is connected to the fourth power supply voltage, and the gate of the ninth PMOS transistor is connected to the drain of the seventh PMOS transistor. The source of the tenth PMOS transistor is connected to the fourth power supply voltage, and the gate of the tenth PMOS transistor is connected to the clock signal. The drain of the seventh NMOS transistor is connected to the drain of the seventh PMOS transistor and the gate of the eighth NMOS transistor. The source of the seventh NMOS transistor is connected to the drain of the ninth NMOS transistor. The gate of the seventh NMOS transistor is connected to the drain of the eighth NMOS transistor, the drain of the ninth PMOS transistor, and the second terminal of the phase-locked loop. The source of the eighth NMOS transistor is connected to the drain of the tenth NMOS transistor; The source of the ninth NMOS transistor is connected to the drain of the eleventh NMOS transistor, and the gate of the ninth NMOS transistor is connected to the second end of the load array. The source of the tenth NMOS transistor is connected to the drain of the eleventh NMOS transistor, and the gate of the tenth NMOS transistor is connected to the output terminal and the input terminal of the third inverter. The source of the eleventh NMOS transistor is grounded, and the gate of the eleventh NMOS transistor is connected to the second control signal.

6. The decision feedback equalizer according to claim 4, characterized in that, The latch includes: an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, and a fifteenth NMOS transistor, wherein, The source of the eleventh PMOS transistor is connected to the fifth power supply voltage, the drain of the eleventh PMOS transistor is connected to the drain of the twelfth PMOS transistor, and the gate of the eleventh PMOS transistor is connected to the second terminal of the sensitive signal amplifier. The source of the twelfth PMOS transistor is connected to the fifth power supply voltage, and the gate of the twelfth PMOS transistor is connected to the drain of the thirteenth PMOS transistor. The source of the thirteenth PMOS transistor is connected to the fifth power supply voltage, and the gate of the thirteenth PMOS transistor is connected to the drain of the eleventh PMOS transistor. The source of the fourteenth PMOS transistor is connected to the fifth power supply voltage, and the gate of the fourteenth PMOS transistor is connected to the third terminal of the sensitive signal amplifier and the first terminal of the feedback inverter array. The drain of the twelfth NMOS transistor is connected to the drain of the eleventh PMOS transistor and the drain of the thirteenth NMOS transistor. The source of the twelfth NMOS transistor is grounded, and the gate of the twelfth NMOS transistor is connected to the second terminal of the sensitive signal amplifier. The source of the thirteenth NMOS transistor is grounded, and the gate of the thirteenth NMOS transistor is connected to the drain of the thirteenth PMOS transistor. The drain of the fourteenth NMOS transistor is connected to the drain of the thirteenth PMOS transistor and the drain of the fifteenth NMOS transistor. The source of the fourteenth NMOS transistor is grounded, and the gate of the fourteenth NMOS transistor is connected to the drain of the eleventh PMOS transistor. The source of the fifteenth NMOS transistor is grounded, and the gate of the fifteenth NMOS transistor is connected to the gate of the fourteenth PMOS transistor.

7. A single-ended receiving device, characterized in that, include: The isolation circuit, the self-biased receiver front-end circuit, the serial-to-parallel converter, and the decision feedback equalizer according to any one of claims 1-6, wherein, The first terminal of the isolation circuit is connected to a data signal, and the second terminal of the isolation circuit is connected to the first terminal of the self-biased receiver front-end circuit. The second terminal of the self-biased receiver front-end circuit is connected to the first terminal of the main inverter array. The first terminal of the main inverter array is connected to a data signal, the second terminal of the main inverter array is connected to the first terminal of the load array, the third terminal of the main inverter array is connected to a first power supply voltage, the third terminal of the main inverter array is grounded, and the control terminal of the main inverter array is connected to a first control signal. The second terminal of the load array is connected to the first terminal of the comparator circuit, the third terminal of the load array is connected to the second power supply voltage, the fourth terminal of the load array is grounded, and the control terminal of the load array is connected to the load control word. The second terminal of the comparator circuit is connected to the first terminal of the serial-to-parallel converter, and the third terminal of the comparator circuit is connected to the first terminal of the feedback inverter array. The second terminal of the feedback inverter array is connected to the second terminal of the main inverter array, the third terminal of the feedback inverter array is connected to the third power supply voltage, the fourth terminal of the feedback inverter array is grounded, and the control terminal of the feedback inverter array is connected to the equalization coefficient control word. The second terminal of the serial-to-parallel converter outputs a data signal.

8. The single-ended receiving device according to claim 7, characterized in that, The isolation circuit includes an AC coupling capacitor.

9. The single-ended receiving device according to claim 8, characterized in that, The self-biased receiver front-end circuit includes: a gain circuit and a gain compensation circuit, wherein... The first terminal of the gain circuit is connected to the second terminal of the isolation circuit, and the second terminal of the gain circuit is connected to the first terminal of the gain compensation circuit. The second terminal of the gain compensation circuit is connected to the first terminal of the main inverter array, and the third terminal of the gain compensation circuit is connected to the gain control word.

10. The single-ended receiving device according to claim 9, characterized in that, The gain circuit includes: a fifteenth PMOS transistor, a sixteenth NMOS transistor, and an adjustable resistor, wherein, The source of the fifteenth PMOS transistor is connected to the sixth power supply voltage. The drain of the fifteenth PMOS transistor is connected to the drain of the sixteenth NMOS transistor, the first end of the adjustable resistor, and the first end of the gain compensation circuit. The gate of the fifteenth PMOS transistor is connected to the gate of the sixteenth NMOS transistor, the first end of the adjustable resistor, and the second end of the isolation circuit. The source of the sixteenth NMOS transistor is grounded.

11. The single-ended receiving device according to claim 9, characterized in that, The gain compensation circuit includes: a sixteenth PMOS transistor, a seventeenth PMOS transistor, a seventeenth NMOS transistor, an eighteenth NMOS transistor, and a fourth inverter, wherein, The source of the sixteenth PMOS transistor is connected to the seventh power supply voltage, the drain of the sixteenth PMOS transistor is connected to the source of the seventeenth PMOS transistor, and the gate of the sixteenth PMOS transistor is connected to the output terminal of the fourth inverter. The drain of the seventeenth PMOS transistor is connected to the drain of the seventeenth NMOS transistor, the gate of the seventeenth PMOS transistor is connected to the gate of the seventeenth NMOS transistor and the second terminal of the gain circuit, and the drain of the seventeenth PMOS transistor is connected to the first terminal of the main inverter array. The source of the seventeenth NMOS transistor is connected to the drain of the eighteenth NMOS transistor; The source of the eighteenth NMOS transistor is grounded, the gate of the eighteenth NMOS transistor is connected to the input terminal of the fourth inverter, and the gate of the eighteenth NMOS transistor is connected to the gain control word.

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