Manufacturing method of circuit board and circuit board

Abstract

The embodiment of the invention provides a circuit board manufacturing method and a circuit board, and the method comprises the steps: manufacturing a first circuit board according to a circuit design file, the circuit design file comprises a design position of a via hole 21, and the first circuit board comprises a first via hole formed according to the design position; measuring the actual position of the first via hole on the first circuit board; comparing the actual position with the design position to obtain offset data of the first via hole relative to the design position; correcting the design position according to the offset data to obtain an updated circuit design file; and manufacturing the circuit board according to the updated circuit design file. According to the method, data are measured by using a 3D AOI (Automatic Optic Inspection) machine, personnel perform corresponding compensation translation on windowing data of a windowing hole, namely a via hole in advance, pnl / set / pcs dynamic compensation windowing can be realized by LDI, the position precision of the via hole processed on a circuit board can be improved, and thus the reliability of the circuit board is improved.

Description

Technical Field

[0001] The present application relates to the technical field of circuit boards, and in particular to a method for manufacturing a circuit board and a circuit board. Background Art

[0002] Printed circuit boards (PCBs) are widely used in a variety of electronic devices, including power supplies, control systems, inverters, and other devices or systems. PCBs are typically equipped with vias, which are used to achieve electrical connections between different conductor layers.

[0003] With the development of miniaturization, high performance and multi-functionality of electronic equipment, the package size of circuit boards is getting smaller and smaller, making the processing of vias on circuit boards difficult and prone to inaccurate via positions. Summary of the Invention

[0004] The embodiments of the present application provide a method for manufacturing a circuit board and a circuit board, which can improve the position accuracy of via holes processed on the circuit board, thereby improving the reliability of the circuit board.

[0005] The present invention provides a method for manufacturing a circuit board, including: manufacturing a first circuit board according to a circuit design file, wherein the circuit design file includes a design position of a via hole, and the first circuit board includes a first via hole formed according to the design position; measuring an actual position of the first via hole on the first circuit board; Comparing the actual position with the designed position to obtain offset data of the first via relative to the designed position; Correcting the design position according to the offset data to obtain an updated circuit design file; A circuit board is manufactured according to the updated circuit design file.

[0006] In some embodiments, the circuit design file includes a plurality of vias and the first circuit board includes a plurality of first vias, and the offset data includes offset data of each first via relative to a design position of the corresponding via.

[0007] In some embodiments, the modifying the designed position according to the offset data includes: If the offset data of the plurality of first via holes are consistent, calculating average offset data according to the offset data of the plurality of first via holes, the average offset data including an offset direction and an offset amount; The design position of each via in the circuit design file is adjusted in a direction opposite to the offset direction by the offset amount.

[0008] In some embodiments, the modifying the designed position according to the offset data includes: If the offset data of the plurality of first vias are inconsistent, dividing the first circuit board into a plurality of areas, each of the areas including at least one first via; respectively calculating average offset data of one or more first vias in each of the regions, the average offset data including an offset direction and an offset amount; The offset amount is adjusted in the circuit design file and in the design position of each via hole corresponding to each region in the opposite direction of the offset direction.

[0009] In some embodiments, the offset data includes offset data in a first direction and offset data in a second direction, the first direction is perpendicular to the second direction, and a plane formed by the first direction and the second direction is a plane where the circuit of the first circuit board is located.

[0010] In some embodiments, comparing the actual position with the designed position to obtain offset data of the first via relative to the designed position includes: Comparing the first direction value of the actual position with the first direction value of the designed position to obtain offset data of the first direction; The second direction value of the actual position is compared with the second direction value of the designed position to obtain offset data of the second direction.

[0011] In some embodiments, measuring the actual position of the first via on the first circuit board includes: The first circuit board is scanned using a three-dimensional automatic optical detection device to obtain the actual position of the first via hole on the first circuit board.

[0012] The present application also provides a circuit board, including: A core board having a cavity formed thereon, wherein an embedded device is disposed in the cavity, and the embedded device includes a pad; A photosensitive material layer is provided on the core board and located on one side of the pad. A via is formed on the photosensitive material layer. The via is electrically connected to the pad and is formed according to the via in the circuit design file.

[0013] In some embodiments, the embedded device is a chip.

[0014] The circuit board manufacturing method provided in the embodiment of the present application uses 3D AOI machine measurement data, and personnel make corresponding compensatory translations in advance for the window opening data of the window hole, i.e., the via hole. LDI can realize pnl / set / pcs dynamic compensation window opening, which can improve the position accuracy of the via holes processed on the circuit board, thereby improving the reliability of the circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] To more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. Those skilled in the art can also derive other drawings based on these drawings without inventive effort.

[0016] Figure 1 Schematic diagram of the process of manufacturing a circuit board according to an embodiment of the present application.

[0017] Figure 2 This is a first structural schematic diagram of a circuit board according to an embodiment of the present application.

[0018] Figure 3 This is a second structural schematic diagram of the circuit board according to an embodiment of the present application.

[0019] Figure 4 This is a third structural schematic diagram of the circuit board according to an embodiment of the present application.

[0020] Figure 5 This is a fourth structural schematic diagram of the circuit board according to an embodiment of the present application.

[0021] Figure 6 This is a fifth structural diagram of a circuit board according to an embodiment of the present application; Figure 7 This is a sixth structural diagram of the circuit board according to an embodiment of the present application.

[0022] Among them, 100, circuit board; 10, core board; 11, cavity; 20, photosensitive material layer; 21, via; 30, insulation layer; 40, embedded device; 41, pad; 50, blind hole; 60, double-sided sputtering deposition seed layer; 70, copper layer. DETAILED DESCRIPTION

[0023] The following will be combined with the accompanying drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making any creative work are within the scope of protection of this application.

[0024] The present invention provides a method for manufacturing a circuit board 100. The method involves forming the circuit board 100 through a process involving patch placement, ABF (build-up insulating film) pressing, and tape removal, followed by data measurement using a 3D AOI machine (a type of automated inspection equipment based on optical imaging and three-dimensional reconstruction). Personnel then perform corresponding compensation translation in advance for the window opening data of the via 21. Laser direct imaging (LDI) allows for dynamic compensation of the window opening for pnl (panel), set (set unit), and pcs (piece), improving the positional accuracy of the via 21 machined on the circuit board 100 and thereby enhancing the reliability of the circuit board 100. Figure 1 , Figure 1 1 is a flow chart of a method for manufacturing a circuit board 100 according to an embodiment of the present application. The manufacturing method includes the following steps: 210, manufacturing a first circuit board according to a circuit design file, wherein the circuit design file includes a design position of the via hole 21, and the first circuit board includes a first via hole formed according to the design position; 220, measuring an actual position of a first via hole on a first circuit board; 230, comparing the actual position with the designed position to obtain offset data of the first via relative to the designed position; 240, correcting the design position according to the offset data to obtain an updated circuit design file; 250 , manufacturing the circuit board 100 according to the updated circuit design file.

[0025] Circuit design files are a complete set of documents describing the circuit principles, structure, layout, and manufacturing requirements in electronic engineering. They are used throughout the entire design, verification, production, and maintenance process. These files include the design location of via 21, which includes parameters such as its theoretical coordinates (X and Y coordinates), theoretical depth, and theoretical diameter. For example, Gerber files are an industry-standard format for describing circuit board geometry in PCB manufacturing. They are equivalent to "digital blueprints" of PCBs, defining all manufacturing details such as copper layers, solder mask, and drill holes, serving as a bridge between design and production. Another example is ODB++ files. ODB++ (Open Database++) is an open data exchange format widely used in PCB design and manufacturing. Developed by Valor Computerized Systems (now part of Siemens EDA), ODB++ is an open data exchange format widely used in PCB design and manufacturing. It was developed by Valor Computerized Systems (now part of Siemens EDA) to replace the traditional Gerber file format, providing more complete and structured manufacturing data and optimizing the design-to-production process. The first circuit board is in its initial state. Vias 21 are key structures in PCBs that enable multi-layer signal interconnection and directly impact circuit performance, reliability, and manufacturability. The via hole 21 is specifically formed on the photosensitive material layer 20 of the circuit board 100 by exposure and development or laser drilling.

[0026] As an example, when manufacturing circuit board 100, a first circuit board is first manufactured according to the circuit design file. Specifically, a first via hole 21 is formed in the photosensitive material layer 20 of first circuit board 100 according to the designed location of the via hole 21 in the Gerber file or ODB++ file. For example, the photosensitive material layer 20 of circuit board 100 can be patterned to form the via hole 21 in the following manner: After pre-treating the copper foil surface (e.g., cleaning with an abrasive brush or chemical cleaning), a photoresist is applied to the copper foil surface using a dry or wet film process. UV light is then irradiated (exposed) to portions of the photoresist, causing a photochemical reaction to form a basic pattern. A chemical solution is used to dissolve the photoresist in the exposed areas (i.e., the areas irradiated by the UV light), exposing the copper surface to be etched. An acidic or alkaline etching solution is then used to dissolve the exposed copper surface, forming the desired circuit pattern and window. A dedicated stripping solution is then used to remove any remaining photoresist. Subsequently, plasma etching is performed on the photosensitive material layer 20 to form the via hole 21. Subsequently, a conductive layer is formed in the via 21. For example, a uniform metal seed layer can be deposited on the inner wall of the via 21 through a sputtering process. The metal seed layer can be a thin layer of copper or titanium copper. Then, a copper layer of a certain thickness is formed on the metal seed layer through an electroplating process, thereby forming a conductive layer in the via 21.

[0027] Subsequently, the designer uses 3D AOI to measure the actual position of the first via on the first circuit board. Specifically, the designer uses three-dimensional automatic optical inspection equipment (for example, high-precision 3D AOI equipment) to scan the first circuit board to obtain the actual position of the first via on the first circuit board, that is, the actual three-dimensional coordinate data, and records key parameters such as the position (X, Y coordinates), depth and aperture of each first via.

[0028] Subsequently, designers used 3D AOI to compare the actual positions obtained with the designed positions, obtaining offset data for the first vias relative to the designed positions. Specifically, the position (X, Y coordinates), depth, and diameter of each first via were compared with the original designed coordinates (the theoretical coordinates (X, Y coordinates), theoretical depth, and theoretical diameter in the Gerber file), and the deviation (ΔX, ΔY) for each via was calculated and statistically analyzed. The circuit design file includes multiple vias 21, and the first circuit board includes multiple first vias. The offset data includes the offset data for each first via relative to the designed position of the corresponding via 21. This allows for the acquisition of multiple sets of data, providing more accurate data analysis for subsequent work, thereby improving reliability.

[0029] Subsequently, the designer uses 3D AOI to correct the design position based on the offset data, obtaining an updated circuit design file. Specifically, based on the comparison results, if the offset data of multiple first vias is consistent, that is, the offset is overall, that is, the multiple first vias exhibit systematic deviation (for example, all offset in the same direction), then the average offset data is calculated based on the offset data of multiple first vias. Then, based on the deviation analysis results, the compensation direction and value are determined. Specifically, the design position of each via 21 in the circuit design file is adjusted in the opposite direction of the offset direction. The graphics are then translated in the Gerber file or ODB++ file, and the compensation value is applied to obtain the updated circuit design file. If the offset data for multiple first vias is inconsistent, or localized,—that is, if the multiple first vias exhibit localized deviations and uneven distribution—then the first circuit board is divided into multiple regions (e.g., the four corners or the center of the PCB) for statistical analysis, with each region containing at least one first via. The average offset data for one or more first vias within each region is calculated. Based on the deviation analysis results for each region, a compensation direction and value are determined for each region. Specifically, the design position of each via 21 in the circuit design file corresponding to each region is adjusted in the opposite direction of the offset. The design is then translated in the Gerber or ODB++ file, and the compensation value is applied to generate an updated circuit design file. Finally, the circuit board is manufactured based on the updated circuit design file. In this example, by using 3D AOI measurement data, personnel pre-programmed compensation for the window opening data of the via 21. LDI enables dynamic window opening compensation (pnl, set, or pcs), improving the positional accuracy of the vias 21 machined on the circuit board 100 and thereby enhancing the reliability of the circuit board 100.

[0030] The average offset data includes an offset direction and an offset amount, and the offset data includes offset data in a first direction and offset data in a second direction. The first direction is perpendicular to the second direction, and the plane formed by the first direction and the second direction is the plane where the circuit of the first circuit board is located. For example, the first direction is the X direction on the first circuit board, and the second direction is the Y direction on the first circuit board.

[0031] In some examples, the design position of each via 21 in the circuit design file is adjusted in the opposite direction of the offset direction. Specifically, the first-direction value of the actual position is compared with the first-direction value of the designed position to obtain the first-direction offset data; and the second-direction value of the actual position is compared with the second-direction value of the designed position to obtain the second-direction offset data. The software tools used in the above content are CAM software (such as CAM350, Genesis) or batch scripts. The CAM software or scripts batch-translate the graphics in the Gerber or ODB++ files and apply the compensation value to adjust the design position of the via 21 in the windowing data, ensuring efficiency and accuracy. For example, if 3D AOI measurement shows that the actual position of the via 21 is offset by 0.05mm in the X direction and by 0.03mm in the Y direction, the graphics in the Gerber or ODB++ file are translated and the compensation value is applied. In other words, the design position of the via 21 in the windowing data in the CAM software needs to be adjusted by 0.05mm in the X direction and 0.03mm in the Y direction. If 3D AOI measurement shows that the actual position of via 21 is offset by 0.08mm in the X direction and 0.05mm in the Y direction, then the graphic should be translated in the Gerber or ODB++ file and the compensation values ​​should be applied. In other words, in the CAM software, the design position of via 21 in the windowing data should be reduced by 0.08mm in the X direction and increased by 0.05mm in the Y direction.

[0032] In some examples, after obtaining the updated circuit design file, verification and iterative secondary testing can be performed. Specifically, circuit board 100 is manufactured according to the updated circuit design file, and the actual position of via 21 on the first circuit board is measured again using 3D AOI to confirm whether the actual position of via 21 is aligned with the actual position of via 21 in the circuit design file. If there is still a deviation, the analysis is repeated and the compensation value is fine-tuned until the accuracy requirement is met (usually ≤±7μm). After verification, the alignment accuracy is improved. Through a systematic data-driven compensation process, the position accuracy of via 21 processed on circuit board 100 can be effectively improved, thereby enhancing reliability and production efficiency. In addition, for the production of multiple batches of circuit boards, a real-time feedback system can be established to automatically update the compensation parameters to improve production efficiency.

[0033] An embodiment of the present application provides a circuit board 100. The circuit board 100 can be applied to devices or systems such as power supplies, control systems, and inverters.

[0034] refer to Figure 2-Figure 7 , Figure 2 This is a first structural diagram of the circuit board 100 according to an embodiment of the present application. Figure 3 This is a second structural diagram of the circuit board 100 according to an embodiment of the present application. Figure 4This is a third structural diagram of the circuit board 100 according to an embodiment of the present application. Figure 5 This is a fourth structural diagram of the circuit board 100 according to an embodiment of the present application. Figure 6 This is a fifth structural diagram of the circuit board 100 according to an embodiment of the present application. Figure 7 FIG6 is a sixth structural diagram of a circuit board 100 according to an embodiment of the present application. The circuit board 100 includes a core board 10 and a photosensitive material layer 20 .

[0035] The core substrate 10 may be a copper-clad laminate, which includes a substrate and copper layers covering both sides of the substrate. For example, the substrate can be FR4 (epoxy fiberglass) or other high-frequency substrates, which can provide mechanical support. Both sides of the substrate are covered with copper foil having a thickness of 18μm to 35μm. The copper foil can be chemically etched to form the desired circuit pattern. An insulating layer 30 and a conductive layer attached to the insulating layer are provided on the first surface of the core substrate 10. The conductive layer can be copper foil. For example, the insulating layer 30 can be an epoxy insulating film (ABF) having a thickness of 20μm to 50μm, and the copper foil can be an electrolytic copper foil having a thickness of 5μm to 12μm. The copper foil can be chemically etched to form the desired circuit pattern. In practical applications, the copper foil can be roughened to enhance adhesion to the ABF. This allows the core substrate 10 to have a multilayer circuit pattern.

[0036] When manufacturing the circuit board 100, one or more cavities 11 are first formed on the core board 10. When there are multiple cavities 11, the multiple cavities 11 are spaced apart. Figure 2 As shown. The cavity 11 can be formed by laser cutting or mechanical cutting. The shape, size, and depth of the cavity 11 can be set according to requirements. In practical applications, the cavity 11 can be a square cavity and pass through the core plate 10.

[0037] Then, if Figure 2 As shown, an embedded device 40 is provided in the cavity. The number of embedded devices 40 is the same as the number of cavities 11, and one embedded device 40 is provided in each cavity 11. The embedded device 40 can be a functional module such as a chip, an antenna, or an electronic component such as a resistor, a capacitor, or an inductor. For example, in one example, the embedded device 40 is a chip. The embedded device 40 includes a solder pad 41, specifically, a solder pad 41 is provided on a surface of the embedded device 40 away from the insulating layer 30. The solder pad 41 can be used to achieve electrical connection between other electronic components or circuits and the chip. It can be understood that in actual applications, the number of the solder pads 41 is multiple, and the multiple solder pads 41 are spaced apart from each other.

[0038] Then, if Figure 3As shown, a blind hole 50 is laser-printed on the insulating layer 30 on the first surface of the core board 10, and a photosensitive material layer 20 is laminated on the second surface of the core board 10. The photosensitive material layer 20 is located on one side of the pad 41. There are multiple blind holes 50.

[0039] Then, if Figure 4 As shown, vias 21 are formed in the photosensitive material layer 20 and are electrically connected to the pads 41. Specifically, the photosensitive material layer 20 of the circuit board 100 can be patterned to form the vias 21 in the following manner: After pre-treating the copper foil surface (e.g., cleaning with an abrasive brush and chemically cleaning), photoresist is applied to the copper foil surface using a dry or wet film process. UV light is then irradiated (exposed) to portions of the photoresist, causing a photochemical reaction to form a basic pattern. A chemical solution dissolves the photoresist in the exposed areas (i.e., the areas irradiated by UV light), exposing the copper surface to be etched. An acidic or alkaline etching solution is used to dissolve the exposed copper surface, forming the desired circuit pattern and window. A dedicated stripping solution is then used to remove any remaining photoresist. Subsequently, the photosensitive material layer 20 is plasma etched to form the vias 21.

[0040] Subsequently, a conductive layer is formed within the via 21. For example, a uniform metal seed layer can be deposited on the inner wall of the via 21 through a sputtering process. The metal seed layer can be a thin layer of copper or titanium copper. Then, a copper layer of a certain thickness is formed on the metal seed layer through an electroplating process, thereby forming a conductive layer within the via 21. Therefore, the via 21 can also be understood as a metallized hole. Thus, other electronic components or circuits can be electrically connected to the pad 41 of the embedded device 40 through the via 21. Among them, the via 21 is formed according to the via 21 in the circuit design file. Specifically, the first circuit board is manufactured according to the circuit design file, and the circuit design file includes the design position of the via 21. First, the first circuit board includes a first via formed according to the design position; then the actual position of the first via on the first circuit board is measured; then the actual position is compared with the design position to obtain the offset data of the first via relative to the design position; then the design position is corrected according to the offset data to obtain an updated circuit design file; finally, the circuit board is manufactured according to the updated circuit design file, which can improve the position accuracy of the via 21 processed on the circuit board 100, thereby improving the reliability of the circuit board 100.

[0041] The circuit board 100 of the embodiment of the present application is provided with an embedded device 40 in the core board 10, which can directly embed the device inside the core board 10, reduce the overall volume of the circuit board 100, and realize the miniaturization of the circuit board 100, and form a via 21 on the PVF build-up layer through exposure and development. The conductive layer in the via 21 is connected to the pad 41 of the embedded device 40. Compared with laser processing, the via 21 of the embodiment of the present application has high processing accuracy, is easy to control the etching depth and accuracy, can avoid the poor hole shape caused by the high temperature and heat of laser processing, and does not have the risk of environmental pollution. It can improve the processing accuracy of the via 21 on the circuit board, effectively increase the wiring density of the circuit board 100, and improve the performance of the circuit board.

[0042] Then, if Figure 5 、 Figure 6 and Figure 7 As shown, in the manufacture of the circuit board, the blind hole 50 and the via 21 are first subjected to double-sided sputtering to deposit a seed layer 60, and then a copper layer 70 is electroplated. Finally, the excess material on the copper layer is removed by etching technology to form the blind hole 50. Among them, the double-sided sputtering deposition seed layer 60 can be used to prepare a metal interconnection layer, a barrier layer and a seed layer to improve the conductivity and reliability of the circuit. The electroplated copper layer 70 is used to thicken the hole copper and the pattern copper to ensure the reliability and conductivity of the interlayer interconnection. For example, the copper layer in the hole is thickened by electroplating the copper layer so that its thickness reaches more than 20 microns, which meets the requirements of a multi-layer circuit board. The excess material on the copper layer is removed by etching technology to form a blind hole 50, and the electrical interconnection of the multi-layer circuit board is achieved by combining the interlayer connection technology to form a complete circuit path.

[0043] This document uses specific examples to illustrate the principles and implementation methods of this application. The description of the above examples is only intended to help understand this application. At the same time, those skilled in the art may vary the specific implementation methods and application scope based on the ideas of this application. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A method for manufacturing a circuit board, characterized in that: include: manufacturing a first circuit board according to a circuit design file, wherein the circuit design file includes a design position of a via hole, and the first circuit board includes a first via hole formed according to the design position; measuring an actual position of the first via hole on the first circuit board; Comparing the actual position with the designed position to obtain offset data of the first via relative to the designed position; Correcting the design position according to the offset data to obtain an updated circuit design file; A circuit board is manufactured according to the updated circuit design file.

2. The manufacturing method according to claim 1, characterized in that The circuit design file includes a plurality of vias, and the first circuit board includes a plurality of first vias. The offset data includes offset data of each first via relative to a design position of the corresponding via.

3. The manufacturing method according to claim 2, characterized in that The correcting the designed position according to the offset data includes: If the offset data of the plurality of first via holes are consistent, calculating average offset data according to the offset data of the plurality of first via holes, the average offset data including an offset direction and an offset amount; The design position of each via in the circuit design file is adjusted in a direction opposite to the offset direction by the offset amount.

4. The manufacturing method according to claim 2, characterized in that The correcting the designed position according to the offset data includes: If the offset data of the plurality of first vias are inconsistent, dividing the first circuit board into a plurality of areas, each of the areas including at least one first via; respectively calculating average offset data of one or more first vias in each of the regions, the average offset data including an offset direction and an offset amount; The offset amount is adjusted in the circuit design file and in the design position of each via hole corresponding to each region in the opposite direction of the offset direction.

5. The manufacturing method according to any one of claims 1 to 4, characterized in that: The offset data includes offset data in a first direction and offset data in a second direction. The first direction is perpendicular to the second direction. A plane formed by the first direction and the second direction is a plane where the circuit of the first circuit board is located.

6. The manufacturing method according to claim 5, characterized in that The comparing the actual position with the designed position to obtain offset data of the first via relative to the designed position includes: Comparing the first direction value of the actual position with the first direction value of the designed position to obtain offset data of the first direction; The second direction value of the actual position is compared with the second direction value of the designed position to obtain offset data of the second direction.

7. The manufacturing method according to any one of claims 1 to 4, characterized in that: Measuring the actual position of the first via hole on the first circuit board includes: The first circuit board is scanned using a three-dimensional automatic optical detection device to obtain the actual position of the first via hole on the first circuit board.

8. A circuit board, characterized in that: The circuit board is manufactured by the manufacturing method according to any one of claims 1 to 7.

9. The circuit board according to claim 8, wherein: include: A core board having a cavity formed thereon, wherein an embedded device is disposed in the cavity, and the embedded device includes a pad; A photosensitive material layer is provided on the core board and located on one side of the pad. A via is formed on the photosensitive material layer. The via is electrically connected to the pad and is formed according to the via in the circuit design file.

10. The circuit board according to claim 9, wherein: The embedded device is a chip.

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