Radiation-proof reinforced Flash storage unit, memory and method
By connecting two isolated floating gate units in parallel in the Flash storage unit and judging the data state based on the total number of electrons, the data flipping problem of the Flash memory in the space radiation environment is solved, and the data stability and radiation resistance performance are improved.
Patent Information
- Application Number
- CN202511225816.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-29
- Publication Date
- 2025-10-03
AI Technical Summary
Existing Flash memories are prone to data errors due to single-particle upsets in space radiation environments. Traditional reinforcement technologies such as DICE cannot be applied to floating-gate cells, and triple-mode redundancy technology sacrifices cell area and power consumption.
A first floating gate unit and a second floating gate unit are arranged in parallel, which are physically isolated by a set isolation distance. The data state is determined according to the total number of electrons stored in the two floating gate units to ensure data stability.
The design is simplified and easy to implement, which significantly improves the anti-flip performance of the storage unit and ensures the data stability of the Flash memory in a space environment.
Smart Images
Figure CN120751705A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of integrated circuit reinforcement design, and relates to an anti-radiation reinforced Flash storage unit and a data storage method. Background Art
[0002] The storage unit of the Flash memory is a single floating gate unit. When the floating gate unit needs to be filled with data "0", a programming operation is performed, that is, a write voltage is applied to the control gate of the unit where data needs to be written, and the substrate is grounded at the same time. Electrons in the floating gate are injected, and the floating gate unit stores data "0"; when the floating gate unit needs to be filled with data "1", an erase operation is performed, that is, an erase voltage is applied to the substrate, and the control gate is grounded at the same time. The electrons in the floating gate are pulled out to the substrate, and the floating gate unit stores data "1".
[0003] When Flash memory operates in a space radiation environment, the data stored in the Flash memory may flip, causing malfunctions in the electronic system where the memory resides, such as data errors or program anomalies. For example, research has found that when a single high-energy particle strikes a floating gate cell, it causes a localized, transient high-density charge accumulation, resulting in a large loss of electrons stored in the floating gate cell. This causes an error in the floating gate cell, causing the data in the floating gate cell to flip from "0" to "1." In such cases, technical measures are needed to improve the radiation resistance of the Flash memory's storage cells to reduce the memory's soft error rate.
[0004] Numerous literature has proposed design hardening techniques for memory cells to resist single-event upsets, such as dual interlocked storage cells (DICE) and triple-module redundancy. These techniques are widely used in memory cells such as latches, flip-flops, and SRAM cells. However, due to different data storage mechanisms, DICE cannot be applied to floating-gate cells for hardening, while triple-module redundancy sacrifices significant cell area and increases power consumption. Therefore, designing hardened Flash memory cells to improve their resistance to upsets has become a technical challenge. Summary of the Invention
[0005] In response to the problems existing in the above-mentioned traditional technologies, the present invention proposes a radiation-hardened Flash storage unit, a radiation-hardened Flash memory, and a Flash unit data storage method, which can effectively strengthen the storage unit of the Flash memory and improve the anti-flip performance of the storage unit.
[0006] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: In one aspect, a radiation-hardened Flash memory cell is provided, comprising a first floating gate cell and a second floating gate cell arranged in parallel, wherein the first floating gate cell and the second floating gate cell are physically isolated by a set isolation distance; the control gate of each floating gate cell has the same connection mode, the source has the same connection mode, the drain has the same connection mode, and the substrate has the same connection mode; When the total number of electrons stored in the two floating gate cells is greater than or equal to x, the data state of the storage cell is 0. When the total number of electrons stored in the two floating gate cells is less than x, the data state of the storage cell is 1. x is the total number of electrons when a single floating gate cell is full of electrons.
[0007] On the other hand, a radiation-hardened Flash memory is provided, comprising a plurality of identical memory cells, each comprising a first floating gate cell and a second floating gate cell connected in parallel, the first floating gate cell and the second floating gate cell being physically isolated by a set isolation distance; each floating gate cell has a control gate connected in the same manner, a source connected in the same manner, a drain connected in the same manner, and a substrate connected in the same manner; When the total number of electrons stored in the two floating gate cells is greater than or equal to x, the data state of the storage cell is 0. When the total number of electrons stored in the two floating gate cells is less than x, the data state of the storage cell is 1. x is the total number of electrons when a single floating gate cell is full of electrons.
[0008] In another aspect, a Flash unit data storage method is provided, which is applied to a radiation-hardened Flash memory cell, wherein the memory cell includes a first floating gate cell and a second floating gate cell arranged in parallel, the first floating gate cell and the second floating gate cell being physically isolated by a set isolation distance; the control gate of each floating gate cell is connected in the same manner, the source is connected in the same manner, the drain is connected in the same manner, and the substrate is connected in the same manner; When the total number of electrons stored in the two floating gate cells is greater than or equal to x, the data state of the storage cell is 0, and when the total number of electrons stored in the two floating gate cells is less than x, the data state of the storage cell is 1; x is the total number of electrons when a single floating gate cell is full of electrons; The above-mentioned Flash unit data storage method comprises the steps of: A programming operation is performed on the memory cell to fill the memory cell with data 0; the programming operation is to apply a write voltage to the control gates of the two floating gate cells respectively, and at the same time, the substrates of the two floating gate cells are grounded respectively.
[0009] One of the above technical solutions has the following advantages and beneficial effects: The above-mentioned radiation-hardened Flash storage unit, memory and method, by connecting two floating gate units in parallel into one storage unit, use two floating gate units to store the same data, and judge the data state of the storage unit based on the total number of electrons stored in the two floating gate units. When one of the floating gate units has a reduction in electrons due to heavy ion irradiation, since the total number of electrons stored in the two floating gate units will still be greater than the total number of electrons when a single floating gate unit is full of electrons, the data of the storage unit is ensured not to change. The structural design is simple and easy to implement, which greatly improves the anti-flip performance of the storage unit and ensures the data stability of the storage unit of the Flash memory in a space environment. BRIEF DESCRIPTION OF THE DRAWINGS
[0010] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0011] Figure 1 Schematic diagram of the structure of a radiation-hardened Flash storage unit in one embodiment; Figure 2 A schematic diagram of programming and erasing operations of a memory cell according to one embodiment; Figure 2 (a) is the programming operation of memory cell A. Figure 2 (b) is the erase operation of memory cell B; Figure 3 Schematic diagram of the total amount of electrons in a floating gate of a memory cell before and after electron irradiation in one embodiment; Figure 3 (a) is the total amount of electrons in the floating gate of memory cell A before and after electron irradiation. Figure 3 (b) is the total amount of electrons in the floating gate of memory cell B before and after electron irradiation; Figure 4 Schematic diagram of the unit composition of a radiation-hardened Flash memory in one embodiment; Figure 5 FIG. 4 is a flow chart of a Flash unit data storage method according to an embodiment. DETAILED DESCRIPTION
[0012] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and Examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the description of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.
[0013] It should be noted that, when referred to in this document as an "embodiment", it means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present invention. The presentation of this phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It will be understood by those skilled in the art that the embodiments described herein may be combined with other embodiments. The term "and / or" used in this document refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.
[0014] The following describes the implementation of the present invention in detail with reference to the accompanying drawings in the embodiments of the present invention.
[0015] In one embodiment, Figure 1 As shown, a radiation-hardened Flash memory cell is provided, comprising a first floating gate cell and a second floating gate cell arranged in parallel, the first floating gate cell and the second floating gate cell being physically isolated by a set isolation distance. Each floating gate cell has the same control gate connection, source connection, drain connection, and substrate connection. When the total number of electrons stored in the two floating gate cells is greater than or equal to x, the data state of the memory cell is 0; when the total number of electrons stored in the two floating gate cells is less than x, the data state of the memory cell is 1; x is the total number of electrons when a single floating gate cell is full of electrons. Figure 1 D is the set isolation distance, e - For electronics.
[0016] It can be understood that in this embodiment, two floating gate cells are connected in parallel to form a memory cell. The two floating gate cells have the same parameter specifications. The two parallel floating gate cells have the same circuit connection relationship at the circuit layout position of the memory cell to which they belong, that is, the connection method of the control gate of the first floating gate cell is the same as the connection method of the control gate of the second floating gate cell, the connection method of the source of the first floating gate cell is the same as the connection method of the source of the second floating gate cell, the connection method of the drain of the first floating gate cell is the same as the connection method of the drain of the second floating gate cell, and the connection method of the substrate of the first floating gate cell is the same as the connection method of the substrate of the second floating gate cell. This ensures that during the process of performing a programming operation or an erasing operation on the memory cell, the two floating gate cells inside operate in exactly the same manner, thereby storing the same data.
[0017] To prevent the same heavy ion from causing simultaneous electron leakage in two parallel floating gate cells, the two floating gate cells must be physically isolated on the circuit layout by a set isolation distance D. This isolation distance D is primarily determined by the process node and the heavy ion LET (Linear Energy Transfer) value. LET is a physical quantity that describes the energy loss per unit path length of a charged particle (such as heavy ions and protons) when penetrating a material, and is measured in MeV cm² / mg. In semiconductor devices, the LET value directly reflects the particle's ionization ability: the higher the LET value, the more electron-hole pairs are generated per unit path length, and the greater the risk of single-event effects (SEEs) such as SEE and SEE lockup.
[0018] As process nodes shrink (e.g., from 14nm to 7nm), the physical size of floating gate cells decreases, and the distance between floating gate cells decreases, dramatically increasing their sensitivity to single-event radiation. For example, when a particle strikes a floating gate cell, the resulting electron-hole pairs are collected by that floating gate cell and its surrounding cells, causing the threshold voltages of multiple cells to shift, potentially causing errors in those cells. Consequently, shrinking process nodes results in more cells being susceptible to single-event effects.
[0019] To prevent the same heavy ion from causing simultaneous electron leakage in two parallel floating gate cells, the physical locations of the two floating gate cells should be staggered as much as possible. In practical applications, the first floating gate cell can be placed in a first array, and the second floating gate cell in a second array. This way, the two floating gate cells are separated by a physical distance of one array, making simultaneous electron leakage virtually impossible.
[0020] Specifically, assuming that the total number of electrons when a floating gate unit is filled with electrons is x, when the total number of electrons stored in the two floating gate units in the storage unit is greater than or equal to x, the data state of the storage unit is "0"; conversely, when the total number of electrons stored in the two floating gate units in the storage unit is less than x, the data state of the storage unit is "1".
[0021] like Figure 2 As shown, Figure 2 (a) is the programming operation of memory cell A. Figure 2 (b) is the erase operation of memory cell B. When the memory cell needs to be filled with data "0", the programming operation is performed. Figure 2 Taking the memory cell A in FIG as an example, a write voltage is applied to the control gates of the floating gate cells A1 and A2, and the substrates of both are grounded. The two floating gate cells are filled with electrons, and the data state of the memory cell A is "0".
[0022] When a memory cell needs to be filled with data "1", an erase operation is performed. Figure 2 Taking the memory cell B in the example, an erase voltage is applied to the substrates of the floating gate cells B1 and B2, and at the same time, the control gates of both are grounded. The electrons stored in the two floating gate cells are pulled out to the substrate, and the data state of the memory cell B is "1".
[0023] like Figure 3 As shown, Figure 3 In (a), when the floating gate electron count of one of the floating gate cells of memory cell A decreases due to heavy ion irradiation, the total number of electrons stored in the two floating gate cells will still be greater than x, so that the data state of memory cell A remains "0", thereby achieving an anti-flip effect. Figure 3 In (b), because the total number of electrons stored in the two floating gate cells of memory cell B with data "1" is less than x, memory cell B with data "1" does not flip due to heavy ion irradiation. In the figure, Vcg is the control gate voltage, Vs is the source voltage, Vd is the drain voltage, and Vb is the substrate voltage.
[0024] The above-mentioned radiation-resistant reinforced Flash storage unit connects two floating gate units in parallel into one storage unit, uses two floating gate units to store the same data, and judges the data state of the storage unit based on the total number of electrons stored in the two floating gate units. When one of the floating gate units has a reduction in electrons due to heavy ion irradiation, the total number of electrons stored in the two floating gate units will still be greater than the total number of electrons when a single floating gate unit is full of electrons, thereby ensuring that the data of the storage unit does not change. This structural design is simple and easy to implement, which greatly improves the anti-flip performance of the storage unit and ensures the data stability of the storage unit of the Flash memory in a space environment.
[0025] In one embodiment, Figure 4 A radiation-hardened Flash memory is also provided, comprising a plurality of identical memory cells, each comprising a first floating gate cell and a second floating gate cell arranged in parallel, the first floating gate cell and the second floating gate cell being physically isolated by a predetermined isolation distance. Each floating gate cell has the same control gate connection, source connection, drain connection, and substrate connection. When the total number of electrons stored in the two floating gate cells is greater than or equal to x, the data state of the memory cell is 0; when the total number of electrons stored in the two floating gate cells is less than x, the data state of the memory cell is 1; x is the total number of electrons when a single floating gate cell is full of electrons.
[0026] It will be understood that each memory cell in the Flash memory of this embodiment utilizes a radiation-hardened Flash memory cell with a reinforced design. The detailed explanation of this embodiment can be similarly understood with reference to the description of the radiation-hardened Flash memory cell embodiment described above. Furthermore, the specific circuit connections of each memory cell on the circuit layout can be similarly understood with reference to the existing circuit connections of each memory cell in conventional Flash memories in the art, and will not be further elaborated here. N is the total number of memory cells in the radiation-hardened Flash memory.
[0027] The above-mentioned radiation-hardened Flash memory is constructed by connecting two floating gate units in parallel for each storage unit. The two floating gate units store the same data, and the data state of the storage unit is judged based on the total number of electrons stored in the two floating gate units. When one of the floating gate units has a decrease in electrons due to heavy ion irradiation, the total number of electrons stored in the two floating gate units will still be greater than the total number of electrons when a single floating gate unit is full of electrons, thereby ensuring that the data of the storage unit does not change. This structural design is simple and easy to implement, which greatly improves the anti-flip performance of the storage unit and ensures the data stability of the Flash memory in a space environment.
[0028] In one embodiment, Figure 5 A Flash cell data storage method is also provided, which is applied to a radiation-hardened Flash memory cell. The memory cell includes a first floating gate cell and a second floating gate cell arranged in parallel, and the first floating gate cell and the second floating gate cell are physically isolated by a set isolation distance. The control gate, source, drain, and substrate of each floating gate cell are connected in the same manner. When the total number of electrons stored in the two floating gate cells is greater than or equal to x, the data state of the memory cell is 0; when the total number of electrons stored in the two floating gate cells is less than x, the data state of the memory cell is 1; x is the total number of electrons when a single floating gate cell is full of electrons.
[0029] The above-mentioned Flash unit data storage method may include the following step S12: S12, performing a programming operation on the memory cell to fill the memory cell with data 0; the programming operation is to apply a write voltage to the control gates of the two floating gate cells respectively, and at the same time, ground the substrates of the two floating gate cells respectively.
[0030] It can be understood that the specific explanation of the radiation-hardened Flash storage unit in this embodiment can be understood by referring to the description of the above-mentioned radiation-hardened Flash storage unit embodiment, and will not be repeated here.
[0031] The above-mentioned Flash unit data storage method utilizes an improved radiation-hardened Flash storage unit. When one of the floating gate units has a reduction in electrons due to heavy ion irradiation, the total number of electrons stored in the two floating gate units will still be greater than the total number of electrons when a single floating gate unit is full of electrons. Therefore, it ensures that the data filled in the storage unit does not change. This structural design is simple and easy to implement, which greatly improves the anti-flip performance of the storage unit and ensures the data stability of the storage unit of the Flash memory in a space environment.
[0032] In one embodiment, when one of the floating gate cells in a memory cell experiences a reduction in floating gate electrons due to heavy ion irradiation, the data state of the memory cell remains unchanged if the total number of electrons stored in both floating gate cells is greater than x. This reinforced design of parallel dual floating gate cells can significantly improve the memory cell's anti-flip performance.
[0033] In one embodiment, Figure 5 As shown, the above Flash unit data storage method may further include the following step S14: S14, performing an erase operation on the memory cell to fill the memory cell with data 1; the erase operation is to apply an erase voltage to the substrates of the two floating gate cells respectively, and at the same time, ground the control gates of the two floating gate cells respectively.
[0034] By performing an erase operation on the improved storage cell to fill the data "1", since the total number of electrons stored in the two floating gate units in the storage cell with data "1" is less than x, the storage cell with data "1" will not be flipped due to heavy ion irradiation, ensuring the data stability in this data state.
[0035] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0036] The above embodiments merely illustrate several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of the present invention.
Claims
1. A radiation-hardened Flash storage unit, characterized in that: The method comprises a first floating gate unit and a second floating gate unit arranged in parallel, wherein the first floating gate unit and the second floating gate unit are physically isolated from each other by a set isolation distance; the connection mode of the control gate of each floating gate unit is the same, the connection mode of the source electrode is the same, the connection mode of the drain electrode is the same, and the connection mode of the substrate is the same; When the total number of electrons stored in the two floating gate cells is greater than or equal to x, the data state of the storage cell is 0. When the total number of electrons stored in the two floating gate cells is less than x, the data state of the storage cell is 1. x is the total number of electrons when a single floating gate cell is full of electrons.
2. A radiation-hardened Flash memory, characterized in that: The invention comprises a plurality of identical memory cells, each memory cell comprising a first floating gate cell and a second floating gate cell arranged in parallel, the first floating gate cell and the second floating gate cell being physically isolated by a set isolation distance; the control gate of each floating gate cell has the same connection mode, the source has the same connection mode, the drain has the same connection mode, and the substrate has the same connection mode; When the total number of electrons stored in the two floating gate cells is greater than or equal to x, the data state of the storage cell is 0. When the total number of electrons stored in the two floating gate cells is less than x, the data state of the storage cell is 1. x is the total number of electrons when a single floating gate cell is full of electrons.
3. A Flash unit data storage method, characterized in that: The invention is applied to a radiation-hardened Flash memory cell, the memory cell comprising a first floating gate cell and a second floating gate cell arranged in parallel, the first floating gate cell and the second floating gate cell being physically isolated by a set isolation distance; the control gate of each floating gate cell has the same connection mode, the source electrode has the same connection mode, the drain electrode has the same connection mode, and the substrate has the same connection mode; When the total number of electrons stored in the two floating gate cells is greater than or equal to x, the data state of the storage cell is 0, and when the total number of electrons stored in the two floating gate cells is less than x, the data state of the storage cell is 1; x is the total number of electrons when a single floating gate cell is full of electrons; The Flash unit data storage method comprises the steps of: A programming operation is performed on the memory cell to fill the memory cell with data 0; the programming operation is to apply a write voltage to the control gates of the two floating gate cells respectively, and at the same time, the substrates of the two floating gate cells are grounded respectively.
4. The Flash unit data storage method according to claim 3, characterized in that: Also includes the steps: An erase operation is performed on the memory cell to fill the memory cell with data 1. The erase operation is to apply an erase voltage to the substrates of the two floating gate cells respectively, and at the same time, the control gates of the two floating gate cells are grounded respectively.
5. The Flash unit data storage method according to claim 3 or 4, characterized in that: When one of the floating gate cells in the memory cell has a floating gate electron reduction due to heavy ion irradiation, if the total number of electrons stored in the two floating gate cells is greater than x, the data state of the memory cell remains unchanged.