GaN-based diode and preparation method thereof
By integrating a recessed Schottky diode and a gate-adjustable structure into a GaN-based diode, the contradiction between high withstand voltage and low reverse turn-on voltage is resolved, achieving the performance of high withstand voltage and low reverse conduction voltage drop. This is compatible with commercial p-GaN gate HEMT processes, avoiding additional process steps and reducing costs.
Patent Information
- Application Number
- CN202510774308.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-11
- Publication Date
- 2025-10-03
AI Technical Summary
Existing GaN diodes have a contradiction in achieving high withstand voltage and low reverse turn-on voltage. Traditional processes are difficult to be compatible, and the introduction of additional process steps increases costs.
A GaN-based diode structure is adopted. By integrating a recessed Schottky diode in the anode and combining it with a controllable gate, a diode anode is formed, avoiding additional process steps and utilizing a commercial p-GaN gate HEMT process to achieve high withstand voltage and low reverse turn-on voltage.
The GaN-based diode performance with high withstand voltage and low reverse turn-on voltage is achieved, which reduces the reverse conduction voltage drop, improves the forward stand-off withstand voltage, avoids additional process steps and saves costs.
Smart Images
Figure CN120751712A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of power semiconductors, and in particular relates to a GaN-based diode and a preparation technology thereof. Background Art
[0002] Compared to traditional silicon, GaN material offers significant advantages in electron saturation velocity, bandgap width, and critical breakdown electric field. The high-concentration, high-mobility 2DEG at the AlGaN / GaN heterojunction is a unique characteristic of GaN HEMTs. Compared to package-in-package solutions, monolithic integration of GaN significantly mitigates parasitic effects, further improving power system performance and reducing area costs. Monolithic integration platforms based on GaN heterojunctions require lateral GaN diodes or rectifiers with high withstand voltage and low turn-on voltage. Common power diodes include Schottky diodes, whose turn-on voltage is related to the Schottky barrier, and p-GaN gate L-FERs (which can be formed by shorting the gate-source of a p-GaN HEMT). However, their reverse conduction voltage drop is directly related to the threshold voltage of the p-GaN HEMT. This low reverse conduction voltage conflicted with the high threshold voltage requirement of enhancement-mode p-GaN HEMTs.
[0003] Therefore, to address this issue and simultaneously achieve high withstand voltage and low reverse turn-on voltage, a diode technology with gate-adjustable reverse turn-on voltage and breakdown voltage is proposed. On the one hand, a recessed Schottky diode integrated into the anode blocks the forward current path, forming the diode anode. On the other hand, by applying a forward voltage drop to the gate, the turn-on voltage drop during reverse conduction is reduced and the forward standoff voltage is increased. Summary of the Invention
[0004] To address the above issues, and to achieve the performance of a diode with high withstand voltage and low reverse turn-on voltage, while being compatible with the mainstream commercial p-GaN gate HEMT process and avoiding the introduction of additional process steps, the present invention proposes a GaN-based diode and its preparation technology.
[0005] The technical solution adopted in the present invention is:
[0006] A GaN-based diode comprises a substrate 10, a group III nitride buffer layer 20, a GaN channel layer 30, and a group III nitride barrier layer 40, which are stacked in sequence from bottom to top along the vertical direction of the device; the GaN channel layer 30 and the group III nitride barrier layer 40 form a heterojunction, and a 2DEG is formed at the heterojunction interface; a P-type doped group III nitride 50 is provided on one side of the upper surface of the group III nitride barrier layer 40, and the lateral width of the P-type doped group III nitride 50 is smaller than the lateral width of the group III nitride barrier layer 40; a TiN layer 60 is provided on the upper surface of the P-type doped group III nitride 50, and a TiN layer 60 is provided on the upper surface of the P-type doped group III nitride 50. The upper surface of the III-nitride barrier layer 40 at both ends of the TiN layer 60 has a first passivation layer 70, and the first passivation layer 70 completely surrounds the P-type doped III-nitride 50 and the TiN layer 60 in the vertical and lateral directions of the device, that is, the first passivation layer 70 has a protruding structure above the TiN layer 60, and the lateral width of the protruding structure is greater than the lateral width of the P-type doped III-nitride 50 and the TiN layer 60, and the vertical height of the first passivation layer 70 outside the protruding structure is equal to the sum of the vertical heights of the P-type doped III-nitride 50 and the TiN layer 60; a first field plate 80 is provided on one side of the protruding structure of the first passivation layer 70, and the first field plate 80 is provided on the other side of the first passivation layer 70. 0 and the raised structure of the first passivation layer 70, and the vertical height of the first field plate 80 is less than the vertical height of the raised structure of the first passivation layer 70; a second passivation layer 90 is provided on the upper surface of the first passivation layer 70, the second passivation layer 90 completely covers the first passivation layer 70 and the first field plate 80, and the second passivation layer 90 completely surrounds the raised structure of the first passivation layer 70 and the first field plate 80 in the vertical and lateral directions of the device, that is, the second passivation layer 90 has two raised structures, which are respectively defined as the first raised structure of the second passivation layer 90 and the second raised structure of the second passivation layer 90, wherein the first raised structure of the second passivation layer 90 is located above the raised structure of the first passivation layer 70, and The lateral width of the first raised structure of the second passivation layer 90 is greater than the raised structure of the first passivation layer 70. The second raised structure of the second passivation layer 90 is located above the first field plate 80, and the lateral width of the second raised structure of the second passivation layer 90 is greater than the lateral width of the first field plate 80. The upper surface height of the first raised structure of the second passivation layer 90 is greater than the upper surface height of the second raised structure of the second passivation layer 90, and the upper surface height of the second raised structure of the second passivation layer 90 is greater than the upper surface height of the second passivation layer 90 excluding the raised structure. The vertical height of the second passivation layer 90 excluding the first and second raised structures is the same as the vertical height of the raised structure of the first passivation layer 70.An anode ohmic metal 110 and a cathode ohmic metal 120 are respectively provided at both ends of the device, wherein the anode ohmic metal 110 is adjacent to the P-type doped group III nitride 50 and the TiN layer 60, and the P-type doped group III nitride 50 and the TiN layer 60 are located between the anode ohmic metal 110 and the first field plate 80; the anode ohmic metal 110 and the cathode ohmic metal 120 are both spaced apart from the edge of the device, and the anode ohmic metal 110 and the cathode ohmic metal 120 are both sequentially passed through the second passivation layer 90 and the first passivation layer 70 and then extend into the group III nitride barrier layer 40, and the bottom of the anode ohmic metal 110 and the cathode ohmic metal 120 are spaced apart from the bottom of the group III nitride barrier layer 40; the anode ohmic metal 110 and The portion of the cathode ohmic metal 120 located in the second passivation layer 90 has a groove, and the bottom of the groove is spaced apart from the bottom of the second passivation layer 90. The anode ohmic metal 110 and the cathode ohmic metal 120 both extend to both sides along the surface of the second passivation layer 90 at the end of the groove, one side extending to the edge of the device, and the other side extending to the same width as the one side. There is a distance between the portion of the anode ohmic metal 110 extending along the surface of the second passivation layer 90 and the side of the first protruding structure of the second passivation layer 90. A second field plate 100 is provided on the upper surface of the second passivation layer 90 between the second protruding structure of the second passivation layer 90 and the cathode ohmic metal 120, and the side of the second field plate 100 is spaced apart from the side of the second protruding structure of the second passivation layer 90. Contact, at the same time, the second field plate 100 also extends along the surface of the second convex structure of the second passivation layer 90 in the direction close to the first convex structure of the second passivation layer 90, and the end of the extended part is located directly above the first field plate 80 in the vertical direction of the device; a third passivation layer 130 is provided above the second passivation layer 90, and the third passivation layer 130 fills the grooves formed by the anode ohmic metal 110 and the cathode ohmic metal 120 in the second passivation layer 90, and the third passivation layer 130 completely covers the anode ohmic metal 110, the cathode ohmic metal 120, the second passivation layer 90, and the upper surface of the second field plate 100, and the third passivation layer 130 also has a convex structure, and the convex structure of the third passivation layer 130 is located between the first convex structure of the second passivation layer 90 and the second field plate 100, the lateral width of the raised structure of the third passivation layer 130 is greater than the total lateral width from the side of the first raised structure of the second passivation layer 90 close to the anode ohmic metal 110 to the side of the second field plate 100 close to the cathode ohmic metal 120; a gate metal 140 is provided on the upper surface of the TiN layer 60, and the gate metal 140 sequentially penetrates the raised structure of the third passivation layer 130, the first raised structure of the second passivation layer 90, and the raised structure of the first passivation layer 70 along the vertical direction of the device and is connected to the upper surface of the TiN layer 60, the upper layer of the gate metal 140 extends to both sides along the upper surface of the raised structure of the third passivation layer 130, and the two end portions and the extended portion of the upper layer of the gate metal 140 also extend upward along the vertical direction of the device to form two raised gate structures;A third field plate 160 is provided on the upper surface of the third passivation layer 130 near the cathode ohmic metal 120, and the side surface of the third field plate 160 is connected to the side surface of the raised structure of the third passivation layer 130, and the third field plate 160 also extends along the upper surface of the raised structure of the third passivation layer 130 toward the side near the anode ohmic metal 110, and the end surface of the extended portion is located directly above the second field plate 100 in the vertical direction of the device; an anode Schottky metal 150 is also provided between the anode ohmic metal 110 and the gate metal 140, and the anode Schottky metal 150 extends along the side surface of the raised structure of the third passivation layer 130 and the first raised structure of the second passivation layer 90, and then extends into the Ga The upper layer of the N-channel layer 30 contacts the 2DEG. The anode Schottky metal 150 contacts the side of the extension portion of the anode ohmic metal 110 on the upper surface of the second passivation layer 90. The anode Schottky metal 150 extends along the upper surface of the extension portion of the anode ohmic metal 110 to a groove close to the anode ohmic metal 110. The side of the anode Schottky metal 150 adjacent to the gate metal 140 extends along the upper surface of the raised portion of the third passivation layer 130 to close to the gate metal 140. The upper surface of the portion of the anode Schottky metal 150 extending along the upper surface of the anode ohmic metal 110 is flush with the upper surface of the portion of the anode Schottky metal 150 extending along the upper surface of the raised portion of the third passivation layer 130 in the lateral direction. The anode ohmic metal 110 and the anode Schottky metal 160 are connected to form a diode anode structure.
[0007] Furthermore, the substrate 10 is made of one of Si, sapphire and SiC.
[0008] Furthermore, the cathode ohmic metal 120 and the anode ohmic metal 110 are made of any one of Ti / Au, Ti / Al / Ni / Au, and Ti / Al that can form an ohmic contact with the 2DEG.
[0009] Furthermore, the contact between the gate metal 140 and the P-type doped group III nitride 50 layer, and the contact between the anode Schottky metal 160 and the 2DEG are Schottky contacts, and the material used for the anode Schottky metal 160 and the gate metal 140 is any one of Pt / Au, W / Au, and Ni / Au that forms a Schottky contact with the 2DEG and p-GaN.
[0010] Furthermore, the material of the first field plate 80 is one of Al, Ti, and Au; the material of the second field plate 100 and the anode ohmic metal 110 is consistent; and the material of the third field plate 160 and the gate metal 140 is consistent.
[0011] A method for preparing a GaN-based diode, comprising:
[0012] S1, sequentially forming a group III nitride buffer layer 20, a GaN channel layer 30, a group III nitride barrier layer 40 and a P-type doped group III nitride 50 on the upper surface of a substrate 10;
[0013] S2, etching away the excess P-type doped group III nitride 50, and depositing a TiN layer 60 on the surface of the remaining P-type doped group III nitride 50;
[0014] S3, growing a first passivation layer 70 on the P-type doped group III nitride 50 and the TiN layer 60;
[0015] S4, etching away the excess first passivation layer 70, retaining the first passivation layer 70 with the protruding structure, and growing the first field plate 80 on the side of the protruding structure of the first passivation layer 70 close to the center of the device;
[0016] S5, growing a second passivation layer 90 on the first passivation layer 70 and the first field plate 80, and etching grooves required for the anode ohmic metal 110 and the cathode ohmic metal 120 at the same time;
[0017] S6, depositing an anode ohmic metal 110 and a cathode ohmic metal 120 in the etched groove, and forming a second field plate 100 on the second passivation layer 90;
[0018] S7, growing a third passivation layer 130 on the second passivation layer 90, the second field plate 100, the anode ohmic metal 110 and the cathode ohmic metal 120;
[0019] S8, etching grooves required for the anode Schottky metal 150 and the gate metal 140;
[0020] S9 , filling the etched groove with the anode Schottky metal 150 and the gate metal 140 , and forming a third field plate 160 on the third passivation layer 130 .
[0021] The beneficial effects of the present invention are that, based on the epitaxial structure and preparation process of a commercial p-GaN gate HEMT, a Schottky diode is integrated onto the anode to form a gate-controllable diode, and based on the p-GaN HEMT power device, no additional preparation steps are required. The barrier layer in the recessed anode Schottky metal is completely etched away, achieving forward current blocking capability for the device. By applying a positive gate voltage, the reverse conduction voltage drop and forward standoff voltage of the gate-controlled diode can be adjusted, further reducing the reverse conduction voltage drop and improving the standoff voltage of the device. This not only avoids the introduction of additional process steps and saves costs, but also achieves the performance of a GaN-based diode with high withstand voltage and low reverse conduction voltage drop. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figure 1 Schematic diagram of the complete structure of the device proposed in the present invention.
[0023] Figure 2 This is a schematic diagram of the epitaxial structure of the device proposed in the present invention.
[0024] Figure 3 This is a schematic diagram of the structure of the device proposed in the present invention after the growth of the P-type doped Group III nitride layer of the gate and the TiN layer on the upper surface thereof are completed.
[0025] Figure 4 This is a schematic diagram of the structure of the device proposed in the present invention after a passivation layer is grown.
[0026] Figure 5 This is a schematic diagram of the structure of the device proposed in the present invention after the primary field plate growth is completed.
[0027] Figure 6 This is a schematic diagram of the structure of the device proposed in the present invention after the growth of two passivation layers is completed and the ohmic anode and ohmic cathode grooves are etched.
[0028] Figure 7 This is a schematic diagram of the structure of the device proposed in the present invention after the ohmic anode, ohmic cathode and second-level field plate are grown.
[0029] Figure 8 This is a schematic diagram of the structure of the device proposed in the present invention after the growth of the second passivation layer is completed.
[0030] Figure 9 This is a schematic diagram of the structure of the device proposed in the present invention after the growth of three passivation layers is completed and the Schottky anode and Schottky gate grooves are etched.
[0031] Figure 10 This is the complete structure of the GaN-based diode device proposed by the present invention.
[0032] Figure 11 This is a schematic diagram of the structure of a traditional device after the three passivation layers are grown and only the Schottky gate groove is etched.
[0033] Figure 12 It is a GaN diode without a Schottky cathode integrated diode structure.
[0034] Figure 13 This is the electrical simulation diagram when the device is turned on. DETAILED DESCRIPTION
[0035] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0036] The present invention proposes a GaN-based diode and its preparation technology, wherein the preparation method is to first prepare Figure 2 The epitaxial structure shown, along Figure 2 An epitaxial structure is obtained from bottom to top, including a substrate 10, a group III nitride buffer layer 20 located above the substrate 10, a GaN channel layer 30 located above the group III nitride buffer layer 20, and a group III nitride barrier layer 40 located above the GaN channel layer 30. The GaN channel layer 30 and the group III nitride barrier layer 40 form a heterojunction, forming a 2DEG at the heterojunction interface.
[0037] like Figure 3 As shown, the gate control structure is located on the III-nitride barrier layer 40 between the anode and cathode structures. The gate structure includes a P-type doped III-nitride 50 and TiN 60 located on the upper surface of the P-type doped III-nitride 50 .
[0038] like Figure 4 As shown, the growth of the passivation layer is completed. The passivation layer 70 is any one of an oxide layer and an insulating layer, including but not limited to SiO2, Si3N4, etc.
[0039] like Figure 5 As shown, the growth of the first-level field plate 80 is completed and is located on the right side of the gate structure and above the first passivation layer 70 .
[0040] like Figure 6 As shown, the etching of the ohmic anode and the ohmic cathode is completed.
[0041] like Figure 7 As shown, the growth of cathode ohmic metal, anode ohmic metal and second-level field plate is completed, and the anode ohmic metal 120 is located in the device GaN channel layer 30 or the group III nitride barrier layer 40; the cathode structure is located at the other end of the device group III nitride barrier layer 40, and is formed by the cathode ohmic metal 110, and the cathode ohmic metal 110 is located on the side away from the anode structure, and is located in the device GaN channel layer 30 or the group III nitride barrier layer 40, and the second-level field plate is located above the second passivation layer 90 and to the upper right of the first-level field plate 80.
[0042] like Figure 8 As shown, the growth of the third passivation layer 130 is completed.
[0043] like Figure 9 As shown, the groove etching of the anode Schottky metal 160 and the gate opening etching of the passivation layer (70, 90, 130) above the gate metal 140 are performed in the same step.
[0044] like Figure 10As shown, the Schottky metal 160 and the gate metal 140 are deposited in the same step. The TiN 60 insertion layer plays a role in protecting the surface of the P-type doped group III nitride 50 during the opening etching of the passivation layer (70, 90, 130). The anode structure is located at one end of the device's III-nitride barrier layer 40, and includes a diode anode structure formed by connecting an anode ohmic metal 120 and an anode Schottky metal 160. The anode ohmic metal 120 is located in the device's GaN channel layer 30 or the III-nitride barrier layer 40. The bottom of the anode Schottky metal 160 is located in the GaN channel layer 30, and the top is in contact with and connected to the anode ohmic metal 120. The cathode structure is located at the other end of the device's III-nitride barrier layer 40 and is formed by a cathode ohmic metal 110. The cathode ohmic metal 110 is located on a side away from the anode structure and is located in the device's GaN channel layer 30 or the III-nitride barrier layer 40. The gate structure is located on the III-nitride barrier layer 40 between the anode and cathode structures, and the gate structure includes a P-type doped III-nitride 50, TiN 60 located on the upper surface of the P-type doped III-nitride 50, and a gate metal 140 located on the TiN 60.
[0045] like Figure 11 and Figure 12 As shown, the process flow does not include the growth of cathode Schottky metal, thereby avoiding the introduction of additional process steps and saving costs.
[0046] The working principle and technical advantages of the GaN-based diode and its preparation technology proposed in the present invention are:
[0047] Based on commercial p-GaN / AlGaN / GaN-on-Si power integrated epitaxial structures and fabrication technologies, the traditional Schottky diode structure is incompatible with p-GaN HEMTs, adding additional process costs and reducing integration area efficiency. The low reverse conduction voltage drop of the p-GaN gate-based L-FER conflicts with the requirements of the enhancement-mode p-GaN HEMT, resulting in significant reverse conduction losses. Figure 1 This is a schematic diagram of the device structure of the present invention. Its technical advantage is that the process is fully compatible with the commercial p-GaN gate HEMT platform process and does not add additional process steps. Figure 13As can be seen, on the one hand, because the 2DEG between the drain and source is completely etched in the recessed Schottky anode region, and the forward conduction channel directly from the drain to the source is blocked by the potential barrier of the anode Schottky diode, it maintains strong blocking capability even after applying a forward gate voltage. Compared with traditional structures, on the one hand, when applying a positive gate voltage to the gate during reverse conduction, the reverse conduction voltage drop is reduced due to the lowered potential barrier of the gate, thereby reducing reverse conduction losses. The peak electric field of the gate on the cathode side is weakened by the positive gate voltage, thereby increasing the device offset length and improving the forward off-state withstand voltage.
Claims
1. A GaN-based diode, comprising a substrate (10), a group III nitride buffer layer (20), a GaN channel layer (30), and a group III nitride barrier layer (40) stacked in sequence from bottom to top along a vertical direction of the device; the GaN channel layer (30) and the group III nitride barrier layer (40) form a heterojunction, and a 2DEG is formed at the heterojunction interface; characterized in that: A P-type doped group III nitride (50) is provided on one side of the upper surface of the group III nitride barrier layer (40), and the lateral width of the P-type doped group III nitride (50) is smaller than the lateral width of the group III nitride barrier layer (40); a TiN layer (60) is provided on the upper surface of the P-type doped group III nitride (50), and a first passivation layer (70) is provided on the upper surface of the group III nitride barrier layer (40) at both ends of the P-type doped group III nitride (50) and the TiN layer (60), and the first passivation layer (70) completely surrounds the P-type doped group III nitride (50) and the TiN layer (60) in the vertical and lateral directions of the device, i.e., the first passivation layer (70) is provided. A passivation layer (70) has a protruding structure above the TiN layer (60), and the lateral width of the protruding structure is greater than the lateral widths of the P-type doped group III nitride (50) and the TiN layer (60), and the vertical height of the first passivation layer (70) outside the protruding structure is equal to the sum of the vertical heights of the P-type doped group III nitride (50) and the TiN layer (60); a first field plate (80) is provided on one side of the protruding structure of the first passivation layer (70), a spacing is provided between the first field plate (80) and the protruding structure of the first passivation layer (70), and the vertical height of the first field plate (80) is less than the vertical height of the protruding structure of the first passivation layer (70); A second passivation layer (90) is provided on the upper surface of the first passivation layer (70), the second passivation layer (90) completely covers the first passivation layer (70) and the first field plate (80), and the second passivation layer (90) completely surrounds the first passivation layer (70) protrusion structure and the first field plate (80) in the vertical and lateral directions of the device, that is, the second passivation layer (90) has two protrusion structures, which are respectively defined as the second passivation layer (90) first protrusion structure and the second passivation layer (90) second protrusion structure, wherein the second passivation layer (90) first protrusion structure is located above the first passivation layer (70) protrusion structure, and the lateral width of the second passivation layer (90) first protrusion structure is greater than the lateral width of the first passivation layer (70) protrusion structure. The second convex structure of the second passivation layer (90) is located above the first field plate (80), and the lateral width of the second convex structure of the second passivation layer (90) is greater than the lateral width of the first field plate (80), the upper surface height of the first convex structure of the second passivation layer (90) is greater than the upper surface height of the second convex structure of the second passivation layer (90), and the upper surface height of the second convex structure of the second passivation layer (90) is greater than the upper surface height of the second passivation layer (90) except the convex structure, and the vertical height of the second passivation layer (90) except the first convex structure and the second convex structure is the same as the vertical height of the convex structure of the first passivation layer (70); and there are anode ohmic metal ( 110) and a cathode ohmic metal (120), wherein the anode ohmic metal (110) is adjacent to the P-type doped group III nitride (50) and the TiN layer (60), and the P-type doped group III nitride (50) and the TiN layer (60) are located between the anode ohmic metal (110) and the first field plate (80); the anode ohmic metal (110) and the cathode ohmic metal (120) are spaced from the edge of the device, and the anode ohmic metal (110) and the cathode ohmic metal (120) are sequentially passed through the second passivation layer (90) and the first passivation layer (70) and then extend into the group III nitride barrier layer (40), and the anode ohmic metal (110) and the cathode ohmic metal (120) are spaced from the edge of the device. 20) has a gap with the bottom of the group III nitride barrier layer (40); the portions of the anode ohmic metal (110) and the cathode ohmic metal (120) located in the second passivation layer (90) both have a groove, the bottom of the groove has a gap with the bottom of the second passivation layer (90), the anode ohmic metal (110) and the cathode ohmic metal (120) both extend to both sides along the surface of the second passivation layer (90) at the end of the groove, one side extends to the edge of the device, and the other side extends to the same width as the one side, wherein the portion of the anode ohmic metal (110) extending along the surface of the second passivation layer (90) has a gap with the side surface of the first protruding structure of the second passivation layer (90);A second field plate (100) is provided on the upper surface of the second passivation layer (90) between the second protruding structure of the second passivation layer (90) and the cathode ohmic metal (120), and a side surface of the second field plate (100) contacts a side surface of the second protruding structure of the second passivation layer (90), and the second field plate (100) also extends along the surface of the second protruding structure of the second passivation layer (90) in a direction close to the first protruding structure of the second passivation layer (90), and the end of the extended portion is located directly above the first field plate (80) in the vertical direction of the device; A third passivation layer (130) is provided above the second passivation layer (90), the third passivation layer (130) fills the grooves formed in the second passivation layer (90) by the anode ohmic metal (110) and the cathode ohmic metal (120), and the third passivation layer (130) completely covers the upper surfaces of the anode ohmic metal (110), the cathode ohmic metal (120), the second passivation layer (90), and the second field plate (100), and the third passivation layer (130) also has a protrusion The structure comprises a third passivation layer (130) protruding structure located above the first protruding structure of the second passivation layer (90) and the second field plate (100), wherein the lateral width of the protruding structure of the third passivation layer (130) is greater than the total lateral width from the side of the first protruding structure of the second passivation layer (90) close to the anode ohmic metal (110) to the side of the second field plate (100) close to the cathode ohmic metal (120); and a gate metal (140) is provided on the upper surface of the TiN layer (60), wherein the gate The gate metal (140) sequentially penetrates the raised structure of the third passivation layer (130), the first raised structure of the second passivation layer (90), and the raised structure of the first passivation layer (70) along the vertical direction of the device, and is then connected to the upper surface of the TiN layer (60); the upper layer of the gate metal (140) extends to both sides along the upper surface of the raised structure of the third passivation layer (130), and the two end portions and the extended portion of the upper layer of the gate metal (140) also extend upward along the vertical direction of the device to form two raised gate structures; a third field plate (160) is provided on the upper surface of the third passivation layer (130) on the side close to the cathode ohmic metal (120); the side surface of the third field plate (160) is connected to the side surface of the raised structure of the third passivation layer (130), and the third field plate (160) also extends along the upper surface of the raised structure of the third passivation layer (130) to the side close to the anode ohmic metal (110), and the end surface of the extended portion is located directly above the second field plate (100) in the vertical direction of the device; An anode Schottky metal (150) is provided between the anode ohmic metal (110) and the gate metal (140). The anode Schottky metal (150) extends along the side of the protruding structure of the third passivation layer (130) and the first protruding structure of the second passivation layer (90), and sequentially penetrates the third passivation layer (130), the second passivation layer (90), the first passivation layer (70), the group III nitride barrier layer (40) in a vertical direction of the device downward, and then extends into the upper layer of the GaN channel layer (30) to contact the 2DEG. The anode Schottky metal (150) contacts the side of the extended portion of the anode ohmic metal (110) on the upper surface of the second passivation layer (90), and the anode Schottky metal (150) extends along the upper surface of the extended portion of the anode ohmic metal (110) to a groove close to the anode ohmic metal (110), and the side of the anode Schottky metal (150) adjacent to the gate metal (140) extends along the upper surface of the raised portion of the third passivation layer (130) to close to the gate metal (140), and the upper surface of the portion of the anode Schottky metal (150) extending along the upper surface of the anode ohmic metal (110) and the upper surface of the portion of the anode Schottky metal (150) extending along the upper surface of the raised portion of the third passivation layer (130) are flush in the lateral direction; the anode ohmic metal (110) and the anode Schottky metal (160) are connected to form a diode anode structure.
2. A GaN-based diode according to claim 1, characterized in that: The material used for the substrate (10) is one of Si, sapphire and SiC.
3. A GaN-based diode according to claim 1, characterized in that: The cathode ohmic metal (120) and the anode ohmic metal (110) are made of any one of Ti / Au, Ti / Al / Ni / Au, and Ti / Al that can form an ohmic contact with the 2DEG.
4. A GaN-based diode according to claim 1, characterized in that: The contact between the gate metal (140) and the P-type doped group III nitride (50) layer, and the contact between the anode Schottky metal (160) and the 2DEG are Schottky contacts, and the material used for the anode Schottky metal (160) and the gate metal (140) is any one of Pt / Au, W / Au, and Ni / Au that forms a Schottky contact with the 2DEG and p-GaN.
5. The GaN-based diode according to claim 1, characterized in that: The material used for the first field plate (80) is one of Al, Ti, and Au; the material used for the second field plate (100) and the anode ohmic metal (110) is consistent; and the material used for the third field plate (160) and the gate metal (140) is consistent.
6. A method for preparing the GaN-based diode according to claim 1, characterized in that: include: S1, sequentially generating a group III nitride buffer layer (20), a GaN channel layer (30), a group III nitride barrier layer (40), and a P-type doped group III nitride (50) on the upper surface of a substrate (10); S2, etching away the excess P-type doped group III nitride (50), and depositing a TiN layer (60) on the surface of the remaining P-type doped group III nitride (50); S3, growing a first passivation layer (70) on the P-type doped group III nitride (50) and the TiN layer (60); S4, etching away the excess first passivation layer (70), retaining the first passivation layer (70) having the convex structure, and growing a first field plate (80) on a side of the convex structure of the first passivation layer (70) close to the center of the device; S5, growing a second passivation layer (90) on the first passivation layer (70) and the first field plate (80), and simultaneously etching grooves required for the anode ohmic metal (110) and the cathode ohmic metal (120); S6, depositing an anode ohmic metal (110) and a cathode ohmic metal (120) in the etched groove, and simultaneously generating a second field plate (100) on the second passivation layer (90); S7, growing a third passivation layer (130) on the second passivation layer (90), the second field plate (100), the anode ohmic metal (110), and the cathode ohmic metal (120); S8, etching grooves required for the anode Schottky metal (150) and the gate metal (140); S9, filling the etched groove with an anode Schottky metal (150) and a gate metal (140), and simultaneously generating a third field plate (160) on the third passivation layer (130).